1/* $OpenBSD: if_sereg.h,v 1.4 2010/09/05 12:42:54 miod Exp $ */ 2 3/*- 4 * Copyright (c) 2008, 2009, 2010 Nikolay Denev <ndenev@gmail.com> 5 * Copyright (c) 2007, 2008 Alexander Pohoyda <alexander.pohoyda@gmx.net> 6 * Copyright (c) 1997, 1998, 1999 7 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Bill Paul. 20 * 4. Neither the name of the author nor the names of any co-contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 27 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL AUTHORS OR 28 * THE VOICES IN THEIR HEADS BE LIABLE FOR ANY DIRECT, INDIRECT, 29 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 33 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 35 * OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * $FreeBSD: src/sys/dev/sge/if_sgereg.h,v 1.7 2010/07/08 18:22:49 yongari Exp $ 38 */ 39 40#define TX_CTL 0x00 41#define TX_DESC 0x04 42#define Reserved0 0x08 43#define TX_NEXT 0x0c 44 45#define RX_CTL 0x10 46#define RX_DESC 0x14 47#define Reserved1 0x18 48#define RX_NEXT 0x1c 49 50#define IntrStatus 0x20 51#define IntrMask 0x24 52#define IntrControl 0x28 53#define IntrTimer 0x2c 54 55#define PMControl 0x30 56#define Reserved2 0x34 57#define ROMControl 0x38 58#define ROMInterface 0x3c 59#define StationControl 0x40 60#define GMIIControl 0x44 61#define GMacIOCR 0x48 62#define GMacIOCTL 0x4c 63#define TxMacControl 0x50 64#define TxMacTimeLimit 0x54 65#define RGMIIDelay 0x58 66#define Reserved3 0x5c 67#define RxMacControl 0x60 /* 1 WORD */ 68#define RxMacAddr 0x62 /* 6x BYTE */ 69#define RxHashTable 0x68 /* 1 LONG */ 70#define RxHashTable2 0x6c /* 1 LONG */ 71#define RxWakeOnLan 0x70 72#define RxWakeOnLanData 0x74 73#define RxMPSControl 0x78 74#define Reserved4 0x7c 75 76/* 77 * IntrStatus Register Content 78 */ 79#define INTR_SOFT 0x40000000 80#define INTR_TIMER 0x20000000 81#define INTR_PAUSE_FRAME 0x00080000 82#define INTR_MAGIC_FRAME 0x00040000 83#define INTR_WAKE_FRAME 0x00020000 84#define INTR_LINK 0x00010000 85#define INTR_RX_IDLE 0x00000080 86#define INTR_RX_DONE 0x00000040 87#define INTR_TXQ1_IDLE 0x00000020 88#define INTR_TXQ1_DONE 0x00000010 89#define INTR_TX_IDLE 0x00000008 90#define INTR_TX_DONE 0x00000004 91#define INTR_RX_HALT 0x00000002 92#define INTR_TX_HALT 0x00000001 93 94#define SE_INTRS \ 95 (INTR_RX_IDLE | INTR_RX_DONE | INTR_TXQ1_IDLE | \ 96 INTR_TXQ1_DONE |INTR_TX_IDLE | INTR_TX_DONE | \ 97 INTR_TX_HALT | INTR_RX_HALT) 98 99/* 100 * RxStatusDesc Register Content 101 */ 102#define RxRES 0x00200000 103#define RxCRC 0x00080000 104#define RxRUNT 0x00100000 105#define RxRWT 0x00400000 106 107/* 108 * RX_CTL Register Content 109 */ 110#define RX_CTL_POLL 0x00000010 111#define RX_CTL_ENB 0x00000001 112 113/* 114 * TX_CTL Register Content 115 */ 116#define TX_CTL_POLL 0x00000010 117#define TX_CTL_ENB 0x00000001 118 119/* 120 * RxMacControl Register Content 121 */ 122#define AcceptBroadcast 0x0800 123#define AcceptMulticast 0x0400 124#define AcceptMyPhys 0x0200 125#define AcceptAllPhys 0x0100 126#define AcceptErr 0x0020 127#define AcceptRunt 0x0010 128#define RXMAC_STRIP_VLAN 0x0020 129#define RXMAC_STRIP_FCS 0x0010 130#define RXMAC_PAD_ENB 0x0004 131#define RXMAC_CSUM_ENB 0x0002 132 133#define SE_RX_PAD_BYTES 10 134 135/* Station control register. */ 136#define SC_LOOPBACK 0x80000000 137#define SC_RGMII 0x00008000 138#define SC_FDX 0x00001000 139#define SC_SPEED_MASK 0x00000c00 140#define SC_SPEED_10 0x00000400 141#define SC_SPEED_100 0x00000800 142#define SC_SPEED_1000 0x00000c00 143 144/* 145 * Gigabit Media Independent Interface CTL register 146 */ 147#define GMI_DATA 0xffff0000 148#define GMI_DATA_SHIFT 16 149#define GMI_REG 0x0000f800 150#define GMI_REG_SHIFT 11 151#define GMI_PHY 0x000007c0 152#define GMI_PHY_SHIFT 6 153#define GMI_OP_WR 0x00000020 154#define GMI_OP_RD 0x00000000 155#define GMI_REQ 0x00000010 156#define GMI_MDIO 0x00000008 157#define GMI_MDDIR 0x00000004 158#define GMI_MDC 0x00000002 159#define GMI_MDEN 0x00000001 160 161/* Tx descriptor command bits. */ 162#define TDC_OWN 0x80000000 163#define TDC_INTR 0x40000000 164#define TDC_THOL3 0x30000000 165#define TDC_THOL2 0x20000000 166#define TDC_THOL1 0x10000000 167#define TDC_THOL0 0x00000000 168#define TDC_LS 0x08000000 169#define TDC_IP_CSUM 0x04000000 170#define TDC_TCP_CSUM 0x02000000 171#define TDC_UDP_CSUM 0x01000000 172#define TDC_BST 0x00800000 173#define TDC_EXT 0x00400000 174#define TDC_DEF 0x00200000 175#define TDC_BKF 0x00100000 176#define TDC_CRS 0x00080000 177#define TDC_COL 0x00040000 178#define TDC_CRC 0x00020000 179#define TDC_PAD 0x00010000 180#define TDC_VLAN_MASK 0x0000FFFF 181 182#define SE_TX_INTR_FRAMES 32 183 184/* 185 * TX descriptor status bits. 186 */ 187#define TDS_OWC 0x00080000 188#define TDS_ABT 0x00040000 189#define TDS_FIFO 0x00020000 190#define TDS_CRS 0x00010000 191#define TDS_COLLS 0x0000ffff 192#define SE_TX_ERROR(x) ((x) & (TDS_OWC | TDS_ABT | TDS_FIFO | TDS_CRS)) 193#define TX_ERR_BITS "\20" \ 194 "\21CRS\22FIFO\23ABT\24OWC" 195 196/* Rx descriptor command bits. */ 197#define RDC_OWN 0x80000000 198#define RDC_INTR 0x40000000 199#define RDC_IP_CSUM 0x20000000 200#define RDC_TCP_CSUM 0x10000000 201#define RDC_UDP_CSUM 0x08000000 202#define RDC_IP_CSUM_OK 0x04000000 203#define RDC_TCP_CSUM_OK 0x02000000 204#define RDC_UDP_CSUM_OK 0x01000000 205#define RDC_WAKEUP 0x00400000 206#define RDC_MAGIC 0x00200000 207#define RDC_PAUSE 0x00100000 208#define RDC_BCAST 0x000c0000 209#define RDC_MCAST 0x00080000 210#define RDC_UCAST 0x00040000 211#define RDC_CRCOFF 0x00020000 212#define RDC_PREADD 0x00010000 213#define RDC_VLAN_MASK 0x0000FFFF 214 215/* 216 * RX descriptor status bits 217 */ 218#define RDS_VLAN 0x80000000 219#define RDS_DESCS 0x3f000000 220#define RDS_ABORT 0x00800000 221#define RDS_SHORT 0x00400000 222#define RDS_LIMIT 0x00200000 223#define RDS_MIIER 0x00100000 224#define RDS_OVRUN 0x00080000 225#define RDS_NIBON 0x00040000 226#define RDS_COLON 0x00020000 227#define RDS_CRCOK 0x00010000 228#define SE_RX_ERROR(x) \ 229 ((x) & (RDS_COLON | RDS_NIBON | RDS_OVRUN | RDS_MIIER | \ 230 RDS_LIMIT | RDS_SHORT | RDS_ABORT)) 231#define SE_RX_NSEGS(x) (((x) & RDS_DESCS) >> 24) 232#define RX_ERR_BITS "\20" \ 233 "\21CRCOK\22COLON\23NIBON\24OVRUN" \ 234 "\25MIIER\26LIMIT\27SHORT\30ABORT" \ 235 "\40VLAN" 236 237#define RING_END 0x80000000 238#define SE_RX_BYTES(x) ((x) & 0xFFFF) 239#define SE_INC(x, y) (x) = (((x) + 1) % y) 240 241/* Taken from Solaris driver */ 242#define EI_DATA 0xffff0000 243#define EI_DATA_SHIFT 16 244#define EI_OFFSET 0x0000fc00 245#define EI_OFFSET_SHIFT 10 246#define EI_OP 0x00000300 247#define EI_OP_SHIFT 8 248#define EI_OP_RD (2 << EI_OP_SHIFT) 249#define EI_OP_WR (1 << EI_OP_SHIFT) 250#define EI_REQ 0x00000080 251#define EI_DO 0x00000008 252#define EI_DI 0x00000004 253#define EI_CLK 0x00000002 254#define EI_CS 0x00000001 255 256/* 257 * EEPROM Addresses 258 */ 259#define EEPROMSignature 0x00 260#define EEPROMCLK 0x01 261#define EEPROMInfo 0x02 262#define EEPROMMACAddr 0x03 263 264#define SE_TIMEOUT 1000 265 266struct se_desc { 267 u_int32_t se_sts_size; 268 u_int32_t se_cmdsts; 269 u_int32_t se_ptr; 270 u_int32_t se_flags; 271}; 272