if_re_pci.c revision 1.45 
1/*	$OpenBSD: if_re_pci.c,v 1.45 2015/01/26 09:58:47 brad Exp $	*/
2
3/*
4 * Copyright (c) 2005 Peter Valchev <pvalchev@openbsd.org>
5 *
6 * Permission to use, copy, modify, and distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 */
18
19/*
20 * PCI front-end for the Realtek 8169
21 */
22
23#include <sys/param.h>
24#include <sys/endian.h>
25#include <sys/systm.h>
26#include <sys/sockio.h>
27#include <sys/mbuf.h>
28#include <sys/malloc.h>
29#include <sys/kernel.h>
30#include <sys/device.h>
31#include <sys/timeout.h>
32#include <sys/socket.h>
33
34#include <net/if.h>
35#include <net/if_dl.h>
36#include <net/if_media.h>
37
38#include <netinet/in.h>
39#include <netinet/if_ether.h>
40
41#include <dev/mii/mii.h>
42#include <dev/mii/miivar.h>
43
44#include <dev/pci/pcireg.h>
45#include <dev/pci/pcivar.h>
46#include <dev/pci/pcidevs.h>
47
48#include <dev/ic/rtl81x9reg.h>
49#include <dev/ic/revar.h>
50
51struct re_pci_softc {
52	/* General */
53	struct rl_softc sc_rl;
54
55	/* PCI-specific data */
56	void *sc_ih;
57	pci_chipset_tag_t sc_pc;
58	pcitag_t sc_pcitag;
59
60	bus_size_t sc_iosize;
61};
62
63const struct pci_matchid re_pci_devices[] = {
64	{ PCI_VENDOR_COREGA, PCI_PRODUCT_COREGA_CGLAPCIGT },
65	{ PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE528T },
66	{ PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T_C1 },
67	{ PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8101E },
68	{ PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8168 },
69	{ PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169 },
70	{ PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169SC },
71	{ PCI_VENDOR_TTTECH, PCI_PRODUCT_TTTECH_MC322 },
72	{ PCI_VENDOR_USR2, PCI_PRODUCT_USR2_USR997902 }
73};
74
75#define RE_LINKSYS_EG1032_SUBID 0x00241737
76
77int	re_pci_probe(struct device *, void *, void *);
78void	re_pci_attach(struct device *, struct device *, void *);
79int	re_pci_detach(struct device *, int);
80int	re_pci_activate(struct device *, int);
81
82/*
83 * PCI autoconfig definitions
84 */
85struct cfattach re_pci_ca = {
86	sizeof(struct re_pci_softc),
87	re_pci_probe,
88	re_pci_attach,
89	re_pci_detach,
90	re_pci_activate
91};
92
93/*
94 * Probe for a Realtek 8169/8110 chip. Check the PCI vendor and device
95 * IDs against our list and return a device name if we find a match.
96 */
97int
98re_pci_probe(struct device *parent, void *match, void *aux)
99{
100	struct pci_attach_args *pa = aux;
101	pci_chipset_tag_t pc = pa->pa_pc;
102	pcireg_t subid;
103
104	subid = pci_conf_read(pc, pa->pa_tag, PCI_SUBSYS_ID_REG);
105
106	/* C+ mode 8139's */
107	if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_REALTEK &&
108	    PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_REALTEK_RT8139 &&
109	    PCI_REVISION(pa->pa_class) == 0x20)
110		return (1);
111
112	if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_LINKSYS &&
113	    PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_LINKSYS_EG1032 &&
114	    subid == RE_LINKSYS_EG1032_SUBID)
115		return (1);
116
117	return (pci_matchbyid((struct pci_attach_args *)aux, re_pci_devices,
118	    nitems(re_pci_devices)));
119}
120
121/*
122 * PCI-specific attach routine
123 */
124void
125re_pci_attach(struct device *parent, struct device *self, void *aux)
126{
127	struct re_pci_softc	*psc = (struct re_pci_softc *)self;
128	struct rl_softc		*sc = &psc->sc_rl;
129	struct pci_attach_args	*pa = aux;
130	pci_chipset_tag_t	pc = pa->pa_pc;
131	pci_intr_handle_t	ih;
132	const char		*intrstr = NULL;
133	pcireg_t		reg;
134	int			rrs;
135
136	pci_set_powerstate(pa->pa_pc, pa->pa_tag, PCI_PMCSR_STATE_D0);
137
138#ifndef SMALL_KERNEL
139	/* Enable power management for wake on lan. */
140	pci_conf_write(pc, pa->pa_tag, RL_PCI_PMCSR, RL_PME_EN);
141#endif
142
143	/*
144	 * Map control/status registers.
145	 */
146	if (pci_mapreg_map(pa, RL_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0,
147	    &sc->rl_btag, &sc->rl_bhandle, NULL, &psc->sc_iosize, 0)) {
148		if (pci_mapreg_map(pa, RL_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0,
149		    &sc->rl_btag, &sc->rl_bhandle, NULL, &psc->sc_iosize, 0)) {
150			printf(": can't map mem or i/o space\n");
151			return;
152		}
153	}
154
155	/* Allocate interrupt */
156	if (pci_intr_map_msi(pa, &ih) == 0)
157		sc->rl_flags |= RL_FLAG_MSI;
158	else if (pci_intr_map(pa, &ih) != 0) {
159		printf(": couldn't map interrupt\n");
160		return;
161	}
162	intrstr = pci_intr_string(pc, ih);
163	psc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, re_intr, sc,
164	    sc->sc_dev.dv_xname);
165	if (psc->sc_ih == NULL) {
166		printf(": couldn't establish interrupt");
167		if (intrstr != NULL)
168			printf(" at %s", intrstr);
169		return;
170	}
171
172	sc->sc_dmat = pa->pa_dmat;
173	psc->sc_pc = pc;
174
175	/*
176	 * PCI Express check.
177	 */
178	if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PCIEXPRESS,
179	    &sc->rl_expcap, NULL)) {
180		if (!(PCI_VENDOR(pa->pa_id) == PCI_VENDOR_REALTEK &&
181		    PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_REALTEK_RT8101E)) {
182			/* Set PCIe maximum read request size to 2048. */
183			reg = pci_conf_read(pa->pa_pc, pa->pa_tag,
184			    sc->rl_expcap + PCI_PCIE_DCSR);
185			reg = (reg & ~PCI_PCIE_DCSR_MPS);
186			reg >>= 12;
187			rrs = (1 << (reg + 7));
188			if (rrs < 2048) {
189				reg = pci_conf_read(pa->pa_pc, pa->pa_tag,
190				    sc->rl_expcap + PCI_PCIE_DCSR);
191				reg = (reg & ~PCI_PCIE_DCSR_MPS) |
192				    (fls(2048) - 8) << 12;
193				pci_conf_write(pa->pa_pc, pa->pa_tag,
194				    sc->rl_expcap + PCI_PCIE_DCSR, reg);
195			}
196		}
197		sc->rl_flags |= RL_FLAG_PCIE;
198	}
199
200	if (!(PCI_VENDOR(pa->pa_id) == PCI_VENDOR_REALTEK &&
201	    PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_REALTEK_RT8139)) {
202		u_int8_t	cfg;
203
204		CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
205		cfg = CSR_READ_1(sc, RL_CFG2);
206		if (sc->rl_flags & RL_FLAG_MSI) {
207			cfg |= RL_CFG2_MSI;
208			CSR_WRITE_1(sc, RL_CFG2, cfg);
209		} else {
210			if ((cfg & RL_CFG2_MSI) != 0) {
211				cfg &= ~RL_CFG2_MSI;
212				CSR_WRITE_1(sc, RL_CFG2, cfg);
213			}
214		}
215		CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
216	}
217
218	sc->sc_product = PCI_PRODUCT(pa->pa_id);
219
220	/* Call bus-independent attach routine */
221	if (re_attach(sc, intrstr)) {
222		pci_intr_disestablish(pc, psc->sc_ih);
223		bus_space_unmap(sc->rl_btag, sc->rl_bhandle, psc->sc_iosize);
224	}
225}
226
227int
228re_pci_detach(struct device *self, int flags)
229{
230	struct re_pci_softc	*psc = (struct re_pci_softc *)self;
231	struct rl_softc		*sc = &psc->sc_rl;
232	struct ifnet		*ifp = &sc->sc_arpcom.ac_if;
233
234	/* Remove timeout handler */
235	timeout_del(&sc->timer_handle);
236
237	/* Detach PHY */
238	if (LIST_FIRST(&sc->sc_mii.mii_phys) != NULL)
239		mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY);
240
241	/* Delete media stuff */
242	ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY);
243	ether_ifdetach(ifp);
244	if_detach(ifp);
245
246	/* Disable interrupts */
247	if (psc->sc_ih != NULL)
248		pci_intr_disestablish(psc->sc_pc, psc->sc_ih);
249
250	/* Free pci resources */
251	bus_space_unmap(sc->rl_btag, sc->rl_bhandle, psc->sc_iosize);
252
253	return (0);
254}
255
256int
257re_pci_activate(struct device *self, int act)
258{
259	struct re_pci_softc	*psc = (struct re_pci_softc *)self;
260	struct rl_softc		*sc = &psc->sc_rl;
261	struct ifnet 		*ifp = &sc->sc_arpcom.ac_if;
262
263	switch (act) {
264	case DVACT_SUSPEND:
265		if (ifp->if_flags & IFF_RUNNING)
266			re_stop(ifp);
267		break;
268	case DVACT_RESUME:
269		if (ifp->if_flags & IFF_UP)
270			re_init(ifp);
271		break;
272	}
273
274	return (0);
275}
276