if_lge.c revision 1.23
1/* $OpenBSD: if_lge.c,v 1.23 2005/09/11 18:17:08 mickey Exp $ */ 2/* 3 * Copyright (c) 2001 Wind River Systems 4 * Copyright (c) 1997, 1998, 1999, 2000, 2001 5 * Bill Paul <william.paul@windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: src/sys/dev/lge/if_lge.c,v 1.6 2001/06/20 19:47:55 bmilekic Exp $ 35 */ 36 37/* 38 * Level 1 LXT1001 gigabit ethernet driver for FreeBSD. Public 39 * documentation not available, but ask me nicely. 40 * 41 * Written by Bill Paul <william.paul@windriver.com> 42 * Wind River Systems 43 */ 44 45/* 46 * The Level 1 chip is used on some D-Link, SMC and Addtron NICs. 47 * It's a 64-bit PCI part that supports TCP/IP checksum offload, 48 * VLAN tagging/insertion, GMII and TBI (1000baseX) ports. There 49 * are three supported methods for data transfer between host and 50 * NIC: programmed I/O, traditional scatter/gather DMA and Packet 51 * Propulsion Technology (tm) DMA. The latter mechanism is a form 52 * of double buffer DMA where the packet data is copied to a 53 * pre-allocated DMA buffer who's physical address has been loaded 54 * into a table at device initialization time. The rationale is that 55 * the virtual to physical address translation needed for normal 56 * scatter/gather DMA is more expensive than the data copy needed 57 * for double buffering. This may be true in Windows NT and the like, 58 * but it isn't true for us, at least on the x86 arch. This driver 59 * uses the scatter/gather I/O method for both TX and RX. 60 * 61 * The LXT1001 only supports TCP/IP checksum offload on receive. 62 * Also, the VLAN tagging is done using a 16-entry table which allows 63 * the chip to perform hardware filtering based on VLAN tags. Sadly, 64 * our vlan support doesn't currently play well with this kind of 65 * hardware support. 66 * 67 * Special thanks to: 68 * - Jeff James at Intel, for arranging to have the LXT1001 manual 69 * released (at long last) 70 * - Beny Chen at D-Link, for actually sending it to me 71 * - Brad Short and Keith Alexis at SMC, for sending me sample 72 * SMC9462SX and SMC9462TX adapters for testing 73 * - Paul Saab at Y!, for not killing me (though it remains to be seen 74 * if in fact he did me much of a favor) 75 */ 76 77#include "bpfilter.h" 78 79#include <sys/param.h> 80#include <sys/systm.h> 81#include <sys/sockio.h> 82#include <sys/mbuf.h> 83#include <sys/malloc.h> 84#include <sys/kernel.h> 85#include <sys/device.h> 86#include <sys/socket.h> 87 88#include <net/if.h> 89#include <net/if_dl.h> 90#include <net/if_media.h> 91 92#ifdef INET 93#include <netinet/in.h> 94#include <netinet/in_systm.h> 95#include <netinet/in_var.h> 96#include <netinet/ip.h> 97#include <netinet/if_ether.h> 98#endif 99 100#if NVLAN > 0 101#include <net/if_types.h> 102#include <net/if_vlan_var.h> 103#endif 104 105#if NBPFILTER > 0 106#include <net/bpf.h> 107#endif 108 109#include <uvm/uvm_extern.h> /* for vtophys */ 110#include <uvm/uvm_pmap.h> /* for vtophys */ 111 112#include <dev/pci/pcireg.h> 113#include <dev/pci/pcivar.h> 114#include <dev/pci/pcidevs.h> 115 116#include <dev/mii/mii.h> 117#include <dev/mii/miivar.h> 118 119#define LGE_USEIOSPACE 120 121#include <dev/pci/if_lgereg.h> 122 123int lge_probe(struct device *, void *, void *); 124void lge_attach(struct device *, struct device *, void *); 125 126int lge_alloc_jumbo_mem(struct lge_softc *); 127void lge_free_jumbo_mem(struct lge_softc *); 128void *lge_jalloc(struct lge_softc *); 129void lge_jfree(caddr_t, u_int, void *); 130 131int lge_newbuf(struct lge_softc *, struct lge_rx_desc *, 132 struct mbuf *); 133int lge_encap(struct lge_softc *, struct mbuf *, u_int32_t *); 134void lge_rxeof(struct lge_softc *, int); 135void lge_rxeoc(struct lge_softc *); 136void lge_txeof(struct lge_softc *); 137int lge_intr(void *); 138void lge_tick(void *); 139void lge_start(struct ifnet *); 140int lge_ioctl(struct ifnet *, u_long, caddr_t); 141void lge_init(void *); 142void lge_stop(struct lge_softc *); 143void lge_watchdog(struct ifnet *); 144void lge_shutdown(void *); 145int lge_ifmedia_upd(struct ifnet *); 146void lge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 147 148void lge_eeprom_getword(struct lge_softc *, int, u_int16_t *); 149void lge_read_eeprom(struct lge_softc *, caddr_t, int, int, int); 150 151int lge_miibus_readreg(struct device *, int, int); 152void lge_miibus_writereg(struct device *, int, int, int); 153void lge_miibus_statchg(struct device *); 154 155void lge_setmulti(struct lge_softc *); 156void lge_reset(struct lge_softc *); 157int lge_list_rx_init(struct lge_softc *); 158int lge_list_tx_init(struct lge_softc *); 159 160#ifdef LGE_USEIOSPACE 161#define LGE_RES SYS_RES_IOPORT 162#define LGE_RID LGE_PCI_LOIO 163#else 164#define LGE_RES SYS_RES_MEMORY 165#define LGE_RID LGE_PCI_LOMEM 166#endif 167 168#ifdef LGE_DEBUG 169#define DPRINTF(x) if (lgedebug) printf x 170#define DPRINTFN(n,x) if (lgedebug >= (n)) printf x 171int lgedebug = 0; 172#else 173#define DPRINTF(x) 174#define DPRINTFN(n,x) 175#endif 176 177#define LGE_SETBIT(sc, reg, x) \ 178 CSR_WRITE_4(sc, reg, \ 179 CSR_READ_4(sc, reg) | (x)) 180 181#define LGE_CLRBIT(sc, reg, x) \ 182 CSR_WRITE_4(sc, reg, \ 183 CSR_READ_4(sc, reg) & ~(x)) 184 185#define SIO_SET(x) \ 186 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | x) 187 188#define SIO_CLR(x) \ 189 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~x) 190 191/* 192 * Read a word of data stored in the EEPROM at address 'addr.' 193 */ 194void lge_eeprom_getword(sc, addr, dest) 195 struct lge_softc *sc; 196 int addr; 197 u_int16_t *dest; 198{ 199 register int i; 200 u_int32_t val; 201 202 CSR_WRITE_4(sc, LGE_EECTL, LGE_EECTL_CMD_READ| 203 LGE_EECTL_SINGLEACCESS|((addr >> 1) << 8)); 204 205 for (i = 0; i < LGE_TIMEOUT; i++) 206 if (!(CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ)) 207 break; 208 209 if (i == LGE_TIMEOUT) { 210 printf("%s: EEPROM read timed out\n", sc->sc_dv.dv_xname); 211 return; 212 } 213 214 val = CSR_READ_4(sc, LGE_EEDATA); 215 216 if (addr & 1) 217 *dest = (val >> 16) & 0xFFFF; 218 else 219 *dest = val & 0xFFFF; 220 221 return; 222} 223 224/* 225 * Read a sequence of words from the EEPROM. 226 */ 227void lge_read_eeprom(sc, dest, off, cnt, swap) 228 struct lge_softc *sc; 229 caddr_t dest; 230 int off; 231 int cnt; 232 int swap; 233{ 234 int i; 235 u_int16_t word = 0, *ptr; 236 237 for (i = 0; i < cnt; i++) { 238 lge_eeprom_getword(sc, off + i, &word); 239 ptr = (u_int16_t *)(dest + (i * 2)); 240 if (swap) 241 *ptr = ntohs(word); 242 else 243 *ptr = word; 244 } 245 246 return; 247} 248 249int lge_miibus_readreg(dev, phy, reg) 250 struct device * dev; 251 int phy, reg; 252{ 253 struct lge_softc *sc = (struct lge_softc *)dev; 254 int i; 255 256 /* 257 * If we have a non-PCS PHY, pretend that the internal 258 * autoneg stuff at PHY address 0 isn't there so that 259 * the miibus code will find only the GMII PHY. 260 */ 261 if (sc->lge_pcs == 0 && phy == 0) 262 return(0); 263 264 CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ); 265 266 for (i = 0; i < LGE_TIMEOUT; i++) 267 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) 268 break; 269 270 if (i == LGE_TIMEOUT) { 271 printf("%s: PHY read timed out\n", sc->sc_dv.dv_xname); 272 return(0); 273 } 274 275 return(CSR_READ_4(sc, LGE_GMIICTL) >> 16); 276} 277 278void lge_miibus_writereg(dev, phy, reg, data) 279 struct device * dev; 280 int phy, reg, data; 281{ 282 struct lge_softc *sc = (struct lge_softc *)dev; 283 int i; 284 285 CSR_WRITE_4(sc, LGE_GMIICTL, 286 (data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE); 287 288 for (i = 0; i < LGE_TIMEOUT; i++) 289 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) 290 break; 291 292 if (i == LGE_TIMEOUT) { 293 printf("%s: PHY write timed out\n", sc->sc_dv.dv_xname); 294 } 295} 296 297void lge_miibus_statchg(dev) 298 struct device * dev; 299{ 300 struct lge_softc *sc = (struct lge_softc *)dev; 301 struct mii_data *mii = &sc->lge_mii; 302 303 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_SPEED); 304 switch (IFM_SUBTYPE(mii->mii_media_active)) { 305 case IFM_1000_T: 306 case IFM_1000_SX: 307 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 308 break; 309 case IFM_100_TX: 310 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_100); 311 break; 312 case IFM_10_T: 313 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_10); 314 break; 315 default: 316 /* 317 * Choose something, even if it's wrong. Clearing 318 * all the bits will hose autoneg on the internal 319 * PHY. 320 */ 321 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 322 break; 323 } 324 325 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 326 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 327 } else { 328 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 329 } 330 331 return; 332} 333 334void lge_setmulti(sc) 335 struct lge_softc *sc; 336{ 337 struct arpcom *ac = &sc->arpcom; 338 struct ifnet *ifp = &ac->ac_if; 339 struct ether_multi *enm; 340 struct ether_multistep step; 341 u_int32_t h = 0, hashes[2] = { 0, 0 }; 342 343 /* Make sure multicast hash table is enabled. */ 344 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_MCAST); 345 346allmulti: 347 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 348 CSR_WRITE_4(sc, LGE_MAR0, 0xFFFFFFFF); 349 CSR_WRITE_4(sc, LGE_MAR1, 0xFFFFFFFF); 350 return; 351 } 352 353 /* first, zot all the existing hash bits */ 354 CSR_WRITE_4(sc, LGE_MAR0, 0); 355 CSR_WRITE_4(sc, LGE_MAR1, 0); 356 357 /* now program new ones */ 358 ETHER_FIRST_MULTI(step, ac, enm); 359 while (enm != NULL) { 360 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 361 ifp->if_flags |= IFF_ALLMULTI; 362 goto allmulti; 363 } 364 h = (ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) >> 26) & 365 0x0000003F; 366 if (h < 32) 367 hashes[0] |= (1 << h); 368 else 369 hashes[1] |= (1 << (h - 32)); 370 ETHER_NEXT_MULTI(step, enm); 371 } 372 373 CSR_WRITE_4(sc, LGE_MAR0, hashes[0]); 374 CSR_WRITE_4(sc, LGE_MAR1, hashes[1]); 375 376 return; 377} 378 379void lge_reset(sc) 380 struct lge_softc *sc; 381{ 382 register int i; 383 384 LGE_SETBIT(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_SOFTRST); 385 386 for (i = 0; i < LGE_TIMEOUT; i++) { 387 if (!(CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST)) 388 break; 389 } 390 391 if (i == LGE_TIMEOUT) 392 printf("%s: reset never completed\n", sc->sc_dv.dv_xname); 393 394 /* Wait a little while for the chip to get its brains in order. */ 395 DELAY(1000); 396 397 return; 398} 399 400/* 401 * Probe for a Level 1 chip. Check the PCI vendor and device 402 * IDs against our list and return a device name if we find a match. 403 */ 404int lge_probe(parent, match, aux) 405 struct device *parent; 406 void *match; 407 void *aux; 408{ 409 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 410 411 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_LEVEL1 && 412 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_LEVEL1_LXT1001) 413 return (1); 414 415 return (0); 416} 417 418/* 419 * Attach the interface. Allocate softc structures, do ifmedia 420 * setup and ethernet/BPF attach. 421 */ 422void lge_attach(parent, self, aux) 423 struct device *parent, *self; 424 void *aux; 425{ 426 struct lge_softc *sc = (struct lge_softc *)self; 427 struct pci_attach_args *pa = aux; 428 pci_chipset_tag_t pc = pa->pa_pc; 429 pci_intr_handle_t ih; 430 const char *intrstr = NULL; 431 bus_size_t iosize; 432 bus_dma_segment_t seg; 433 bus_dmamap_t dmamap; 434 int s, rseg; 435 u_char eaddr[ETHER_ADDR_LEN]; 436 u_int32_t command; 437 struct ifnet *ifp; 438 int error = 0; 439 caddr_t kva; 440 441 s = splimp(); 442 443 bzero(sc, sizeof(struct lge_softc)); 444 445 /* 446 * Handle power management nonsense. 447 */ 448 DPRINTFN(5, ("Preparing for conf read\n")); 449 command = pci_conf_read(pc, pa->pa_tag, LGE_PCI_CAPID) & 0x000000FF; 450 if (command == 0x01) { 451 command = pci_conf_read(pc, pa->pa_tag, LGE_PCI_PWRMGMTCTRL); 452 if (command & LGE_PSTATE_MASK) { 453 pcireg_t iobase, membase, irq; 454 455 /* Save important PCI config data. */ 456 iobase = pci_conf_read(pc, pa->pa_tag, LGE_PCI_LOIO); 457 membase = pci_conf_read(pc, pa->pa_tag, LGE_PCI_LOMEM); 458 irq = pci_conf_read(pc, pa->pa_tag, LGE_PCI_INTLINE); 459 460 /* Reset the power state. */ 461 printf("%s: chip is in D%d power mode " 462 "-- setting to D0\n", sc->sc_dv.dv_xname, 463 command & LGE_PSTATE_MASK); 464 command &= 0xFFFFFFFC; 465 pci_conf_write(pc, pa->pa_tag, 466 LGE_PCI_PWRMGMTCTRL, command); 467 468 /* Restore PCI config data. */ 469 pci_conf_write(pc, pa->pa_tag, LGE_PCI_LOIO, iobase); 470 pci_conf_write(pc, pa->pa_tag, LGE_PCI_LOMEM, membase); 471 pci_conf_write(pc, pa->pa_tag, LGE_PCI_INTLINE, irq); 472 } 473 } 474 475 /* 476 * Map control/status registers. 477 */ 478 DPRINTFN(5, ("Map control/status regs\n")); 479 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 480 481#ifdef LGE_USEIOSPACE 482 if (!(command & PCI_COMMAND_IO_ENABLE)) { 483 printf("%s: failed to enable I/O ports!\n", 484 sc->sc_dv.dv_xname); 485 error = ENXIO; 486 goto fail; 487 } 488 /* 489 * Map control/status registers. 490 */ 491 DPRINTFN(5, ("pci_mapreg_map\n")); 492 if (pci_mapreg_map(pa, LGE_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 493 &sc->lge_btag, &sc->lge_bhandle, NULL, &iosize, 0)) { 494 printf(": can't map i/o space\n"); 495 goto fail; 496 } 497#else 498 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 499 printf("%s: failed to enable memory mapping!\n", 500 sc->sc_dv.dv_xname); 501 error = ENXIO; 502 goto fail; 503 } 504 DPRINTFN(5, ("pci_mapreg_map\n")); 505 if (pci_mapreg_map(pa, LGE_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0, 506 &sc->lge_btag, &sc->lge_bhandle, NULL, &iosize, 0)) { 507 printf(": can't map mem space\n"); 508 goto fail; 509 } 510#endif 511 512 DPRINTFN(5, ("pci_intr_map\n")); 513 if (pci_intr_map(pa, &ih)) { 514 printf(": couldn't map interrupt\n"); 515 goto fail_1; 516 } 517 518 DPRINTFN(5, ("pci_intr_string\n")); 519 intrstr = pci_intr_string(pc, ih); 520 DPRINTFN(5, ("pci_intr_establish\n")); 521 sc->lge_intrhand = pci_intr_establish(pc, ih, IPL_NET, lge_intr, sc, 522 sc->sc_dv.dv_xname); 523 if (sc->lge_intrhand == NULL) { 524 printf(": couldn't establish interrupt"); 525 if (intrstr != NULL) 526 printf(" at %s", intrstr); 527 printf("\n"); 528 goto fail_1; 529 } 530 printf(": %s", intrstr); 531 532 /* Reset the adapter. */ 533 DPRINTFN(5, ("lge_reset\n")); 534 lge_reset(sc); 535 536 /* 537 * Get station address from the EEPROM. 538 */ 539 DPRINTFN(5, ("lge_read_eeprom\n")); 540 lge_read_eeprom(sc, (caddr_t)&eaddr[0], LGE_EE_NODEADDR_0, 1, 0); 541 lge_read_eeprom(sc, (caddr_t)&eaddr[2], LGE_EE_NODEADDR_1, 1, 0); 542 lge_read_eeprom(sc, (caddr_t)&eaddr[4], LGE_EE_NODEADDR_2, 1, 0); 543 544 /* 545 * A Level 1 chip was detected. Inform the world. 546 */ 547 printf(": address: %s\n", ether_sprintf(eaddr)); 548 549 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 550 551 sc->sc_dmatag = pa->pa_dmat; 552 DPRINTFN(5, ("bus_dmamem_alloc\n")); 553 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct lge_list_data), 554 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 555 printf("%s: can't alloc rx buffers\n", sc->sc_dv.dv_xname); 556 goto fail_1; 557 } 558 DPRINTFN(5, ("bus_dmamem_map\n")); 559 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 560 sizeof(struct lge_list_data), &kva, 561 BUS_DMA_NOWAIT)) { 562 printf("%s: can't map dma buffers (%d bytes)\n", 563 sc->sc_dv.dv_xname, sizeof(struct lge_list_data)); 564 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 565 goto fail_1; 566 } 567 DPRINTFN(5, ("bus_dmamem_create\n")); 568 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct lge_list_data), 1, 569 sizeof(struct lge_list_data), 0, 570 BUS_DMA_NOWAIT, &dmamap)) { 571 printf("%s: can't create dma map\n", sc->sc_dv.dv_xname); 572 bus_dmamem_unmap(sc->sc_dmatag, kva, 573 sizeof(struct lge_list_data)); 574 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 575 goto fail_1; 576 } 577 DPRINTFN(5, ("bus_dmamem_load\n")); 578 if (bus_dmamap_load(sc->sc_dmatag, dmamap, kva, 579 sizeof(struct lge_list_data), NULL, 580 BUS_DMA_NOWAIT)) { 581 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 582 bus_dmamem_unmap(sc->sc_dmatag, kva, 583 sizeof(struct lge_list_data)); 584 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 585 goto fail_1; 586 } 587 588 DPRINTFN(5, ("bzero\n")); 589 sc->lge_ldata = (struct lge_list_data *)kva; 590 bzero(sc->lge_ldata, sizeof(struct lge_list_data)); 591 592 /* Try to allocate memory for jumbo buffers. */ 593 DPRINTFN(5, ("lge_alloc_jumbo_mem\n")); 594 if (lge_alloc_jumbo_mem(sc)) { 595 printf("%s: jumbo buffer allocation failed\n", 596 sc->sc_dv.dv_xname); 597 goto fail_1; 598 } 599 600 ifp = &sc->arpcom.ac_if; 601 ifp->if_softc = sc; 602 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 603 ifp->if_ioctl = lge_ioctl; 604 ifp->if_start = lge_start; 605 ifp->if_watchdog = lge_watchdog; 606 ifp->if_baudrate = 1000000000; 607 IFQ_SET_MAXLEN(&ifp->if_snd, LGE_TX_LIST_CNT - 1); 608 IFQ_SET_READY(&ifp->if_snd); 609 DPRINTFN(5, ("bcopy\n")); 610 bcopy(sc->sc_dv.dv_xname, ifp->if_xname, IFNAMSIZ); 611 612 if (CSR_READ_4(sc, LGE_GMIIMODE) & LGE_GMIIMODE_PCSENH) 613 sc->lge_pcs = 1; 614 else 615 sc->lge_pcs = 0; 616 617 /* 618 * Do MII setup. 619 */ 620 DPRINTFN(5, ("mii setup\n")); 621 sc->lge_mii.mii_ifp = ifp; 622 sc->lge_mii.mii_readreg = lge_miibus_readreg; 623 sc->lge_mii.mii_writereg = lge_miibus_writereg; 624 sc->lge_mii.mii_statchg = lge_miibus_statchg; 625 ifmedia_init(&sc->lge_mii.mii_media, 0, lge_ifmedia_upd, 626 lge_ifmedia_sts); 627 mii_attach(&sc->sc_dv, &sc->lge_mii, 0xffffffff, MII_PHY_ANY, 628 MII_OFFSET_ANY, 0); 629 630 if (LIST_FIRST(&sc->lge_mii.mii_phys) == NULL) { 631 printf("%s: no PHY found!\n", sc->sc_dv.dv_xname); 632 ifmedia_add(&sc->lge_mii.mii_media, IFM_ETHER|IFM_MANUAL, 633 0, NULL); 634 ifmedia_set(&sc->lge_mii.mii_media, IFM_ETHER|IFM_MANUAL); 635 } 636 else 637 ifmedia_set(&sc->lge_mii.mii_media, IFM_ETHER|IFM_AUTO); 638 639 /* 640 * Call MI attach routine. 641 */ 642 DPRINTFN(5, ("if_attach\n")); 643 if_attach(ifp); 644 DPRINTFN(5, ("ether_ifattach\n")); 645 ether_ifattach(ifp); 646 DPRINTFN(5, ("timeout_set\n")); 647 timeout_set(&sc->lge_timeout, lge_tick, sc); 648 timeout_add(&sc->lge_timeout, hz); 649 650fail_1: 651 bus_space_unmap(sc->lge_btag, sc->lge_bhandle, iosize); 652fail: 653 splx(s); 654} 655 656/* 657 * Initialize the transmit descriptors. 658 */ 659int lge_list_tx_init(sc) 660 struct lge_softc *sc; 661{ 662 struct lge_list_data *ld; 663 struct lge_ring_data *cd; 664 int i; 665 666 cd = &sc->lge_cdata; 667 ld = sc->lge_ldata; 668 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 669 ld->lge_tx_list[i].lge_mbuf = NULL; 670 ld->lge_tx_list[i].lge_ctl = 0; 671 } 672 673 cd->lge_tx_prod = cd->lge_tx_cons = 0; 674 675 return(0); 676} 677 678 679/* 680 * Initialize the RX descriptors and allocate mbufs for them. Note that 681 * we arralge the descriptors in a closed ring, so that the last descriptor 682 * points back to the first. 683 */ 684int lge_list_rx_init(sc) 685 struct lge_softc *sc; 686{ 687 struct lge_list_data *ld; 688 struct lge_ring_data *cd; 689 int i; 690 691 ld = sc->lge_ldata; 692 cd = &sc->lge_cdata; 693 694 cd->lge_rx_prod = cd->lge_rx_cons = 0; 695 696 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 697 698 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 699 if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0) 700 break; 701 if (lge_newbuf(sc, &ld->lge_rx_list[i], NULL) == ENOBUFS) 702 return(ENOBUFS); 703 } 704 705 /* Clear possible 'rx command queue empty' interrupt. */ 706 CSR_READ_4(sc, LGE_ISR); 707 708 return(0); 709} 710 711/* 712 * Initialize an RX descriptor and attach an MBUF cluster. 713 */ 714int lge_newbuf(sc, c, m) 715 struct lge_softc *sc; 716 struct lge_rx_desc *c; 717 struct mbuf *m; 718{ 719 struct mbuf *m_new = NULL; 720 caddr_t *buf = NULL; 721 722 if (m == NULL) { 723 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 724 if (m_new == NULL) { 725 return(ENOBUFS); 726 } 727 728 /* Allocate the jumbo buffer */ 729 buf = lge_jalloc(sc); 730 if (buf == NULL) { 731 m_freem(m_new); 732 return(ENOBUFS); 733 } 734 /* Attach the buffer to the mbuf */ 735 m_new->m_data = m_new->m_ext.ext_buf = (void *)buf; 736 m_new->m_flags |= M_EXT; 737 m_new->m_ext.ext_size = m_new->m_pkthdr.len = 738 m_new->m_len = LGE_JLEN; 739 m_new->m_ext.ext_free = lge_jfree; 740 m_new->m_ext.ext_arg = sc; 741 MCLINITREFERENCE(m_new); 742 } else { 743 m_new = m; 744 m_new->m_len = m_new->m_pkthdr.len = ETHER_MAX_LEN_JUMBO; 745 m_new->m_data = m_new->m_ext.ext_buf; 746 } 747 748 /* 749 * Adjust alignment so packet payload begins on a 750 * longword boundary. Mandatory for Alpha, useful on 751 * x86 too. 752 */ 753 m_adj(m_new, ETHER_ALIGN); 754 755 c->lge_mbuf = m_new; 756 c->lge_fragptr_hi = 0; 757 c->lge_fragptr_lo = vtophys(mtod(m_new, caddr_t)); 758 c->lge_fraglen = m_new->m_len; 759 c->lge_ctl = m_new->m_len | LGE_RXCTL_WANTINTR | LGE_FRAGCNT(1); 760 c->lge_sts = 0; 761 762 /* 763 * Put this buffer in the RX command FIFO. To do this, 764 * we just write the physical address of the descriptor 765 * into the RX descriptor address registers. Note that 766 * there are two registers, one high DWORD and one low 767 * DWORD, which lets us specify a 64-bit address if 768 * desired. We only use a 32-bit address for now. 769 * Writing to the low DWORD register is what actually 770 * causes the command to be issued, so we do that 771 * last. 772 */ 773 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_LO, vtophys(c)); 774 LGE_INC(sc->lge_cdata.lge_rx_prod, LGE_RX_LIST_CNT); 775 776 return(0); 777} 778 779int lge_alloc_jumbo_mem(sc) 780 struct lge_softc *sc; 781{ 782 caddr_t ptr, kva; 783 bus_dma_segment_t seg; 784 bus_dmamap_t dmamap; 785 int i, rseg; 786 struct lge_jpool_entry *entry; 787 788 /* Grab a big chunk o' storage. */ 789 if (bus_dmamem_alloc(sc->sc_dmatag, LGE_JMEM, PAGE_SIZE, 0, 790 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 791 printf("%s: can't alloc rx buffers\n", sc->sc_dv.dv_xname); 792 return (ENOBUFS); 793 } 794 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, LGE_JMEM, &kva, 795 BUS_DMA_NOWAIT)) { 796 printf("%s: can't map dma buffers (%d bytes)\n", 797 sc->sc_dv.dv_xname, LGE_JMEM); 798 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 799 return (ENOBUFS); 800 } 801 if (bus_dmamap_create(sc->sc_dmatag, LGE_JMEM, 1, 802 LGE_JMEM, 0, BUS_DMA_NOWAIT, &dmamap)) { 803 printf("%s: can't create dma map\n", sc->sc_dv.dv_xname); 804 bus_dmamem_unmap(sc->sc_dmatag, kva, LGE_JMEM); 805 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 806 return (ENOBUFS); 807 } 808 if (bus_dmamap_load(sc->sc_dmatag, dmamap, kva, LGE_JMEM, 809 NULL, BUS_DMA_NOWAIT)) { 810 printf("%s: can't load dma map\n", sc->sc_dv.dv_xname); 811 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 812 bus_dmamem_unmap(sc->sc_dmatag, kva, LGE_JMEM); 813 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 814 return (ENOBUFS); 815 } 816 sc->lge_cdata.lge_jumbo_buf = (caddr_t)kva; 817 DPRINTFN(1,("lge_jumbo_buf = 0x%08X\n", sc->lge_cdata.lge_jumbo_buf)); 818 DPRINTFN(1,("LGE_JLEN = 0x%08X\n", LGE_JLEN)); 819 820 LIST_INIT(&sc->lge_jfree_listhead); 821 LIST_INIT(&sc->lge_jinuse_listhead); 822 823 /* 824 * Now divide it up into 9K pieces and save the addresses 825 * in an array. 826 */ 827 ptr = sc->lge_cdata.lge_jumbo_buf; 828 for (i = 0; i < LGE_JSLOTS; i++) { 829 sc->lge_cdata.lge_jslots[i] = ptr; 830 ptr += LGE_JLEN; 831 entry = malloc(sizeof(struct lge_jpool_entry), 832 M_DEVBUF, M_NOWAIT); 833 if (entry == NULL) { 834 bus_dmamap_unload(sc->sc_dmatag, dmamap); 835 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 836 bus_dmamem_unmap(sc->sc_dmatag, kva, LGE_JMEM); 837 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 838 sc->lge_cdata.lge_jumbo_buf = NULL; 839 printf("%s: no memory for jumbo buffer queue!\n", 840 sc->sc_dv.dv_xname); 841 return(ENOBUFS); 842 } 843 entry->slot = i; 844 LIST_INSERT_HEAD(&sc->lge_jfree_listhead, 845 entry, jpool_entries); 846 } 847 848 return(0); 849} 850 851/* 852 * Allocate a jumbo buffer. 853 */ 854void *lge_jalloc(sc) 855 struct lge_softc *sc; 856{ 857 struct lge_jpool_entry *entry; 858 859 entry = LIST_FIRST(&sc->lge_jfree_listhead); 860 861 if (entry == NULL) { 862#ifdef LGE_VERBOSE 863 printf("%s: no free jumbo buffers\n", sc->sc_dv.dv_xname); 864#endif 865 return(NULL); 866 } 867 868 LIST_REMOVE(entry, jpool_entries); 869 LIST_INSERT_HEAD(&sc->lge_jinuse_listhead, entry, jpool_entries); 870 return(sc->lge_cdata.lge_jslots[entry->slot]); 871} 872 873/* 874 * Release a jumbo buffer. 875 */ 876void lge_jfree(buf, size, arg) 877 caddr_t buf; 878 u_int size; 879 void *arg; 880{ 881 struct lge_softc *sc; 882 int i; 883 struct lge_jpool_entry *entry; 884 885 /* Extract the softc struct pointer. */ 886 sc = (struct lge_softc *)arg; 887 888 if (sc == NULL) 889 panic("lge_jfree: can't find softc pointer!"); 890 891 /* calculate the slot this buffer belongs to */ 892 i = ((vaddr_t)buf - (vaddr_t)sc->lge_cdata.lge_jumbo_buf) / LGE_JLEN; 893 894 if ((i < 0) || (i >= LGE_JSLOTS)) 895 panic("lge_jfree: asked to free buffer that we don't manage!"); 896 897 entry = LIST_FIRST(&sc->lge_jinuse_listhead); 898 if (entry == NULL) 899 panic("lge_jfree: buffer not in use!"); 900 entry->slot = i; 901 LIST_REMOVE(entry, jpool_entries); 902 LIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry, jpool_entries); 903 904 return; 905} 906 907/* 908 * A frame has been uploaded: pass the resulting mbuf chain up to 909 * the higher level protocols. 910 */ 911void lge_rxeof(sc, cnt) 912 struct lge_softc *sc; 913 int cnt; 914{ 915 struct mbuf *m; 916 struct ifnet *ifp; 917 struct lge_rx_desc *cur_rx; 918 int c, i, total_len = 0; 919 u_int32_t rxsts, rxctl; 920 921 ifp = &sc->arpcom.ac_if; 922 923 /* Find out how many frames were processed. */ 924 c = cnt; 925 i = sc->lge_cdata.lge_rx_cons; 926 927 /* Suck them in. */ 928 while(c) { 929 struct mbuf *m0 = NULL; 930 931 cur_rx = &sc->lge_ldata->lge_rx_list[i]; 932 rxctl = cur_rx->lge_ctl; 933 rxsts = cur_rx->lge_sts; 934 m = cur_rx->lge_mbuf; 935 cur_rx->lge_mbuf = NULL; 936 total_len = LGE_RXBYTES(cur_rx); 937 LGE_INC(i, LGE_RX_LIST_CNT); 938 c--; 939 940 /* 941 * If an error occurs, update stats, clear the 942 * status word and leave the mbuf cluster in place: 943 * it should simply get re-used next time this descriptor 944 * comes up in the ring. 945 */ 946 if (rxctl & LGE_RXCTL_ERRMASK) { 947 ifp->if_ierrors++; 948 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 949 continue; 950 } 951 952 if (lge_newbuf(sc, &LGE_RXTAIL(sc), NULL) == ENOBUFS) { 953 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, 954 ifp, NULL); 955 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 956 if (m0 == NULL) { 957 ifp->if_ierrors++; 958 continue; 959 } 960 m = m0; 961 } else { 962 m->m_pkthdr.rcvif = ifp; 963 m->m_pkthdr.len = m->m_len = total_len; 964 } 965 966 ifp->if_ipackets++; 967 968#if NBPFILTER > 0 969 /* 970 * Handle BPF listeners. Let the BPF user see the packet. 971 */ 972 if (ifp->if_bpf) 973 bpf_mtap(ifp->if_bpf, m); 974#endif 975 976 /* Do IP checksum checking. */ 977#if 0 978 if (rxsts & LGE_RXSTS_ISIP) 979 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 980 if (!(rxsts & LGE_RXSTS_IPCSUMERR)) 981 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 982 if ((rxsts & LGE_RXSTS_ISTCP && 983 !(rxsts & LGE_RXSTS_TCPCSUMERR)) || 984 (rxsts & LGE_RXSTS_ISUDP && 985 !(rxsts & LGE_RXSTS_UDPCSUMERR))) { 986 m->m_pkthdr.csum_flags |= 987 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 988 m->m_pkthdr.csum_data = 0xffff; 989 } 990#endif 991 992 if (rxsts & LGE_RXSTS_ISIP) { 993 if (rxsts & LGE_RXSTS_IPCSUMERR) 994 m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_BAD; 995 else 996 m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK; 997 } 998 if (rxsts & LGE_RXSTS_ISTCP) { 999 if (rxsts & LGE_RXSTS_TCPCSUMERR) 1000 m->m_pkthdr.csum_flags |= M_TCP_CSUM_IN_BAD; 1001 else 1002 m->m_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK; 1003 } 1004 if (rxsts & LGE_RXSTS_ISUDP) { 1005 if (rxsts & LGE_RXSTS_UDPCSUMERR) 1006 m->m_pkthdr.csum_flags |= M_UDP_CSUM_IN_BAD; 1007 else 1008 m->m_pkthdr.csum_flags |= M_UDP_CSUM_IN_OK; 1009 } 1010 1011 ether_input_mbuf(ifp, m); 1012 } 1013 1014 sc->lge_cdata.lge_rx_cons = i; 1015 1016 return; 1017} 1018 1019void lge_rxeoc(sc) 1020 struct lge_softc *sc; 1021{ 1022 struct ifnet *ifp; 1023 1024 ifp = &sc->arpcom.ac_if; 1025 ifp->if_flags &= ~IFF_RUNNING; 1026 lge_init(sc); 1027 return; 1028} 1029 1030/* 1031 * A frame was downloaded to the chip. It's safe for us to clean up 1032 * the list buffers. 1033 */ 1034 1035void lge_txeof(sc) 1036 struct lge_softc *sc; 1037{ 1038 struct lge_tx_desc *cur_tx = NULL; 1039 struct ifnet *ifp; 1040 u_int32_t idx, txdone; 1041 1042 ifp = &sc->arpcom.ac_if; 1043 1044 /* Clear the timeout timer. */ 1045 ifp->if_timer = 0; 1046 1047 /* 1048 * Go through our tx list and free mbufs for those 1049 * frames that have been transmitted. 1050 */ 1051 idx = sc->lge_cdata.lge_tx_cons; 1052 txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT); 1053 1054 while (idx != sc->lge_cdata.lge_tx_prod && txdone) { 1055 cur_tx = &sc->lge_ldata->lge_tx_list[idx]; 1056 1057 ifp->if_opackets++; 1058 if (cur_tx->lge_mbuf != NULL) { 1059 m_freem(cur_tx->lge_mbuf); 1060 cur_tx->lge_mbuf = NULL; 1061 } 1062 cur_tx->lge_ctl = 0; 1063 1064 txdone--; 1065 LGE_INC(idx, LGE_TX_LIST_CNT); 1066 ifp->if_timer = 0; 1067 } 1068 1069 sc->lge_cdata.lge_tx_cons = idx; 1070 1071 if (cur_tx != NULL) 1072 ifp->if_flags &= ~IFF_OACTIVE; 1073 1074 return; 1075} 1076 1077void lge_tick(xsc) 1078 void *xsc; 1079{ 1080 struct lge_softc *sc = xsc; 1081 struct mii_data *mii = &sc->lge_mii; 1082 struct ifnet *ifp = &sc->arpcom.ac_if; 1083 int s; 1084 1085 s = splimp(); 1086 1087 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_SINGLE_COLL_PKTS); 1088 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL); 1089 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_MULTI_COLL_PKTS); 1090 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL); 1091 1092 if (!sc->lge_link) { 1093 mii_tick(mii); 1094 if (mii->mii_media_status & IFM_ACTIVE && 1095 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1096 sc->lge_link++; 1097 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX|| 1098 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) 1099 printf("%s: gigabit link up\n", 1100 sc->sc_dv.dv_xname); 1101 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1102 lge_start(ifp); 1103 } 1104 } 1105 1106 timeout_add(&sc->lge_timeout, hz); 1107 1108 splx(s); 1109 1110 return; 1111} 1112 1113int lge_intr(arg) 1114 void *arg; 1115{ 1116 struct lge_softc *sc; 1117 struct ifnet *ifp; 1118 u_int32_t status; 1119 int claimed = 0; 1120 1121 sc = arg; 1122 ifp = &sc->arpcom.ac_if; 1123 1124 /* Supress unwanted interrupts */ 1125 if (!(ifp->if_flags & IFF_UP)) { 1126 lge_stop(sc); 1127 return (0); 1128 } 1129 1130 for (;;) { 1131 /* 1132 * Reading the ISR register clears all interrupts, and 1133 * clears the 'interrupts enabled' bit in the IMR 1134 * register. 1135 */ 1136 status = CSR_READ_4(sc, LGE_ISR); 1137 1138 if ((status & LGE_INTRS) == 0) 1139 break; 1140 1141 claimed = 1; 1142 1143 if ((status & (LGE_ISR_TXCMDFIFO_EMPTY|LGE_ISR_TXDMA_DONE))) 1144 lge_txeof(sc); 1145 1146 if (status & LGE_ISR_RXDMA_DONE) 1147 lge_rxeof(sc, LGE_RX_DMACNT(status)); 1148 1149 if (status & LGE_ISR_RXCMDFIFO_EMPTY) 1150 lge_rxeoc(sc); 1151 1152 if (status & LGE_ISR_PHY_INTR) { 1153 sc->lge_link = 0; 1154 timeout_del(&sc->lge_timeout); 1155 lge_tick(sc); 1156 } 1157 } 1158 1159 /* Re-enable interrupts. */ 1160 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|LGE_IMR_INTR_ENB); 1161 1162 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1163 lge_start(ifp); 1164 1165 return claimed; 1166} 1167 1168/* 1169 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1170 * pointers to the fragment pointers. 1171 */ 1172int lge_encap(sc, m_head, txidx) 1173 struct lge_softc *sc; 1174 struct mbuf *m_head; 1175 u_int32_t *txidx; 1176{ 1177 struct lge_frag *f = NULL; 1178 struct lge_tx_desc *cur_tx; 1179 struct mbuf *m; 1180 int frag = 0, tot_len = 0; 1181 1182 /* 1183 * Start packing the mbufs in this chain into 1184 * the fragment pointers. Stop when we run out 1185 * of fragments or hit the end of the mbuf chain. 1186 */ 1187 m = m_head; 1188 cur_tx = &sc->lge_ldata->lge_tx_list[*txidx]; 1189 frag = 0; 1190 1191 for (m = m_head; m != NULL; m = m->m_next) { 1192 if (m->m_len != 0) { 1193 tot_len += m->m_len; 1194 f = &cur_tx->lge_frags[frag]; 1195 f->lge_fraglen = m->m_len; 1196 f->lge_fragptr_lo = vtophys(mtod(m, vaddr_t)); 1197 f->lge_fragptr_hi = 0; 1198 frag++; 1199 } 1200 } 1201 1202 if (m != NULL) 1203 return(ENOBUFS); 1204 1205 cur_tx->lge_mbuf = m_head; 1206 cur_tx->lge_ctl = LGE_TXCTL_WANTINTR|LGE_FRAGCNT(frag)|tot_len; 1207 LGE_INC((*txidx), LGE_TX_LIST_CNT); 1208 1209 /* Queue for transmit */ 1210 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_LO, vtophys(cur_tx)); 1211 1212 return(0); 1213} 1214 1215/* 1216 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1217 * to the mbuf data regions directly in the transmit lists. We also save a 1218 * copy of the pointers since the transmit list fragment pointers are 1219 * physical addresses. 1220 */ 1221 1222void lge_start(ifp) 1223 struct ifnet *ifp; 1224{ 1225 struct lge_softc *sc; 1226 struct mbuf *m_head = NULL; 1227 u_int32_t idx; 1228 int pkts = 0; 1229 1230 sc = ifp->if_softc; 1231 1232 if (!sc->lge_link) 1233 return; 1234 1235 idx = sc->lge_cdata.lge_tx_prod; 1236 1237 if (ifp->if_flags & IFF_OACTIVE) 1238 return; 1239 1240 while(sc->lge_ldata->lge_tx_list[idx].lge_mbuf == NULL) { 1241 if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0) 1242 break; 1243 1244 IFQ_POLL(&ifp->if_snd, m_head); 1245 if (m_head == NULL) 1246 break; 1247 1248 if (lge_encap(sc, m_head, &idx)) { 1249 ifp->if_flags |= IFF_OACTIVE; 1250 break; 1251 } 1252 1253 /* now we are committed to transmit the packet */ 1254 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1255 pkts++; 1256 1257#if NBPFILTER > 0 1258 /* 1259 * If there's a BPF listener, bounce a copy of this frame 1260 * to him. 1261 */ 1262 if (ifp->if_bpf) 1263 bpf_mtap(ifp->if_bpf, m_head); 1264#endif 1265 } 1266 if (pkts == 0) 1267 return; 1268 1269 sc->lge_cdata.lge_tx_prod = idx; 1270 1271 /* 1272 * Set a timeout in case the chip goes out to lunch. 1273 */ 1274 ifp->if_timer = 5; 1275 1276 return; 1277} 1278 1279void lge_init(xsc) 1280 void *xsc; 1281{ 1282 struct lge_softc *sc = xsc; 1283 struct ifnet *ifp = &sc->arpcom.ac_if; 1284 int s; 1285 1286 if (ifp->if_flags & IFF_RUNNING) 1287 return; 1288 1289 s = splimp(); 1290 1291 /* 1292 * Cancel pending I/O and free all RX/TX buffers. 1293 */ 1294 lge_stop(sc); 1295 lge_reset(sc); 1296 1297 /* Set MAC address */ 1298 CSR_WRITE_4(sc, LGE_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1299 CSR_WRITE_4(sc, LGE_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1300 1301 /* Init circular RX list. */ 1302 if (lge_list_rx_init(sc) == ENOBUFS) { 1303 printf("%s: initialization failed: no " 1304 "memory for rx buffers\n", sc->sc_dv.dv_xname); 1305 lge_stop(sc); 1306 splx(s); 1307 return; 1308 } 1309 1310 /* 1311 * Init tx descriptors. 1312 */ 1313 lge_list_tx_init(sc); 1314 1315 /* Set initial value for MODE1 register. */ 1316 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_UCAST| 1317 LGE_MODE1_TX_CRC|LGE_MODE1_TXPAD| 1318 LGE_MODE1_RX_FLOWCTL|LGE_MODE1_SETRST_CTL0| 1319 LGE_MODE1_SETRST_CTL1|LGE_MODE1_SETRST_CTL2); 1320 1321 /* If we want promiscuous mode, set the allframes bit. */ 1322 if (ifp->if_flags & IFF_PROMISC) { 1323 CSR_WRITE_4(sc, LGE_MODE1, 1324 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_PROMISC); 1325 } else { 1326 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_PROMISC); 1327 } 1328 1329 /* 1330 * Set the capture broadcast bit to capture broadcast frames. 1331 */ 1332 if (ifp->if_flags & IFF_BROADCAST) { 1333 CSR_WRITE_4(sc, LGE_MODE1, 1334 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_BCAST); 1335 } else { 1336 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_BCAST); 1337 } 1338 1339 /* Packet padding workaround? */ 1340 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RMVPAD); 1341 1342 /* No error frames */ 1343 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ERRPKTS); 1344 1345 /* Receive large frames */ 1346 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_GIANTS); 1347 1348 /* Workaround: disable RX/TX flow control */ 1349 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_TX_FLOWCTL); 1350 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_FLOWCTL); 1351 1352 /* Make sure to strip CRC from received frames */ 1353 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_CRC); 1354 1355 /* Turn off magic packet mode */ 1356 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_MPACK_ENB); 1357 1358 /* Turn off all VLAN stuff */ 1359 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX|LGE_MODE1_VLAN_TX| 1360 LGE_MODE1_VLAN_STRIP|LGE_MODE1_VLAN_INSERT); 1361 1362 /* Workarond: FIFO overflow */ 1363 CSR_WRITE_2(sc, LGE_RXFIFO_HIWAT, 0x3FFF); 1364 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL1|LGE_IMR_RXFIFO_WAT); 1365 1366 /* 1367 * Load the multicast filter. 1368 */ 1369 lge_setmulti(sc); 1370 1371 /* 1372 * Enable hardware checksum validation for all received IPv4 1373 * packets, do not reject packets with bad checksums. 1374 */ 1375 CSR_WRITE_4(sc, LGE_MODE2, LGE_MODE2_RX_IPCSUM| 1376 LGE_MODE2_RX_TCPCSUM|LGE_MODE2_RX_UDPCSUM| 1377 LGE_MODE2_RX_ERRCSUM); 1378 1379 /* 1380 * Enable the delivery of PHY interrupts based on 1381 * link/speed/duplex status chalges. 1382 */ 1383 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_GMIIPOLL); 1384 1385 /* Enable receiver and transmitter. */ 1386 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 1387 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_ENB); 1388 1389 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_HI, 0); 1390 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_TX_ENB); 1391 1392 /* 1393 * Enable interrupts. 1394 */ 1395 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0| 1396 LGE_IMR_SETRST_CTL1|LGE_IMR_INTR_ENB|LGE_INTRS); 1397 1398 lge_ifmedia_upd(ifp); 1399 1400 ifp->if_flags |= IFF_RUNNING; 1401 ifp->if_flags &= ~IFF_OACTIVE; 1402 1403 splx(s); 1404 1405 timeout_add(&sc->lge_timeout, hz); 1406 1407 return; 1408} 1409 1410/* 1411 * Set media options. 1412 */ 1413int lge_ifmedia_upd(ifp) 1414 struct ifnet *ifp; 1415{ 1416 struct lge_softc *sc = ifp->if_softc; 1417 struct mii_data *mii = &sc->lge_mii; 1418 1419 sc->lge_link = 0; 1420 if (mii->mii_instance) { 1421 struct mii_softc *miisc; 1422 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1423 miisc = LIST_NEXT(miisc, mii_list)) 1424 mii_phy_reset(miisc); 1425 } 1426 mii_mediachg(mii); 1427 1428 return(0); 1429} 1430 1431/* 1432 * Report current media status. 1433 */ 1434void lge_ifmedia_sts(ifp, ifmr) 1435 struct ifnet *ifp; 1436 struct ifmediareq *ifmr; 1437{ 1438 struct lge_softc *sc = ifp->if_softc; 1439 struct mii_data *mii = &sc->lge_mii; 1440 1441 mii_pollstat(mii); 1442 ifmr->ifm_active = mii->mii_media_active; 1443 ifmr->ifm_status = mii->mii_media_status; 1444 1445 return; 1446} 1447 1448int lge_ioctl(ifp, command, data) 1449 struct ifnet *ifp; 1450 u_long command; 1451 caddr_t data; 1452{ 1453 struct lge_softc *sc = ifp->if_softc; 1454 struct ifreq *ifr = (struct ifreq *) data; 1455 struct ifaddr *ifa = (struct ifaddr *)data; 1456 struct mii_data *mii; 1457 int s, error = 0; 1458 1459 s = splimp(); 1460 1461 switch(command) { 1462 case SIOCSIFADDR: 1463 ifp->if_flags |= IFF_UP; 1464 switch (ifa->ifa_addr->sa_family) { 1465#ifdef INET 1466 case AF_INET: 1467 lge_init(sc); 1468 arp_ifinit(&sc->arpcom, ifa); 1469 break; 1470#endif /* INET */ 1471 default: 1472 lge_init(sc); 1473 break; 1474 } 1475 break; 1476 case SIOCSIFMTU: 1477 if (ifr->ifr_mtu > ETHERMTU_JUMBO) 1478 error = EINVAL; 1479 else 1480 ifp->if_mtu = ifr->ifr_mtu; 1481 break; 1482 case SIOCSIFFLAGS: 1483 if (ifp->if_flags & IFF_UP) { 1484 if (ifp->if_flags & IFF_RUNNING && 1485 ifp->if_flags & IFF_PROMISC && 1486 !(sc->lge_if_flags & IFF_PROMISC)) { 1487 CSR_WRITE_4(sc, LGE_MODE1, 1488 LGE_MODE1_SETRST_CTL1| 1489 LGE_MODE1_RX_PROMISC); 1490 } else if (ifp->if_flags & IFF_RUNNING && 1491 !(ifp->if_flags & IFF_PROMISC) && 1492 sc->lge_if_flags & IFF_PROMISC) { 1493 CSR_WRITE_4(sc, LGE_MODE1, 1494 LGE_MODE1_RX_PROMISC); 1495 } else { 1496 ifp->if_flags &= ~IFF_RUNNING; 1497 lge_init(sc); 1498 } 1499 } else { 1500 if (ifp->if_flags & IFF_RUNNING) 1501 lge_stop(sc); 1502 } 1503 sc->lge_if_flags = ifp->if_flags; 1504 error = 0; 1505 break; 1506 case SIOCADDMULTI: 1507 case SIOCDELMULTI: 1508 error = (command == SIOCADDMULTI) 1509 ? ether_addmulti(ifr, &sc->arpcom) 1510 : ether_delmulti(ifr, &sc->arpcom); 1511 1512 if (error == ENETRESET) { 1513 if (ifp->if_flags & IFF_RUNNING) 1514 lge_setmulti(sc); 1515 error = 0; 1516 } 1517 break; 1518 case SIOCGIFMEDIA: 1519 case SIOCSIFMEDIA: 1520 mii = &sc->lge_mii; 1521 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1522 break; 1523 default: 1524 error = EINVAL; 1525 break; 1526 } 1527 1528 splx(s); 1529 1530 return(error); 1531} 1532 1533void lge_watchdog(ifp) 1534 struct ifnet *ifp; 1535{ 1536 struct lge_softc *sc; 1537 1538 sc = ifp->if_softc; 1539 1540 ifp->if_oerrors++; 1541 printf("%s: watchdog timeout\n", sc->sc_dv.dv_xname); 1542 1543 lge_stop(sc); 1544 lge_reset(sc); 1545 ifp->if_flags &= ~IFF_RUNNING; 1546 lge_init(sc); 1547 1548 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1549 lge_start(ifp); 1550 1551 return; 1552} 1553 1554/* 1555 * Stop the adapter and free any mbufs allocated to the 1556 * RX and TX lists. 1557 */ 1558void lge_stop(sc) 1559 struct lge_softc *sc; 1560{ 1561 register int i; 1562 struct ifnet *ifp; 1563 1564 ifp = &sc->arpcom.ac_if; 1565 ifp->if_timer = 0; 1566 timeout_del(&sc->lge_timeout); 1567 1568 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1569 1570 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_INTR_ENB); 1571 1572 /* Disable receiver and transmitter. */ 1573 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ENB|LGE_MODE1_TX_ENB); 1574 sc->lge_link = 0; 1575 1576 /* 1577 * Free data in the RX lists. 1578 */ 1579 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 1580 if (sc->lge_ldata->lge_rx_list[i].lge_mbuf != NULL) { 1581 m_freem(sc->lge_ldata->lge_rx_list[i].lge_mbuf); 1582 sc->lge_ldata->lge_rx_list[i].lge_mbuf = NULL; 1583 } 1584 } 1585 bzero((char *)&sc->lge_ldata->lge_rx_list, 1586 sizeof(sc->lge_ldata->lge_rx_list)); 1587 1588 /* 1589 * Free the TX list buffers. 1590 */ 1591 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 1592 if (sc->lge_ldata->lge_tx_list[i].lge_mbuf != NULL) { 1593 m_freem(sc->lge_ldata->lge_tx_list[i].lge_mbuf); 1594 sc->lge_ldata->lge_tx_list[i].lge_mbuf = NULL; 1595 } 1596 } 1597 1598 bzero((char *)&sc->lge_ldata->lge_tx_list, 1599 sizeof(sc->lge_ldata->lge_tx_list)); 1600 1601 return; 1602} 1603 1604/* 1605 * Stop all chip I/O so that the kernel's probe routines don't 1606 * get confused by errant DMAs when rebooting. 1607 */ 1608void lge_shutdown(xsc) 1609 void *xsc; 1610{ 1611 struct lge_softc *sc = (struct lge_softc *)xsc; 1612 1613 lge_reset(sc); 1614 lge_stop(sc); 1615 1616 return; 1617} 1618 1619struct cfattach lge_ca = { 1620 sizeof(struct lge_softc), lge_probe, lge_attach 1621}; 1622 1623struct cfdriver lge_cd = { 1624 0, "lge", DV_IFNET 1625}; 1626