if_em.h revision 1.63
1/************************************************************************** 2 3Copyright (c) 2001-2003, Intel Corporation 4All rights reserved. 5 6Redistribution and use in source and binary forms, with or without 7modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30POSSIBILITY OF SUCH DAMAGE. 31 32***************************************************************************/ 33 34/* $FreeBSD: if_em.h,v 1.26 2004/09/01 23:22:41 pdeuskar Exp $ */ 35/* $OpenBSD: if_em.h,v 1.63 2016/01/07 04:21:36 dlg Exp $ */ 36 37#ifndef _EM_H_DEFINED_ 38#define _EM_H_DEFINED_ 39 40#include "bpfilter.h" 41#include "vlan.h" 42 43#include <sys/param.h> 44#include <sys/systm.h> 45#include <sys/sockio.h> 46#include <sys/mbuf.h> 47#include <sys/malloc.h> 48#include <sys/kernel.h> 49#include <sys/device.h> 50#include <sys/socket.h> 51#include <sys/timeout.h> 52#include <sys/atomic.h> 53 54#include <net/if.h> 55#include <net/if_media.h> 56 57#include <netinet/in.h> 58#include <netinet/ip.h> 59#include <netinet/if_ether.h> 60#include <netinet/tcp.h> 61#include <netinet/udp.h> 62 63#if NBPFILTER > 0 64#include <net/bpf.h> 65#endif 66 67typedef int boolean_t; 68#define TRUE 1 69#define FALSE 0 70 71#include <dev/pci/pcireg.h> 72#include <dev/pci/pcivar.h> 73#include <dev/pci/pcidevs.h> 74 75#include <dev/pci/if_em_hw.h> 76 77/* Tunables */ 78 79/* 80 * EM_TXD: Maximum number of Transmit Descriptors 81 * Valid Range: 80-256 for 82542 and 82543-based adapters 82 * 80-4096 for others 83 * Default Value: 256 84 * This value is the number of transmit descriptors allocated by the driver. 85 * Increasing this value allows the driver to queue more transmits. Each 86 * descriptor is 16 bytes. 87 * Since TDLEN should be multiple of 128bytes, the number of transmit 88 * descriptors should meet the following condition. 89 * (num_tx_desc * sizeof(struct em_tx_desc)) % 128 == 0 90 */ 91#define EM_MAX_TXD_82543 256 92#define EM_MAX_TXD 512 93 94/* 95 * EM_RXD - Maximum number of receive Descriptors 96 * Valid Range: 80-256 for 82542 and 82543-based adapters 97 * 80-4096 for others 98 * Default Value: 256 99 * This value is the number of receive descriptors allocated by the driver. 100 * Increasing this value allows the driver to buffer more incoming packets. 101 * Each descriptor is 16 bytes. A receive buffer is also allocated for each 102 * descriptor. The maximum MTU size is 16110. 103 * Since TDLEN should be multiple of 128bytes, the number of transmit 104 * descriptors should meet the following condition. 105 * (num_tx_desc * sizeof(struct em_tx_desc)) % 128 == 0 106 */ 107#define EM_MAX_RXD_82543 256 108#define EM_MAX_RXD 256 109 110/* 111 * MAX_INTS_PER_SEC (ITR - Interrupt Throttle Register) 112 * The Interrupt Throttle Register (ITR) limits the delivery of interrupts 113 * to a reasonable rate by providing a guaranteed inter-interrupt delay 114 * between interrupts asserted by the Ethernet controller. 115 */ 116#define MAX_INTS_PER_SEC 8000 117#define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256) 118 119/* 120 * EM_TIDV - Transmit Interrupt Delay Value 121 * Valid Range: 0-65535 (0=off) 122 * Default Value: 64 123 * This value delays the generation of transmit interrupts in units of 124 * 1.024 microseconds. Transmit interrupt reduction can improve CPU 125 * efficiency if properly tuned for specific network traffic. If the 126 * system is reporting dropped transmits, this value may be set too high 127 * causing the driver to run out of available transmit descriptors. 128 */ 129#define EM_TIDV 64 130 131/* 132 * EM_TADV - Transmit Absolute Interrupt Delay Value 133 * (Not valid for 82542/82543/82544) 134 * Valid Range: 0-65535 (0=off) 135 * Default Value: 64 136 * This value, in units of 1.024 microseconds, limits the delay in which a 137 * transmit interrupt is generated. Useful only if EM_TIDV is non-zero, 138 * this value ensures that an interrupt is generated after the initial 139 * packet is sent on the wire within the set amount of time. Proper tuning, 140 * along with EM_TIDV, may improve traffic throughput in specific 141 * network conditions. 142 */ 143#define EM_TADV 64 144 145/* 146 * EM_RDTR - Receive Interrupt Delay Timer (Packet Timer) 147 * Valid Range: 0-65535 (0=off) 148 * Default Value: 0 149 * This value delays the generation of receive interrupts in units of 1.024 150 * microseconds. Receive interrupt reduction can improve CPU efficiency if 151 * properly tuned for specific network traffic. Increasing this value adds 152 * extra latency to frame reception and can end up decreasing the throughput 153 * of TCP traffic. If the system is reporting dropped receives, this value 154 * may be set too high, causing the driver to run out of available receive 155 * descriptors. 156 * 157 * CAUTION: When setting EM_RDTR to a value other than 0, adapters 158 * may hang (stop transmitting) under certain network conditions. 159 * If this occurs a WATCHDOG message is logged in the system 160 * event log. In addition, the controller is automatically reset, 161 * restoring the network connection. To eliminate the potential 162 * for the hang ensure that EM_RDTR is set to 0. 163 */ 164#define EM_RDTR 0 165 166/* 167 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544) 168 * Valid Range: 0-65535 (0=off) 169 * Default Value: 64 170 * This value, in units of 1.024 microseconds, limits the delay in which a 171 * receive interrupt is generated. Useful only if EM_RDTR is non-zero, 172 * this value ensures that an interrupt is generated after the initial 173 * packet is received within the set amount of time. Proper tuning, 174 * along with EM_RDTR, may improve traffic throughput in specific network 175 * conditions. 176 */ 177#define EM_RADV 64 178 179/* 180 * This parameter controls the duration of transmit watchdog timer. 181 */ 182#define EM_TX_TIMEOUT 5 /* set to 5 seconds */ 183 184/* 185 * Thise parameter controls the minimum number of available transmit 186 * descriptors needed before we attempt transmission of a packet. 187 */ 188#define EM_TX_OP_THRESHOLD (sc->num_tx_desc / 32) 189 190/* 191 * This parameter controls whether or not autonegotiation is enabled. 192 * 0 - Disable autonegotiation 193 * 1 - Enable autonegotiation 194 */ 195#define DO_AUTO_NEG 1 196 197/* 198 * This parameter control whether or not the driver will wait for 199 * autonegotiation to complete. 200 * 1 - Wait for autonegotiation to complete 201 * 0 - Don't wait for autonegotiation to complete 202 */ 203#define WAIT_FOR_AUTO_NEG_DEFAULT 0 204 205/* 206 * EM_MASTER_SLAVE is only defined to enable a workaround for a known 207 * compatibility issue with 82541/82547 devices and some switches. 208 * See the "Known Limitations" section of the README file for a complete 209 * description and a list of affected switches. 210 * 211 * 0 = Hardware default 212 * 1 = Master mode 213 * 2 = Slave mode 214 * 3 = Auto master/slave 215 */ 216/* #define EM_MASTER_SLAVE 2 */ 217 218/* Tunables -- End */ 219 220#define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 221 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 222 ADVERTISE_1000_FULL) 223 224#define EM_MMBA 0x0010 /* Mem base address */ 225#define EM_FLASH 0x0014 /* Flash memory on ICH8 */ 226#define EM_ROUNDUP(size, unit) (((size) + (unit) - 1) & ~((unit) - 1)) 227 228#define EM_SMARTSPEED_DOWNSHIFT 3 229#define EM_SMARTSPEED_MAX 15 230 231#define MAX_NUM_MULTICAST_ADDRESSES 128 232 233/* 234 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 235 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will 236 * also optimize cache line size effect. H/W supports up to cache line size 128. 237 */ 238#define EM_DBA_ALIGN 128 239 240#define SPEED_MODE_BIT (1<<21) /* On PCI-E MACs only */ 241 242/* Defines for printing debug information */ 243#define DEBUG_INIT 0 244#define DEBUG_IOCTL 0 245#define DEBUG_HW 0 246 247#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 248#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 249#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 250#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 251#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 252#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 253#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 254#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 255#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 256 257/* Supported RX Buffer Sizes */ 258#define EM_RXBUFFER_2048 2048 259#define EM_RXBUFFER_4096 4096 260#define EM_RXBUFFER_8192 8192 261#define EM_RXBUFFER_16384 16384 262 263#ifdef __STRICT_ALIGNMENT 264#define EM_MCLBYTES (EM_RXBUFFER_2048 + ETHER_ALIGN) 265#else 266#define EM_MCLBYTES EM_RXBUFFER_2048 267#endif 268 269#define EM_MAX_SCATTER 64 270#define EM_TSO_SIZE 65535 271 272struct em_buffer { 273 int next_eop; /* Index of the desc to watch */ 274 struct mbuf *m_head; 275 bus_dmamap_t map; /* bus_dma map for packet */ 276}; 277 278/* 279 * Bus dma allocation structure used by 280 * em_dma_malloc and em_dma_free. 281 */ 282struct em_dma_alloc { 283 bus_addr_t dma_paddr; 284 caddr_t dma_vaddr; 285 bus_dma_tag_t dma_tag; 286 bus_dmamap_t dma_map; 287 bus_dma_segment_t dma_seg; 288 bus_size_t dma_size; 289 int dma_nseg; 290}; 291 292typedef enum _XSUM_CONTEXT_T { 293 OFFLOAD_NONE, 294 OFFLOAD_TCP_IP, 295 OFFLOAD_UDP_IP 296} XSUM_CONTEXT_T; 297 298/* For 82544 PCI-X Workaround */ 299typedef struct _ADDRESS_LENGTH_PAIR 300{ 301 u_int64_t address; 302 u_int32_t length; 303} ADDRESS_LENGTH_PAIR, *PADDRESS_LENGTH_PAIR; 304 305typedef struct _DESCRIPTOR_PAIR 306{ 307 ADDRESS_LENGTH_PAIR descriptor[4]; 308 u_int32_t elements; 309} DESC_ARRAY, *PDESC_ARRAY; 310 311/* Our adapter structure */ 312struct em_softc { 313 struct device sc_dev; 314 struct arpcom interface_data; 315 struct em_hw hw; 316 317 /* OpenBSD operating-system-specific structures */ 318 struct em_osdep osdep; 319 struct ifmedia media; 320 int io_rid; 321 322 void *sc_intrhand; 323 struct timeout em_intr_enable; 324 struct timeout timer_handle; 325 struct timeout tx_fifo_timer_handle; 326 327 /* Info about the board itself */ 328 u_int32_t part_num; 329 u_int8_t link_active; 330 u_int16_t link_speed; 331 u_int16_t link_duplex; 332 u_int32_t smartspeed; 333 u_int32_t tx_int_delay; 334 u_int32_t tx_abs_int_delay; 335 u_int32_t rx_int_delay; 336 u_int32_t rx_abs_int_delay; 337 338 XSUM_CONTEXT_T active_checksum_context; 339 340 /* 341 * Transmit definitions 342 * 343 * We have an array of num_tx_desc descriptors (handled 344 * by the controller) paired with an array of tx_buffers 345 * (at tx_buffer_area). 346 * The index of the next available descriptor is next_avail_tx_desc. 347 * The number of remaining tx_desc is num_tx_desc_avail. 348 */ 349 struct em_dma_alloc txdma; /* bus_dma glue for tx desc */ 350 struct em_tx_desc *tx_desc_base; 351 u_int32_t next_avail_tx_desc; 352 u_int32_t next_tx_to_clean; 353 volatile u_int32_t num_tx_desc_avail; 354 u_int32_t num_tx_desc; 355 u_int32_t txd_cmd; 356 struct em_buffer *tx_buffer_area; 357 bus_dma_tag_t txtag; /* dma tag for tx */ 358 359 /* 360 * Receive definitions 361 * 362 * we have an array of num_rx_desc rx_desc (handled by the 363 * controller), and paired with an array of rx_buffers 364 * (at rx_buffer_area). 365 * The next pair to check on receive is at offset next_rx_desc_to_check 366 */ 367 struct em_dma_alloc rxdma; /* bus_dma glue for rx desc */ 368 struct em_rx_desc *rx_desc_base; 369 struct if_rxring rx_ring; 370 u_int32_t next_rx_desc_to_check; 371 u_int32_t last_rx_desc_filled; 372 u_int32_t rx_buffer_len; 373 u_int16_t num_rx_desc; 374 struct em_buffer *rx_buffer_area; 375 bus_dma_tag_t rxtag; 376 377 /* 378 * First/last mbuf pointers, for 379 * collecting multisegment RX packets. 380 */ 381 struct mbuf *fmp; 382 struct mbuf *lmp; 383 384 /* Misc stats maintained by the driver */ 385 unsigned long dropped_pkts; 386 unsigned long mbuf_alloc_failed; 387 unsigned long mbuf_cluster_failed; 388 unsigned long no_tx_desc_avail1; 389 unsigned long no_tx_desc_avail2; 390 unsigned long no_tx_map_avail; 391 unsigned long no_tx_dma_setup; 392 unsigned long watchdog_events; 393 unsigned long rx_overruns; 394 395 /* Used in for 82547 10Mb Half workaround */ 396 #define EM_PBA_BYTES_SHIFT 0xA 397 #define EM_TX_HEAD_ADDR_SHIFT 7 398 #define EM_PBA_TX_MASK 0xFFFF0000 399 #define EM_FIFO_HDR 0x10 400 401 #define EM_82547_PKT_THRESH 0x3e0 402 403 u_int32_t tx_fifo_size; 404 u_int32_t tx_fifo_head; 405 u_int32_t tx_fifo_head_addr; 406 u_int64_t tx_fifo_reset_cnt; 407 u_int64_t tx_fifo_wrk_cnt; 408 u_int32_t tx_head_addr; 409 410 /* For 82544 PCI-X Workaround */ 411 boolean_t pcix_82544; 412 struct em_hw_stats stats; 413}; 414 415#endif /* _EM_H_DEFINED_ */ 416