1/************************************************************************** 2 3Copyright (c) 2001-2003, Intel Corporation 4All rights reserved. 5 6Redistribution and use in source and binary forms, with or without 7modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30POSSIBILITY OF SUCH DAMAGE. 31 32***************************************************************************/ 33 34/* $FreeBSD: if_em.h,v 1.26 2004/09/01 23:22:41 pdeuskar Exp $ */ 35/* $OpenBSD: if_em.h,v 1.83 2024/02/16 22:30:54 mglocker Exp $ */ 36 37#ifndef _EM_H_DEFINED_ 38#define _EM_H_DEFINED_ 39 40#include "bpfilter.h" 41#include "vlan.h" 42#include "kstat.h" 43 44#include <sys/param.h> 45#include <sys/systm.h> 46#include <sys/sockio.h> 47#include <sys/mbuf.h> 48#include <sys/malloc.h> 49#include <sys/kernel.h> 50#include <sys/device.h> 51#include <sys/socket.h> 52#include <sys/timeout.h> 53#include <sys/atomic.h> 54#include <sys/kstat.h> 55 56#include <net/if.h> 57#include <net/if_media.h> 58#include <net/route.h> 59 60#include <netinet/in.h> 61#include <netinet/ip.h> 62#include <netinet/if_ether.h> 63#include <netinet/tcp.h> 64#include <netinet/tcp_timer.h> 65#include <netinet/tcp_var.h> 66#include <netinet/udp.h> 67 68#if NBPFILTER > 0 69#include <net/bpf.h> 70#endif 71 72typedef int boolean_t; 73#define TRUE 1 74#define FALSE 0 75 76#include <dev/pci/pcireg.h> 77#include <dev/pci/pcivar.h> 78#include <dev/pci/pcidevs.h> 79 80#include <dev/pci/if_em_hw.h> 81 82/* Tunables */ 83 84/* 85 * EM_TXD: Maximum number of Transmit Descriptors 86 * Valid Range: 80-256 for 82542 and 82543-based adapters 87 * 80-4096 for others 88 * Default Value: 256 89 * This value is the number of transmit descriptors allocated by the driver. 90 * Increasing this value allows the driver to queue more transmits. Each 91 * descriptor is 16 bytes. 92 * Since TDLEN should be multiple of 128bytes, the number of transmit 93 * descriptors should meet the following condition. 94 * (num_tx_desc * sizeof(struct em_tx_desc)) % 128 == 0 95 */ 96#define EM_MAX_TXD_82543 256 97#define EM_MAX_TXD 512 98 99/* 100 * EM_RXD - Maximum number of receive Descriptors 101 * Valid Range: 80-256 for 82542 and 82543-based adapters 102 * 80-4096 for others 103 * Default Value: 256 104 * This value is the number of receive descriptors allocated by the driver. 105 * Increasing this value allows the driver to buffer more incoming packets. 106 * Each descriptor is 16 bytes. A receive buffer is also allocated for each 107 * descriptor. The maximum MTU size is 16110. 108 * Since TDLEN should be multiple of 128bytes, the number of transmit 109 * descriptors should meet the following condition. 110 * (num_tx_desc * sizeof(struct em_tx_desc)) % 128 == 0 111 */ 112#define EM_MAX_RXD_82543 256 113#define EM_MAX_RXD 256 114 115/* 116 * MAX_INTS_PER_SEC (ITR - Interrupt Throttle Register) 117 * The Interrupt Throttle Register (ITR) limits the delivery of interrupts 118 * to a reasonable rate by providing a guaranteed inter-interrupt delay 119 * between interrupts asserted by the Ethernet controller. 120 */ 121#define MAX_INTS_PER_SEC 8000 122#define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256) 123 124/* 125 * EM_TIDV - Transmit Interrupt Delay Value 126 * Valid Range: 0-65535 (0=off) 127 * Default Value: 64 128 * This value delays the generation of transmit interrupts in units of 129 * 1.024 microseconds. Transmit interrupt reduction can improve CPU 130 * efficiency if properly tuned for specific network traffic. If the 131 * system is reporting dropped transmits, this value may be set too high 132 * causing the driver to run out of available transmit descriptors. 133 */ 134#define EM_TIDV 64 135 136/* 137 * EM_TADV - Transmit Absolute Interrupt Delay Value 138 * (Not valid for 82542/82543/82544) 139 * Valid Range: 0-65535 (0=off) 140 * Default Value: 64 141 * This value, in units of 1.024 microseconds, limits the delay in which a 142 * transmit interrupt is generated. Useful only if EM_TIDV is non-zero, 143 * this value ensures that an interrupt is generated after the initial 144 * packet is sent on the wire within the set amount of time. Proper tuning, 145 * along with EM_TIDV, may improve traffic throughput in specific 146 * network conditions. 147 */ 148#define EM_TADV 64 149 150/* 151 * EM_RDTR - Receive Interrupt Delay Timer (Packet Timer) 152 * Valid Range: 0-65535 (0=off) 153 * Default Value: 0 154 * This value delays the generation of receive interrupts in units of 1.024 155 * microseconds. Receive interrupt reduction can improve CPU efficiency if 156 * properly tuned for specific network traffic. Increasing this value adds 157 * extra latency to frame reception and can end up decreasing the throughput 158 * of TCP traffic. If the system is reporting dropped receives, this value 159 * may be set too high, causing the driver to run out of available receive 160 * descriptors. 161 * 162 * CAUTION: When setting EM_RDTR to a value other than 0, adapters 163 * may hang (stop transmitting) under certain network conditions. 164 * If this occurs a WATCHDOG message is logged in the system 165 * event log. In addition, the controller is automatically reset, 166 * restoring the network connection. To eliminate the potential 167 * for the hang ensure that EM_RDTR is set to 0. 168 */ 169#define EM_RDTR 0 170 171/* 172 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544) 173 * Valid Range: 0-65535 (0=off) 174 * Default Value: 64 175 * This value, in units of 1.024 microseconds, limits the delay in which a 176 * receive interrupt is generated. Useful only if EM_RDTR is non-zero, 177 * this value ensures that an interrupt is generated after the initial 178 * packet is received within the set amount of time. Proper tuning, 179 * along with EM_RDTR, may improve traffic throughput in specific network 180 * conditions. 181 */ 182#define EM_RADV 64 183 184/* 185 * This parameter controls the duration of transmit watchdog timer. 186 */ 187#define EM_TX_TIMEOUT 5 /* set to 5 seconds */ 188 189/* 190 * This parameter controls the minimum number of available transmit 191 * descriptors needed before we attempt transmission of a packet. 192 */ 193#define EM_TX_OP_THRESHOLD (sc->num_tx_desc / 32) 194 195/* 196 * This parameter controls whether or not autonegotiation is enabled. 197 * 0 - Disable autonegotiation 198 * 1 - Enable autonegotiation 199 */ 200#define DO_AUTO_NEG 1 201 202/* 203 * This parameter control whether or not the driver will wait for 204 * autonegotiation to complete. 205 * 1 - Wait for autonegotiation to complete 206 * 0 - Don't wait for autonegotiation to complete 207 */ 208#define WAIT_FOR_AUTO_NEG_DEFAULT 0 209 210/* 211 * EM_MASTER_SLAVE is only defined to enable a workaround for a known 212 * compatibility issue with 82541/82547 devices and some switches. 213 * See the "Known Limitations" section of the README file for a complete 214 * description and a list of affected switches. 215 * 216 * 0 = Hardware default 217 * 1 = Master mode 218 * 2 = Slave mode 219 * 3 = Auto master/slave 220 */ 221/* #define EM_MASTER_SLAVE 2 */ 222 223/* Tunables -- End */ 224 225#define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 226 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 227 ADVERTISE_1000_FULL) 228 229#define EM_MMBA 0x0010 /* Mem base address */ 230#define EM_FLASH 0x0014 /* Flash memory on ICH8 */ 231#define EM_ROUNDUP(size, unit) (((size) + (unit) - 1) & ~((unit) - 1)) 232 233#define EM_SMARTSPEED_DOWNSHIFT 3 234#define EM_SMARTSPEED_MAX 15 235 236#define MAX_NUM_MULTICAST_ADDRESSES 128 237 238#define PCICFG_DESC_RING_STATUS 0xe4 239#define FLUSH_DESC_REQUIRED 0x100 240 241/* 242 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 243 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will 244 * also optimize cache line size effect. H/W supports up to cache line size 128. 245 */ 246#define EM_DBA_ALIGN 128 247 248#define SPEED_MODE_BIT (1<<21) /* On PCI-E MACs only */ 249 250/* Defines for printing debug information */ 251#define DEBUG_INIT 0 252#define DEBUG_IOCTL 0 253#define DEBUG_HW 0 254 255#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 256#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 257#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 258#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 259#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 260#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 261#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 262#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 263#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 264 265/* Supported RX Buffer Sizes */ 266#define EM_RXBUFFER_2048 2048 267#define EM_RXBUFFER_4096 4096 268#define EM_RXBUFFER_8192 8192 269#define EM_RXBUFFER_16384 16384 270 271#define EM_MCLBYTES (EM_RXBUFFER_2048 + ETHER_ALIGN) 272 273#define EM_MAX_SCATTER 64 274#define EM_TSO_SIZE 65535 275#define EM_TSO_SEG_SIZE 4096 /* Max dma segment size */ 276 277struct em_packet { 278 int pkt_eop; /* Index of the desc to watch */ 279 struct mbuf *pkt_m; 280 bus_dmamap_t pkt_map; /* bus_dma map for packet */ 281}; 282 283/* 284 * Bus dma allocation structure used by 285 * em_dma_malloc and em_dma_free. 286 */ 287struct em_dma_alloc { 288 caddr_t dma_vaddr; 289 bus_dmamap_t dma_map; 290 bus_dma_segment_t dma_seg; 291 bus_size_t dma_size; 292 int dma_nseg; 293}; 294 295typedef enum _XSUM_CONTEXT_T { 296 OFFLOAD_NONE, 297 OFFLOAD_TCP_IP, 298 OFFLOAD_UDP_IP 299} XSUM_CONTEXT_T; 300 301/* For 82544 PCI-X Workaround */ 302typedef struct _ADDRESS_LENGTH_PAIR 303{ 304 u_int64_t address; 305 u_int32_t length; 306} ADDRESS_LENGTH_PAIR, *PADDRESS_LENGTH_PAIR; 307 308typedef struct _DESCRIPTOR_PAIR 309{ 310 ADDRESS_LENGTH_PAIR descriptor[4]; 311 u_int32_t elements; 312} DESC_ARRAY, *PDESC_ARRAY; 313 314/* 315 * Receive definitions 316 * 317 * we have an array of num_rx_desc rx_desc (handled by the 318 * controller), and paired with an array of rx_buffers 319 * (at rx_buffer_area). 320 * The next pair to check on receive is at offset next_rx_desc_to_check 321 */ 322struct em_rx { 323 struct em_dma_alloc sc_rx_dma; /* bus_dma glue for rx desc */ 324 struct em_rx_desc *sc_rx_desc_ring; 325 u_int sc_rx_desc_head; 326 u_int sc_rx_desc_tail; 327 struct em_packet *sc_rx_pkts_ring; 328 329 struct if_rxring sc_rx_ring; 330 331 /* 332 * First/last mbuf pointers, for 333 * collecting multisegment RX packets. 334 */ 335 struct mbuf *fmp; 336 struct mbuf *lmp; 337 338 /* Statistics */ 339 unsigned long dropped_pkts; 340}; 341 342/* 343 * Transmit definitions 344 * 345 * We have an array of num_tx_desc descriptors (handled 346 * by the controller) paired with an array of tx_buffers 347 * (at tx_buffer_area). 348 * The index of the next available descriptor is next_avail_tx_desc. 349 * The number of remaining tx_desc is num_tx_desc_avail. 350 */ 351struct em_tx { 352 struct em_dma_alloc sc_tx_dma; /* bus_dma glue for tx desc */ 353 struct em_tx_desc *sc_tx_desc_ring; 354 u_int sc_tx_desc_head; 355 u_int sc_tx_desc_tail; 356 struct em_packet *sc_tx_pkts_ring; 357 358 u_int32_t sc_txd_cmd; 359 360 XSUM_CONTEXT_T active_checksum_context; 361}; 362 363struct em_softc; 364struct em_queue { 365 struct em_softc *sc; 366 uint32_t me; /* queue index, also msix vector */ 367 uint32_t eims; /* msix only */ 368 void *tag; /* NULL in legacy, check sc_intrhand */ 369 char name[8]; 370 struct em_tx tx; 371 struct em_rx rx; 372 373 struct timeout rx_refill; 374}; 375 376 377#define FOREACH_QUEUE(_sc, _que) \ 378 for ((_que) = (_sc)->queues; \ 379 (_que) < ((_sc)->queues + (_sc)->num_queues); \ 380 (_que)++) 381 382/* Our adapter structure */ 383struct em_softc { 384 struct device sc_dev; 385 struct arpcom sc_ac; 386 387 bus_dma_tag_t sc_dmat; 388 389 struct em_hw hw; 390 391 /* OpenBSD operating-system-specific structures */ 392 struct em_osdep osdep; 393 struct ifmedia media; 394 int io_rid; 395 int legacy_irq; 396 397 void *sc_intrhand; 398 struct timeout em_intr_enable; 399 struct timeout timer_handle; 400 struct timeout tx_fifo_timer_handle; 401 402 /* Info about the board itself */ 403 u_int32_t part_num; 404 u_int8_t link_active; 405 u_int16_t link_speed; 406 u_int16_t link_duplex; 407 u_int32_t smartspeed; 408 u_int32_t tx_int_delay; 409 u_int32_t tx_abs_int_delay; 410 u_int32_t rx_int_delay; 411 u_int32_t rx_abs_int_delay; 412 struct rwlock sfflock; 413 414 u_int sc_tx_slots; 415 u_int sc_rx_slots; 416 u_int32_t sc_rx_buffer_len; 417 418 /* Misc stats maintained by the driver */ 419 unsigned long mbuf_alloc_failed; 420 unsigned long mbuf_cluster_failed; 421 unsigned long no_tx_desc_avail1; 422 unsigned long no_tx_desc_avail2; 423 unsigned long no_tx_map_avail; 424 unsigned long no_tx_dma_setup; 425 unsigned long watchdog_events; 426 unsigned long rx_overruns; 427 428 /* Used in for 82547 10Mb Half workaround */ 429 #define EM_PBA_BYTES_SHIFT 0xA 430 #define EM_TX_HEAD_ADDR_SHIFT 7 431 #define EM_PBA_TX_MASK 0xFFFF0000 432 #define EM_FIFO_HDR 0x10 433 434 #define EM_82547_PKT_THRESH 0x3e0 435 436 /* 437 * These are all 82547 members for the workaround. The chip is pretty 438 * old, single queue, so keep it here to avoid further changes. 439 */ 440 u_int32_t tx_fifo_size; 441 u_int32_t tx_fifo_head; 442 u_int32_t tx_fifo_head_addr; 443 u_int64_t tx_fifo_reset_cnt; 444 u_int64_t tx_fifo_wrk_cnt; 445 u_int32_t tx_head_addr; 446 447 /* For 82544 PCI-X Workaround */ 448 boolean_t pcix_82544; 449 450 int msix; 451 uint32_t msix_linkvec; 452 uint32_t msix_linkmask; 453 uint32_t msix_queuesmask; 454 int num_queues; 455 struct em_queue *queues; 456 457 struct kstat *kstat; 458 struct mutex kstat_mtx; 459}; 460 461#define DEVNAME(_sc) ((_sc)->sc_dev.dv_xname) 462 463#endif /* _EM_H_DEFINED_ */ 464