if_em.h revision 1.55
1/************************************************************************** 2 3Copyright (c) 2001-2003, Intel Corporation 4All rights reserved. 5 6Redistribution and use in source and binary forms, with or without 7modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30POSSIBILITY OF SUCH DAMAGE. 31 32***************************************************************************/ 33 34/* $FreeBSD: if_em.h,v 1.26 2004/09/01 23:22:41 pdeuskar Exp $ */ 35/* $OpenBSD: if_em.h,v 1.55 2015/08/21 09:16:06 kettenis Exp $ */ 36 37#ifndef _EM_H_DEFINED_ 38#define _EM_H_DEFINED_ 39 40#include "bpfilter.h" 41#include "vlan.h" 42 43#include <sys/param.h> 44#include <sys/systm.h> 45#include <sys/sockio.h> 46#include <sys/mbuf.h> 47#include <sys/malloc.h> 48#include <sys/kernel.h> 49#include <sys/device.h> 50#include <sys/socket.h> 51#include <sys/timeout.h> 52 53#include <net/if.h> 54#include <net/if_dl.h> 55#include <net/if_media.h> 56 57#include <netinet/in.h> 58#include <netinet/ip.h> 59#include <netinet/if_ether.h> 60#include <netinet/tcp.h> 61#include <netinet/udp.h> 62 63#if NVLAN > 0 64#include <net/if_types.h> 65#include <net/if_vlan_var.h> 66#endif 67 68#if NBPFILTER > 0 69#include <net/bpf.h> 70#endif 71 72typedef int boolean_t; 73#define TRUE 1 74#define FALSE 0 75 76#include <dev/pci/pcireg.h> 77#include <dev/pci/pcivar.h> 78#include <dev/pci/pcidevs.h> 79 80#include <dev/pci/if_em_hw.h> 81 82/* Tunables */ 83 84/* 85 * EM_TXD: Maximum number of Transmit Descriptors 86 * Valid Range: 80-256 for 82542 and 82543-based adapters 87 * 80-4096 for others 88 * Default Value: 256 89 * This value is the number of transmit descriptors allocated by the driver. 90 * Increasing this value allows the driver to queue more transmits. Each 91 * descriptor is 16 bytes. 92 * Since TDLEN should be multiple of 128bytes, the number of transmit 93 * descriptors should meet the following condition. 94 * (num_tx_desc * sizeof(struct em_tx_desc)) % 128 == 0 95 */ 96#define EM_MAX_TXD_82543 256 97#define EM_MAX_TXD 512 98 99/* 100 * EM_RXD - Maximum number of receive Descriptors 101 * Valid Range: 80-256 for 82542 and 82543-based adapters 102 * 80-4096 for others 103 * Default Value: 256 104 * This value is the number of receive descriptors allocated by the driver. 105 * Increasing this value allows the driver to buffer more incoming packets. 106 * Each descriptor is 16 bytes. A receive buffer is also allocated for each 107 * descriptor. The maximum MTU size is 16110. 108 * Since TDLEN should be multiple of 128bytes, the number of transmit 109 * descriptors should meet the following condition. 110 * (num_tx_desc * sizeof(struct em_tx_desc)) % 128 == 0 111 */ 112#define EM_MAX_RXD_82543 256 113#define EM_MAX_RXD 256 114 115/* 116 * MAX_INTS_PER_SEC (ITR - Interrupt Throttle Register) 117 * The Interrupt Throttle Register (ITR) limits the delivery of interrupts 118 * to a reasonable rate by providing a guaranteed inter-interrupt delay 119 * between interrupts asserted by the Ethernet controller. 120 */ 121#define MAX_INTS_PER_SEC 8000 122#define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256) 123 124/* 125 * EM_TIDV - Transmit Interrupt Delay Value 126 * Valid Range: 0-65535 (0=off) 127 * Default Value: 64 128 * This value delays the generation of transmit interrupts in units of 129 * 1.024 microseconds. Transmit interrupt reduction can improve CPU 130 * efficiency if properly tuned for specific network traffic. If the 131 * system is reporting dropped transmits, this value may be set too high 132 * causing the driver to run out of available transmit descriptors. 133 */ 134#define EM_TIDV 64 135 136/* 137 * EM_TADV - Transmit Absolute Interrupt Delay Value 138 * (Not valid for 82542/82543/82544) 139 * Valid Range: 0-65535 (0=off) 140 * Default Value: 64 141 * This value, in units of 1.024 microseconds, limits the delay in which a 142 * transmit interrupt is generated. Useful only if EM_TIDV is non-zero, 143 * this value ensures that an interrupt is generated after the initial 144 * packet is sent on the wire within the set amount of time. Proper tuning, 145 * along with EM_TIDV, may improve traffic throughput in specific 146 * network conditions. 147 */ 148#define EM_TADV 64 149 150/* 151 * EM_RDTR - Receive Interrupt Delay Timer (Packet Timer) 152 * Valid Range: 0-65535 (0=off) 153 * Default Value: 0 154 * This value delays the generation of receive interrupts in units of 1.024 155 * microseconds. Receive interrupt reduction can improve CPU efficiency if 156 * properly tuned for specific network traffic. Increasing this value adds 157 * extra latency to frame reception and can end up decreasing the throughput 158 * of TCP traffic. If the system is reporting dropped receives, this value 159 * may be set too high, causing the driver to run out of available receive 160 * descriptors. 161 * 162 * CAUTION: When setting EM_RDTR to a value other than 0, adapters 163 * may hang (stop transmitting) under certain network conditions. 164 * If this occurs a WATCHDOG message is logged in the system 165 * event log. In addition, the controller is automatically reset, 166 * restoring the network connection. To eliminate the potential 167 * for the hang ensure that EM_RDTR is set to 0. 168 */ 169#define EM_RDTR 0 170 171/* 172 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544) 173 * Valid Range: 0-65535 (0=off) 174 * Default Value: 64 175 * This value, in units of 1.024 microseconds, limits the delay in which a 176 * receive interrupt is generated. Useful only if EM_RDTR is non-zero, 177 * this value ensures that an interrupt is generated after the initial 178 * packet is received within the set amount of time. Proper tuning, 179 * along with EM_RDTR, may improve traffic throughput in specific network 180 * conditions. 181 */ 182#define EM_RADV 64 183 184/* 185 * This parameter controls the duration of transmit watchdog timer. 186 */ 187#define EM_TX_TIMEOUT 5 /* set to 5 seconds */ 188 189/* 190 * These parameters control when the driver calls the routine to reclaim 191 * transmit descriptors. 192 */ 193#define EM_TX_CLEANUP_THRESHOLD (sc->num_tx_desc / 8) 194#define EM_TX_OP_THRESHOLD (sc->num_tx_desc / 32) 195 196/* 197 * This parameter controls whether or not autonegotiation is enabled. 198 * 0 - Disable autonegotiation 199 * 1 - Enable autonegotiation 200 */ 201#define DO_AUTO_NEG 1 202 203/* 204 * This parameter control whether or not the driver will wait for 205 * autonegotiation to complete. 206 * 1 - Wait for autonegotiation to complete 207 * 0 - Don't wait for autonegotiation to complete 208 */ 209#define WAIT_FOR_AUTO_NEG_DEFAULT 0 210 211/* 212 * EM_MASTER_SLAVE is only defined to enable a workaround for a known 213 * compatibility issue with 82541/82547 devices and some switches. 214 * See the "Known Limitations" section of the README file for a complete 215 * description and a list of affected switches. 216 * 217 * 0 = Hardware default 218 * 1 = Master mode 219 * 2 = Slave mode 220 * 3 = Auto master/slave 221 */ 222/* #define EM_MASTER_SLAVE 2 */ 223 224/* Tunables -- End */ 225 226#define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 227 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 228 ADVERTISE_1000_FULL) 229 230#define EM_MMBA 0x0010 /* Mem base address */ 231#define EM_FLASH 0x0014 /* Flash memory on ICH8 */ 232#define EM_ROUNDUP(size, unit) (((size) + (unit) - 1) & ~((unit) - 1)) 233 234#define EM_SMARTSPEED_DOWNSHIFT 3 235#define EM_SMARTSPEED_MAX 15 236 237#define MAX_NUM_MULTICAST_ADDRESSES 128 238 239/* 240 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 241 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will 242 * also optimize cache line size effect. H/W supports up to cache line size 128. 243 */ 244#define EM_DBA_ALIGN 128 245 246#define SPEED_MODE_BIT (1<<21) /* On PCI-E MACs only */ 247 248/* Defines for printing debug information */ 249#define DEBUG_INIT 0 250#define DEBUG_IOCTL 0 251#define DEBUG_HW 0 252 253#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 254#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 255#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 256#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 257#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 258#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 259#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 260#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 261#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 262 263/* Supported RX Buffer Sizes */ 264#define EM_RXBUFFER_2048 2048 265#define EM_RXBUFFER_4096 4096 266#define EM_RXBUFFER_8192 8192 267#define EM_RXBUFFER_16384 16384 268 269#define EM_MAX_SCATTER 64 270#define EM_TSO_SIZE 65535 271 272struct em_buffer { 273 int next_eop; /* Index of the desc to watch */ 274 struct mbuf *m_head; 275 bus_dmamap_t map; /* bus_dma map for packet */ 276}; 277 278/* 279 * Bus dma allocation structure used by 280 * em_dma_malloc and em_dma_free. 281 */ 282struct em_dma_alloc { 283 bus_addr_t dma_paddr; 284 caddr_t dma_vaddr; 285 bus_dma_tag_t dma_tag; 286 bus_dmamap_t dma_map; 287 bus_dma_segment_t dma_seg; 288 bus_size_t dma_size; 289 int dma_nseg; 290}; 291 292typedef enum _XSUM_CONTEXT_T { 293 OFFLOAD_NONE, 294 OFFLOAD_TCP_IP, 295 OFFLOAD_UDP_IP 296} XSUM_CONTEXT_T; 297 298/* For 82544 PCI-X Workaround */ 299typedef struct _ADDRESS_LENGTH_PAIR 300{ 301 u_int64_t address; 302 u_int32_t length; 303} ADDRESS_LENGTH_PAIR, *PADDRESS_LENGTH_PAIR; 304 305typedef struct _DESCRIPTOR_PAIR 306{ 307 ADDRESS_LENGTH_PAIR descriptor[4]; 308 u_int32_t elements; 309} DESC_ARRAY, *PDESC_ARRAY; 310 311/* Our adapter structure */ 312struct em_softc { 313 struct device sc_dv; 314 struct arpcom interface_data; 315 struct em_hw hw; 316 317 /* OpenBSD operating-system-specific structures */ 318 struct em_osdep osdep; 319 struct ifmedia media; 320 int io_rid; 321 322 void *sc_intrhand; 323 struct timeout em_intr_enable; 324 struct timeout timer_handle; 325 struct timeout tx_fifo_timer_handle; 326 327#ifdef __STRICT_ALIGNMENT 328 /* Used for carrying forward alignment adjustments */ 329 unsigned char align_buf[ETHER_ALIGN]; /* tail of unaligned packet */ 330 u_int8_t align_buf_len; /* bytes in tail */ 331#endif /* __STRICT_ALIGNMENT */ 332 333 /* Info about the board itself */ 334 u_int32_t part_num; 335 u_int8_t link_active; 336 u_int16_t link_speed; 337 u_int16_t link_duplex; 338 u_int32_t smartspeed; 339 u_int32_t tx_int_delay; 340 u_int32_t tx_abs_int_delay; 341 u_int32_t rx_int_delay; 342 u_int32_t rx_abs_int_delay; 343 344 XSUM_CONTEXT_T active_checksum_context; 345 346 /* 347 * Transmit definitions 348 * 349 * We have an array of num_tx_desc descriptors (handled 350 * by the controller) paired with an array of tx_buffers 351 * (at tx_buffer_area). 352 * The index of the next available descriptor is next_avail_tx_desc. 353 * The number of remaining tx_desc is num_tx_desc_avail. 354 */ 355 struct em_dma_alloc txdma; /* bus_dma glue for tx desc */ 356 struct em_tx_desc *tx_desc_base; 357 u_int32_t next_avail_tx_desc; 358 u_int32_t next_tx_to_clean; 359 volatile u_int16_t num_tx_desc_avail; 360 u_int16_t num_tx_desc; 361 u_int32_t txd_cmd; 362 struct em_buffer *tx_buffer_area; 363 bus_dma_tag_t txtag; /* dma tag for tx */ 364 365 /* 366 * Receive definitions 367 * 368 * we have an array of num_rx_desc rx_desc (handled by the 369 * controller), and paired with an array of rx_buffers 370 * (at rx_buffer_area). 371 * The next pair to check on receive is at offset next_rx_desc_to_check 372 */ 373 struct em_dma_alloc rxdma; /* bus_dma glue for rx desc */ 374 struct em_rx_desc *rx_desc_base; 375 struct if_rxring rx_ring; 376 struct mutex rx_mtx; 377 u_int32_t next_rx_desc_to_check; 378 u_int32_t last_rx_desc_filled; 379 u_int32_t rx_buffer_len; 380 u_int16_t num_rx_desc; 381 struct em_buffer *rx_buffer_area; 382 bus_dma_tag_t rxtag; 383 384 /* 385 * First/last mbuf pointers, for 386 * collecting multisegment RX packets. 387 */ 388 struct mbuf *fmp; 389 struct mbuf *lmp; 390 391 /* Misc stats maintained by the driver */ 392 unsigned long dropped_pkts; 393 unsigned long mbuf_alloc_failed; 394 unsigned long mbuf_cluster_failed; 395 unsigned long no_tx_desc_avail1; 396 unsigned long no_tx_desc_avail2; 397 unsigned long no_tx_map_avail; 398 unsigned long no_tx_dma_setup; 399 unsigned long watchdog_events; 400 unsigned long rx_overruns; 401 402 /* Used in for 82547 10Mb Half workaround */ 403 #define EM_PBA_BYTES_SHIFT 0xA 404 #define EM_TX_HEAD_ADDR_SHIFT 7 405 #define EM_PBA_TX_MASK 0xFFFF0000 406 #define EM_FIFO_HDR 0x10 407 408 #define EM_82547_PKT_THRESH 0x3e0 409 410 u_int32_t tx_fifo_size; 411 u_int32_t tx_fifo_head; 412 u_int32_t tx_fifo_head_addr; 413 u_int64_t tx_fifo_reset_cnt; 414 u_int64_t tx_fifo_wrk_cnt; 415 u_int32_t tx_head_addr; 416 417 /* For 82544 PCI-X Workaround */ 418 boolean_t pcix_82544; 419 struct em_hw_stats stats; 420}; 421 422#endif /* _EM_H_DEFINED_ */ 423