if_em.h revision 1.53
1/************************************************************************** 2 3Copyright (c) 2001-2003, Intel Corporation 4All rights reserved. 5 6Redistribution and use in source and binary forms, with or without 7modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30POSSIBILITY OF SUCH DAMAGE. 31 32***************************************************************************/ 33 34/* $FreeBSD: if_em.h,v 1.26 2004/09/01 23:22:41 pdeuskar Exp $ */ 35/* $OpenBSD: if_em.h,v 1.53 2014/07/22 13:12:11 mpi Exp $ */ 36 37#ifndef _EM_H_DEFINED_ 38#define _EM_H_DEFINED_ 39 40#include "bpfilter.h" 41#include "vlan.h" 42 43#include <sys/param.h> 44#include <sys/systm.h> 45#include <sys/sockio.h> 46#include <sys/mbuf.h> 47#include <sys/malloc.h> 48#include <sys/kernel.h> 49#include <sys/device.h> 50#include <sys/socket.h> 51#include <sys/timeout.h> 52 53#include <net/if.h> 54#include <net/if_dl.h> 55#include <net/if_media.h> 56 57#ifdef INET 58#include <netinet/in.h> 59#include <netinet/ip.h> 60#include <netinet/if_ether.h> 61#include <netinet/tcp.h> 62#include <netinet/udp.h> 63#endif 64 65#if NVLAN > 0 66#include <net/if_types.h> 67#include <net/if_vlan_var.h> 68#endif 69 70#if NBPFILTER > 0 71#include <net/bpf.h> 72#endif 73 74typedef int boolean_t; 75#define TRUE 1 76#define FALSE 0 77 78#include <dev/pci/pcireg.h> 79#include <dev/pci/pcivar.h> 80#include <dev/pci/pcidevs.h> 81 82#include <dev/pci/if_em_hw.h> 83 84/* Tunables */ 85 86/* 87 * EM_TXD: Maximum number of Transmit Descriptors 88 * Valid Range: 80-256 for 82542 and 82543-based adapters 89 * 80-4096 for others 90 * Default Value: 256 91 * This value is the number of transmit descriptors allocated by the driver. 92 * Increasing this value allows the driver to queue more transmits. Each 93 * descriptor is 16 bytes. 94 * Since TDLEN should be multiple of 128bytes, the number of transmit 95 * descriptors should meet the following condition. 96 * (num_tx_desc * sizeof(struct em_tx_desc)) % 128 == 0 97 */ 98#define EM_MAX_TXD_82543 256 99#define EM_MAX_TXD 512 100 101/* 102 * EM_RXD - Maximum number of receive Descriptors 103 * Valid Range: 80-256 for 82542 and 82543-based adapters 104 * 80-4096 for others 105 * Default Value: 256 106 * This value is the number of receive descriptors allocated by the driver. 107 * Increasing this value allows the driver to buffer more incoming packets. 108 * Each descriptor is 16 bytes. A receive buffer is also allocated for each 109 * descriptor. The maximum MTU size is 16110. 110 * Since TDLEN should be multiple of 128bytes, the number of transmit 111 * descriptors should meet the following condition. 112 * (num_tx_desc * sizeof(struct em_tx_desc)) % 128 == 0 113 */ 114#define EM_MAX_RXD_82543 256 115#define EM_MAX_RXD 256 116 117/* 118 * MAX_INTS_PER_SEC (ITR - Interrupt Throttle Register) 119 * The Interrupt Throttle Register (ITR) limits the delivery of interrupts 120 * to a reasonable rate by providing a guaranteed inter-interrupt delay 121 * between interrupts asserted by the Ethernet controller. 122 */ 123#define MAX_INTS_PER_SEC 8000 124#define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256) 125 126/* 127 * EM_TIDV - Transmit Interrupt Delay Value 128 * Valid Range: 0-65535 (0=off) 129 * Default Value: 64 130 * This value delays the generation of transmit interrupts in units of 131 * 1.024 microseconds. Transmit interrupt reduction can improve CPU 132 * efficiency if properly tuned for specific network traffic. If the 133 * system is reporting dropped transmits, this value may be set too high 134 * causing the driver to run out of available transmit descriptors. 135 */ 136#define EM_TIDV 64 137 138/* 139 * EM_TADV - Transmit Absolute Interrupt Delay Value 140 * (Not valid for 82542/82543/82544) 141 * Valid Range: 0-65535 (0=off) 142 * Default Value: 64 143 * This value, in units of 1.024 microseconds, limits the delay in which a 144 * transmit interrupt is generated. Useful only if EM_TIDV is non-zero, 145 * this value ensures that an interrupt is generated after the initial 146 * packet is sent on the wire within the set amount of time. Proper tuning, 147 * along with EM_TIDV, may improve traffic throughput in specific 148 * network conditions. 149 */ 150#define EM_TADV 64 151 152/* 153 * EM_RDTR - Receive Interrupt Delay Timer (Packet Timer) 154 * Valid Range: 0-65535 (0=off) 155 * Default Value: 0 156 * This value delays the generation of receive interrupts in units of 1.024 157 * microseconds. Receive interrupt reduction can improve CPU efficiency if 158 * properly tuned for specific network traffic. Increasing this value adds 159 * extra latency to frame reception and can end up decreasing the throughput 160 * of TCP traffic. If the system is reporting dropped receives, this value 161 * may be set too high, causing the driver to run out of available receive 162 * descriptors. 163 * 164 * CAUTION: When setting EM_RDTR to a value other than 0, adapters 165 * may hang (stop transmitting) under certain network conditions. 166 * If this occurs a WATCHDOG message is logged in the system 167 * event log. In addition, the controller is automatically reset, 168 * restoring the network connection. To eliminate the potential 169 * for the hang ensure that EM_RDTR is set to 0. 170 */ 171#define EM_RDTR 0 172 173/* 174 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544) 175 * Valid Range: 0-65535 (0=off) 176 * Default Value: 64 177 * This value, in units of 1.024 microseconds, limits the delay in which a 178 * receive interrupt is generated. Useful only if EM_RDTR is non-zero, 179 * this value ensures that an interrupt is generated after the initial 180 * packet is received within the set amount of time. Proper tuning, 181 * along with EM_RDTR, may improve traffic throughput in specific network 182 * conditions. 183 */ 184#define EM_RADV 64 185 186/* 187 * This parameter controls the duration of transmit watchdog timer. 188 */ 189#define EM_TX_TIMEOUT 5 /* set to 5 seconds */ 190 191/* 192 * These parameters control when the driver calls the routine to reclaim 193 * transmit descriptors. 194 */ 195#define EM_TX_CLEANUP_THRESHOLD (sc->num_tx_desc / 8) 196#define EM_TX_OP_THRESHOLD (sc->num_tx_desc / 32) 197 198/* 199 * This parameter controls whether or not autonegotiation is enabled. 200 * 0 - Disable autonegotiation 201 * 1 - Enable autonegotiation 202 */ 203#define DO_AUTO_NEG 1 204 205/* 206 * This parameter control whether or not the driver will wait for 207 * autonegotiation to complete. 208 * 1 - Wait for autonegotiation to complete 209 * 0 - Don't wait for autonegotiation to complete 210 */ 211#define WAIT_FOR_AUTO_NEG_DEFAULT 0 212 213/* 214 * EM_MASTER_SLAVE is only defined to enable a workaround for a known 215 * compatibility issue with 82541/82547 devices and some switches. 216 * See the "Known Limitations" section of the README file for a complete 217 * description and a list of affected switches. 218 * 219 * 0 = Hardware default 220 * 1 = Master mode 221 * 2 = Slave mode 222 * 3 = Auto master/slave 223 */ 224/* #define EM_MASTER_SLAVE 2 */ 225 226/* Tunables -- End */ 227 228#define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 229 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 230 ADVERTISE_1000_FULL) 231 232#define EM_MMBA 0x0010 /* Mem base address */ 233#define EM_FLASH 0x0014 /* Flash memory on ICH8 */ 234#define EM_ROUNDUP(size, unit) (((size) + (unit) - 1) & ~((unit) - 1)) 235 236#define EM_SMARTSPEED_DOWNSHIFT 3 237#define EM_SMARTSPEED_MAX 15 238 239#define MAX_NUM_MULTICAST_ADDRESSES 128 240 241/* 242 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 243 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will 244 * also optimize cache line size effect. H/W supports up to cache line size 128. 245 */ 246#define EM_DBA_ALIGN 128 247 248#define SPEED_MODE_BIT (1<<21) /* On PCI-E MACs only */ 249 250/* Defines for printing debug information */ 251#define DEBUG_INIT 0 252#define DEBUG_IOCTL 0 253#define DEBUG_HW 0 254 255#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 256#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 257#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 258#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 259#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 260#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 261#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 262#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 263#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 264 265/* Supported RX Buffer Sizes */ 266#define EM_RXBUFFER_2048 2048 267#define EM_RXBUFFER_4096 4096 268#define EM_RXBUFFER_8192 8192 269#define EM_RXBUFFER_16384 16384 270 271#define EM_MAX_SCATTER 64 272#define EM_TSO_SIZE 65535 273 274struct em_buffer { 275 int next_eop; /* Index of the desc to watch */ 276 struct mbuf *m_head; 277 bus_dmamap_t map; /* bus_dma map for packet */ 278}; 279 280/* 281 * Bus dma allocation structure used by 282 * em_dma_malloc and em_dma_free. 283 */ 284struct em_dma_alloc { 285 bus_addr_t dma_paddr; 286 caddr_t dma_vaddr; 287 bus_dma_tag_t dma_tag; 288 bus_dmamap_t dma_map; 289 bus_dma_segment_t dma_seg; 290 bus_size_t dma_size; 291 int dma_nseg; 292}; 293 294typedef enum _XSUM_CONTEXT_T { 295 OFFLOAD_NONE, 296 OFFLOAD_TCP_IP, 297 OFFLOAD_UDP_IP 298} XSUM_CONTEXT_T; 299 300/* For 82544 PCI-X Workaround */ 301typedef struct _ADDRESS_LENGTH_PAIR 302{ 303 u_int64_t address; 304 u_int32_t length; 305} ADDRESS_LENGTH_PAIR, *PADDRESS_LENGTH_PAIR; 306 307typedef struct _DESCRIPTOR_PAIR 308{ 309 ADDRESS_LENGTH_PAIR descriptor[4]; 310 u_int32_t elements; 311} DESC_ARRAY, *PDESC_ARRAY; 312 313/* Our adapter structure */ 314struct em_softc { 315 struct device sc_dv; 316 struct arpcom interface_data; 317 struct em_hw hw; 318 319 /* OpenBSD operating-system-specific structures */ 320 struct em_osdep osdep; 321 struct ifmedia media; 322 int io_rid; 323 324 void *sc_intrhand; 325 struct timeout em_intr_enable; 326 struct timeout timer_handle; 327 struct timeout tx_fifo_timer_handle; 328 329#ifdef __STRICT_ALIGNMENT 330 /* Used for carrying forward alignment adjustments */ 331 unsigned char align_buf[ETHER_ALIGN]; /* tail of unaligned packet */ 332 u_int8_t align_buf_len; /* bytes in tail */ 333#endif /* __STRICT_ALIGNMENT */ 334 335 /* Info about the board itself */ 336 u_int32_t part_num; 337 u_int8_t link_active; 338 u_int16_t link_speed; 339 u_int16_t link_duplex; 340 u_int32_t smartspeed; 341 u_int32_t tx_int_delay; 342 u_int32_t tx_abs_int_delay; 343 u_int32_t rx_int_delay; 344 u_int32_t rx_abs_int_delay; 345 346 XSUM_CONTEXT_T active_checksum_context; 347 348 /* 349 * Transmit definitions 350 * 351 * We have an array of num_tx_desc descriptors (handled 352 * by the controller) paired with an array of tx_buffers 353 * (at tx_buffer_area). 354 * The index of the next available descriptor is next_avail_tx_desc. 355 * The number of remaining tx_desc is num_tx_desc_avail. 356 */ 357 struct em_dma_alloc txdma; /* bus_dma glue for tx desc */ 358 struct em_tx_desc *tx_desc_base; 359 u_int32_t next_avail_tx_desc; 360 u_int32_t next_tx_to_clean; 361 volatile u_int16_t num_tx_desc_avail; 362 u_int16_t num_tx_desc; 363 u_int32_t txd_cmd; 364 struct em_buffer *tx_buffer_area; 365 bus_dma_tag_t txtag; /* dma tag for tx */ 366 367 /* 368 * Receive definitions 369 * 370 * we have an array of num_rx_desc rx_desc (handled by the 371 * controller), and paired with an array of rx_buffers 372 * (at rx_buffer_area). 373 * The next pair to check on receive is at offset next_rx_desc_to_check 374 */ 375 struct em_dma_alloc rxdma; /* bus_dma glue for rx desc */ 376 struct em_rx_desc *rx_desc_base; 377 struct if_rxring rx_ring; 378 u_int32_t next_rx_desc_to_check; 379 u_int32_t last_rx_desc_filled; 380 u_int32_t rx_buffer_len; 381 u_int16_t num_rx_desc; 382 struct em_buffer *rx_buffer_area; 383 bus_dma_tag_t rxtag; 384 385 /* 386 * First/last mbuf pointers, for 387 * collecting multisegment RX packets. 388 */ 389 struct mbuf *fmp; 390 struct mbuf *lmp; 391 392 /* Misc stats maintained by the driver */ 393 unsigned long dropped_pkts; 394 unsigned long mbuf_alloc_failed; 395 unsigned long mbuf_cluster_failed; 396 unsigned long no_tx_desc_avail1; 397 unsigned long no_tx_desc_avail2; 398 unsigned long no_tx_map_avail; 399 unsigned long no_tx_dma_setup; 400 unsigned long watchdog_events; 401 unsigned long rx_overruns; 402 403 /* Used in for 82547 10Mb Half workaround */ 404 #define EM_PBA_BYTES_SHIFT 0xA 405 #define EM_TX_HEAD_ADDR_SHIFT 7 406 #define EM_PBA_TX_MASK 0xFFFF0000 407 #define EM_FIFO_HDR 0x10 408 409 #define EM_82547_PKT_THRESH 0x3e0 410 411 u_int32_t tx_fifo_size; 412 u_int32_t tx_fifo_head; 413 u_int32_t tx_fifo_head_addr; 414 u_int64_t tx_fifo_reset_cnt; 415 u_int64_t tx_fifo_wrk_cnt; 416 u_int32_t tx_head_addr; 417 418 /* For 82544 PCI-X Workaround */ 419 boolean_t pcix_82544; 420 struct em_hw_stats stats; 421}; 422 423#endif /* _EM_H_DEFINED_ */ 424