if_em.h revision 1.31
1/************************************************************************** 2 3Copyright (c) 2001-2003, Intel Corporation 4All rights reserved. 5 6Redistribution and use in source and binary forms, with or without 7modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30POSSIBILITY OF SUCH DAMAGE. 31 32***************************************************************************/ 33 34/* $FreeBSD: if_em.h,v 1.26 2004/09/01 23:22:41 pdeuskar Exp $ */ 35/* $OpenBSD: if_em.h,v 1.31 2006/11/10 21:15:56 brad Exp $ */ 36 37#ifndef _EM_H_DEFINED_ 38#define _EM_H_DEFINED_ 39 40#include "bpfilter.h" 41#include "vlan.h" 42 43#include <sys/param.h> 44#include <sys/systm.h> 45#include <sys/sockio.h> 46#include <sys/mbuf.h> 47#include <sys/malloc.h> 48#include <sys/kernel.h> 49#include <sys/device.h> 50#include <sys/socket.h> 51 52#include <net/if.h> 53#include <net/if_dl.h> 54#include <net/if_media.h> 55 56#ifdef INET 57#include <netinet/in.h> 58#include <netinet/in_systm.h> 59#include <netinet/in_var.h> 60#include <netinet/ip.h> 61#include <netinet/if_ether.h> 62#include <netinet/tcp.h> 63#include <netinet/udp.h> 64#endif 65 66#if NVLAN > 0 67#include <net/if_types.h> 68#include <net/if_vlan_var.h> 69#endif 70 71#if NBPFILTER > 0 72#include <net/bpf.h> 73#endif 74 75#include <uvm/uvm_extern.h> 76 77#include <dev/pci/pcireg.h> 78#include <dev/pci/pcivar.h> 79#include <dev/pci/pcidevs.h> 80 81#include <dev/pci/if_em_hw.h> 82 83/* Tunables */ 84 85/* 86 * EM_TXD: Maximum number of Transmit Descriptors 87 * Valid Range: 80-256 for 82542 and 82543-based adapters 88 * 80-4096 for others 89 * Default Value: 256 90 * This value is the number of transmit descriptors allocated by the driver. 91 * Increasing this value allows the driver to queue more transmits. Each 92 * descriptor is 16 bytes. 93 * Since TDLEN should be multiple of 128bytes, the number of transmit 94 * desscriptors should meet the following condition. 95 * (num_tx_desc * sizeof(struct em_tx_desc)) % 128 == 0 96 */ 97#define EM_MIN_TXD 12 98#define EM_MAX_TXD_82543 256 99#define EM_MAX_TXD 512 100 101/* 102 * EM_RXD - Maximum number of receive Descriptors 103 * Valid Range: 80-256 for 82542 and 82543-based adapters 104 * 80-4096 for others 105 * Default Value: 256 106 * This value is the number of receive descriptors allocated by the driver. 107 * Increasing this value allows the driver to buffer more incoming packets. 108 * Each descriptor is 16 bytes. A receive buffer is also allocated for each 109 * descriptor. The maximum MTU size is 16110. 110 * Since TDLEN should be multiple of 128bytes, the number of transmit 111 * desscriptors should meet the following condition. 112 * (num_tx_desc * sizeof(struct em_tx_desc)) % 128 == 0 113 */ 114#define EM_MIN_RXD 12 115#define EM_MAX_RXD 256 116 117/* 118 * EM_TIDV - Transmit Interrupt Delay Value 119 * Valid Range: 0-65535 (0=off) 120 * Default Value: 64 121 * This value delays the generation of transmit interrupts in units of 122 * 1.024 microseconds. Transmit interrupt reduction can improve CPU 123 * efficiency if properly tuned for specific network traffic. If the 124 * system is reporting dropped transmits, this value may be set too high 125 * causing the driver to run out of available transmit descriptors. 126 */ 127#define EM_TIDV 64 128 129/* 130 * EM_TADV - Transmit Absolute Interrupt Delay Value 131 * (Not valid for 82542/82543/82544) 132 * Valid Range: 0-65535 (0=off) 133 * Default Value: 64 134 * This value, in units of 1.024 microseconds, limits the delay in which a 135 * transmit interrupt is generated. Useful only if EM_TIDV is non-zero, 136 * this value ensures that an interrupt is generated after the initial 137 * packet is sent on the wire within the set amount of time. Proper tuning, 138 * along with EM_TIDV, may improve traffic throughput in specific 139 * network conditions. 140 */ 141#define EM_TADV 64 142 143/* 144 * EM_RDTR - Receive Interrupt Delay Timer (Packet Timer) 145 * Valid Range: 0-65535 (0=off) 146 * Default Value: 0 147 * This value delays the generation of receive interrupts in units of 1.024 148 * microseconds. Receive interrupt reduction can improve CPU efficiency if 149 * properly tuned for specific network traffic. Increasing this value adds 150 * extra latency to frame reception and can end up decreasing the throughput 151 * of TCP traffic. If the system is reporting dropped receives, this value 152 * may be set too high, causing the driver to run out of available receive 153 * descriptors. 154 * 155 * CAUTION: When setting EM_RDTR to a value other than 0, adapters 156 * may hang (stop transmitting) under certain network conditions. 157 * If this occurs a WATCHDOG message is logged in the system 158 * event log. In addition, the controller is automatically reset, 159 * restoring the network connection. To eliminate the potential 160 * for the hang ensure that EM_RDTR is set to 0. 161 */ 162#define EM_RDTR 0 163 164/* 165 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544) 166 * Valid Range: 0-65535 (0=off) 167 * Default Value: 64 168 * This value, in units of 1.024 microseconds, limits the delay in which a 169 * receive interrupt is generated. Useful only if EM_RDTR is non-zero, 170 * this value ensures that an interrupt is generated after the initial 171 * packet is received within the set amount of time. Proper tuning, 172 * along with EM_RDTR, may improve traffic throughput in specific network 173 * conditions. 174 */ 175#define EM_RADV 64 176 177/* 178 * This parameter controls the duration of transmit watchdog timer. 179 */ 180#define EM_TX_TIMEOUT 5 /* set to 5 seconds */ 181 182/* 183 * This parameter controls when the driver calls the routine to reclaim 184 * transmit descriptors. 185 */ 186#define EM_TX_CLEANUP_THRESHOLD (sc->num_tx_desc / 8) 187 188/* 189 * This parameter controls whether or not autonegotation is enabled. 190 * 0 - Disable autonegotiation 191 * 1 - Enable autonegotiation 192 */ 193#define DO_AUTO_NEG 1 194 195/* 196 * This parameter control whether or not the driver will wait for 197 * autonegotiation to complete. 198 * 1 - Wait for autonegotiation to complete 199 * 0 - Don't wait for autonegotiation to complete 200 */ 201#define WAIT_FOR_AUTO_NEG_DEFAULT 0 202 203/* 204 * EM_MASTER_SLAVE is only defined to enable a workaround for a known 205 * compatibility issue with 82541/82547 devices and some switches. 206 * See the "Known Limitations" section of the README file for a complete 207 * description and a list of affected switches. 208 * 209 * 0 = Hardware default 210 * 1 = Master mode 211 * 2 = Slave mode 212 * 3 = Auto master/slave 213 */ 214/* #define EM_MASTER_SLAVE 2 */ 215 216/* Tunables -- End */ 217 218#define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 219 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 220 ADVERTISE_1000_FULL) 221 222#define EM_MMBA 0x0010 /* Mem base address */ 223#define EM_FLASH 0x0014 /* Flash memory on ICH8 */ 224#define EM_ROUNDUP(size, unit) (((size) + (unit) - 1) & ~((unit) - 1)) 225 226#define EM_SMARTSPEED_DOWNSHIFT 3 227#define EM_SMARTSPEED_MAX 15 228 229#define MAX_NUM_MULTICAST_ADDRESSES 128 230 231/* 232 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 233 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will 234 * also optimize cache line size effect. H/W supports up to cache line size 128. 235 */ 236#define EM_DBA_ALIGN 128 237 238#define SPEED_MODE_BIT (1<<21) /* On PCI-E MACs only */ 239 240/* Defines for printing debug information */ 241#define DEBUG_INIT 0 242#define DEBUG_IOCTL 0 243#define DEBUG_HW 0 244 245#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 246#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 247#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 248#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 249#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 250#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 251#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 252#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 253#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 254 255/* Supported RX Buffer Sizes */ 256#define EM_RXBUFFER_2048 2048 257#define EM_RXBUFFER_4096 4096 258#define EM_RXBUFFER_8192 8192 259#define EM_RXBUFFER_16384 16384 260 261#define EM_MAX_SCATTER 64 262#define EM_TSO_SIZE 65535 263 264struct em_buffer { 265 struct mbuf *m_head; 266 bus_dmamap_t map; /* bus_dma map for packet */ 267}; 268 269/* 270 * Bus dma allocation structure used by 271 * em_dma_malloc and em_dma_free. 272 */ 273struct em_dma_alloc { 274 bus_addr_t dma_paddr; 275 caddr_t dma_vaddr; 276 bus_dma_tag_t dma_tag; 277 bus_dmamap_t dma_map; 278 bus_dma_segment_t dma_seg; 279 bus_size_t dma_size; 280 int dma_nseg; 281}; 282 283typedef enum _XSUM_CONTEXT_T { 284 OFFLOAD_NONE, 285 OFFLOAD_TCP_IP, 286 OFFLOAD_UDP_IP 287} XSUM_CONTEXT_T; 288 289/* For 82544 PCI-X Workaround */ 290typedef struct _ADDRESS_LENGTH_PAIR 291{ 292 u_int64_t address; 293 u_int32_t length; 294} ADDRESS_LENGTH_PAIR, *PADDRESS_LENGTH_PAIR; 295 296typedef struct _DESCRIPTOR_PAIR 297{ 298 ADDRESS_LENGTH_PAIR descriptor[4]; 299 u_int32_t elements; 300} DESC_ARRAY, *PDESC_ARRAY; 301 302/* Our adapter structure */ 303struct em_softc { 304 struct device sc_dv; 305 struct arpcom interface_data; 306 struct em_hw hw; 307 308 /* OpenBSD operating-system-specific structures */ 309 struct em_osdep osdep; 310 struct ifmedia media; 311 int io_rid; 312 313 void *sc_intrhand; 314 struct timeout em_intr_enable; 315 struct timeout timer_handle; 316 struct timeout tx_fifo_timer_handle; 317 int if_flags; 318 void *sc_powerhook; 319 void *sc_shutdownhook; 320 321#ifdef __STRICT_ALIGNMENT 322 /* Used for carrying forward alignment adjustments */ 323 unsigned char align_buf[ETHER_ALIGN]; /* tail of unaligned packet */ 324 u_int8_t align_buf_len; /* bytes in tail */ 325#endif /* __STRICT_ALIGNMENT */ 326 327 /* Info about the board itself */ 328 u_int32_t part_num; 329 u_int8_t link_active; 330 u_int16_t link_speed; 331 u_int16_t link_duplex; 332 u_int32_t smartspeed; 333 u_int32_t tx_int_delay; 334 u_int32_t tx_abs_int_delay; 335 u_int32_t rx_int_delay; 336 u_int32_t rx_abs_int_delay; 337 338 XSUM_CONTEXT_T active_checksum_context; 339 340 /* 341 * Transmit definitions 342 * 343 * We have an array of num_tx_desc descriptors (handled 344 * by the controller) paired with an array of tx_buffers 345 * (at tx_buffer_area). 346 * The index of the next available descriptor is next_avail_tx_desc. 347 * The number of remaining tx_desc is num_tx_desc_avail. 348 */ 349 struct em_dma_alloc txdma; /* bus_dma glue for tx desc */ 350 struct em_tx_desc *tx_desc_base; 351 u_int32_t next_avail_tx_desc; 352 u_int32_t oldest_used_tx_desc; 353 volatile u_int16_t num_tx_desc_avail; 354 u_int16_t num_tx_desc; 355 u_int32_t txd_cmd; 356 struct em_buffer *tx_buffer_area; 357 bus_dma_tag_t txtag; /* dma tag for tx */ 358 359 /* 360 * Receive definitions 361 * 362 * we have an array of num_rx_desc rx_desc (handled by the 363 * controller), and paired with an array of rx_buffers 364 * (at rx_buffer_area). 365 * The next pair to check on receive is at offset next_rx_desc_to_check 366 */ 367 struct em_dma_alloc rxdma; /* bus_dma glue for rx desc */ 368 struct em_rx_desc *rx_desc_base; 369 u_int32_t next_rx_desc_to_check; 370 u_int32_t rx_buffer_len; 371 u_int16_t num_rx_desc; 372 struct em_buffer *rx_buffer_area; 373 bus_dma_tag_t rxtag; 374 bus_dmamap_t rx_sparemap; 375 376 /* 377 * First/last mbuf pointers, for 378 * collecting multisegment RX packets. 379 */ 380 struct mbuf *fmp; 381 struct mbuf *lmp; 382 383 /* Misc stats maintained by the driver */ 384 unsigned long dropped_pkts; 385 unsigned long mbuf_alloc_failed; 386 unsigned long mbuf_cluster_failed; 387 unsigned long no_tx_desc_avail1; 388 unsigned long no_tx_desc_avail2; 389 unsigned long no_tx_map_avail; 390 unsigned long no_tx_dma_setup; 391 unsigned long watchdog_events; 392 unsigned long rx_overruns; 393 394 /* Used in for 82547 10Mb Half workaround */ 395 #define EM_PBA_BYTES_SHIFT 0xA 396 #define EM_TX_HEAD_ADDR_SHIFT 7 397 #define EM_PBA_TX_MASK 0xFFFF0000 398 #define EM_FIFO_HDR 0x10 399 400 #define EM_82547_PKT_THRESH 0x3e0 401 402 u_int32_t tx_fifo_size; 403 u_int32_t tx_fifo_head; 404 u_int32_t tx_fifo_head_addr; 405 u_int64_t tx_fifo_reset_cnt; 406 u_int64_t tx_fifo_wrk_cnt; 407 u_int32_t tx_head_addr; 408 409 /* For 82544 PCI-X Workaround */ 410 boolean_t pcix_82544; 411 412 struct em_hw_stats stats; 413}; 414 415#endif /* _EM_H_DEFINED_ */ 416