if_em.h revision 1.28
1/************************************************************************** 2 3Copyright (c) 2001-2003, Intel Corporation 4All rights reserved. 5 6Redistribution and use in source and binary forms, with or without 7modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30POSSIBILITY OF SUCH DAMAGE. 31 32***************************************************************************/ 33 34/* $FreeBSD: if_em.h,v 1.26 2004/09/01 23:22:41 pdeuskar Exp $ */ 35/* $OpenBSD: if_em.h,v 1.28 2006/09/17 17:51:01 brad Exp $ */ 36 37#ifndef _EM_H_DEFINED_ 38#define _EM_H_DEFINED_ 39 40#include "bpfilter.h" 41#include "vlan.h" 42 43#include <sys/param.h> 44#include <sys/systm.h> 45#include <sys/sockio.h> 46#include <sys/mbuf.h> 47#include <sys/malloc.h> 48#include <sys/kernel.h> 49#include <sys/device.h> 50#include <sys/socket.h> 51 52#include <net/if.h> 53#include <net/if_dl.h> 54#include <net/if_media.h> 55 56#ifdef INET 57#include <netinet/in.h> 58#include <netinet/in_systm.h> 59#include <netinet/in_var.h> 60#include <netinet/ip.h> 61#include <netinet/if_ether.h> 62#include <netinet/tcp.h> 63#include <netinet/udp.h> 64#endif 65 66#if NVLAN > 0 67#include <net/if_types.h> 68#include <net/if_vlan_var.h> 69#endif 70 71#if NBPFILTER > 0 72#include <net/bpf.h> 73#endif 74 75#include <uvm/uvm_extern.h> 76 77#include <dev/pci/pcireg.h> 78#include <dev/pci/pcivar.h> 79#include <dev/pci/pcidevs.h> 80 81#include <dev/pci/if_em_hw.h> 82 83/* Tunables */ 84 85/* 86 * EM_TXD: Maximum number of Transmit Descriptors 87 * Valid Range: 80-256 for 82542 and 82543-based adapters 88 * 80-4096 for others 89 * Default Value: 256 90 * This value is the number of transmit descriptors allocated by the driver. 91 * Increasing this value allows the driver to queue more transmits. Each 92 * descriptor is 16 bytes. 93 * Since TDLEN should be multiple of 128bytes, the number of transmit 94 * desscriptors should meet the following condition. 95 * (num_tx_desc * sizeof(struct em_tx_desc)) % 128 == 0 96 */ 97#define EM_MIN_TXD 12 98#define EM_MAX_TXD_82543 256 99#define EM_MAX_TXD 512 100 101/* 102 * EM_RXD - Maximum number of receive Descriptors 103 * Valid Range: 80-256 for 82542 and 82543-based adapters 104 * 80-4096 for others 105 * Default Value: 256 106 * This value is the number of receive descriptors allocated by the driver. 107 * Increasing this value allows the driver to buffer more incoming packets. 108 * Each descriptor is 16 bytes. A receive buffer is also allocated for each 109 * descriptor. The maximum MTU size is 16110. 110 * Since TDLEN should be multiple of 128bytes, the number of transmit 111 * desscriptors should meet the following condition. 112 * (num_tx_desc * sizeof(struct em_tx_desc)) % 128 == 0 113 */ 114#define EM_MIN_RXD 12 115#define EM_MAX_RXD 256 116 117/* 118 * EM_TIDV - Transmit Interrupt Delay Value 119 * Valid Range: 0-65535 (0=off) 120 * Default Value: 64 121 * This value delays the generation of transmit interrupts in units of 122 * 1.024 microseconds. Transmit interrupt reduction can improve CPU 123 * efficiency if properly tuned for specific network traffic. If the 124 * system is reporting dropped transmits, this value may be set too high 125 * causing the driver to run out of available transmit descriptors. 126 */ 127#define EM_TIDV 64 128 129/* 130 * EM_TADV - Transmit Absolute Interrupt Delay Value (Not valid for 82542/82543/82544) 131 * Valid Range: 0-65535 (0=off) 132 * Default Value: 64 133 * This value, in units of 1.024 microseconds, limits the delay in which a 134 * transmit interrupt is generated. Useful only if EM_TIDV is non-zero, 135 * this value ensures that an interrupt is generated after the initial 136 * packet is sent on the wire within the set amount of time. Proper tuning, 137 * along with EM_TIDV, may improve traffic throughput in specific 138 * network conditions. 139 */ 140#define EM_TADV 64 141 142/* 143 * EM_RDTR - Receive Interrupt Delay Timer (Packet Timer) 144 * Valid Range: 0-65535 (0=off) 145 * Default Value: 0 146 * This value delays the generation of receive interrupts in units of 1.024 147 * microseconds. Receive interrupt reduction can improve CPU efficiency if 148 * properly tuned for specific network traffic. Increasing this value adds 149 * extra latency to frame reception and can end up decreasing the throughput 150 * of TCP traffic. If the system is reporting dropped receives, this value 151 * may be set too high, causing the driver to run out of available receive 152 * descriptors. 153 * 154 * CAUTION: When setting EM_RDTR to a value other than 0, adapters 155 * may hang (stop transmitting) under certain network conditions. 156 * If this occurs a WATCHDOG message is logged in the system event log. 157 * In addition, the controller is automatically reset, restoring the 158 * network connection. To eliminate the potential for the hang 159 * ensure that EM_RDTR is set to 0. 160 */ 161#define EM_RDTR 0 162 163/* 164 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544) 165 * Valid Range: 0-65535 (0=off) 166 * Default Value: 64 167 * This value, in units of 1.024 microseconds, limits the delay in which a 168 * receive interrupt is generated. Useful only if EM_RDTR is non-zero, 169 * this value ensures that an interrupt is generated after the initial 170 * packet is received within the set amount of time. Proper tuning, 171 * along with EM_RDTR, may improve traffic throughput in specific network 172 * conditions. 173 */ 174#define EM_RADV 64 175 176/* 177 * This parameter controls the duration of transmit watchdog timer. 178 */ 179#define EM_TX_TIMEOUT 5 /* set to 5 seconds */ 180 181/* 182 * This parameter controls when the driver calls the routine to reclaim 183 * transmit descriptors. 184 */ 185#define EM_TX_CLEANUP_THRESHOLD (sc->num_tx_desc / 8) 186 187/* 188 * This parameter controls whether or not autonegotation is enabled. 189 * 0 - Disable autonegotiation 190 * 1 - Enable autonegotiation 191 */ 192#define DO_AUTO_NEG 1 193 194/* 195 * This parameter control whether or not the driver will wait for 196 * autonegotiation to complete. 197 * 1 - Wait for autonegotiation to complete 198 * 0 - Don't wait for autonegotiation to complete 199 */ 200#define WAIT_FOR_AUTO_NEG_DEFAULT 0 201 202/* 203 * EM_MASTER_SLAVE is only defined to enable a workaround for a known compatibility issue 204 * with 82541/82547 devices and some switches. See the "Known Limitations" section of 205 * the README file for a complete description and a list of affected switches. 206 * 207 * 0 = Hardware default 208 * 1 = Master mode 209 * 2 = Slave mode 210 * 3 = Auto master/slave 211 */ 212/* #define EM_MASTER_SLAVE 2 */ 213 214/* Tunables -- End */ 215 216#define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 217 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 218 ADVERTISE_1000_FULL) 219 220#define EM_MMBA 0x0010 /* Mem base address */ 221#define EM_FLASH 0x0014 /* Flash memory on ICH8 */ 222#define EM_ROUNDUP(size, unit) (((size) + (unit) - 1) & ~((unit) - 1)) 223 224#define EM_SMARTSPEED_DOWNSHIFT 3 225#define EM_SMARTSPEED_MAX 15 226 227#define MAX_NUM_MULTICAST_ADDRESSES 128 228 229/* Defines for printing debug information */ 230#define DEBUG_INIT 0 231#define DEBUG_IOCTL 0 232#define DEBUG_HW 0 233 234#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 235#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 236#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 237#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 238#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 239#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 240#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 241#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 242#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 243 244/* Supported RX Buffer Sizes */ 245#define EM_RXBUFFER_2048 2048 246#define EM_RXBUFFER_4096 4096 247#define EM_RXBUFFER_8192 8192 248#define EM_RXBUFFER_16384 16384 249 250#define EM_MAX_SCATTER 64 251 252struct em_buffer { 253 struct mbuf *m_head; 254 bus_dmamap_t map; /* bus_dma map for packet */ 255}; 256 257struct em_q { 258 bus_dmamap_t map; /* bus_dma map for packet */ 259}; 260 261/* 262 * Bus dma allocation structure used by 263 * em_dma_malloc and em_dma_free. 264 */ 265struct em_dma_alloc { 266 bus_addr_t dma_paddr; 267 caddr_t dma_vaddr; 268 bus_dma_tag_t dma_tag; 269 bus_dmamap_t dma_map; 270 bus_dma_segment_t dma_seg; 271 bus_size_t dma_size; 272 int dma_nseg; 273}; 274 275typedef enum _XSUM_CONTEXT_T { 276 OFFLOAD_NONE, 277 OFFLOAD_TCP_IP, 278 OFFLOAD_UDP_IP 279} XSUM_CONTEXT_T; 280 281/* For 82544 PCI-X Workaround */ 282typedef struct _ADDRESS_LENGTH_PAIR 283{ 284 u_int64_t address; 285 u_int32_t length; 286} ADDRESS_LENGTH_PAIR, *PADDRESS_LENGTH_PAIR; 287 288typedef struct _DESCRIPTOR_PAIR 289{ 290 ADDRESS_LENGTH_PAIR descriptor[4]; 291 u_int32_t elements; 292} DESC_ARRAY, *PDESC_ARRAY; 293 294/* Our adapter structure */ 295struct em_softc { 296 struct device sc_dv; 297 struct arpcom interface_data; 298 struct em_hw hw; 299 300 /* OpenBSD operating-system-specific structures */ 301 struct em_osdep osdep; 302 struct ifmedia media; 303 int io_rid; 304 305 void *sc_intrhand; 306 struct timeout em_intr_enable; 307 struct timeout timer_handle; 308 struct timeout tx_fifo_timer_handle; 309 int if_flags; 310 void *sc_powerhook; 311 void *sc_shutdownhook; 312 313#ifdef __STRICT_ALIGNMENT 314 /* Used for carrying forward alignment adjustments */ 315 unsigned char align_buf[ETHER_ALIGN]; /* tail of unaligned packet */ 316 u_int8_t align_buf_len; /* bytes in tail */ 317#endif /* __STRICT_ALIGNMENT */ 318 319 /* Info about the board itself */ 320 u_int32_t part_num; 321 u_int8_t link_active; 322 u_int16_t link_speed; 323 u_int16_t link_duplex; 324 u_int32_t smartspeed; 325 u_int32_t tx_int_delay; 326 u_int32_t tx_abs_int_delay; 327 u_int32_t rx_int_delay; 328 u_int32_t rx_abs_int_delay; 329 330 XSUM_CONTEXT_T active_checksum_context; 331 332 /* 333 * Transmit definitions 334 * 335 * We have an array of num_tx_desc descriptors (handled 336 * by the controller) paired with an array of tx_buffers 337 * (at tx_buffer_area). 338 * The index of the next available descriptor is next_avail_tx_desc. 339 * The number of remaining tx_desc is num_tx_desc_avail. 340 */ 341 struct em_dma_alloc txdma; /* bus_dma glue for tx desc */ 342 struct em_tx_desc *tx_desc_base; 343 u_int32_t next_avail_tx_desc; 344 u_int32_t oldest_used_tx_desc; 345 volatile u_int16_t num_tx_desc_avail; 346 u_int16_t num_tx_desc; 347 u_int32_t txd_cmd; 348 struct em_buffer *tx_buffer_area; 349 bus_dma_tag_t txtag; /* dma tag for tx */ 350 351 /* 352 * Receive definitions 353 * 354 * we have an array of num_rx_desc rx_desc (handled by the 355 * controller), and paired with an array of rx_buffers 356 * (at rx_buffer_area). 357 * The next pair to check on receive is at offset next_rx_desc_to_check 358 */ 359 struct em_dma_alloc rxdma; /* bus_dma glue for rx desc */ 360 struct em_rx_desc *rx_desc_base; 361 u_int32_t next_rx_desc_to_check; 362 u_int16_t num_rx_desc; 363 u_int32_t rx_buffer_len; 364 struct em_buffer *rx_buffer_area; 365 bus_dma_tag_t rxtag; 366 367 /* Jumbo frame */ 368 struct mbuf *fmp; 369 struct mbuf *lmp; 370 371 /* Misc stats maintained by the driver */ 372 unsigned long dropped_pkts; 373 unsigned long mbuf_alloc_failed; 374 unsigned long mbuf_cluster_failed; 375 unsigned long no_tx_desc_avail1; 376 unsigned long no_tx_desc_avail2; 377 unsigned long no_tx_map_avail; 378 unsigned long no_tx_dma_setup; 379 unsigned long watchdog_events; 380 unsigned long rx_overruns; 381 382 /* Used in for 82547 10Mb Half workaround */ 383 #define EM_PBA_BYTES_SHIFT 0xA 384 #define EM_TX_HEAD_ADDR_SHIFT 7 385 #define EM_PBA_TX_MASK 0xFFFF0000 386 #define EM_FIFO_HDR 0x10 387 388 #define EM_82547_PKT_THRESH 0x3e0 389 390 u_int32_t tx_fifo_size; 391 u_int32_t tx_fifo_head; 392 u_int32_t tx_fifo_head_addr; 393 u_int64_t tx_fifo_reset_cnt; 394 u_int64_t tx_fifo_wrk_cnt; 395 u_int32_t tx_head_addr; 396 397 /* For 82544 PCI-X Workaround */ 398 boolean_t pcix_82544; 399 400 struct em_hw_stats stats; 401}; 402 403#endif /* _EM_H_DEFINED_ */ 404