if_em.h revision 1.25
1/************************************************************************** 2 3Copyright (c) 2001-2003, Intel Corporation 4All rights reserved. 5 6Redistribution and use in source and binary forms, with or without 7modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30POSSIBILITY OF SUCH DAMAGE. 31 32***************************************************************************/ 33 34/* $FreeBSD: if_em.h,v 1.26 2004/09/01 23:22:41 pdeuskar Exp $ */ 35/* $OpenBSD: if_em.h,v 1.25 2006/07/05 01:15:30 brad Exp $ */ 36 37#ifndef _EM_H_DEFINED_ 38#define _EM_H_DEFINED_ 39 40#include "bpfilter.h" 41#include "vlan.h" 42 43#include <sys/param.h> 44#include <sys/systm.h> 45#include <sys/sockio.h> 46#include <sys/mbuf.h> 47#include <sys/malloc.h> 48#include <sys/kernel.h> 49#include <sys/device.h> 50#include <sys/socket.h> 51 52#include <net/if.h> 53#include <net/if_dl.h> 54#include <net/if_media.h> 55 56#ifdef INET 57#include <netinet/in.h> 58#include <netinet/in_systm.h> 59#include <netinet/in_var.h> 60#include <netinet/ip.h> 61#include <netinet/if_ether.h> 62#include <netinet/tcp.h> 63#include <netinet/udp.h> 64#endif 65 66#if NVLAN > 0 67#include <net/if_types.h> 68#include <net/if_vlan_var.h> 69#endif 70 71#if NBPFILTER > 0 72#include <net/bpf.h> 73#endif 74 75#include <uvm/uvm_extern.h> 76 77#include <dev/pci/pcireg.h> 78#include <dev/pci/pcivar.h> 79#include <dev/pci/pcidevs.h> 80 81#include <dev/pci/if_em_hw.h> 82 83/* Tunables */ 84 85/* 86 * EM_(MIN/MAX)_TXD: Maximum number of Transmit Descriptors 87 * Valid Range: 80-256 for 82542 and 82543-based adapters 88 * 80-4096 for others 89 * Default Value: 256 90 * This value is the number of transmit descriptors allocated by the driver. 91 * Increasing this value allows the driver to queue more transmits. Each 92 * descriptor is 16 bytes. 93 */ 94#define EM_MIN_TXD 12 95#define EM_MAX_TXD 256 96#define EM_MAX_TXD_82544 512 97 98/* 99 * EM_(MIN/MAX)_RXD - Maximum number of receive Descriptors 100 * Valid Range: 80-256 for 82542 and 82543-based adapters 101 * 80-4096 for others 102 * Default Value: 256 103 * This value is the number of receive descriptors allocated by the driver. 104 * Increasing this value allows the driver to buffer more incoming packets. 105 * Each descriptor is 16 bytes. A receive buffer is also allocated for each 106 * descriptor. The maximum MTU size is 16110. 107 * 108 */ 109#define EM_MIN_RXD 12 110#define EM_MAX_RXD 256 111 112/* 113 * EM_TIDV - Transmit Interrupt Delay Value 114 * Valid Range: 0-65535 (0=off) 115 * Default Value: 64 116 * This value delays the generation of transmit interrupts in units of 117 * 1.024 microseconds. Transmit interrupt reduction can improve CPU 118 * efficiency if properly tuned for specific network traffic. If the 119 * system is reporting dropped transmits, this value may be set too high 120 * causing the driver to run out of available transmit descriptors. 121 */ 122#define EM_TIDV 64 123 124/* 125 * EM_TADV - Transmit Absolute Interrupt Delay Value (Not valid for 82542/82543/82544) 126 * Valid Range: 0-65535 (0=off) 127 * Default Value: 64 128 * This value, in units of 1.024 microseconds, limits the delay in which a 129 * transmit interrupt is generated. Useful only if EM_TIDV is non-zero, 130 * this value ensures that an interrupt is generated after the initial 131 * packet is sent on the wire within the set amount of time. Proper tuning, 132 * along with EM_TIDV, may improve traffic throughput in specific 133 * network conditions. 134 */ 135#define EM_TADV 64 136 137/* 138 * EM_RDTR - Receive Interrupt Delay Timer (Packet Timer) 139 * Valid Range: 0-65535 (0=off) 140 * Default Value: 0 141 * This value delays the generation of receive interrupts in units of 1.024 142 * microseconds. Receive interrupt reduction can improve CPU efficiency if 143 * properly tuned for specific network traffic. Increasing this value adds 144 * extra latency to frame reception and can end up decreasing the throughput 145 * of TCP traffic. If the system is reporting dropped receives, this value 146 * may be set too high, causing the driver to run out of available receive 147 * descriptors. 148 * 149 * CAUTION: When setting EM_RDTR to a value other than 0, adapters 150 * may hang (stop transmitting) under certain network conditions. 151 * If this occurs a WATCHDOG message is logged in the system event log. 152 * In addition, the controller is automatically reset, restoring the 153 * network connection. To eliminate the potential for the hang 154 * ensure that EM_RDTR is set to 0. 155 */ 156#define EM_RDTR 0 157 158/* 159 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544) 160 * Valid Range: 0-65535 (0=off) 161 * Default Value: 64 162 * This value, in units of 1.024 microseconds, limits the delay in which a 163 * receive interrupt is generated. Useful only if EM_RDTR is non-zero, 164 * this value ensures that an interrupt is generated after the initial 165 * packet is received within the set amount of time. Proper tuning, 166 * along with EM_RDTR, may improve traffic throughput in specific network 167 * conditions. 168 */ 169#define EM_RADV 64 170 171/* 172 * This parameter controls the duration of transmit watchdog timer. 173 */ 174#define EM_TX_TIMEOUT 5 /* set to 5 seconds */ 175 176/* 177 * This parameter controls when the driver calls the routine to reclaim 178 * transmit descriptors. 179 */ 180#define EM_TX_CLEANUP_THRESHOLD (sc->num_tx_desc / 8) 181 182/* 183 * This parameter controls whether or not autonegotation is enabled. 184 * 0 - Disable autonegotiation 185 * 1 - Enable autonegotiation 186 */ 187#define DO_AUTO_NEG 1 188 189/* 190 * This parameter control whether or not the driver will wait for 191 * autonegotiation to complete. 192 * 1 - Wait for autonegotiation to complete 193 * 0 - Don't wait for autonegotiation to complete 194 */ 195#define WAIT_FOR_AUTO_NEG_DEFAULT 0 196 197/* 198 * EM_MASTER_SLAVE is only defined to enable a workaround for a known compatibility issue 199 * with 82541/82547 devices and some switches. See the "Known Limitations" section of 200 * the README file for a complete description and a list of affected switches. 201 * 202 * 0 = Hardware default 203 * 1 = Master mode 204 * 2 = Slave mode 205 * 3 = Auto master/slave 206 */ 207/* #define EM_MASTER_SLAVE 2 */ 208 209/* Tunables -- End */ 210 211#define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 212 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 213 ADVERTISE_1000_FULL) 214 215#define EM_MMBA 0x0010 /* Mem base address */ 216#define EM_ROUNDUP(size, unit) (((size) + (unit) - 1) & ~((unit) - 1)) 217 218#define EM_SMARTSPEED_DOWNSHIFT 3 219#define EM_SMARTSPEED_MAX 15 220 221#define MAX_NUM_MULTICAST_ADDRESSES 128 222 223/* Defines for printing debug information */ 224#define DEBUG_INIT 0 225#define DEBUG_IOCTL 0 226#define DEBUG_HW 0 227 228#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 229#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 230#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 231#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 232#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 233#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 234#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 235#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 236#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 237 238/* Supported RX Buffer Sizes */ 239#define EM_RXBUFFER_2048 2048 240#define EM_RXBUFFER_4096 4096 241#define EM_RXBUFFER_8192 8192 242#define EM_RXBUFFER_16384 16384 243 244#define EM_MAX_SCATTER 64 245 246struct em_buffer { 247 struct mbuf *m_head; 248 bus_dmamap_t map; /* bus_dma map for packet */ 249}; 250 251struct em_q { 252 bus_dmamap_t map; /* bus_dma map for packet */ 253}; 254 255/* 256 * Bus dma allocation structure used by 257 * em_dma_malloc and em_dma_free. 258 */ 259struct em_dma_alloc { 260 bus_addr_t dma_paddr; 261 caddr_t dma_vaddr; 262 bus_dma_tag_t dma_tag; 263 bus_dmamap_t dma_map; 264 bus_dma_segment_t dma_seg; 265 bus_size_t dma_size; 266 int dma_nseg; 267}; 268 269typedef enum _XSUM_CONTEXT_T { 270 OFFLOAD_NONE, 271 OFFLOAD_TCP_IP, 272 OFFLOAD_UDP_IP 273} XSUM_CONTEXT_T; 274 275/* For 82544 PCI-X Workaround */ 276typedef struct _ADDRESS_LENGTH_PAIR 277{ 278 u_int64_t address; 279 u_int32_t length; 280} ADDRESS_LENGTH_PAIR, *PADDRESS_LENGTH_PAIR; 281 282typedef struct _DESCRIPTOR_PAIR 283{ 284 ADDRESS_LENGTH_PAIR descriptor[4]; 285 u_int32_t elements; 286} DESC_ARRAY, *PDESC_ARRAY; 287 288/* Our adapter structure */ 289struct em_softc { 290 struct device sc_dv; 291 struct arpcom interface_data; 292 struct em_hw hw; 293 294 /* OpenBSD operating-system-specific structures */ 295 struct em_osdep osdep; 296 struct ifmedia media; 297 int io_rid; 298 299 void *sc_intrhand; 300 struct timeout em_intr_enable; 301 struct timeout timer_handle; 302 struct timeout tx_fifo_timer_handle; 303 void *sc_powerhook; 304 void *sc_shutdownhook; 305 306#ifdef __STRICT_ALIGNMENT 307 /* Used for carrying forward alignment adjustments */ 308 unsigned char align_buf[ETHER_ALIGN]; /* tail of unaligned packet */ 309 u_int8_t align_buf_len; /* bytes in tail */ 310#endif /* __STRICT_ALIGNMENT */ 311 312 /* Info about the board itself */ 313 u_int32_t part_num; 314 u_int8_t link_active; 315 u_int16_t link_speed; 316 u_int16_t link_duplex; 317 u_int32_t smartspeed; 318 u_int32_t tx_int_delay; 319 u_int32_t tx_abs_int_delay; 320 u_int32_t rx_int_delay; 321 u_int32_t rx_abs_int_delay; 322 323 XSUM_CONTEXT_T active_checksum_context; 324 325 /* 326 * Transmit definitions 327 * 328 * We have an array of num_tx_desc descriptors (handled 329 * by the controller) paired with an array of tx_buffers 330 * (at tx_buffer_area). 331 * The index of the next available descriptor is next_avail_tx_desc. 332 * The number of remaining tx_desc is num_tx_desc_avail. 333 */ 334 struct em_dma_alloc txdma; /* bus_dma glue for tx desc */ 335 struct em_tx_desc *tx_desc_base; 336 u_int32_t next_avail_tx_desc; 337 u_int32_t oldest_used_tx_desc; 338 volatile u_int16_t num_tx_desc_avail; 339 u_int16_t num_tx_desc; 340 u_int32_t txd_cmd; 341 struct em_buffer *tx_buffer_area; 342 bus_dma_tag_t txtag; /* dma tag for tx */ 343 344 /* 345 * Receive definitions 346 * 347 * we have an array of num_rx_desc rx_desc (handled by the 348 * controller), and paired with an array of rx_buffers 349 * (at rx_buffer_area). 350 * The next pair to check on receive is at offset next_rx_desc_to_check 351 */ 352 struct em_dma_alloc rxdma; /* bus_dma glue for rx desc */ 353 struct em_rx_desc *rx_desc_base; 354 u_int32_t next_rx_desc_to_check; 355 u_int16_t num_rx_desc; 356 u_int32_t rx_buffer_len; 357 struct em_buffer *rx_buffer_area; 358 bus_dma_tag_t rxtag; 359 360 /* Jumbo frame */ 361 struct mbuf *fmp; 362 struct mbuf *lmp; 363 364 /* Misc stats maintained by the driver */ 365 unsigned long dropped_pkts; 366 unsigned long mbuf_alloc_failed; 367 unsigned long mbuf_cluster_failed; 368 unsigned long no_tx_desc_avail1; 369 unsigned long no_tx_desc_avail2; 370 unsigned long no_tx_map_avail; 371 unsigned long no_tx_dma_setup; 372 unsigned long watchdog_events; 373 unsigned long rx_overruns; 374 375 /* Used in for 82547 10Mb Half workaround */ 376 #define EM_PBA_BYTES_SHIFT 0xA 377 #define EM_TX_HEAD_ADDR_SHIFT 7 378 #define EM_PBA_TX_MASK 0xFFFF0000 379 #define EM_FIFO_HDR 0x10 380 381 #define EM_82547_PKT_THRESH 0x3e0 382 383 u_int32_t tx_fifo_size; 384 u_int32_t tx_fifo_head; 385 u_int32_t tx_fifo_head_addr; 386 u_int64_t tx_fifo_reset_cnt; 387 u_int64_t tx_fifo_wrk_cnt; 388 u_int32_t tx_head_addr; 389 390 /* For 82544 PCI-X Workaround */ 391 boolean_t pcix_82544; 392 393 struct em_hw_stats stats; 394}; 395 396#endif /* _EM_H_DEFINED_ */ 397