if_em.h revision 1.12 
1/**************************************************************************
2
3Copyright (c) 2001-2003, Intel Corporation
4All rights reserved.
5
6Redistribution and use in source and binary forms, with or without
7modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10    this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13    notice, this list of conditions and the following disclaimer in the
14    documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17    contributors may be used to endorse or promote products derived from
18    this software without specific prior written permission.
19
20THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30POSSIBILITY OF SUCH DAMAGE.
31
32***************************************************************************/
33
34/* $FreeBSD: if_em.h,v 1.26 2004/09/01 23:22:41 pdeuskar Exp $ */
35/* $OpenBSD: if_em.h,v 1.12 2005/07/02 06:15:44 deraadt Exp $ */
36
37#ifndef _EM_H_DEFINED_
38#define _EM_H_DEFINED_
39
40#include <dev/pci/if_em_hw.h>
41
42/* Tunables */
43
44/*
45 * EM_MAX_TXD: Maximum number of Transmit Descriptors
46 * Valid Range: 80-256 for 82542 and 82543-based adapters
47 *              80-4096 for others
48 * Default Value: 256
49 *   This value is the number of transmit descriptors allocated by the driver.
50 *   Increasing this value allows the driver to queue more transmits. Each
51 *   descriptor is 16 bytes.
52 */
53#define EM_MIN_TXD                      12
54#define EM_MAX_TXD                      256
55
56/*
57 * EM_MAX_RXD - Maximum number of receive Descriptors
58 * Valid Range: 80-256 for 82542 and 82543-based adapters
59 *              80-4096 for others
60 * Default Value: 256
61 *   This value is the number of receive descriptors allocated by the driver.
62 *   Increasing this value allows the driver to buffer more incoming packets.
63 *   Each descriptor is 16 bytes.  A receive buffer is also allocated for each
64 *   descriptor. The maximum MTU size is 16110.
65 *
66 */
67#define EM_MIN_RXD                      12
68#define EM_MAX_RXD                      256
69
70/*
71 * EM_TIDV - Transmit Interrupt Delay Value
72 * Valid Range: 0-65535 (0=off)
73 * Default Value: 64
74 *   This value delays the generation of transmit interrupts in units of
75 *   1.024 microseconds. Transmit interrupt reduction can improve CPU
76 *   efficiency if properly tuned for specific network traffic. If the
77 *   system is reporting dropped transmits, this value may be set too high
78 *   causing the driver to run out of available transmit descriptors.
79 */
80#define EM_TIDV                         64
81
82/*
83 * EM_TADV - Transmit Absolute Interrupt Delay Value (Not valid for 82542/82543/82544)
84 * Valid Range: 0-65535 (0=off)
85 * Default Value: 64
86 *   This value, in units of 1.024 microseconds, limits the delay in which a
87 *   transmit interrupt is generated. Useful only if EM_TIDV is non-zero,
88 *   this value ensures that an interrupt is generated after the initial
89 *   packet is sent on the wire within the set amount of time.  Proper tuning,
90 *   along with EM_TIDV, may improve traffic throughput in specific
91 *   network conditions.
92 */
93#define EM_TADV                         64
94
95/*
96 * EM_RDTR - Receive Interrupt Delay Timer (Packet Timer)
97 * Valid Range: 0-65535 (0=off)
98 * Default Value: 0
99 *   This value delays the generation of receive interrupts in units of 1.024
100 *   microseconds.  Receive interrupt reduction can improve CPU efficiency if
101 *   properly tuned for specific network traffic. Increasing this value adds
102 *   extra latency to frame reception and can end up decreasing the throughput
103 *   of TCP traffic. If the system is reporting dropped receives, this value
104 *   may be set too high, causing the driver to run out of available receive
105 *   descriptors.
106 *
107 *   CAUTION: When setting EM_RDTR to a value other than 0, adapters
108 *            may hang (stop transmitting) under certain network conditions.
109 *            If this occurs a WATCHDOG message is logged in the system event log.
110 *            In addition, the controller is automatically reset, restoring the
111 *            network connection. To eliminate the potential for the hang
112 *            ensure that EM_RDTR is set to 0.
113 */
114#define EM_RDTR                         0
115
116/*
117 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544)
118 * Valid Range: 0-65535 (0=off)
119 * Default Value: 64
120 *   This value, in units of 1.024 microseconds, limits the delay in which a
121 *   receive interrupt is generated. Useful only if EM_RDTR is non-zero,
122 *   this value ensures that an interrupt is generated after the initial
123 *   packet is received within the set amount of time.  Proper tuning,
124 *   along with EM_RDTR, may improve traffic throughput in specific network
125 *   conditions.
126 */
127#define EM_RADV                         64
128
129
130/*
131 * This parameter controls the maximum no of times the driver will loop
132 * in the isr.
133 *           Minimum Value = 1
134 */
135#define EM_MAX_INTR                     3
136
137/*
138 * Inform the stack about transmit checksum offload capabilities.
139 */
140#define EM_CHECKSUM_FEATURES            (CSUM_TCP | CSUM_UDP)
141
142/*
143 * This parameter controls the duration of transmit watchdog timer.
144 */
145#define EM_TX_TIMEOUT                   5    /* set to 5 seconds */
146
147/*
148 * This parameter controls when the driver calls the routine to reclaim
149 * transmit descriptors.
150 */
151#define EM_TX_CLEANUP_THRESHOLD         EM_MAX_TXD / 8
152
153/*
154 * This parameter controls whether or not autonegotation is enabled.
155 *              0 - Disable autonegotiation
156 *              1 - Enable  autonegotiation
157 */
158#define DO_AUTO_NEG                     1
159
160/*
161 * This parameter control whether or not the driver will wait for
162 * autonegotiation to complete.
163 *              1 - Wait for autonegotiation to complete
164 *              0 - Don't wait for autonegotiation to complete
165 */
166#define WAIT_FOR_AUTO_NEG_DEFAULT       0
167
168/*
169 * EM_MASTER_SLAVE is only defined to enable a workaround for a known compatibility issue
170 * with 82541/82547 devices and some switches.  See the "Known Limitations" section of
171 * the README file for a complete description and a list of affected switches.
172 *
173 *              0 = Hardware default
174 *              1 = Master mode
175 *              2 = Slave mode
176 *              3 = Auto master/slave
177 */
178/* #define EM_MASTER_SLAVE      2 */
179
180/* Tunables -- End */
181
182#define AUTONEG_ADV_DEFAULT             (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
183                                         ADVERTISE_100_HALF | ADVERTISE_100_FULL | \
184                                         ADVERTISE_1000_FULL)
185
186#define EM_VENDOR_ID                    0x8086
187#define EM_MMBA                         0x0010 /* Mem base address */
188#define EM_ROUNDUP(size, unit) (((size) + (unit) - 1) & ~((unit) - 1))
189
190#define EM_JUMBO_PBA                    0x00000028
191#define EM_DEFAULT_PBA                  0x00000030
192#define EM_SMARTSPEED_DOWNSHIFT         3
193#define EM_SMARTSPEED_MAX               15
194
195#define MAX_NUM_MULTICAST_ADDRESSES     128
196#define PCI_ANY_ID                      (~0U)
197
198/* Defines for printing debug information */
199#define DEBUG_INIT  0
200#define DEBUG_IOCTL 0
201#define DEBUG_HW    0
202
203#define INIT_DEBUGOUT(S)            if (DEBUG_INIT)  printf(S "\n")
204#define INIT_DEBUGOUT1(S, A)        if (DEBUG_INIT)  printf(S "\n", A)
205#define INIT_DEBUGOUT2(S, A, B)     if (DEBUG_INIT)  printf(S "\n", A, B)
206#define IOCTL_DEBUGOUT(S)           if (DEBUG_IOCTL) printf(S "\n")
207#define IOCTL_DEBUGOUT1(S, A)       if (DEBUG_IOCTL) printf(S "\n", A)
208#define IOCTL_DEBUGOUT2(S, A, B)    if (DEBUG_IOCTL) printf(S "\n", A, B)
209#define HW_DEBUGOUT(S)              if (DEBUG_HW) printf(S "\n")
210#define HW_DEBUGOUT1(S, A)          if (DEBUG_HW) printf(S "\n", A)
211#define HW_DEBUGOUT2(S, A, B)       if (DEBUG_HW) printf(S "\n", A, B)
212
213/* Supported RX Buffer Sizes */
214#define EM_RXBUFFER_2048        2048
215#define EM_RXBUFFER_4096        4096
216#define EM_RXBUFFER_8192        8192
217#define EM_RXBUFFER_16384      16384
218
219#define EM_MAX_SCATTER            64
220
221struct em_buffer {
222        struct mbuf    *m_head;
223	bus_dmamap_t	map;		/* bus_dma map for packet */
224};
225
226struct em_q {
227	bus_dmamap_t       map;         /* bus_dma map for packet */
228};
229
230/*
231 * Bus dma allocation structure used by
232 * em_dma_malloc and em_dma_free.
233 */
234struct em_dma_alloc {
235	bus_addr_t              dma_paddr;
236	caddr_t                 dma_vaddr;
237	bus_dma_tag_t           dma_tag;
238	bus_dmamap_t            dma_map;
239	bus_dma_segment_t       dma_seg;
240	bus_size_t              dma_size;
241	int                     dma_nseg;
242};
243
244typedef enum _XSUM_CONTEXT_T {
245	OFFLOAD_NONE,
246	OFFLOAD_TCP_IP,
247	OFFLOAD_UDP_IP
248} XSUM_CONTEXT_T;
249
250struct em_softc;
251struct em_int_delay_info {
252        struct em_softc *sc;    /* Back-pointer to the sc struct */
253        int offset;                     /* Register offset to read/write */
254        int value;                      /* Current value in usecs */
255};
256
257/* For 82544 PCIX  Workaround */
258typedef struct _ADDRESS_LENGTH_PAIR
259{
260    u_int64_t   address;
261    u_int32_t   length;
262} ADDRESS_LENGTH_PAIR, *PADDRESS_LENGTH_PAIR;
263
264typedef struct _DESCRIPTOR_PAIR
265{
266    ADDRESS_LENGTH_PAIR descriptor[4];
267    u_int32_t   elements;
268} DESC_ARRAY, *PDESC_ARRAY;
269
270/* Our adapter structure */
271struct em_softc {
272	struct device	sc_dv;
273	struct arpcom	interface_data;
274	struct em_softc *next;
275	struct em_softc *prev;
276	struct em_hw    hw;
277
278	/* OpenBSD operating-system-specific structures */
279	struct em_osdep osdep;
280	struct ifmedia  media;
281	int             io_rid;
282
283	void           *sc_intrhand;
284	struct timeout	em_intr_enable;
285	struct timeout	timer_handle;
286	struct timeout	tx_fifo_timer_handle;
287	void		*sc_powerhook;
288
289#ifdef __STRICT_ALIGNMENT
290	/* Used for carrying forward alignment adjustments */
291	unsigned char	align_buf[ETHER_ALIGN];	/* tail of unaligned packet */
292	u_int8_t	align_buf_len;		/* bytes in tail */
293#endif /* __STRICT_ALIGNMENT */
294
295	/* Info about the board itself */
296	u_int32_t       part_num;
297	u_int8_t        link_active;
298	u_int16_t       link_speed;
299	u_int16_t       link_duplex;
300	u_int32_t       smartspeed;
301	struct em_int_delay_info tx_int_delay;
302	struct em_int_delay_info tx_abs_int_delay;
303	struct em_int_delay_info rx_int_delay;
304	struct em_int_delay_info rx_abs_int_delay;
305
306	XSUM_CONTEXT_T  active_checksum_context;
307
308        /*
309         * Transmit definitions
310         *
311         * We have an array of num_tx_desc descriptors (handled
312         * by the controller) paired with an array of tx_buffers
313         * (at tx_buffer_area).
314         * The index of the next available descriptor is next_avail_tx_desc.
315         * The number of remaining tx_desc is num_tx_desc_avail.
316         */
317	struct em_dma_alloc	txdma;		/* bus_dma glue for tx desc */
318	struct em_tx_desc	*tx_desc_base;
319	u_int32_t		next_avail_tx_desc;
320	u_int32_t		oldest_used_tx_desc;
321	volatile u_int16_t	num_tx_desc_avail;
322	u_int16_t		num_tx_desc;
323	u_int32_t		txd_cmd;
324	struct em_buffer	*tx_buffer_area;
325	bus_dma_tag_t		txtag;		/* dma tag for tx */
326
327        /*
328         * Receive definitions
329         *
330         * we have an array of num_rx_desc rx_desc (handled by the
331         * controller), and paired with an array of rx_buffers
332         * (at rx_buffer_area).
333         * The next pair to check on receive is at offset next_rx_desc_to_check
334         */
335	struct em_dma_alloc	rxdma;		/* bus_dma glue for rx desc */
336	struct em_rx_desc	*rx_desc_base;
337	u_int32_t		next_rx_desc_to_check;
338	u_int16_t		num_rx_desc;
339	u_int32_t		rx_buffer_len;
340	struct em_buffer	*rx_buffer_area;
341	bus_dma_tag_t		rxtag;
342
343	/* Jumbo frame */
344	struct mbuf        *fmp;
345	struct mbuf        *lmp;
346
347	/* Misc stats maintained by the driver */
348	unsigned long   dropped_pkts;
349	unsigned long   mbuf_alloc_failed;
350	unsigned long   mbuf_cluster_failed;
351	unsigned long   no_tx_desc_avail1;
352	unsigned long   no_tx_desc_avail2;
353	unsigned long   no_tx_map_avail;
354        unsigned long   no_tx_dma_setup;
355
356	/* Used in for 82547 10Mb Half workaround */
357	#define EM_PBA_BYTES_SHIFT	0xA
358	#define EM_TX_HEAD_ADDR_SHIFT	7
359	#define EM_PBA_TX_MASK		0xFFFF0000
360	#define EM_FIFO_HDR              0x10
361
362	#define EM_82547_PKT_THRESH      0x3e0
363
364	u_int32_t       tx_fifo_size;
365	u_int32_t       tx_fifo_head;
366	u_int32_t       tx_fifo_head_addr;
367	u_int64_t       tx_fifo_reset_cnt;
368	u_int64_t       tx_fifo_wrk_cnt;
369	u_int32_t       tx_head_addr;
370
371        /* For 82544 PCIX Workaround */
372        boolean_t       pcix_82544;
373        boolean_t       in_detach;
374
375	struct em_hw_stats stats;
376};
377
378static inline int spl_use_arg(void *);
379static inline int spl_use_arg(void *v) { return splnet(); }
380#define EM_LOCK_INIT(_sc, _name)
381#define EM_LOCK_DESTROY(_sc)
382#define EM_LOCK_STATE()		int em_hidden_splnet_s
383#define EM_LOCK(_sc)		em_hidden_splnet_s = spl_use_arg(_sc)
384#define EM_UNLOCK(_sc)		splx(em_hidden_splnet_s)
385#define EM_LOCK_ASSERT(_sc)	splassert(IPL_NET)
386
387#endif                                                  /* _EM_H_DEFINED_ */
388