1// SPDX-License-Identifier: MIT 2/* 3 * Copyright 2019 Intel Corporation. 4 */ 5 6#include "i915_drv.h" 7#include "i915_utils.h" 8#include "intel_pch.h" 9 10/* Map PCH device id to PCH type, or PCH_NONE if unknown. */ 11static enum intel_pch 12intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id) 13{ 14 switch (id) { 15 case INTEL_PCH_IBX_DEVICE_ID_TYPE: 16 drm_dbg_kms(&dev_priv->drm, "Found Ibex Peak PCH\n"); 17 drm_WARN_ON(&dev_priv->drm, GRAPHICS_VER(dev_priv) != 5); 18 return PCH_IBX; 19 case INTEL_PCH_CPT_DEVICE_ID_TYPE: 20 drm_dbg_kms(&dev_priv->drm, "Found CougarPoint PCH\n"); 21 drm_WARN_ON(&dev_priv->drm, 22 GRAPHICS_VER(dev_priv) != 6 && !IS_IVYBRIDGE(dev_priv)); 23 return PCH_CPT; 24 case INTEL_PCH_PPT_DEVICE_ID_TYPE: 25 drm_dbg_kms(&dev_priv->drm, "Found PantherPoint PCH\n"); 26 drm_WARN_ON(&dev_priv->drm, 27 GRAPHICS_VER(dev_priv) != 6 && !IS_IVYBRIDGE(dev_priv)); 28 /* PPT is CPT compatible */ 29 return PCH_CPT; 30 case INTEL_PCH_LPT_DEVICE_ID_TYPE: 31 drm_dbg_kms(&dev_priv->drm, "Found LynxPoint PCH\n"); 32 drm_WARN_ON(&dev_priv->drm, 33 !IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)); 34 drm_WARN_ON(&dev_priv->drm, 35 IS_HASWELL_ULT(dev_priv) || IS_BROADWELL_ULT(dev_priv)); 36 return PCH_LPT; 37 case INTEL_PCH_LPT_LP_DEVICE_ID_TYPE: 38 drm_dbg_kms(&dev_priv->drm, "Found LynxPoint LP PCH\n"); 39 drm_WARN_ON(&dev_priv->drm, 40 !IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)); 41 drm_WARN_ON(&dev_priv->drm, 42 !IS_HASWELL_ULT(dev_priv) && !IS_BROADWELL_ULT(dev_priv)); 43 return PCH_LPT; 44 case INTEL_PCH_WPT_DEVICE_ID_TYPE: 45 drm_dbg_kms(&dev_priv->drm, "Found WildcatPoint PCH\n"); 46 drm_WARN_ON(&dev_priv->drm, 47 !IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)); 48 drm_WARN_ON(&dev_priv->drm, 49 IS_HASWELL_ULT(dev_priv) || IS_BROADWELL_ULT(dev_priv)); 50 /* WPT is LPT compatible */ 51 return PCH_LPT; 52 case INTEL_PCH_WPT_LP_DEVICE_ID_TYPE: 53 drm_dbg_kms(&dev_priv->drm, "Found WildcatPoint LP PCH\n"); 54 drm_WARN_ON(&dev_priv->drm, 55 !IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)); 56 drm_WARN_ON(&dev_priv->drm, 57 !IS_HASWELL_ULT(dev_priv) && !IS_BROADWELL_ULT(dev_priv)); 58 /* WPT is LPT compatible */ 59 return PCH_LPT; 60 case INTEL_PCH_SPT_DEVICE_ID_TYPE: 61 drm_dbg_kms(&dev_priv->drm, "Found SunrisePoint PCH\n"); 62 drm_WARN_ON(&dev_priv->drm, 63 !IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv)); 64 return PCH_SPT; 65 case INTEL_PCH_SPT_LP_DEVICE_ID_TYPE: 66 drm_dbg_kms(&dev_priv->drm, "Found SunrisePoint LP PCH\n"); 67 drm_WARN_ON(&dev_priv->drm, 68 !IS_SKYLAKE(dev_priv) && 69 !IS_KABYLAKE(dev_priv) && 70 !IS_COFFEELAKE(dev_priv) && 71 !IS_COMETLAKE(dev_priv)); 72 return PCH_SPT; 73 case INTEL_PCH_KBP_DEVICE_ID_TYPE: 74 drm_dbg_kms(&dev_priv->drm, "Found Kaby Lake PCH (KBP)\n"); 75 drm_WARN_ON(&dev_priv->drm, 76 !IS_SKYLAKE(dev_priv) && 77 !IS_KABYLAKE(dev_priv) && 78 !IS_COFFEELAKE(dev_priv) && 79 !IS_COMETLAKE(dev_priv)); 80 /* KBP is SPT compatible */ 81 return PCH_SPT; 82 case INTEL_PCH_CNP_DEVICE_ID_TYPE: 83 drm_dbg_kms(&dev_priv->drm, "Found Cannon Lake PCH (CNP)\n"); 84 drm_WARN_ON(&dev_priv->drm, 85 !IS_COFFEELAKE(dev_priv) && 86 !IS_COMETLAKE(dev_priv)); 87 return PCH_CNP; 88 case INTEL_PCH_CNP_LP_DEVICE_ID_TYPE: 89 drm_dbg_kms(&dev_priv->drm, 90 "Found Cannon Lake LP PCH (CNP-LP)\n"); 91 drm_WARN_ON(&dev_priv->drm, 92 !IS_COFFEELAKE(dev_priv) && 93 !IS_COMETLAKE(dev_priv)); 94 return PCH_CNP; 95 case INTEL_PCH_CMP_DEVICE_ID_TYPE: 96 case INTEL_PCH_CMP2_DEVICE_ID_TYPE: 97 drm_dbg_kms(&dev_priv->drm, "Found Comet Lake PCH (CMP)\n"); 98 drm_WARN_ON(&dev_priv->drm, 99 !IS_COFFEELAKE(dev_priv) && 100 !IS_COMETLAKE(dev_priv) && 101 !IS_ROCKETLAKE(dev_priv)); 102 /* CMP is CNP compatible */ 103 return PCH_CNP; 104 case INTEL_PCH_CMP_V_DEVICE_ID_TYPE: 105 drm_dbg_kms(&dev_priv->drm, "Found Comet Lake V PCH (CMP-V)\n"); 106 drm_WARN_ON(&dev_priv->drm, 107 !IS_COFFEELAKE(dev_priv) && 108 !IS_COMETLAKE(dev_priv)); 109 /* CMP-V is based on KBP, which is SPT compatible */ 110 return PCH_SPT; 111 case INTEL_PCH_ICP_DEVICE_ID_TYPE: 112 case INTEL_PCH_ICP2_DEVICE_ID_TYPE: 113 drm_dbg_kms(&dev_priv->drm, "Found Ice Lake PCH\n"); 114 drm_WARN_ON(&dev_priv->drm, !IS_ICELAKE(dev_priv)); 115 return PCH_ICP; 116 case INTEL_PCH_MCC_DEVICE_ID_TYPE: 117 drm_dbg_kms(&dev_priv->drm, "Found Mule Creek Canyon PCH\n"); 118 drm_WARN_ON(&dev_priv->drm, !(IS_JASPERLAKE(dev_priv) || 119 IS_ELKHARTLAKE(dev_priv))); 120 /* MCC is TGP compatible */ 121 return PCH_TGP; 122 case INTEL_PCH_TGP_DEVICE_ID_TYPE: 123 case INTEL_PCH_TGP2_DEVICE_ID_TYPE: 124 drm_dbg_kms(&dev_priv->drm, "Found Tiger Lake LP PCH\n"); 125 drm_WARN_ON(&dev_priv->drm, !IS_TIGERLAKE(dev_priv) && 126 !IS_ROCKETLAKE(dev_priv) && 127 !IS_GEN9_BC(dev_priv)); 128 return PCH_TGP; 129 case INTEL_PCH_JSP_DEVICE_ID_TYPE: 130 drm_dbg_kms(&dev_priv->drm, "Found Jasper Lake PCH\n"); 131 drm_WARN_ON(&dev_priv->drm, !(IS_JASPERLAKE(dev_priv) || 132 IS_ELKHARTLAKE(dev_priv))); 133 /* JSP is ICP compatible */ 134 return PCH_ICP; 135 case INTEL_PCH_ADP_DEVICE_ID_TYPE: 136 case INTEL_PCH_ADP2_DEVICE_ID_TYPE: 137 case INTEL_PCH_ADP3_DEVICE_ID_TYPE: 138 case INTEL_PCH_ADP4_DEVICE_ID_TYPE: 139 drm_dbg_kms(&dev_priv->drm, "Found Alder Lake PCH\n"); 140 drm_WARN_ON(&dev_priv->drm, !IS_ALDERLAKE_S(dev_priv) && 141 !IS_ALDERLAKE_P(dev_priv)); 142 return PCH_ADP; 143 case INTEL_PCH_MTP_DEVICE_ID_TYPE: 144 case INTEL_PCH_MTP2_DEVICE_ID_TYPE: 145 drm_dbg_kms(&dev_priv->drm, "Found Meteor Lake PCH\n"); 146 drm_WARN_ON(&dev_priv->drm, !IS_METEORLAKE(dev_priv)); 147 return PCH_MTP; 148 default: 149 return PCH_NONE; 150 } 151} 152 153static bool intel_is_virt_pch(unsigned short id, 154 unsigned short svendor, unsigned short sdevice) 155{ 156 return (id == INTEL_PCH_P2X_DEVICE_ID_TYPE || 157 id == INTEL_PCH_P3X_DEVICE_ID_TYPE || 158 (id == INTEL_PCH_QEMU_DEVICE_ID_TYPE && 159 svendor == PCI_SUBVENDOR_ID_REDHAT_QUMRANET && 160 sdevice == PCI_SUBDEVICE_ID_QEMU)); 161} 162 163static void 164intel_virt_detect_pch(const struct drm_i915_private *dev_priv, 165 unsigned short *pch_id, enum intel_pch *pch_type) 166{ 167 unsigned short id = 0; 168 169 /* 170 * In a virtualized passthrough environment we can be in a 171 * setup where the ISA bridge is not able to be passed through. 172 * In this case, a south bridge can be emulated and we have to 173 * make an educated guess as to which PCH is really there. 174 */ 175 176 if (IS_METEORLAKE(dev_priv)) 177 id = INTEL_PCH_MTP_DEVICE_ID_TYPE; 178 else if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) 179 id = INTEL_PCH_ADP_DEVICE_ID_TYPE; 180 else if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv)) 181 id = INTEL_PCH_TGP_DEVICE_ID_TYPE; 182 else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) 183 id = INTEL_PCH_MCC_DEVICE_ID_TYPE; 184 else if (IS_ICELAKE(dev_priv)) 185 id = INTEL_PCH_ICP_DEVICE_ID_TYPE; 186 else if (IS_COFFEELAKE(dev_priv) || 187 IS_COMETLAKE(dev_priv)) 188 id = INTEL_PCH_CNP_DEVICE_ID_TYPE; 189 else if (IS_KABYLAKE(dev_priv) || IS_SKYLAKE(dev_priv)) 190 id = INTEL_PCH_SPT_DEVICE_ID_TYPE; 191 else if (IS_HASWELL_ULT(dev_priv) || IS_BROADWELL_ULT(dev_priv)) 192 id = INTEL_PCH_LPT_LP_DEVICE_ID_TYPE; 193 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) 194 id = INTEL_PCH_LPT_DEVICE_ID_TYPE; 195 else if (GRAPHICS_VER(dev_priv) == 6 || IS_IVYBRIDGE(dev_priv)) 196 id = INTEL_PCH_CPT_DEVICE_ID_TYPE; 197 else if (GRAPHICS_VER(dev_priv) == 5) 198 id = INTEL_PCH_IBX_DEVICE_ID_TYPE; 199 200 if (id) 201 drm_dbg_kms(&dev_priv->drm, "Assuming PCH ID %04x\n", id); 202 else 203 drm_dbg_kms(&dev_priv->drm, "Assuming no PCH\n"); 204 205 *pch_type = intel_pch_type(dev_priv, id); 206 207 /* Sanity check virtual PCH id */ 208 if (drm_WARN_ON(&dev_priv->drm, 209 id && *pch_type == PCH_NONE)) 210 id = 0; 211 212 *pch_id = id; 213} 214 215static int 216intel_pch_match(struct pci_attach_args *pa) 217{ 218 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL && 219 PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 220 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_ISA) 221 return 1; 222 return 0; 223} 224 225void intel_detect_pch(struct drm_i915_private *dev_priv) 226{ 227 struct pci_attach_args pa; 228 unsigned short id; 229 enum intel_pch pch_type; 230 pcireg_t subsys; 231 232 /* DG1 has south engine display on the same PCI device */ 233 if (IS_DG1(dev_priv)) { 234 dev_priv->pch_type = PCH_DG1; 235 return; 236 } else if (IS_DG2(dev_priv)) { 237 dev_priv->pch_type = PCH_DG2; 238 return; 239 } 240 241 /* 242 * The reason to probe ISA bridge instead of Dev31:Fun0 is to 243 * make graphics device passthrough work easy for VMM, that only 244 * need to expose ISA bridge to let driver know the real hardware 245 * underneath. This is a requirement from virtualization team. 246 * 247 * In some virtualized environments (e.g. XEN), there is irrelevant 248 * ISA bridge in the system. To work reliably, we should scan trhough 249 * all the ISA bridge devices and check for the first match, instead 250 * of only checking the first one. 251 */ 252 if (pci_find_device(&pa, intel_pch_match)) { 253 id = PCI_PRODUCT(pa.pa_id) & INTEL_PCH_DEVICE_ID_MASK; 254 subsys = pci_conf_read(pa.pa_pc, pa.pa_tag, PCI_SUBSYS_ID_REG); 255 256 pch_type = intel_pch_type(dev_priv, id); 257 if (pch_type != PCH_NONE) { 258 dev_priv->pch_type = pch_type; 259 dev_priv->pch_id = id; 260 } else if (intel_is_virt_pch(id, PCI_VENDOR(subsys), 261 PCI_PRODUCT(subsys))) { 262 intel_virt_detect_pch(dev_priv, &id, &pch_type); 263 dev_priv->pch_type = pch_type; 264 dev_priv->pch_id = id; 265 } 266 } 267 268 /* 269 * Use PCH_NOP (PCH but no South Display) for PCH platforms without 270 * display. 271 */ 272 if (pci_find_device(&pa, intel_pch_match) && !HAS_DISPLAY(dev_priv)) { 273 drm_dbg_kms(&dev_priv->drm, 274 "Display disabled, reverting to NOP PCH\n"); 275 dev_priv->pch_type = PCH_NOP; 276 dev_priv->pch_id = 0; 277 } else if (!pci_find_device(&pa, intel_pch_match)) { 278 if (i915_run_as_guest() && HAS_DISPLAY(dev_priv)) { 279 intel_virt_detect_pch(dev_priv, &id, &pch_type); 280 dev_priv->pch_type = pch_type; 281 dev_priv->pch_id = id; 282 } else { 283 drm_dbg_kms(&dev_priv->drm, "No PCH found.\n"); 284 } 285 } 286 287 pci_dev_put(pch); 288} 289