1231990Smp/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 259243Sobrien */ 359243Sobrien/* 459243Sobrien * 559243Sobrien * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 659243Sobrien * All Rights Reserved. 759243Sobrien * 859243Sobrien * Permission is hereby granted, free of charge, to any person obtaining a 959243Sobrien * copy of this software and associated documentation files (the 1059243Sobrien * "Software"), to deal in the Software without restriction, including 1159243Sobrien * without limitation the rights to use, copy, modify, merge, publish, 1259243Sobrien * distribute, sub license, and/or sell copies of the Software, and to 1359243Sobrien * permit persons to whom the Software is furnished to do so, subject to 1459243Sobrien * the following conditions: 1559243Sobrien * 1659243Sobrien * The above copyright notice and this permission notice (including the 17100616Smp * next paragraph) shall be included in all copies or substantial portions 1859243Sobrien * of the Software. 1959243Sobrien * 2059243Sobrien * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 2159243Sobrien * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 2259243Sobrien * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 2359243Sobrien * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 2459243Sobrien * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 2559243Sobrien * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 2659243Sobrien * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 2759243Sobrien * 2859243Sobrien */ 2959243Sobrien 3059243Sobrien#ifndef _I915_DRV_H_ 3159243Sobrien#define _I915_DRV_H_ 3259243Sobrien 3359243Sobrien#include <uapi/drm/i915_drm.h> 3459243Sobrien 35231990Smp#include <linux/pm_qos.h> 3659243Sobrien 3759243Sobrien#include <drm/ttm/ttm_device.h> 3859243Sobrien 3959243Sobrien#include "vga.h" 40167465Smp 41167465Smpstruct inteldrm_softc; 42167465Smp#define drm_i915_private inteldrm_softc 43167465Smp 44167465Smp#include "display/intel_display_limits.h" 45167465Smp#include "display/intel_display_core.h" 46167465Smp 47167465Smp#include "gem/i915_gem_context_types.h" 48167465Smp#include "gem/i915_gem_shrinker.h" 49167465Smp#include "gem/i915_gem_stolen.h" 5059243Sobrien 5159243Sobrien#include "gt/intel_engine.h" 5259243Sobrien#include "gt/intel_gt_types.h" 5359243Sobrien#include "gt/intel_region_lmem.h" 5459243Sobrien#include "gt/intel_workarounds.h" 5559243Sobrien#include "gt/uc/intel_uc.h" 5659243Sobrien 5759243Sobrien#include "soc/intel_pch.h" 5859243Sobrien 5959243Sobrien#include "i915_drm_client.h" 6059243Sobrien#include "i915_gem.h" 61167465Smp#include "i915_gpu_error.h" 6259243Sobrien#include "i915_params.h" 63167465Smp#include "i915_perf_types.h" 6459243Sobrien#include "i915_scheduler.h" 6559243Sobrien#include "i915_utils.h" 6659243Sobrien#include "intel_device_info.h" 67167465Smp#include "intel_memory_region.h" 68167465Smp#include "intel_runtime_pm.h" 69167465Smp#include "intel_step.h" 70167465Smp#include "intel_uncore.h" 7159243Sobrien 7259243Sobrien#include "drm.h" 73167465Smp 74167465Smp#include <dev/ic/mc6845reg.h> 7559243Sobrien#include <dev/ic/pcdisplayvar.h> 76167465Smp#include <dev/ic/vgareg.h> 77167465Smp#include <dev/ic/vgavar.h> 78167465Smp 79167465Smp#include <sys/task.h> 80167465Smp#include <dev/pci/vga_pcivar.h> 81167465Smp#include <dev/wscons/wsconsio.h> 8259243Sobrien#include <dev/wscons/wsdisplayvar.h> 8359243Sobrien#include <dev/rasops/rasops.h> 84167465Smp 85167465Smpstruct drm_i915_clock_gating_funcs; 8659243Sobrienstruct vlv_s0ix_state; 87145479Smpstruct intel_pxp; 88145479Smp 8959243Sobrien#define GEM_QUIRK_PIN_SWIZZLED_PAGES BIT(0) 9059243Sobrien 9159243Sobrien/* Data Stolen Memory (DSM) aka "i915 stolen memory" */ 9259243Sobrienstruct i915_dsm { 9359243Sobrien /* 9459243Sobrien * The start and end of DSM which we can optionally use to create GEM 9559243Sobrien * objects backed by stolen memory. 9659243Sobrien * 9759243Sobrien * Note that usable_size tells us exactly how much of this we are 9859243Sobrien * actually allowed to use, given that some portion of it is in fact 9959243Sobrien * reserved for use by hardware functions. 10059243Sobrien */ 10159243Sobrien struct resource stolen; 10259243Sobrien 10359243Sobrien /* 10459243Sobrien * Reserved portion of DSM. 10559243Sobrien */ 10659243Sobrien struct resource reserved; 10759243Sobrien 10859243Sobrien /* 10959243Sobrien * Total size minus reserved ranges. 11059243Sobrien * 11159243Sobrien * DSM is segmented in hardware with different portions offlimits to 11259243Sobrien * certain functions. 11359243Sobrien * 114167465Smp * The drm_mm is initialised to the total accessible range, as found 115167465Smp * from the PCI config. On Broadwell+, this is further restricted to 116167465Smp * avoid the first page! The upper end of DSM is reserved for hardware 11759243Sobrien * functions and similarly removed from the accessible range. 11859243Sobrien */ 11959243Sobrien resource_size_t usable_size; 12059243Sobrien}; 12159243Sobrien 122167465Smpstruct i915_suspend_saved_registers { 123167465Smp u32 saveDSPARB; 12459243Sobrien u32 saveSWF0[16]; 12559243Sobrien u32 saveSWF1[16]; 12659243Sobrien u32 saveSWF3[3]; 127167465Smp u16 saveGCDGMBUS; 12859243Sobrien}; 129167465Smp 130167465Smp#define MAX_L3_SLICES 2 131167465Smpstruct intel_l3_parity { 132167465Smp u32 *remap_info[MAX_L3_SLICES]; 133167465Smp struct work_struct error_work; 134167465Smp int which_slice; 135167465Smp}; 136167465Smp 137167465Smpstruct i915_gem_mm { 138145479Smp /* 13959243Sobrien * Shortcut for the stolen region. This points to either 140145479Smp * INTEL_REGION_STOLEN_SMEM for integrated platforms, or 14159243Sobrien * INTEL_REGION_STOLEN_LMEM for discrete, or NULL if the device doesn't 14259243Sobrien * support stolen. 143167465Smp */ 14459243Sobrien struct intel_memory_region *stolen_region; 14559243Sobrien /** Memory allocator for GTT stolen memory */ 14659243Sobrien struct drm_mm stolen; 147167465Smp /** Protects the usage of the GTT stolen memory allocator. This is 14859243Sobrien * always the inner lock when overlapping with struct_mutex. */ 149167465Smp struct rwlock stolen_lock; 150167465Smp 15159243Sobrien /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */ 15259243Sobrien spinlock_t obj_lock; 15359243Sobrien 154167465Smp /** 15559243Sobrien * List of objects which are purgeable. 15659243Sobrien */ 15759243Sobrien struct list_head purge_list; 158167465Smp 15959243Sobrien /** 160167465Smp * List of objects which have allocated pages and are shrinkable. 16159243Sobrien */ 16259243Sobrien struct list_head shrink_list; 16359243Sobrien 16459243Sobrien /** 16559243Sobrien * List of objects which are pending destruction. 16659243Sobrien */ 16759243Sobrien struct llist_head free_list; 16859243Sobrien struct work_struct free_work; 169167465Smp /** 17059243Sobrien * Count of objects pending destructions. Used to skip needlessly 17159243Sobrien * waiting on an RCU barrier if no objects are waiting to be freed. 17259243Sobrien */ 17359243Sobrien atomic_t free_count; 17459243Sobrien 17559243Sobrien /** 17659243Sobrien * tmpfs instance used for shmem backed objects 177167465Smp */ 178167465Smp struct vfsmount *gemfs; 17959243Sobrien 180167465Smp struct intel_memory_region *regions[INTEL_REGION_UNKNOWN]; 18159243Sobrien 18259243Sobrien struct notifier_block oom_notifier; 18359243Sobrien struct notifier_block vmap_notifier; 184167465Smp struct shrinker shrinker; 18559243Sobrien 186145479Smp#ifdef CONFIG_MMU_NOTIFIER 18759243Sobrien /** 18859243Sobrien * notifier_lock for mmu notifiers, memory may not be allocated 189167465Smp * while holding this lock. 19059243Sobrien */ 191167465Smp rwlock_t notifier_lock; 19259243Sobrien#endif 19359243Sobrien 19459243Sobrien /* shrinker accounting, also useful for userland debugging */ 19559243Sobrien u64 shrink_memory; 19659243Sobrien u32 shrink_count; 19759243Sobrien}; 19859243Sobrien 19959243Sobrienstruct i915_virtual_gpu { 20059243Sobrien struct rwlock lock; /* serialises sending of g2v_notify command pkts */ 20159243Sobrien bool active; 20259243Sobrien u32 caps; 20359243Sobrien u32 *initial_mmio; 20459243Sobrien u8 *initial_cfg_space; 20559243Sobrien struct list_head entry; 20659243Sobrien}; 20759243Sobrien 20859243Sobrienstruct i915_selftest_stash { 209167465Smp atomic_t counter; 21059243Sobrien struct ida mock_region_instances; 21159243Sobrien}; 21259243Sobrien 21359243Sobrien 21459243Sobrienstruct inteldrm_softc { 21559243Sobrien#ifdef __OpenBSD__ 21659243Sobrien struct device sc_dev; 21759243Sobrien bus_dma_tag_t dmat; 21859243Sobrien bus_space_tag_t iot; 21959243Sobrien bus_space_tag_t bst; 22059243Sobrien bus_space_handle_t opregion_ioh; 22159243Sobrien bus_space_handle_t opregion_rvda_ioh; 22259243Sobrien bus_size_t opregion_rvda_size; 22359243Sobrien#endif 22459243Sobrien 22559243Sobrien struct drm_device drm; 226167465Smp 22759243Sobrien struct intel_display display; 228167465Smp 229145479Smp /* FIXME: Device release actions should all be moved to drmm_ */ 23059243Sobrien bool do_release; 23159243Sobrien 23259243Sobrien /* i915 device parameters */ 23359243Sobrien struct i915_params params; 23459243Sobrien 23559243Sobrien const struct intel_device_info *__info; /* Use INTEL_INFO() to access. */ 23659243Sobrien struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */ 23759243Sobrien struct intel_driver_caps caps; 23859243Sobrien 23959243Sobrien struct i915_dsm dsm; 24059243Sobrien 24159243Sobrien#ifdef __OpenBSD__ 24259243Sobrien struct pci_attach_args *pa; 24359243Sobrien pci_chipset_tag_t pc; 24459243Sobrien pcitag_t tag; 24559243Sobrien struct extent *memex; 24659243Sobrien pci_intr_handle_t ih; 24759243Sobrien irqreturn_t(*irq_handler) (int, void *); 24859243Sobrien void *irqh; 24959243Sobrien 25059243Sobrien struct vga_pci_bar bar; 25159243Sobrien struct vga_pci_bar *vga_regs; 25259243Sobrien 25359243Sobrien const struct pci_device_id *id; 25459243Sobrien 25559243Sobrien int console; 25659243Sobrien int primary; 25759243Sobrien int nscreens; 25859243Sobrien void (*switchcb)(void *, int, int); 25959243Sobrien void *switchcbarg; 26059243Sobrien void *switchcookie; 26159243Sobrien struct task switchtask; 26259243Sobrien struct rasops_info ro; 26359243Sobrien 26459243Sobrien struct task burner_task; 265167465Smp int burner_fblank; 26659243Sobrien 26759243Sobrien struct backlight_device *backlight; 26859243Sobrien 26959243Sobrien union flush { 27059243Sobrien struct { 27159243Sobrien bus_space_tag_t bst; 27259243Sobrien bus_space_handle_t bsh; 273167465Smp } i9xx; 27459243Sobrien struct { 27559243Sobrien bus_dma_segment_t seg; 27659243Sobrien caddr_t kva; 27759243Sobrien } i8xx; 27859243Sobrien } ifp; 27959243Sobrien struct vm_page *pgs; 28059243Sobrien#endif 28159243Sobrien 28259243Sobrien struct intel_uncore uncore; 28359243Sobrien struct intel_uncore_mmio_debug mmio_debug; 28459243Sobrien 28559243Sobrien struct i915_virtual_gpu vgpu; 28659243Sobrien 28759243Sobrien struct intel_gvt *gvt; 28859243Sobrien 28959243Sobrien struct { 29059243Sobrien struct pci_dev *pdev; 29159243Sobrien struct resource mch_res; 29259243Sobrien bool mchbar_need_disable; 29359243Sobrien } gmch; 294167465Smp 29559243Sobrien struct rb_root uabi_engines; 296167465Smp unsigned int engine_uabi_class_count[I915_LAST_UABI_ENGINE_CLASS + 1]; 297145479Smp 29859243Sobrien /* protects the irq masks */ 29959243Sobrien spinlock_t irq_lock; 30059243Sobrien 30159243Sobrien bool display_irqs_enabled; 30259243Sobrien 30359243Sobrien /* Sideband mailbox protection */ 30459243Sobrien struct rwlock sb_lock; 30559243Sobrien struct pm_qos_request sb_qos; 30659243Sobrien 30759243Sobrien /** Cached value of IMR to avoid reads in updating the bitfield */ 30859243Sobrien union { 30959243Sobrien u32 irq_mask; 31059243Sobrien u32 de_irq_mask[I915_MAX_PIPES]; 31159243Sobrien }; 31259243Sobrien u32 pipestat_irq_mask[I915_MAX_PIPES]; 31359243Sobrien 31459243Sobrien bool preserve_bios_swizzle; 31559243Sobrien 316167465Smp unsigned int fsb_freq, mem_freq, is_ddr3; 31759243Sobrien unsigned int skl_preferred_vco_freq; 31859243Sobrien 31959243Sobrien unsigned int max_dotclk_freq; 32059243Sobrien unsigned int hpll_freq; 32159243Sobrien unsigned int czclk_freq; 32259243Sobrien 32359243Sobrien /** 32459243Sobrien * wq - Driver workqueue for GEM. 32559243Sobrien * 32659243Sobrien * NOTE: Work items scheduled here are not allowed to grab any modeset 32759243Sobrien * locks, for otherwise the flushing done in the pageflip code will 32859243Sobrien * result in deadlocks. 32959243Sobrien */ 33059243Sobrien struct workqueue_struct *wq; 33159243Sobrien 33259243Sobrien /** 33359243Sobrien * unordered_wq - internal workqueue for unordered work 33459243Sobrien * 33559243Sobrien * This workqueue should be used for all unordered work 336167465Smp * scheduling within i915, which used to be scheduled on the 33759243Sobrien * system_wq before moving to a driver instance due 338167465Smp * deprecation of flush_scheduled_work(). 339145479Smp */ 340145479Smp struct workqueue_struct *unordered_wq; 34159243Sobrien 34259243Sobrien /* pm private clock gating functions */ 34359243Sobrien const struct drm_i915_clock_gating_funcs *clock_gating_funcs; 34459243Sobrien 34559243Sobrien /* PCH chipset type */ 34659243Sobrien enum intel_pch pch_type; 34759243Sobrien unsigned short pch_id; 34859243Sobrien 34959243Sobrien unsigned long gem_quirks; 35059243Sobrien 35159243Sobrien struct i915_gem_mm mm; 35259243Sobrien 35359243Sobrien struct intel_l3_parity l3_parity; 35459243Sobrien 35559243Sobrien /* 35659243Sobrien * edram size in MB. 357167465Smp * Cannot be determined by PCIID. You must always read a register. 35859243Sobrien */ 35959243Sobrien u32 edram_size_mb; 36059243Sobrien 36159243Sobrien struct i915_gpu_error gpu_error; 36259243Sobrien 36359243Sobrien u32 suspend_count; 36459243Sobrien struct i915_suspend_saved_registers regfile; 36559243Sobrien struct vlv_s0ix_state *vlv_s0ix_state; 36659243Sobrien 36759243Sobrien struct dram_info { 36859243Sobrien bool wm_lv_0_adjust_needed; 36959243Sobrien u8 num_channels; 37059243Sobrien bool symmetric_memory; 37159243Sobrien enum intel_dram_type { 37259243Sobrien INTEL_DRAM_UNKNOWN, 37359243Sobrien INTEL_DRAM_DDR3, 37459243Sobrien INTEL_DRAM_DDR4, 37559243Sobrien INTEL_DRAM_LPDDR3, 37659243Sobrien INTEL_DRAM_LPDDR4, 37759243Sobrien INTEL_DRAM_DDR5, 378167465Smp INTEL_DRAM_LPDDR5, 37959243Sobrien } type; 380167465Smp u8 num_qgv_points; 381145479Smp u8 num_psf_gv_points; 382145479Smp } dram_info; 38359243Sobrien 38459243Sobrien struct intel_runtime_pm runtime_pm; 38559243Sobrien 38659243Sobrien struct i915_perf perf; 38759243Sobrien 38859243Sobrien struct i915_hwmon *hwmon; 38959243Sobrien 39059243Sobrien /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */ 39159243Sobrien struct intel_gt gt0; 39259243Sobrien 39359243Sobrien /* 39459243Sobrien * i915->gt[0] == &i915->gt0 39559243Sobrien */ 39659243Sobrien struct intel_gt *gt[I915_MAX_GT]; 397167465Smp 39859243Sobrien struct kobject *sysfs_gt; 39959243Sobrien 40059243Sobrien /* Quick lookup of media GT (current platforms only have one) */ 40159243Sobrien struct intel_gt *media_gt; 40259243Sobrien 40359243Sobrien struct { 40459243Sobrien struct i915_gem_contexts { 40559243Sobrien spinlock_t lock; /* locks list */ 40659243Sobrien struct list_head list; 40759243Sobrien } contexts; 40859243Sobrien 40959243Sobrien /* 41059243Sobrien * We replace the local file with a global mappings as the 41159243Sobrien * backing storage for the mmap is on the device and not 41259243Sobrien * on the struct file, and we do not want to prolong the 41359243Sobrien * lifetime of the local fd. To minimise the number of 41459243Sobrien * anonymous inodes we create, we use a global singleton to 41559243Sobrien * share the global mapping. 41659243Sobrien */ 41759243Sobrien struct file *mmap_singleton; 41859243Sobrien } gem; 419167465Smp 42059243Sobrien struct intel_pxp *pxp; 421167465Smp 422145479Smp /* For i915gm/i945gm vblank irq workaround */ 423145479Smp u8 vblank_enabled; 42459243Sobrien 42559243Sobrien bool irq_enabled; 42659243Sobrien 42759243Sobrien struct i915_pmu pmu; 42859243Sobrien 42959243Sobrien /* The TTM device structure. */ 43059243Sobrien struct ttm_device bdev; 43159243Sobrien 43259243Sobrien I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;) 43359243Sobrien 43459243Sobrien /* 43559243Sobrien * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch 43659243Sobrien * will be rejected. Instead look for a better place. 43759243Sobrien */ 43859243Sobrien}; 43959243Sobrien 440167465Smpstatic inline struct drm_i915_private *to_i915(const struct drm_device *dev) 44159243Sobrien{ 44259243Sobrien return container_of(dev, struct drm_i915_private, drm); 44359243Sobrien} 44459243Sobrien 44559243Sobrienstatic inline struct drm_i915_private *kdev_to_i915(struct device *kdev) 44659243Sobrien{ 44759243Sobrien return dev_get_drvdata(kdev); 44859243Sobrien} 44959243Sobrien 45059243Sobrienstatic inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev) 45159243Sobrien{ 45259243Sobrien STUB(); 45359243Sobrien return NULL; 45459243Sobrien#ifdef notyet 45559243Sobrien return pci_get_drvdata(pdev); 45659243Sobrien#endif 45759243Sobrien} 45859243Sobrien 45959243Sobrienstatic inline struct intel_gt *to_gt(struct drm_i915_private *i915) 460167465Smp{ 46159243Sobrien return &i915->gt0; 46259243Sobrien} 46359243Sobrien 46459243Sobrien/* Simple iterator over all initialised engines */ 46559243Sobrien#define for_each_engine(engine__, gt__, id__) \ 46659243Sobrien for ((id__) = 0; \ 46759243Sobrien (id__) < I915_NUM_ENGINES; \ 46859243Sobrien (id__)++) \ 46959243Sobrien for_each_if ((engine__) = (gt__)->engine[(id__)]) 47059243Sobrien 471167465Smp/* Iterator over subset of engines selected by mask */ 47259243Sobrien#define for_each_engine_masked(engine__, gt__, mask__, tmp__) \ 473167465Smp for ((tmp__) = (mask__) & (gt__)->info.engine_mask; \ 474167465Smp (tmp__) ? \ 475145479Smp ((engine__) = (gt__)->engine[__mask_next_bit(tmp__)]), 1 : \ 476145479Smp 0;) 47759243Sobrien 47859243Sobrien#define rb_to_uabi_engine(rb) \ 479145479Smp rb_entry_safe(rb, struct intel_engine_cs, uabi_node) 48059243Sobrien 48159243Sobrien#define for_each_uabi_engine(engine__, i915__) \ 48259243Sobrien for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\ 48359243Sobrien (engine__); \ 48459243Sobrien (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node))) 48559243Sobrien 48659243Sobrien#define for_each_uabi_class_engine(engine__, class__, i915__) \ 48759243Sobrien for ((engine__) = intel_engine_lookup_user((i915__), (class__), 0); \ 48859243Sobrien (engine__) && (engine__)->uabi_class == (class__); \ 48959243Sobrien (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node))) 49059243Sobrien 49159243Sobrien#define INTEL_INFO(i915) ((i915)->__info) 49259243Sobrien#define RUNTIME_INFO(i915) (&(i915)->__runtime) 49359243Sobrien#define DISPLAY_INFO(i915) ((i915)->display.info.__device_info) 49459243Sobrien#define DISPLAY_RUNTIME_INFO(i915) (&(i915)->display.info.__runtime_info) 49559243Sobrien#define DRIVER_CAPS(i915) (&(i915)->caps) 49659243Sobrien 49759243Sobrien#define INTEL_DEVID(i915) (RUNTIME_INFO(i915)->device_id) 49859243Sobrien 49959243Sobrien#define IP_VER(ver, rel) ((ver) << 8 | (rel)) 50059243Sobrien 50159243Sobrien#define GRAPHICS_VER(i915) (RUNTIME_INFO(i915)->graphics.ip.ver) 50259243Sobrien#define GRAPHICS_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->graphics.ip.ver, \ 50359243Sobrien RUNTIME_INFO(i915)->graphics.ip.rel) 50459243Sobrien#define IS_GRAPHICS_VER(i915, from, until) \ 50559243Sobrien (GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until)) 50659243Sobrien 50759243Sobrien#define MEDIA_VER(i915) (RUNTIME_INFO(i915)->media.ip.ver) 50859243Sobrien#define MEDIA_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->media.ip.ver, \ 50959243Sobrien RUNTIME_INFO(i915)->media.ip.rel) 51059243Sobrien#define IS_MEDIA_VER(i915, from, until) \ 51159243Sobrien (MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until)) 51259243Sobrien 51359243Sobrien#define DISPLAY_VER(i915) (DISPLAY_RUNTIME_INFO(i915)->ip.ver) 51459243Sobrien#define IS_DISPLAY_VER(i915, from, until) \ 51559243Sobrien (DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until)) 51659243Sobrien 51759243Sobrien#define INTEL_REVID(i915) ((i915)->drm.pdev->revision) 51859243Sobrien 51959243Sobrien#define INTEL_DISPLAY_STEP(__i915) (RUNTIME_INFO(__i915)->step.display_step) 52059243Sobrien#define INTEL_GRAPHICS_STEP(__i915) (RUNTIME_INFO(__i915)->step.graphics_step) 52159243Sobrien#define INTEL_MEDIA_STEP(__i915) (RUNTIME_INFO(__i915)->step.media_step) 52259243Sobrien#define INTEL_BASEDIE_STEP(__i915) (RUNTIME_INFO(__i915)->step.basedie_step) 52359243Sobrien 52459243Sobrien#define IS_DISPLAY_STEP(__i915, since, until) \ 52559243Sobrien (drm_WARN_ON(&(__i915)->drm, INTEL_DISPLAY_STEP(__i915) == STEP_NONE), \ 52659243Sobrien INTEL_DISPLAY_STEP(__i915) >= (since) && INTEL_DISPLAY_STEP(__i915) < (until)) 52759243Sobrien 52859243Sobrien#define IS_GRAPHICS_STEP(__i915, since, until) \ 52959243Sobrien (drm_WARN_ON(&(__i915)->drm, INTEL_GRAPHICS_STEP(__i915) == STEP_NONE), \ 53059243Sobrien INTEL_GRAPHICS_STEP(__i915) >= (since) && INTEL_GRAPHICS_STEP(__i915) < (until)) 53159243Sobrien 53259243Sobrien#define IS_MEDIA_STEP(__i915, since, until) \ 53359243Sobrien (drm_WARN_ON(&(__i915)->drm, INTEL_MEDIA_STEP(__i915) == STEP_NONE), \ 53459243Sobrien INTEL_MEDIA_STEP(__i915) >= (since) && INTEL_MEDIA_STEP(__i915) < (until)) 53559243Sobrien 53659243Sobrien#define IS_BASEDIE_STEP(__i915, since, until) \ 53759243Sobrien (drm_WARN_ON(&(__i915)->drm, INTEL_BASEDIE_STEP(__i915) == STEP_NONE), \ 53859243Sobrien INTEL_BASEDIE_STEP(__i915) >= (since) && INTEL_BASEDIE_STEP(__i915) < (until)) 53959243Sobrien 54059243Sobrienstatic __always_inline unsigned int 54159243Sobrien__platform_mask_index(const struct intel_runtime_info *info, 54259243Sobrien enum intel_platform p) 54359243Sobrien{ 544167465Smp const unsigned int pbits = 545167465Smp BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS; 54659243Sobrien 54759243Sobrien /* Expand the platform_mask array if this fails. */ 54859243Sobrien BUILD_BUG_ON(INTEL_MAX_PLATFORMS > 54959243Sobrien pbits * ARRAY_SIZE(info->platform_mask)); 55059243Sobrien 55159243Sobrien return p / pbits; 55259243Sobrien} 55359243Sobrien 55459243Sobrienstatic __always_inline unsigned int 55559243Sobrien__platform_mask_bit(const struct intel_runtime_info *info, 55659243Sobrien enum intel_platform p) 55759243Sobrien{ 55859243Sobrien const unsigned int pbits = 55959243Sobrien BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS; 56059243Sobrien 56159243Sobrien return p % pbits + INTEL_SUBPLATFORM_BITS; 56259243Sobrien} 56359243Sobrien 56459243Sobrienstatic inline u32 56559243Sobrienintel_subplatform(const struct intel_runtime_info *info, enum intel_platform p) 56659243Sobrien{ 56759243Sobrien const unsigned int pi = __platform_mask_index(info, p); 56859243Sobrien 56959243Sobrien return info->platform_mask[pi] & INTEL_SUBPLATFORM_MASK; 57059243Sobrien} 57159243Sobrien 57259243Sobrienstatic __always_inline bool 57359243SobrienIS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p) 57459243Sobrien{ 57559243Sobrien const struct intel_runtime_info *info = RUNTIME_INFO(i915); 57659243Sobrien const unsigned int pi = __platform_mask_index(info, p); 57759243Sobrien const unsigned int pb = __platform_mask_bit(info, p); 57859243Sobrien 57959243Sobrien#ifdef notyet 58059243Sobrien BUILD_BUG_ON(!__builtin_constant_p(p)); 58159243Sobrien#endif 58259243Sobrien 58359243Sobrien return info->platform_mask[pi] & BIT(pb); 58459243Sobrien} 58559243Sobrien 58659243Sobrienstatic __always_inline bool 58759243SobrienIS_SUBPLATFORM(const struct drm_i915_private *i915, 58859243Sobrien enum intel_platform p, unsigned int s) 58959243Sobrien{ 59059243Sobrien const struct intel_runtime_info *info = RUNTIME_INFO(i915); 59159243Sobrien const unsigned int pi = __platform_mask_index(info, p); 59259243Sobrien const unsigned int pb = __platform_mask_bit(info, p); 59359243Sobrien const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1; 59459243Sobrien const u32 mask = info->platform_mask[pi]; 59559243Sobrien 59659243Sobrien#ifdef notyet 59759243Sobrien BUILD_BUG_ON(!__builtin_constant_p(p)); 59859243Sobrien BUILD_BUG_ON(!__builtin_constant_p(s)); 59959243Sobrien BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS); 60059243Sobrien#endif 60159243Sobrien 60259243Sobrien /* Shift and test on the MSB position so sign flag can be used. */ 60359243Sobrien return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb); 60459243Sobrien} 60559243Sobrien 60659243Sobrien#define IS_MOBILE(i915) (INTEL_INFO(i915)->is_mobile) 60759243Sobrien#define IS_DGFX(i915) (INTEL_INFO(i915)->is_dgfx) 60859243Sobrien 60959243Sobrien#define IS_I830(i915) IS_PLATFORM(i915, INTEL_I830) 61059243Sobrien#define IS_I845G(i915) IS_PLATFORM(i915, INTEL_I845G) 61159243Sobrien#define IS_I85X(i915) IS_PLATFORM(i915, INTEL_I85X) 61259243Sobrien#define IS_I865G(i915) IS_PLATFORM(i915, INTEL_I865G) 61359243Sobrien#define IS_I915G(i915) IS_PLATFORM(i915, INTEL_I915G) 61459243Sobrien#define IS_I915GM(i915) IS_PLATFORM(i915, INTEL_I915GM) 61559243Sobrien#define IS_I945G(i915) IS_PLATFORM(i915, INTEL_I945G) 61659243Sobrien#define IS_I945GM(i915) IS_PLATFORM(i915, INTEL_I945GM) 61759243Sobrien#define IS_I965G(i915) IS_PLATFORM(i915, INTEL_I965G) 61859243Sobrien#define IS_I965GM(i915) IS_PLATFORM(i915, INTEL_I965GM) 61959243Sobrien#define IS_G45(i915) IS_PLATFORM(i915, INTEL_G45) 62059243Sobrien#define IS_GM45(i915) IS_PLATFORM(i915, INTEL_GM45) 62159243Sobrien#define IS_G4X(i915) (IS_G45(i915) || IS_GM45(i915)) 62259243Sobrien#define IS_PINEVIEW(i915) IS_PLATFORM(i915, INTEL_PINEVIEW) 62359243Sobrien#define IS_G33(i915) IS_PLATFORM(i915, INTEL_G33) 62459243Sobrien#define IS_IRONLAKE(i915) IS_PLATFORM(i915, INTEL_IRONLAKE) 62559243Sobrien#define IS_IRONLAKE_M(i915) \ 62659243Sobrien (IS_PLATFORM(i915, INTEL_IRONLAKE) && IS_MOBILE(i915)) 62759243Sobrien#define IS_SANDYBRIDGE(i915) IS_PLATFORM(i915, INTEL_SANDYBRIDGE) 62859243Sobrien#define IS_IVYBRIDGE(i915) IS_PLATFORM(i915, INTEL_IVYBRIDGE) 62959243Sobrien#define IS_IVB_GT1(i915) (IS_IVYBRIDGE(i915) && \ 63059243Sobrien INTEL_INFO(i915)->gt == 1) 63159243Sobrien#define IS_VALLEYVIEW(i915) IS_PLATFORM(i915, INTEL_VALLEYVIEW) 63259243Sobrien#define IS_CHERRYVIEW(i915) IS_PLATFORM(i915, INTEL_CHERRYVIEW) 63359243Sobrien#define IS_HASWELL(i915) IS_PLATFORM(i915, INTEL_HASWELL) 63459243Sobrien#define IS_BROADWELL(i915) IS_PLATFORM(i915, INTEL_BROADWELL) 63559243Sobrien#define IS_SKYLAKE(i915) IS_PLATFORM(i915, INTEL_SKYLAKE) 63659243Sobrien#define IS_BROXTON(i915) IS_PLATFORM(i915, INTEL_BROXTON) 63759243Sobrien#define IS_KABYLAKE(i915) IS_PLATFORM(i915, INTEL_KABYLAKE) 63859243Sobrien#define IS_GEMINILAKE(i915) IS_PLATFORM(i915, INTEL_GEMINILAKE) 63959243Sobrien#define IS_COFFEELAKE(i915) IS_PLATFORM(i915, INTEL_COFFEELAKE) 64059243Sobrien#define IS_COMETLAKE(i915) IS_PLATFORM(i915, INTEL_COMETLAKE) 64159243Sobrien#define IS_ICELAKE(i915) IS_PLATFORM(i915, INTEL_ICELAKE) 64259243Sobrien#define IS_JASPERLAKE(i915) IS_PLATFORM(i915, INTEL_JASPERLAKE) 64359243Sobrien#define IS_ELKHARTLAKE(i915) IS_PLATFORM(i915, INTEL_ELKHARTLAKE) 64459243Sobrien#define IS_TIGERLAKE(i915) IS_PLATFORM(i915, INTEL_TIGERLAKE) 64559243Sobrien#define IS_ROCKETLAKE(i915) IS_PLATFORM(i915, INTEL_ROCKETLAKE) 64659243Sobrien#define IS_DG1(i915) IS_PLATFORM(i915, INTEL_DG1) 64759243Sobrien#define IS_ALDERLAKE_S(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_S) 64859243Sobrien#define IS_ALDERLAKE_P(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_P) 64959243Sobrien#define IS_XEHPSDV(i915) IS_PLATFORM(i915, INTEL_XEHPSDV) 650167465Smp#define IS_DG2(i915) IS_PLATFORM(i915, INTEL_DG2) 65159243Sobrien#define IS_PONTEVECCHIO(i915) IS_PLATFORM(i915, INTEL_PONTEVECCHIO) 652145479Smp#define IS_METEORLAKE(i915) IS_PLATFORM(i915, INTEL_METEORLAKE) 65359243Sobrien 65459243Sobrien#define IS_METEORLAKE_M(i915) \ 65559243Sobrien IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_M) 65659243Sobrien#define IS_METEORLAKE_P(i915) \ 65759243Sobrien IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_P) 65859243Sobrien#define IS_DG2_G10(i915) \ 65959243Sobrien IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G10) 660167465Smp#define IS_DG2_G11(i915) \ 661167465Smp IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G11) 662167465Smp#define IS_DG2_G12(i915) \ 663167465Smp IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G12) 66459243Sobrien#define IS_RAPTORLAKE_S(i915) \ 66559243Sobrien IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL) 66659243Sobrien#define IS_ALDERLAKE_P_N(i915) \ 667167465Smp IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N) 668167465Smp#define IS_RAPTORLAKE_P(i915) \ 66959243Sobrien IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL) 67059243Sobrien#define IS_RAPTORLAKE_U(i915) \ 67159243Sobrien IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU) 67259243Sobrien#define IS_HASWELL_EARLY_SDV(i915) (IS_HASWELL(i915) && \ 67359243Sobrien (INTEL_DEVID(i915) & 0xFF00) == 0x0C00) 67459243Sobrien#define IS_BROADWELL_ULT(i915) \ 67559243Sobrien IS_SUBPLATFORM(i915, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT) 67659243Sobrien#define IS_BROADWELL_ULX(i915) \ 67759243Sobrien IS_SUBPLATFORM(i915, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX) 67859243Sobrien#define IS_BROADWELL_GT3(i915) (IS_BROADWELL(i915) && \ 67959243Sobrien INTEL_INFO(i915)->gt == 3) 680231990Smp#define IS_HASWELL_ULT(i915) \ 681231990Smp IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT) 682231990Smp#define IS_HASWELL_GT3(i915) (IS_HASWELL(i915) && \ 683167465Smp INTEL_INFO(i915)->gt == 3) 68459243Sobrien#define IS_HASWELL_GT1(i915) (IS_HASWELL(i915) && \ 685167465Smp INTEL_INFO(i915)->gt == 1) 686167465Smp/* ULX machines are also considered ULT. */ 687167465Smp#define IS_HASWELL_ULX(i915) \ 688167465Smp IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX) 689167465Smp#define IS_SKYLAKE_ULT(i915) \ 690167465Smp IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT) 691167465Smp#define IS_SKYLAKE_ULX(i915) \ 692167465Smp IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX) 693167465Smp#define IS_KABYLAKE_ULT(i915) \ 694 IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT) 695#define IS_KABYLAKE_ULX(i915) \ 696 IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX) 697#define IS_SKYLAKE_GT2(i915) (IS_SKYLAKE(i915) && \ 698 INTEL_INFO(i915)->gt == 2) 699#define IS_SKYLAKE_GT3(i915) (IS_SKYLAKE(i915) && \ 700 INTEL_INFO(i915)->gt == 3) 701#define IS_SKYLAKE_GT4(i915) (IS_SKYLAKE(i915) && \ 702 INTEL_INFO(i915)->gt == 4) 703#define IS_KABYLAKE_GT2(i915) (IS_KABYLAKE(i915) && \ 704 INTEL_INFO(i915)->gt == 2) 705#define IS_KABYLAKE_GT3(i915) (IS_KABYLAKE(i915) && \ 706 INTEL_INFO(i915)->gt == 3) 707#define IS_COFFEELAKE_ULT(i915) \ 708 IS_SUBPLATFORM(i915, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT) 709#define IS_COFFEELAKE_ULX(i915) \ 710 IS_SUBPLATFORM(i915, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX) 711#define IS_COFFEELAKE_GT2(i915) (IS_COFFEELAKE(i915) && \ 712 INTEL_INFO(i915)->gt == 2) 713#define IS_COFFEELAKE_GT3(i915) (IS_COFFEELAKE(i915) && \ 714 INTEL_INFO(i915)->gt == 3) 715 716#define IS_COMETLAKE_ULT(i915) \ 717 IS_SUBPLATFORM(i915, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT) 718#define IS_COMETLAKE_ULX(i915) \ 719 IS_SUBPLATFORM(i915, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX) 720#define IS_COMETLAKE_GT2(i915) (IS_COMETLAKE(i915) && \ 721 INTEL_INFO(i915)->gt == 2) 722 723#define IS_ICL_WITH_PORT_F(i915) \ 724 IS_SUBPLATFORM(i915, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF) 725 726#define IS_TIGERLAKE_UY(i915) \ 727 IS_SUBPLATFORM(i915, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY) 728 729 730 731 732 733 734 735 736#define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \ 737 (IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until)) 738 739#define IS_MTL_DISPLAY_STEP(__i915, since, until) \ 740 (IS_METEORLAKE(__i915) && \ 741 IS_DISPLAY_STEP(__i915, since, until)) 742 743#define IS_MTL_MEDIA_STEP(__i915, since, until) \ 744 (IS_METEORLAKE(__i915) && \ 745 IS_MEDIA_STEP(__i915, since, until)) 746 747/* 748 * DG2 hardware steppings are a bit unusual. The hardware design was forked to 749 * create three variants (G10, G11, and G12) which each have distinct 750 * workaround sets. The G11 and G12 forks of the DG2 design reset the GT 751 * stepping back to "A0" for their first iterations, even though they're more 752 * similar to a G10 B0 stepping and G10 C0 stepping respectively in terms of 753 * functionality and workarounds. However the display stepping does not reset 754 * in the same manner --- a specific stepping like "B0" has a consistent 755 * meaning regardless of whether it belongs to a G10, G11, or G12 DG2. 756 * 757 * TLDR: All GT workarounds and stepping-specific logic must be applied in 758 * relation to a specific subplatform (G10/G11/G12), whereas display workarounds 759 * and stepping-specific logic will be applied with a general DG2-wide stepping 760 * number. 761 */ 762#define IS_DG2_GRAPHICS_STEP(__i915, variant, since, until) \ 763 (IS_SUBPLATFORM(__i915, INTEL_DG2, INTEL_SUBPLATFORM_##variant) && \ 764 IS_GRAPHICS_STEP(__i915, since, until)) 765 766#define IS_DG2_DISPLAY_STEP(__i915, since, until) \ 767 (IS_DG2(__i915) && \ 768 IS_DISPLAY_STEP(__i915, since, until)) 769 770#define IS_PVC_BD_STEP(__i915, since, until) \ 771 (IS_PONTEVECCHIO(__i915) && \ 772 IS_BASEDIE_STEP(__i915, since, until)) 773 774#define IS_PVC_CT_STEP(__i915, since, until) \ 775 (IS_PONTEVECCHIO(__i915) && \ 776 IS_GRAPHICS_STEP(__i915, since, until)) 777 778#define IS_LP(i915) (INTEL_INFO(i915)->is_lp) 779#define IS_GEN9_LP(i915) (GRAPHICS_VER(i915) == 9 && IS_LP(i915)) 780#define IS_GEN9_BC(i915) (GRAPHICS_VER(i915) == 9 && !IS_LP(i915)) 781 782#define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id)) 783#define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id) 784 785#define __ENGINE_INSTANCES_MASK(mask, first, count) ({ \ 786 unsigned int first__ = (first); \ 787 unsigned int count__ = (count); \ 788 ((mask) & GENMASK(first__ + count__ - 1, first__)) >> first__; \ 789}) 790 791#define ENGINE_INSTANCES_MASK(gt, first, count) \ 792 __ENGINE_INSTANCES_MASK((gt)->info.engine_mask, first, count) 793 794#define RCS_MASK(gt) \ 795 ENGINE_INSTANCES_MASK(gt, RCS0, I915_MAX_RCS) 796#define BCS_MASK(gt) \ 797 ENGINE_INSTANCES_MASK(gt, BCS0, I915_MAX_BCS) 798#define VDBOX_MASK(gt) \ 799 ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS) 800#define VEBOX_MASK(gt) \ 801 ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS) 802#define CCS_MASK(gt) \ 803 ENGINE_INSTANCES_MASK(gt, CCS0, I915_MAX_CCS) 804 805#define HAS_MEDIA_RATIO_MODE(i915) (INTEL_INFO(i915)->has_media_ratio_mode) 806 807/* 808 * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution 809 * All later gens can run the final buffer from the ppgtt 810 */ 811#define CMDPARSER_USES_GGTT(i915) (GRAPHICS_VER(i915) == 7) 812 813#define HAS_LLC(i915) (INTEL_INFO(i915)->has_llc) 814#define HAS_4TILE(i915) (INTEL_INFO(i915)->has_4tile) 815#define HAS_SNOOP(i915) (INTEL_INFO(i915)->has_snoop) 816#define HAS_EDRAM(i915) ((i915)->edram_size_mb) 817#define HAS_SECURE_BATCHES(i915) (GRAPHICS_VER(i915) < 6) 818#define HAS_WT(i915) HAS_EDRAM(i915) 819 820#define HWS_NEEDS_PHYSICAL(i915) (INTEL_INFO(i915)->hws_needs_physical) 821 822#define HAS_LOGICAL_RING_CONTEXTS(i915) \ 823 (INTEL_INFO(i915)->has_logical_ring_contexts) 824#define HAS_LOGICAL_RING_ELSQ(i915) \ 825 (INTEL_INFO(i915)->has_logical_ring_elsq) 826 827#define HAS_EXECLISTS(i915) HAS_LOGICAL_RING_CONTEXTS(i915) 828 829#define INTEL_PPGTT(i915) (RUNTIME_INFO(i915)->ppgtt_type) 830#define HAS_PPGTT(i915) \ 831 (INTEL_PPGTT(i915) != INTEL_PPGTT_NONE) 832#define HAS_FULL_PPGTT(i915) \ 833 (INTEL_PPGTT(i915) >= INTEL_PPGTT_FULL) 834 835#define HAS_PAGE_SIZES(i915, sizes) ({ \ 836 GEM_BUG_ON((sizes) == 0); \ 837 ((sizes) & ~RUNTIME_INFO(i915)->page_sizes) == 0; \ 838}) 839 840/* Early gen2 have a totally busted CS tlb and require pinned batches. */ 841#define HAS_BROKEN_CS_TLB(i915) (IS_I830(i915) || IS_I845G(i915)) 842 843#define NEEDS_RC6_CTX_CORRUPTION_WA(i915) \ 844 (IS_BROADWELL(i915) || GRAPHICS_VER(i915) == 9) 845 846/* WaRsDisableCoarsePowerGating:skl,cnl */ 847#define NEEDS_WaRsDisableCoarsePowerGating(i915) \ 848 (IS_SKYLAKE_GT3(i915) || IS_SKYLAKE_GT4(i915)) 849 850/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 851 * rows, which changed the alignment requirements and fence programming. 852 */ 853#define HAS_128_BYTE_Y_TILING(i915) (GRAPHICS_VER(i915) != 2 && \ 854 !(IS_I915G(i915) || IS_I915GM(i915))) 855 856#define HAS_RC6(i915) (INTEL_INFO(i915)->has_rc6) 857#define HAS_RC6p(i915) (INTEL_INFO(i915)->has_rc6p) 858#define HAS_RC6pp(i915) (false) /* HW was never validated */ 859 860#define HAS_RPS(i915) (INTEL_INFO(i915)->has_rps) 861 862#define HAS_HECI_PXP(i915) \ 863 (INTEL_INFO(i915)->has_heci_pxp) 864 865#define HAS_HECI_GSCFI(i915) \ 866 (INTEL_INFO(i915)->has_heci_gscfi) 867 868#define HAS_HECI_GSC(i915) (HAS_HECI_PXP(i915) || HAS_HECI_GSCFI(i915)) 869 870#define HAS_RUNTIME_PM(i915) (INTEL_INFO(i915)->has_runtime_pm) 871#define HAS_64BIT_RELOC(i915) (INTEL_INFO(i915)->has_64bit_reloc) 872 873#define HAS_OA_BPC_REPORTING(i915) \ 874 (INTEL_INFO(i915)->has_oa_bpc_reporting) 875#define HAS_OA_SLICE_CONTRIB_LIMITS(i915) \ 876 (INTEL_INFO(i915)->has_oa_slice_contrib_limits) 877#define HAS_OAM(i915) \ 878 (INTEL_INFO(i915)->has_oam) 879 880/* 881 * Set this flag, when platform requires 64K GTT page sizes or larger for 882 * device local memory access. 883 */ 884#define HAS_64K_PAGES(i915) (INTEL_INFO(i915)->has_64k_pages) 885 886#define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i)) 887#define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM) 888 889#define HAS_EXTRA_GT_LIST(i915) (INTEL_INFO(i915)->extra_gt_list) 890 891/* 892 * Platform has the dedicated compression control state for each lmem surfaces 893 * stored in lmem to support the 3D and media compression formats. 894 */ 895#define HAS_FLAT_CCS(i915) (INTEL_INFO(i915)->has_flat_ccs) 896 897#define HAS_GT_UC(i915) (INTEL_INFO(i915)->has_gt_uc) 898 899#define HAS_POOLED_EU(i915) (RUNTIME_INFO(i915)->has_pooled_eu) 900 901#define HAS_GLOBAL_MOCS_REGISTERS(i915) (INTEL_INFO(i915)->has_global_mocs) 902 903#define HAS_GMD_ID(i915) (INTEL_INFO(i915)->has_gmd_id) 904 905#define HAS_L3_CCS_READ(i915) (INTEL_INFO(i915)->has_l3_ccs_read) 906 907/* DPF == dynamic parity feature */ 908#define HAS_L3_DPF(i915) (INTEL_INFO(i915)->has_l3_dpf) 909#define NUM_L3_SLICES(i915) (IS_HASWELL_GT3(i915) ? \ 910 2 : HAS_L3_DPF(i915)) 911 912/* Only valid when HAS_DISPLAY() is true */ 913#define INTEL_DISPLAY_ENABLED(i915) \ 914 (drm_WARN_ON(&(i915)->drm, !HAS_DISPLAY(i915)), \ 915 !(i915)->params.disable_display && \ 916 !intel_opregion_headless_sku(i915)) 917 918#define HAS_GUC_DEPRIVILEGE(i915) \ 919 (INTEL_INFO(i915)->has_guc_deprivilege) 920 921#define HAS_3D_PIPELINE(i915) (INTEL_INFO(i915)->has_3d_pipeline) 922 923#define HAS_ONE_EU_PER_FUSE_BIT(i915) (INTEL_INFO(i915)->has_one_eu_per_fuse_bit) 924 925#define HAS_LMEMBAR_SMEM_STOLEN(i915) (!HAS_LMEM(i915) && \ 926 GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) 927 928#endif 929