1/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 2 */ 3/* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30#ifndef _I915_DRV_H_ 31#define _I915_DRV_H_ 32 33#include <uapi/drm/i915_drm.h> 34 35#include <linux/pm_qos.h> 36 37#include <drm/ttm/ttm_device.h> 38 39#include "vga.h" 40 41struct inteldrm_softc; 42#define drm_i915_private inteldrm_softc 43 44#include "display/intel_display_limits.h" 45#include "display/intel_display_core.h" 46 47#include "gem/i915_gem_context_types.h" 48#include "gem/i915_gem_shrinker.h" 49#include "gem/i915_gem_stolen.h" 50 51#include "gt/intel_engine.h" 52#include "gt/intel_gt_types.h" 53#include "gt/intel_region_lmem.h" 54#include "gt/intel_workarounds.h" 55#include "gt/uc/intel_uc.h" 56 57#include "soc/intel_pch.h" 58 59#include "i915_drm_client.h" 60#include "i915_gem.h" 61#include "i915_gpu_error.h" 62#include "i915_params.h" 63#include "i915_perf_types.h" 64#include "i915_scheduler.h" 65#include "i915_utils.h" 66#include "intel_device_info.h" 67#include "intel_memory_region.h" 68#include "intel_runtime_pm.h" 69#include "intel_step.h" 70#include "intel_uncore.h" 71 72#include "drm.h" 73 74#include <dev/ic/mc6845reg.h> 75#include <dev/ic/pcdisplayvar.h> 76#include <dev/ic/vgareg.h> 77#include <dev/ic/vgavar.h> 78 79#include <sys/task.h> 80#include <dev/pci/vga_pcivar.h> 81#include <dev/wscons/wsconsio.h> 82#include <dev/wscons/wsdisplayvar.h> 83#include <dev/rasops/rasops.h> 84 85struct drm_i915_clock_gating_funcs; 86struct vlv_s0ix_state; 87struct intel_pxp; 88 89#define GEM_QUIRK_PIN_SWIZZLED_PAGES BIT(0) 90 91/* Data Stolen Memory (DSM) aka "i915 stolen memory" */ 92struct i915_dsm { 93 /* 94 * The start and end of DSM which we can optionally use to create GEM 95 * objects backed by stolen memory. 96 * 97 * Note that usable_size tells us exactly how much of this we are 98 * actually allowed to use, given that some portion of it is in fact 99 * reserved for use by hardware functions. 100 */ 101 struct resource stolen; 102 103 /* 104 * Reserved portion of DSM. 105 */ 106 struct resource reserved; 107 108 /* 109 * Total size minus reserved ranges. 110 * 111 * DSM is segmented in hardware with different portions offlimits to 112 * certain functions. 113 * 114 * The drm_mm is initialised to the total accessible range, as found 115 * from the PCI config. On Broadwell+, this is further restricted to 116 * avoid the first page! The upper end of DSM is reserved for hardware 117 * functions and similarly removed from the accessible range. 118 */ 119 resource_size_t usable_size; 120}; 121 122struct i915_suspend_saved_registers { 123 u32 saveDSPARB; 124 u32 saveSWF0[16]; 125 u32 saveSWF1[16]; 126 u32 saveSWF3[3]; 127 u16 saveGCDGMBUS; 128}; 129 130#define MAX_L3_SLICES 2 131struct intel_l3_parity { 132 u32 *remap_info[MAX_L3_SLICES]; 133 struct work_struct error_work; 134 int which_slice; 135}; 136 137struct i915_gem_mm { 138 /* 139 * Shortcut for the stolen region. This points to either 140 * INTEL_REGION_STOLEN_SMEM for integrated platforms, or 141 * INTEL_REGION_STOLEN_LMEM for discrete, or NULL if the device doesn't 142 * support stolen. 143 */ 144 struct intel_memory_region *stolen_region; 145 /** Memory allocator for GTT stolen memory */ 146 struct drm_mm stolen; 147 /** Protects the usage of the GTT stolen memory allocator. This is 148 * always the inner lock when overlapping with struct_mutex. */ 149 struct rwlock stolen_lock; 150 151 /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */ 152 spinlock_t obj_lock; 153 154 /** 155 * List of objects which are purgeable. 156 */ 157 struct list_head purge_list; 158 159 /** 160 * List of objects which have allocated pages and are shrinkable. 161 */ 162 struct list_head shrink_list; 163 164 /** 165 * List of objects which are pending destruction. 166 */ 167 struct llist_head free_list; 168 struct work_struct free_work; 169 /** 170 * Count of objects pending destructions. Used to skip needlessly 171 * waiting on an RCU barrier if no objects are waiting to be freed. 172 */ 173 atomic_t free_count; 174 175 /** 176 * tmpfs instance used for shmem backed objects 177 */ 178 struct vfsmount *gemfs; 179 180 struct intel_memory_region *regions[INTEL_REGION_UNKNOWN]; 181 182 struct notifier_block oom_notifier; 183 struct notifier_block vmap_notifier; 184 struct shrinker shrinker; 185 186#ifdef CONFIG_MMU_NOTIFIER 187 /** 188 * notifier_lock for mmu notifiers, memory may not be allocated 189 * while holding this lock. 190 */ 191 rwlock_t notifier_lock; 192#endif 193 194 /* shrinker accounting, also useful for userland debugging */ 195 u64 shrink_memory; 196 u32 shrink_count; 197}; 198 199struct i915_virtual_gpu { 200 struct rwlock lock; /* serialises sending of g2v_notify command pkts */ 201 bool active; 202 u32 caps; 203 u32 *initial_mmio; 204 u8 *initial_cfg_space; 205 struct list_head entry; 206}; 207 208struct i915_selftest_stash { 209 atomic_t counter; 210 struct ida mock_region_instances; 211}; 212 213 214struct inteldrm_softc { 215#ifdef __OpenBSD__ 216 struct device sc_dev; 217 bus_dma_tag_t dmat; 218 bus_space_tag_t iot; 219 bus_space_tag_t bst; 220 bus_space_handle_t opregion_ioh; 221 bus_space_handle_t opregion_rvda_ioh; 222 bus_size_t opregion_rvda_size; 223#endif 224 225 struct drm_device drm; 226 227 struct intel_display display; 228 229 /* FIXME: Device release actions should all be moved to drmm_ */ 230 bool do_release; 231 232 /* i915 device parameters */ 233 struct i915_params params; 234 235 const struct intel_device_info *__info; /* Use INTEL_INFO() to access. */ 236 struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */ 237 struct intel_driver_caps caps; 238 239 struct i915_dsm dsm; 240 241#ifdef __OpenBSD__ 242 struct pci_attach_args *pa; 243 pci_chipset_tag_t pc; 244 pcitag_t tag; 245 struct extent *memex; 246 pci_intr_handle_t ih; 247 irqreturn_t(*irq_handler) (int, void *); 248 void *irqh; 249 250 struct vga_pci_bar bar; 251 struct vga_pci_bar *vga_regs; 252 253 const struct pci_device_id *id; 254 255 int console; 256 int primary; 257 int nscreens; 258 void (*switchcb)(void *, int, int); 259 void *switchcbarg; 260 void *switchcookie; 261 struct task switchtask; 262 struct rasops_info ro; 263 264 struct task burner_task; 265 int burner_fblank; 266 267 struct backlight_device *backlight; 268 269 union flush { 270 struct { 271 bus_space_tag_t bst; 272 bus_space_handle_t bsh; 273 } i9xx; 274 struct { 275 bus_dma_segment_t seg; 276 caddr_t kva; 277 } i8xx; 278 } ifp; 279 struct vm_page *pgs; 280#endif 281 282 struct intel_uncore uncore; 283 struct intel_uncore_mmio_debug mmio_debug; 284 285 struct i915_virtual_gpu vgpu; 286 287 struct intel_gvt *gvt; 288 289 struct { 290 struct pci_dev *pdev; 291 struct resource mch_res; 292 bool mchbar_need_disable; 293 } gmch; 294 295 struct rb_root uabi_engines; 296 unsigned int engine_uabi_class_count[I915_LAST_UABI_ENGINE_CLASS + 1]; 297 298 /* protects the irq masks */ 299 spinlock_t irq_lock; 300 301 bool display_irqs_enabled; 302 303 /* Sideband mailbox protection */ 304 struct rwlock sb_lock; 305 struct pm_qos_request sb_qos; 306 307 /** Cached value of IMR to avoid reads in updating the bitfield */ 308 union { 309 u32 irq_mask; 310 u32 de_irq_mask[I915_MAX_PIPES]; 311 }; 312 u32 pipestat_irq_mask[I915_MAX_PIPES]; 313 314 bool preserve_bios_swizzle; 315 316 unsigned int fsb_freq, mem_freq, is_ddr3; 317 unsigned int skl_preferred_vco_freq; 318 319 unsigned int max_dotclk_freq; 320 unsigned int hpll_freq; 321 unsigned int czclk_freq; 322 323 /** 324 * wq - Driver workqueue for GEM. 325 * 326 * NOTE: Work items scheduled here are not allowed to grab any modeset 327 * locks, for otherwise the flushing done in the pageflip code will 328 * result in deadlocks. 329 */ 330 struct workqueue_struct *wq; 331 332 /** 333 * unordered_wq - internal workqueue for unordered work 334 * 335 * This workqueue should be used for all unordered work 336 * scheduling within i915, which used to be scheduled on the 337 * system_wq before moving to a driver instance due 338 * deprecation of flush_scheduled_work(). 339 */ 340 struct workqueue_struct *unordered_wq; 341 342 /* pm private clock gating functions */ 343 const struct drm_i915_clock_gating_funcs *clock_gating_funcs; 344 345 /* PCH chipset type */ 346 enum intel_pch pch_type; 347 unsigned short pch_id; 348 349 unsigned long gem_quirks; 350 351 struct i915_gem_mm mm; 352 353 struct intel_l3_parity l3_parity; 354 355 /* 356 * edram size in MB. 357 * Cannot be determined by PCIID. You must always read a register. 358 */ 359 u32 edram_size_mb; 360 361 struct i915_gpu_error gpu_error; 362 363 u32 suspend_count; 364 struct i915_suspend_saved_registers regfile; 365 struct vlv_s0ix_state *vlv_s0ix_state; 366 367 struct dram_info { 368 bool wm_lv_0_adjust_needed; 369 u8 num_channels; 370 bool symmetric_memory; 371 enum intel_dram_type { 372 INTEL_DRAM_UNKNOWN, 373 INTEL_DRAM_DDR3, 374 INTEL_DRAM_DDR4, 375 INTEL_DRAM_LPDDR3, 376 INTEL_DRAM_LPDDR4, 377 INTEL_DRAM_DDR5, 378 INTEL_DRAM_LPDDR5, 379 } type; 380 u8 num_qgv_points; 381 u8 num_psf_gv_points; 382 } dram_info; 383 384 struct intel_runtime_pm runtime_pm; 385 386 struct i915_perf perf; 387 388 struct i915_hwmon *hwmon; 389 390 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */ 391 struct intel_gt gt0; 392 393 /* 394 * i915->gt[0] == &i915->gt0 395 */ 396 struct intel_gt *gt[I915_MAX_GT]; 397 398 struct kobject *sysfs_gt; 399 400 /* Quick lookup of media GT (current platforms only have one) */ 401 struct intel_gt *media_gt; 402 403 struct { 404 struct i915_gem_contexts { 405 spinlock_t lock; /* locks list */ 406 struct list_head list; 407 } contexts; 408 409 /* 410 * We replace the local file with a global mappings as the 411 * backing storage for the mmap is on the device and not 412 * on the struct file, and we do not want to prolong the 413 * lifetime of the local fd. To minimise the number of 414 * anonymous inodes we create, we use a global singleton to 415 * share the global mapping. 416 */ 417 struct file *mmap_singleton; 418 } gem; 419 420 struct intel_pxp *pxp; 421 422 /* For i915gm/i945gm vblank irq workaround */ 423 u8 vblank_enabled; 424 425 bool irq_enabled; 426 427 struct i915_pmu pmu; 428 429 /* The TTM device structure. */ 430 struct ttm_device bdev; 431 432 I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;) 433 434 /* 435 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch 436 * will be rejected. Instead look for a better place. 437 */ 438}; 439 440static inline struct drm_i915_private *to_i915(const struct drm_device *dev) 441{ 442 return container_of(dev, struct drm_i915_private, drm); 443} 444 445static inline struct drm_i915_private *kdev_to_i915(struct device *kdev) 446{ 447 return dev_get_drvdata(kdev); 448} 449 450static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev) 451{ 452 STUB(); 453 return NULL; 454#ifdef notyet 455 return pci_get_drvdata(pdev); 456#endif 457} 458 459static inline struct intel_gt *to_gt(struct drm_i915_private *i915) 460{ 461 return &i915->gt0; 462} 463 464/* Simple iterator over all initialised engines */ 465#define for_each_engine(engine__, gt__, id__) \ 466 for ((id__) = 0; \ 467 (id__) < I915_NUM_ENGINES; \ 468 (id__)++) \ 469 for_each_if ((engine__) = (gt__)->engine[(id__)]) 470 471/* Iterator over subset of engines selected by mask */ 472#define for_each_engine_masked(engine__, gt__, mask__, tmp__) \ 473 for ((tmp__) = (mask__) & (gt__)->info.engine_mask; \ 474 (tmp__) ? \ 475 ((engine__) = (gt__)->engine[__mask_next_bit(tmp__)]), 1 : \ 476 0;) 477 478#define rb_to_uabi_engine(rb) \ 479 rb_entry_safe(rb, struct intel_engine_cs, uabi_node) 480 481#define for_each_uabi_engine(engine__, i915__) \ 482 for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\ 483 (engine__); \ 484 (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node))) 485 486#define for_each_uabi_class_engine(engine__, class__, i915__) \ 487 for ((engine__) = intel_engine_lookup_user((i915__), (class__), 0); \ 488 (engine__) && (engine__)->uabi_class == (class__); \ 489 (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node))) 490 491#define INTEL_INFO(i915) ((i915)->__info) 492#define RUNTIME_INFO(i915) (&(i915)->__runtime) 493#define DISPLAY_INFO(i915) ((i915)->display.info.__device_info) 494#define DISPLAY_RUNTIME_INFO(i915) (&(i915)->display.info.__runtime_info) 495#define DRIVER_CAPS(i915) (&(i915)->caps) 496 497#define INTEL_DEVID(i915) (RUNTIME_INFO(i915)->device_id) 498 499#define IP_VER(ver, rel) ((ver) << 8 | (rel)) 500 501#define GRAPHICS_VER(i915) (RUNTIME_INFO(i915)->graphics.ip.ver) 502#define GRAPHICS_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->graphics.ip.ver, \ 503 RUNTIME_INFO(i915)->graphics.ip.rel) 504#define IS_GRAPHICS_VER(i915, from, until) \ 505 (GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until)) 506 507#define MEDIA_VER(i915) (RUNTIME_INFO(i915)->media.ip.ver) 508#define MEDIA_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->media.ip.ver, \ 509 RUNTIME_INFO(i915)->media.ip.rel) 510#define IS_MEDIA_VER(i915, from, until) \ 511 (MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until)) 512 513#define DISPLAY_VER(i915) (DISPLAY_RUNTIME_INFO(i915)->ip.ver) 514#define IS_DISPLAY_VER(i915, from, until) \ 515 (DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until)) 516 517#define INTEL_REVID(i915) ((i915)->drm.pdev->revision) 518 519#define INTEL_DISPLAY_STEP(__i915) (RUNTIME_INFO(__i915)->step.display_step) 520#define INTEL_GRAPHICS_STEP(__i915) (RUNTIME_INFO(__i915)->step.graphics_step) 521#define INTEL_MEDIA_STEP(__i915) (RUNTIME_INFO(__i915)->step.media_step) 522#define INTEL_BASEDIE_STEP(__i915) (RUNTIME_INFO(__i915)->step.basedie_step) 523 524#define IS_DISPLAY_STEP(__i915, since, until) \ 525 (drm_WARN_ON(&(__i915)->drm, INTEL_DISPLAY_STEP(__i915) == STEP_NONE), \ 526 INTEL_DISPLAY_STEP(__i915) >= (since) && INTEL_DISPLAY_STEP(__i915) < (until)) 527 528#define IS_GRAPHICS_STEP(__i915, since, until) \ 529 (drm_WARN_ON(&(__i915)->drm, INTEL_GRAPHICS_STEP(__i915) == STEP_NONE), \ 530 INTEL_GRAPHICS_STEP(__i915) >= (since) && INTEL_GRAPHICS_STEP(__i915) < (until)) 531 532#define IS_MEDIA_STEP(__i915, since, until) \ 533 (drm_WARN_ON(&(__i915)->drm, INTEL_MEDIA_STEP(__i915) == STEP_NONE), \ 534 INTEL_MEDIA_STEP(__i915) >= (since) && INTEL_MEDIA_STEP(__i915) < (until)) 535 536#define IS_BASEDIE_STEP(__i915, since, until) \ 537 (drm_WARN_ON(&(__i915)->drm, INTEL_BASEDIE_STEP(__i915) == STEP_NONE), \ 538 INTEL_BASEDIE_STEP(__i915) >= (since) && INTEL_BASEDIE_STEP(__i915) < (until)) 539 540static __always_inline unsigned int 541__platform_mask_index(const struct intel_runtime_info *info, 542 enum intel_platform p) 543{ 544 const unsigned int pbits = 545 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS; 546 547 /* Expand the platform_mask array if this fails. */ 548 BUILD_BUG_ON(INTEL_MAX_PLATFORMS > 549 pbits * ARRAY_SIZE(info->platform_mask)); 550 551 return p / pbits; 552} 553 554static __always_inline unsigned int 555__platform_mask_bit(const struct intel_runtime_info *info, 556 enum intel_platform p) 557{ 558 const unsigned int pbits = 559 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS; 560 561 return p % pbits + INTEL_SUBPLATFORM_BITS; 562} 563 564static inline u32 565intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p) 566{ 567 const unsigned int pi = __platform_mask_index(info, p); 568 569 return info->platform_mask[pi] & INTEL_SUBPLATFORM_MASK; 570} 571 572static __always_inline bool 573IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p) 574{ 575 const struct intel_runtime_info *info = RUNTIME_INFO(i915); 576 const unsigned int pi = __platform_mask_index(info, p); 577 const unsigned int pb = __platform_mask_bit(info, p); 578 579#ifdef notyet 580 BUILD_BUG_ON(!__builtin_constant_p(p)); 581#endif 582 583 return info->platform_mask[pi] & BIT(pb); 584} 585 586static __always_inline bool 587IS_SUBPLATFORM(const struct drm_i915_private *i915, 588 enum intel_platform p, unsigned int s) 589{ 590 const struct intel_runtime_info *info = RUNTIME_INFO(i915); 591 const unsigned int pi = __platform_mask_index(info, p); 592 const unsigned int pb = __platform_mask_bit(info, p); 593 const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1; 594 const u32 mask = info->platform_mask[pi]; 595 596#ifdef notyet 597 BUILD_BUG_ON(!__builtin_constant_p(p)); 598 BUILD_BUG_ON(!__builtin_constant_p(s)); 599 BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS); 600#endif 601 602 /* Shift and test on the MSB position so sign flag can be used. */ 603 return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb); 604} 605 606#define IS_MOBILE(i915) (INTEL_INFO(i915)->is_mobile) 607#define IS_DGFX(i915) (INTEL_INFO(i915)->is_dgfx) 608 609#define IS_I830(i915) IS_PLATFORM(i915, INTEL_I830) 610#define IS_I845G(i915) IS_PLATFORM(i915, INTEL_I845G) 611#define IS_I85X(i915) IS_PLATFORM(i915, INTEL_I85X) 612#define IS_I865G(i915) IS_PLATFORM(i915, INTEL_I865G) 613#define IS_I915G(i915) IS_PLATFORM(i915, INTEL_I915G) 614#define IS_I915GM(i915) IS_PLATFORM(i915, INTEL_I915GM) 615#define IS_I945G(i915) IS_PLATFORM(i915, INTEL_I945G) 616#define IS_I945GM(i915) IS_PLATFORM(i915, INTEL_I945GM) 617#define IS_I965G(i915) IS_PLATFORM(i915, INTEL_I965G) 618#define IS_I965GM(i915) IS_PLATFORM(i915, INTEL_I965GM) 619#define IS_G45(i915) IS_PLATFORM(i915, INTEL_G45) 620#define IS_GM45(i915) IS_PLATFORM(i915, INTEL_GM45) 621#define IS_G4X(i915) (IS_G45(i915) || IS_GM45(i915)) 622#define IS_PINEVIEW(i915) IS_PLATFORM(i915, INTEL_PINEVIEW) 623#define IS_G33(i915) IS_PLATFORM(i915, INTEL_G33) 624#define IS_IRONLAKE(i915) IS_PLATFORM(i915, INTEL_IRONLAKE) 625#define IS_IRONLAKE_M(i915) \ 626 (IS_PLATFORM(i915, INTEL_IRONLAKE) && IS_MOBILE(i915)) 627#define IS_SANDYBRIDGE(i915) IS_PLATFORM(i915, INTEL_SANDYBRIDGE) 628#define IS_IVYBRIDGE(i915) IS_PLATFORM(i915, INTEL_IVYBRIDGE) 629#define IS_IVB_GT1(i915) (IS_IVYBRIDGE(i915) && \ 630 INTEL_INFO(i915)->gt == 1) 631#define IS_VALLEYVIEW(i915) IS_PLATFORM(i915, INTEL_VALLEYVIEW) 632#define IS_CHERRYVIEW(i915) IS_PLATFORM(i915, INTEL_CHERRYVIEW) 633#define IS_HASWELL(i915) IS_PLATFORM(i915, INTEL_HASWELL) 634#define IS_BROADWELL(i915) IS_PLATFORM(i915, INTEL_BROADWELL) 635#define IS_SKYLAKE(i915) IS_PLATFORM(i915, INTEL_SKYLAKE) 636#define IS_BROXTON(i915) IS_PLATFORM(i915, INTEL_BROXTON) 637#define IS_KABYLAKE(i915) IS_PLATFORM(i915, INTEL_KABYLAKE) 638#define IS_GEMINILAKE(i915) IS_PLATFORM(i915, INTEL_GEMINILAKE) 639#define IS_COFFEELAKE(i915) IS_PLATFORM(i915, INTEL_COFFEELAKE) 640#define IS_COMETLAKE(i915) IS_PLATFORM(i915, INTEL_COMETLAKE) 641#define IS_ICELAKE(i915) IS_PLATFORM(i915, INTEL_ICELAKE) 642#define IS_JASPERLAKE(i915) IS_PLATFORM(i915, INTEL_JASPERLAKE) 643#define IS_ELKHARTLAKE(i915) IS_PLATFORM(i915, INTEL_ELKHARTLAKE) 644#define IS_TIGERLAKE(i915) IS_PLATFORM(i915, INTEL_TIGERLAKE) 645#define IS_ROCKETLAKE(i915) IS_PLATFORM(i915, INTEL_ROCKETLAKE) 646#define IS_DG1(i915) IS_PLATFORM(i915, INTEL_DG1) 647#define IS_ALDERLAKE_S(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_S) 648#define IS_ALDERLAKE_P(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_P) 649#define IS_XEHPSDV(i915) IS_PLATFORM(i915, INTEL_XEHPSDV) 650#define IS_DG2(i915) IS_PLATFORM(i915, INTEL_DG2) 651#define IS_PONTEVECCHIO(i915) IS_PLATFORM(i915, INTEL_PONTEVECCHIO) 652#define IS_METEORLAKE(i915) IS_PLATFORM(i915, INTEL_METEORLAKE) 653 654#define IS_METEORLAKE_M(i915) \ 655 IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_M) 656#define IS_METEORLAKE_P(i915) \ 657 IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_P) 658#define IS_DG2_G10(i915) \ 659 IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G10) 660#define IS_DG2_G11(i915) \ 661 IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G11) 662#define IS_DG2_G12(i915) \ 663 IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G12) 664#define IS_RAPTORLAKE_S(i915) \ 665 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL) 666#define IS_ALDERLAKE_P_N(i915) \ 667 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N) 668#define IS_RAPTORLAKE_P(i915) \ 669 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL) 670#define IS_RAPTORLAKE_U(i915) \ 671 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU) 672#define IS_HASWELL_EARLY_SDV(i915) (IS_HASWELL(i915) && \ 673 (INTEL_DEVID(i915) & 0xFF00) == 0x0C00) 674#define IS_BROADWELL_ULT(i915) \ 675 IS_SUBPLATFORM(i915, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT) 676#define IS_BROADWELL_ULX(i915) \ 677 IS_SUBPLATFORM(i915, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX) 678#define IS_BROADWELL_GT3(i915) (IS_BROADWELL(i915) && \ 679 INTEL_INFO(i915)->gt == 3) 680#define IS_HASWELL_ULT(i915) \ 681 IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT) 682#define IS_HASWELL_GT3(i915) (IS_HASWELL(i915) && \ 683 INTEL_INFO(i915)->gt == 3) 684#define IS_HASWELL_GT1(i915) (IS_HASWELL(i915) && \ 685 INTEL_INFO(i915)->gt == 1) 686/* ULX machines are also considered ULT. */ 687#define IS_HASWELL_ULX(i915) \ 688 IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX) 689#define IS_SKYLAKE_ULT(i915) \ 690 IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT) 691#define IS_SKYLAKE_ULX(i915) \ 692 IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX) 693#define IS_KABYLAKE_ULT(i915) \ 694 IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT) 695#define IS_KABYLAKE_ULX(i915) \ 696 IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX) 697#define IS_SKYLAKE_GT2(i915) (IS_SKYLAKE(i915) && \ 698 INTEL_INFO(i915)->gt == 2) 699#define IS_SKYLAKE_GT3(i915) (IS_SKYLAKE(i915) && \ 700 INTEL_INFO(i915)->gt == 3) 701#define IS_SKYLAKE_GT4(i915) (IS_SKYLAKE(i915) && \ 702 INTEL_INFO(i915)->gt == 4) 703#define IS_KABYLAKE_GT2(i915) (IS_KABYLAKE(i915) && \ 704 INTEL_INFO(i915)->gt == 2) 705#define IS_KABYLAKE_GT3(i915) (IS_KABYLAKE(i915) && \ 706 INTEL_INFO(i915)->gt == 3) 707#define IS_COFFEELAKE_ULT(i915) \ 708 IS_SUBPLATFORM(i915, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT) 709#define IS_COFFEELAKE_ULX(i915) \ 710 IS_SUBPLATFORM(i915, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX) 711#define IS_COFFEELAKE_GT2(i915) (IS_COFFEELAKE(i915) && \ 712 INTEL_INFO(i915)->gt == 2) 713#define IS_COFFEELAKE_GT3(i915) (IS_COFFEELAKE(i915) && \ 714 INTEL_INFO(i915)->gt == 3) 715 716#define IS_COMETLAKE_ULT(i915) \ 717 IS_SUBPLATFORM(i915, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT) 718#define IS_COMETLAKE_ULX(i915) \ 719 IS_SUBPLATFORM(i915, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX) 720#define IS_COMETLAKE_GT2(i915) (IS_COMETLAKE(i915) && \ 721 INTEL_INFO(i915)->gt == 2) 722 723#define IS_ICL_WITH_PORT_F(i915) \ 724 IS_SUBPLATFORM(i915, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF) 725 726#define IS_TIGERLAKE_UY(i915) \ 727 IS_SUBPLATFORM(i915, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY) 728 729 730 731 732 733 734 735 736#define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \ 737 (IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until)) 738 739#define IS_MTL_DISPLAY_STEP(__i915, since, until) \ 740 (IS_METEORLAKE(__i915) && \ 741 IS_DISPLAY_STEP(__i915, since, until)) 742 743#define IS_MTL_MEDIA_STEP(__i915, since, until) \ 744 (IS_METEORLAKE(__i915) && \ 745 IS_MEDIA_STEP(__i915, since, until)) 746 747/* 748 * DG2 hardware steppings are a bit unusual. The hardware design was forked to 749 * create three variants (G10, G11, and G12) which each have distinct 750 * workaround sets. The G11 and G12 forks of the DG2 design reset the GT 751 * stepping back to "A0" for their first iterations, even though they're more 752 * similar to a G10 B0 stepping and G10 C0 stepping respectively in terms of 753 * functionality and workarounds. However the display stepping does not reset 754 * in the same manner --- a specific stepping like "B0" has a consistent 755 * meaning regardless of whether it belongs to a G10, G11, or G12 DG2. 756 * 757 * TLDR: All GT workarounds and stepping-specific logic must be applied in 758 * relation to a specific subplatform (G10/G11/G12), whereas display workarounds 759 * and stepping-specific logic will be applied with a general DG2-wide stepping 760 * number. 761 */ 762#define IS_DG2_GRAPHICS_STEP(__i915, variant, since, until) \ 763 (IS_SUBPLATFORM(__i915, INTEL_DG2, INTEL_SUBPLATFORM_##variant) && \ 764 IS_GRAPHICS_STEP(__i915, since, until)) 765 766#define IS_DG2_DISPLAY_STEP(__i915, since, until) \ 767 (IS_DG2(__i915) && \ 768 IS_DISPLAY_STEP(__i915, since, until)) 769 770#define IS_PVC_BD_STEP(__i915, since, until) \ 771 (IS_PONTEVECCHIO(__i915) && \ 772 IS_BASEDIE_STEP(__i915, since, until)) 773 774#define IS_PVC_CT_STEP(__i915, since, until) \ 775 (IS_PONTEVECCHIO(__i915) && \ 776 IS_GRAPHICS_STEP(__i915, since, until)) 777 778#define IS_LP(i915) (INTEL_INFO(i915)->is_lp) 779#define IS_GEN9_LP(i915) (GRAPHICS_VER(i915) == 9 && IS_LP(i915)) 780#define IS_GEN9_BC(i915) (GRAPHICS_VER(i915) == 9 && !IS_LP(i915)) 781 782#define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id)) 783#define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id) 784 785#define __ENGINE_INSTANCES_MASK(mask, first, count) ({ \ 786 unsigned int first__ = (first); \ 787 unsigned int count__ = (count); \ 788 ((mask) & GENMASK(first__ + count__ - 1, first__)) >> first__; \ 789}) 790 791#define ENGINE_INSTANCES_MASK(gt, first, count) \ 792 __ENGINE_INSTANCES_MASK((gt)->info.engine_mask, first, count) 793 794#define RCS_MASK(gt) \ 795 ENGINE_INSTANCES_MASK(gt, RCS0, I915_MAX_RCS) 796#define BCS_MASK(gt) \ 797 ENGINE_INSTANCES_MASK(gt, BCS0, I915_MAX_BCS) 798#define VDBOX_MASK(gt) \ 799 ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS) 800#define VEBOX_MASK(gt) \ 801 ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS) 802#define CCS_MASK(gt) \ 803 ENGINE_INSTANCES_MASK(gt, CCS0, I915_MAX_CCS) 804 805#define HAS_MEDIA_RATIO_MODE(i915) (INTEL_INFO(i915)->has_media_ratio_mode) 806 807/* 808 * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution 809 * All later gens can run the final buffer from the ppgtt 810 */ 811#define CMDPARSER_USES_GGTT(i915) (GRAPHICS_VER(i915) == 7) 812 813#define HAS_LLC(i915) (INTEL_INFO(i915)->has_llc) 814#define HAS_4TILE(i915) (INTEL_INFO(i915)->has_4tile) 815#define HAS_SNOOP(i915) (INTEL_INFO(i915)->has_snoop) 816#define HAS_EDRAM(i915) ((i915)->edram_size_mb) 817#define HAS_SECURE_BATCHES(i915) (GRAPHICS_VER(i915) < 6) 818#define HAS_WT(i915) HAS_EDRAM(i915) 819 820#define HWS_NEEDS_PHYSICAL(i915) (INTEL_INFO(i915)->hws_needs_physical) 821 822#define HAS_LOGICAL_RING_CONTEXTS(i915) \ 823 (INTEL_INFO(i915)->has_logical_ring_contexts) 824#define HAS_LOGICAL_RING_ELSQ(i915) \ 825 (INTEL_INFO(i915)->has_logical_ring_elsq) 826 827#define HAS_EXECLISTS(i915) HAS_LOGICAL_RING_CONTEXTS(i915) 828 829#define INTEL_PPGTT(i915) (RUNTIME_INFO(i915)->ppgtt_type) 830#define HAS_PPGTT(i915) \ 831 (INTEL_PPGTT(i915) != INTEL_PPGTT_NONE) 832#define HAS_FULL_PPGTT(i915) \ 833 (INTEL_PPGTT(i915) >= INTEL_PPGTT_FULL) 834 835#define HAS_PAGE_SIZES(i915, sizes) ({ \ 836 GEM_BUG_ON((sizes) == 0); \ 837 ((sizes) & ~RUNTIME_INFO(i915)->page_sizes) == 0; \ 838}) 839 840/* Early gen2 have a totally busted CS tlb and require pinned batches. */ 841#define HAS_BROKEN_CS_TLB(i915) (IS_I830(i915) || IS_I845G(i915)) 842 843#define NEEDS_RC6_CTX_CORRUPTION_WA(i915) \ 844 (IS_BROADWELL(i915) || GRAPHICS_VER(i915) == 9) 845 846/* WaRsDisableCoarsePowerGating:skl,cnl */ 847#define NEEDS_WaRsDisableCoarsePowerGating(i915) \ 848 (IS_SKYLAKE_GT3(i915) || IS_SKYLAKE_GT4(i915)) 849 850/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 851 * rows, which changed the alignment requirements and fence programming. 852 */ 853#define HAS_128_BYTE_Y_TILING(i915) (GRAPHICS_VER(i915) != 2 && \ 854 !(IS_I915G(i915) || IS_I915GM(i915))) 855 856#define HAS_RC6(i915) (INTEL_INFO(i915)->has_rc6) 857#define HAS_RC6p(i915) (INTEL_INFO(i915)->has_rc6p) 858#define HAS_RC6pp(i915) (false) /* HW was never validated */ 859 860#define HAS_RPS(i915) (INTEL_INFO(i915)->has_rps) 861 862#define HAS_HECI_PXP(i915) \ 863 (INTEL_INFO(i915)->has_heci_pxp) 864 865#define HAS_HECI_GSCFI(i915) \ 866 (INTEL_INFO(i915)->has_heci_gscfi) 867 868#define HAS_HECI_GSC(i915) (HAS_HECI_PXP(i915) || HAS_HECI_GSCFI(i915)) 869 870#define HAS_RUNTIME_PM(i915) (INTEL_INFO(i915)->has_runtime_pm) 871#define HAS_64BIT_RELOC(i915) (INTEL_INFO(i915)->has_64bit_reloc) 872 873#define HAS_OA_BPC_REPORTING(i915) \ 874 (INTEL_INFO(i915)->has_oa_bpc_reporting) 875#define HAS_OA_SLICE_CONTRIB_LIMITS(i915) \ 876 (INTEL_INFO(i915)->has_oa_slice_contrib_limits) 877#define HAS_OAM(i915) \ 878 (INTEL_INFO(i915)->has_oam) 879 880/* 881 * Set this flag, when platform requires 64K GTT page sizes or larger for 882 * device local memory access. 883 */ 884#define HAS_64K_PAGES(i915) (INTEL_INFO(i915)->has_64k_pages) 885 886#define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i)) 887#define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM) 888 889#define HAS_EXTRA_GT_LIST(i915) (INTEL_INFO(i915)->extra_gt_list) 890 891/* 892 * Platform has the dedicated compression control state for each lmem surfaces 893 * stored in lmem to support the 3D and media compression formats. 894 */ 895#define HAS_FLAT_CCS(i915) (INTEL_INFO(i915)->has_flat_ccs) 896 897#define HAS_GT_UC(i915) (INTEL_INFO(i915)->has_gt_uc) 898 899#define HAS_POOLED_EU(i915) (RUNTIME_INFO(i915)->has_pooled_eu) 900 901#define HAS_GLOBAL_MOCS_REGISTERS(i915) (INTEL_INFO(i915)->has_global_mocs) 902 903#define HAS_GMD_ID(i915) (INTEL_INFO(i915)->has_gmd_id) 904 905#define HAS_L3_CCS_READ(i915) (INTEL_INFO(i915)->has_l3_ccs_read) 906 907/* DPF == dynamic parity feature */ 908#define HAS_L3_DPF(i915) (INTEL_INFO(i915)->has_l3_dpf) 909#define NUM_L3_SLICES(i915) (IS_HASWELL_GT3(i915) ? \ 910 2 : HAS_L3_DPF(i915)) 911 912/* Only valid when HAS_DISPLAY() is true */ 913#define INTEL_DISPLAY_ENABLED(i915) \ 914 (drm_WARN_ON(&(i915)->drm, !HAS_DISPLAY(i915)), \ 915 !(i915)->params.disable_display && \ 916 !intel_opregion_headless_sku(i915)) 917 918#define HAS_GUC_DEPRIVILEGE(i915) \ 919 (INTEL_INFO(i915)->has_guc_deprivilege) 920 921#define HAS_3D_PIPELINE(i915) (INTEL_INFO(i915)->has_3d_pipeline) 922 923#define HAS_ONE_EU_PER_FUSE_BIT(i915) (INTEL_INFO(i915)->has_one_eu_per_fuse_bit) 924 925#define HAS_LMEMBAR_SMEM_STOLEN(i915) (!HAS_LMEM(i915) && \ 926 GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) 927 928#endif 929