1/* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Eddie Dong <eddie.dong@intel.com> 25 * Kevin Tian <kevin.tian@intel.com> 26 * 27 * Contributors: 28 * Ping Gao <ping.a.gao@intel.com> 29 * Zhi Wang <zhi.a.wang@intel.com> 30 * Bing Niu <bing.niu@intel.com> 31 * 32 */ 33 34#include "i915_drv.h" 35#include "gvt.h" 36#include "i915_pvinfo.h" 37 38void populate_pvinfo_page(struct intel_vgpu *vgpu) 39{ 40 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 41 /* setup the ballooning information */ 42 vgpu_vreg64_t(vgpu, vgtif_reg(magic)) = VGT_MAGIC; 43 vgpu_vreg_t(vgpu, vgtif_reg(version_major)) = 1; 44 vgpu_vreg_t(vgpu, vgtif_reg(version_minor)) = 0; 45 vgpu_vreg_t(vgpu, vgtif_reg(display_ready)) = 0; 46 vgpu_vreg_t(vgpu, vgtif_reg(vgt_id)) = vgpu->id; 47 48 vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_PPGTT; 49 vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HWSP_EMULATION; 50 vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HUGE_GTT; 51 52 vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)) = 53 vgpu_aperture_gmadr_base(vgpu); 54 vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.mappable_gmadr.size)) = 55 vgpu_aperture_sz(vgpu); 56 vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.base)) = 57 vgpu_hidden_gmadr_base(vgpu); 58 vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.size)) = 59 vgpu_hidden_sz(vgpu); 60 61 vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.fence_num)) = vgpu_fence_sz(vgpu); 62 63 vgpu_vreg_t(vgpu, vgtif_reg(cursor_x_hot)) = UINT_MAX; 64 vgpu_vreg_t(vgpu, vgtif_reg(cursor_y_hot)) = UINT_MAX; 65 66 gvt_dbg_core("Populate PVINFO PAGE for vGPU %d\n", vgpu->id); 67 gvt_dbg_core("aperture base [GMADR] 0x%llx size 0x%llx\n", 68 vgpu_aperture_gmadr_base(vgpu), vgpu_aperture_sz(vgpu)); 69 gvt_dbg_core("hidden base [GMADR] 0x%llx size=0x%llx\n", 70 vgpu_hidden_gmadr_base(vgpu), vgpu_hidden_sz(vgpu)); 71 gvt_dbg_core("fence size %d\n", vgpu_fence_sz(vgpu)); 72 73 drm_WARN_ON(&i915->drm, sizeof(struct vgt_if) != VGT_PVINFO_SIZE); 74} 75 76/* 77 * vGPU type name is defined as GVTg_Vx_y which contains the physical GPU 78 * generation type (e.g V4 as BDW server, V5 as SKL server). 79 * 80 * Depening on the physical SKU resource, we might see vGPU types like 81 * GVTg_V4_8, GVTg_V4_4, GVTg_V4_2, etc. We can create different types of 82 * vGPU on same physical GPU depending on available resource. Each vGPU 83 * type will have a different number of avail_instance to indicate how 84 * many vGPU instance can be created for this type. 85 */ 86#define VGPU_MAX_WEIGHT 16 87#define VGPU_WEIGHT(vgpu_num) \ 88 (VGPU_MAX_WEIGHT / (vgpu_num)) 89 90static const struct intel_vgpu_config intel_vgpu_configs[] = { 91 { MB_TO_BYTES(64), MB_TO_BYTES(384), 4, VGPU_WEIGHT(8), GVT_EDID_1024_768, "8" }, 92 { MB_TO_BYTES(128), MB_TO_BYTES(512), 4, VGPU_WEIGHT(4), GVT_EDID_1920_1200, "4" }, 93 { MB_TO_BYTES(256), MB_TO_BYTES(1024), 4, VGPU_WEIGHT(2), GVT_EDID_1920_1200, "2" }, 94 { MB_TO_BYTES(512), MB_TO_BYTES(2048), 4, VGPU_WEIGHT(1), GVT_EDID_1920_1200, "1" }, 95}; 96 97/** 98 * intel_gvt_init_vgpu_types - initialize vGPU type list 99 * @gvt : GVT device 100 * 101 * Initialize vGPU type list based on available resource. 102 * 103 */ 104int intel_gvt_init_vgpu_types(struct intel_gvt *gvt) 105{ 106 unsigned int low_avail = gvt_aperture_sz(gvt) - HOST_LOW_GM_SIZE; 107 unsigned int high_avail = gvt_hidden_sz(gvt) - HOST_HIGH_GM_SIZE; 108 unsigned int num_types = ARRAY_SIZE(intel_vgpu_configs); 109 unsigned int i; 110 111 gvt->types = kcalloc(num_types, sizeof(struct intel_vgpu_type), 112 GFP_KERNEL); 113 if (!gvt->types) 114 return -ENOMEM; 115 116 gvt->mdev_types = kcalloc(num_types, sizeof(*gvt->mdev_types), 117 GFP_KERNEL); 118 if (!gvt->mdev_types) 119 goto out_free_types; 120 121 for (i = 0; i < num_types; ++i) { 122 const struct intel_vgpu_config *conf = &intel_vgpu_configs[i]; 123 124 if (low_avail / conf->low_mm == 0) 125 break; 126 if (conf->weight < 1 || conf->weight > VGPU_MAX_WEIGHT) 127 goto out_free_mdev_types; 128 129 sprintf(gvt->types[i].name, "GVTg_V%u_%s", 130 GRAPHICS_VER(gvt->gt->i915) == 8 ? 4 : 5, conf->name); 131 gvt->types[i].conf = conf; 132 133 gvt_dbg_core("type[%d]: %s avail %u low %u high %u fence %u weight %u res %s\n", 134 i, gvt->types[i].name, 135 min(low_avail / conf->low_mm, 136 high_avail / conf->high_mm), 137 conf->low_mm, conf->high_mm, conf->fence, 138 conf->weight, vgpu_edid_str(conf->edid)); 139 140 gvt->mdev_types[i] = &gvt->types[i].type; 141 gvt->mdev_types[i]->sysfs_name = gvt->types[i].name; 142 } 143 144 gvt->num_types = i; 145 return 0; 146 147out_free_mdev_types: 148 kfree(gvt->mdev_types); 149out_free_types: 150 kfree(gvt->types); 151 return -EINVAL; 152} 153 154void intel_gvt_clean_vgpu_types(struct intel_gvt *gvt) 155{ 156 kfree(gvt->mdev_types); 157 kfree(gvt->types); 158} 159 160/** 161 * intel_gvt_activate_vgpu - activate a virtual GPU 162 * @vgpu: virtual GPU 163 * 164 * This function is called when user wants to activate a virtual GPU. 165 * 166 */ 167void intel_gvt_activate_vgpu(struct intel_vgpu *vgpu) 168{ 169 set_bit(INTEL_VGPU_STATUS_ACTIVE, vgpu->status); 170} 171 172/** 173 * intel_gvt_deactivate_vgpu - deactivate a virtual GPU 174 * @vgpu: virtual GPU 175 * 176 * This function is called when user wants to deactivate a virtual GPU. 177 * The virtual GPU will be stopped. 178 * 179 */ 180void intel_gvt_deactivate_vgpu(struct intel_vgpu *vgpu) 181{ 182 mutex_lock(&vgpu->vgpu_lock); 183 184 clear_bit(INTEL_VGPU_STATUS_ACTIVE, vgpu->status); 185 186 if (atomic_read(&vgpu->submission.running_workload_num)) { 187 mutex_unlock(&vgpu->vgpu_lock); 188 intel_gvt_wait_vgpu_idle(vgpu); 189 mutex_lock(&vgpu->vgpu_lock); 190 } 191 192 intel_vgpu_stop_schedule(vgpu); 193 194 mutex_unlock(&vgpu->vgpu_lock); 195} 196 197/** 198 * intel_gvt_release_vgpu - release a virtual GPU 199 * @vgpu: virtual GPU 200 * 201 * This function is called when user wants to release a virtual GPU. 202 * The virtual GPU will be stopped and all runtime information will be 203 * destroyed. 204 * 205 */ 206void intel_gvt_release_vgpu(struct intel_vgpu *vgpu) 207{ 208 intel_gvt_deactivate_vgpu(vgpu); 209 210 mutex_lock(&vgpu->vgpu_lock); 211 vgpu->d3_entered = false; 212 intel_vgpu_clean_workloads(vgpu, ALL_ENGINES); 213 intel_vgpu_dmabuf_cleanup(vgpu); 214 mutex_unlock(&vgpu->vgpu_lock); 215} 216 217/** 218 * intel_gvt_destroy_vgpu - destroy a virtual GPU 219 * @vgpu: virtual GPU 220 * 221 * This function is called when user wants to destroy a virtual GPU. 222 * 223 */ 224void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu) 225{ 226 struct intel_gvt *gvt = vgpu->gvt; 227 struct drm_i915_private *i915 = gvt->gt->i915; 228 229 drm_WARN(&i915->drm, test_bit(INTEL_VGPU_STATUS_ACTIVE, vgpu->status), 230 "vGPU is still active!\n"); 231 232 /* 233 * remove idr first so later clean can judge if need to stop 234 * service if no active vgpu. 235 */ 236 mutex_lock(&gvt->lock); 237 idr_remove(&gvt->vgpu_idr, vgpu->id); 238 mutex_unlock(&gvt->lock); 239 240 mutex_lock(&vgpu->vgpu_lock); 241 intel_gvt_debugfs_remove_vgpu(vgpu); 242 intel_vgpu_clean_sched_policy(vgpu); 243 intel_vgpu_clean_submission(vgpu); 244 intel_vgpu_clean_display(vgpu); 245 intel_vgpu_clean_opregion(vgpu); 246 intel_vgpu_reset_ggtt(vgpu, true); 247 intel_vgpu_clean_gtt(vgpu); 248 intel_vgpu_detach_regions(vgpu); 249 intel_vgpu_free_resource(vgpu); 250 intel_vgpu_clean_mmio(vgpu); 251 intel_vgpu_dmabuf_cleanup(vgpu); 252 mutex_unlock(&vgpu->vgpu_lock); 253} 254 255#define IDLE_VGPU_IDR 0 256 257/** 258 * intel_gvt_create_idle_vgpu - create an idle virtual GPU 259 * @gvt: GVT device 260 * 261 * This function is called when user wants to create an idle virtual GPU. 262 * 263 * Returns: 264 * pointer to intel_vgpu, error pointer if failed. 265 */ 266struct intel_vgpu *intel_gvt_create_idle_vgpu(struct intel_gvt *gvt) 267{ 268 struct intel_vgpu *vgpu; 269 enum intel_engine_id i; 270 int ret; 271 272 vgpu = vzalloc(sizeof(*vgpu)); 273 if (!vgpu) 274 return ERR_PTR(-ENOMEM); 275 276 vgpu->id = IDLE_VGPU_IDR; 277 vgpu->gvt = gvt; 278 rw_init(&vgpu->vgpu_lock, "vgpu"); 279 280 for (i = 0; i < I915_NUM_ENGINES; i++) 281 INIT_LIST_HEAD(&vgpu->submission.workload_q_head[i]); 282 283 ret = intel_vgpu_init_sched_policy(vgpu); 284 if (ret) 285 goto out_free_vgpu; 286 287 clear_bit(INTEL_VGPU_STATUS_ACTIVE, vgpu->status); 288 return vgpu; 289 290out_free_vgpu: 291 vfree(vgpu); 292 return ERR_PTR(ret); 293} 294 295/** 296 * intel_gvt_destroy_idle_vgpu - destroy an idle virtual GPU 297 * @vgpu: virtual GPU 298 * 299 * This function is called when user wants to destroy an idle virtual GPU. 300 * 301 */ 302void intel_gvt_destroy_idle_vgpu(struct intel_vgpu *vgpu) 303{ 304 mutex_lock(&vgpu->vgpu_lock); 305 intel_vgpu_clean_sched_policy(vgpu); 306 mutex_unlock(&vgpu->vgpu_lock); 307 308 vfree(vgpu); 309} 310 311int intel_gvt_create_vgpu(struct intel_vgpu *vgpu, 312 const struct intel_vgpu_config *conf) 313{ 314 struct intel_gvt *gvt = vgpu->gvt; 315 struct drm_i915_private *dev_priv = gvt->gt->i915; 316 int ret; 317 318 gvt_dbg_core("low %u MB high %u MB fence %u\n", 319 BYTES_TO_MB(conf->low_mm), BYTES_TO_MB(conf->high_mm), 320 conf->fence); 321 322 mutex_lock(&gvt->lock); 323 ret = idr_alloc(&gvt->vgpu_idr, vgpu, IDLE_VGPU_IDR + 1, GVT_MAX_VGPU, 324 GFP_KERNEL); 325 if (ret < 0) 326 goto out_unlock; 327 328 vgpu->id = ret; 329 vgpu->sched_ctl.weight = conf->weight; 330 rw_init(&vgpu->vgpu_lock, "vgpulk"); 331 rw_init(&vgpu->dmabuf_lock, "vgpudb"); 332 INIT_LIST_HEAD(&vgpu->dmabuf_obj_list_head); 333 INIT_RADIX_TREE(&vgpu->page_track_tree, GFP_KERNEL); 334 idr_init_base(&vgpu->object_idr, 1); 335 intel_vgpu_init_cfg_space(vgpu, 1); 336 vgpu->d3_entered = false; 337 338 ret = intel_vgpu_init_mmio(vgpu); 339 if (ret) 340 goto out_clean_idr; 341 342 ret = intel_vgpu_alloc_resource(vgpu, conf); 343 if (ret) 344 goto out_clean_vgpu_mmio; 345 346 populate_pvinfo_page(vgpu); 347 348 ret = intel_vgpu_init_gtt(vgpu); 349 if (ret) 350 goto out_clean_vgpu_resource; 351 352 ret = intel_vgpu_init_opregion(vgpu); 353 if (ret) 354 goto out_clean_gtt; 355 356 ret = intel_vgpu_init_display(vgpu, conf->edid); 357 if (ret) 358 goto out_clean_opregion; 359 360 ret = intel_vgpu_setup_submission(vgpu); 361 if (ret) 362 goto out_clean_display; 363 364 ret = intel_vgpu_init_sched_policy(vgpu); 365 if (ret) 366 goto out_clean_submission; 367 368 intel_gvt_debugfs_add_vgpu(vgpu); 369 370 ret = intel_gvt_set_opregion(vgpu); 371 if (ret) 372 goto out_clean_sched_policy; 373 374 if (IS_BROADWELL(dev_priv) || IS_BROXTON(dev_priv)) 375 ret = intel_gvt_set_edid(vgpu, PORT_B); 376 else 377 ret = intel_gvt_set_edid(vgpu, PORT_D); 378 if (ret) 379 goto out_clean_sched_policy; 380 381 intel_gvt_update_reg_whitelist(vgpu); 382 mutex_unlock(&gvt->lock); 383 return 0; 384 385out_clean_sched_policy: 386 intel_vgpu_clean_sched_policy(vgpu); 387out_clean_submission: 388 intel_vgpu_clean_submission(vgpu); 389out_clean_display: 390 intel_vgpu_clean_display(vgpu); 391out_clean_opregion: 392 intel_vgpu_clean_opregion(vgpu); 393out_clean_gtt: 394 intel_vgpu_clean_gtt(vgpu); 395out_clean_vgpu_resource: 396 intel_vgpu_free_resource(vgpu); 397out_clean_vgpu_mmio: 398 intel_vgpu_clean_mmio(vgpu); 399out_clean_idr: 400 idr_remove(&gvt->vgpu_idr, vgpu->id); 401out_unlock: 402 mutex_unlock(&gvt->lock); 403 return ret; 404} 405 406/** 407 * intel_gvt_reset_vgpu_locked - reset a virtual GPU by DMLR or GT reset 408 * @vgpu: virtual GPU 409 * @dmlr: vGPU Device Model Level Reset or GT Reset 410 * @engine_mask: engines to reset for GT reset 411 * 412 * This function is called when user wants to reset a virtual GPU through 413 * device model reset or GT reset. The caller should hold the vgpu lock. 414 * 415 * vGPU Device Model Level Reset (DMLR) simulates the PCI level reset to reset 416 * the whole vGPU to default state as when it is created. This vGPU function 417 * is required both for functionary and security concerns.The ultimate goal 418 * of vGPU FLR is that reuse a vGPU instance by virtual machines. When we 419 * assign a vGPU to a virtual machine we must isse such reset first. 420 * 421 * Full GT Reset and Per-Engine GT Reset are soft reset flow for GPU engines 422 * (Render, Blitter, Video, Video Enhancement). It is defined by GPU Spec. 423 * Unlike the FLR, GT reset only reset particular resource of a vGPU per 424 * the reset request. Guest driver can issue a GT reset by programming the 425 * virtual GDRST register to reset specific virtual GPU engine or all 426 * engines. 427 * 428 * The parameter dev_level is to identify if we will do DMLR or GT reset. 429 * The parameter engine_mask is to specific the engines that need to be 430 * resetted. If value ALL_ENGINES is given for engine_mask, it means 431 * the caller requests a full GT reset that we will reset all virtual 432 * GPU engines. For FLR, engine_mask is ignored. 433 */ 434void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr, 435 intel_engine_mask_t engine_mask) 436{ 437 struct intel_gvt *gvt = vgpu->gvt; 438 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler; 439 intel_engine_mask_t resetting_eng = dmlr ? ALL_ENGINES : engine_mask; 440 441 gvt_dbg_core("------------------------------------------\n"); 442 gvt_dbg_core("resseting vgpu%d, dmlr %d, engine_mask %08x\n", 443 vgpu->id, dmlr, engine_mask); 444 445 vgpu->resetting_eng = resetting_eng; 446 447 intel_vgpu_stop_schedule(vgpu); 448 /* 449 * The current_vgpu will set to NULL after stopping the 450 * scheduler when the reset is triggered by current vgpu. 451 */ 452 if (scheduler->current_vgpu == NULL) { 453 mutex_unlock(&vgpu->vgpu_lock); 454 intel_gvt_wait_vgpu_idle(vgpu); 455 mutex_lock(&vgpu->vgpu_lock); 456 } 457 458 intel_vgpu_reset_submission(vgpu, resetting_eng); 459 /* full GPU reset or device model level reset */ 460 if (engine_mask == ALL_ENGINES || dmlr) { 461 intel_vgpu_select_submission_ops(vgpu, ALL_ENGINES, 0); 462 if (engine_mask == ALL_ENGINES) 463 intel_vgpu_invalidate_ppgtt(vgpu); 464 /*fence will not be reset during virtual reset */ 465 if (dmlr) { 466 if(!vgpu->d3_entered) { 467 intel_vgpu_invalidate_ppgtt(vgpu); 468 intel_vgpu_destroy_all_ppgtt_mm(vgpu); 469 } 470 intel_vgpu_reset_ggtt(vgpu, true); 471 intel_vgpu_reset_resource(vgpu); 472 } 473 474 intel_vgpu_reset_mmio(vgpu, dmlr); 475 populate_pvinfo_page(vgpu); 476 477 if (dmlr) { 478 intel_vgpu_reset_display(vgpu); 479 intel_vgpu_reset_cfg_space(vgpu); 480 /* only reset the failsafe mode when dmlr reset */ 481 vgpu->failsafe = false; 482 /* 483 * PCI_D0 is set before dmlr, so reset d3_entered here 484 * after done using. 485 */ 486 if(vgpu->d3_entered) 487 vgpu->d3_entered = false; 488 else 489 vgpu->pv_notified = false; 490 } 491 } 492 493 vgpu->resetting_eng = 0; 494 gvt_dbg_core("reset vgpu%d done\n", vgpu->id); 495 gvt_dbg_core("------------------------------------------\n"); 496} 497 498/** 499 * intel_gvt_reset_vgpu - reset a virtual GPU (Function Level) 500 * @vgpu: virtual GPU 501 * 502 * This function is called when user wants to reset a virtual GPU. 503 * 504 */ 505void intel_gvt_reset_vgpu(struct intel_vgpu *vgpu) 506{ 507 mutex_lock(&vgpu->vgpu_lock); 508 intel_gvt_reset_vgpu_locked(vgpu, true, 0); 509 mutex_unlock(&vgpu->vgpu_lock); 510} 511