1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright �� 2023 Intel Corporation
4 */
5
6#ifndef __INTEL_DP_AUX_REGS_H__
7#define __INTEL_DP_AUX_REGS_H__
8
9#include "intel_display_reg_defs.h"
10
11/*
12 * The aux channel provides a way to talk to the signal sink for DDC etc. Max
13 * packet size supported is 20 bytes in each direction, hence the 5 fixed data
14 * registers
15 */
16#define _DPA_AUX_CH_CTL		(DISPLAY_MMIO_BASE(dev_priv) + 0x64010)
17#define _DPA_AUX_CH_DATA1	(DISPLAY_MMIO_BASE(dev_priv) + 0x64014)
18
19#define _DPB_AUX_CH_CTL		(DISPLAY_MMIO_BASE(dev_priv) + 0x64110)
20#define _DPB_AUX_CH_DATA1	(DISPLAY_MMIO_BASE(dev_priv) + 0x64114)
21
22#define DP_AUX_CH_CTL(aux_ch)	_MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
23#define DP_AUX_CH_DATA(aux_ch, i)	_MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
24
25#define _XELPDP_USBC1_AUX_CH_CTL	0x16F210
26#define _XELPDP_USBC2_AUX_CH_CTL	0x16F410
27#define _XELPDP_USBC3_AUX_CH_CTL	0x16F610
28#define _XELPDP_USBC4_AUX_CH_CTL	0x16F810
29
30#define XELPDP_DP_AUX_CH_CTL(aux_ch)		_MMIO(_PICK(aux_ch, \
31						       _DPA_AUX_CH_CTL, \
32						       _DPB_AUX_CH_CTL, \
33						       0, /* port/aux_ch C is non-existent */ \
34						       _XELPDP_USBC1_AUX_CH_CTL, \
35						       _XELPDP_USBC2_AUX_CH_CTL, \
36						       _XELPDP_USBC3_AUX_CH_CTL, \
37						       _XELPDP_USBC4_AUX_CH_CTL))
38
39#define _XELPDP_USBC1_AUX_CH_DATA1      0x16F214
40#define _XELPDP_USBC2_AUX_CH_DATA1      0x16F414
41#define _XELPDP_USBC3_AUX_CH_DATA1      0x16F614
42#define _XELPDP_USBC4_AUX_CH_DATA1      0x16F814
43
44#define XELPDP_DP_AUX_CH_DATA(aux_ch, i)	_MMIO(_PICK(aux_ch, \
45						       _DPA_AUX_CH_DATA1, \
46						       _DPB_AUX_CH_DATA1, \
47						       0, /* port/aux_ch C is non-existent */ \
48						       _XELPDP_USBC1_AUX_CH_DATA1, \
49						       _XELPDP_USBC2_AUX_CH_DATA1, \
50						       _XELPDP_USBC3_AUX_CH_DATA1, \
51						       _XELPDP_USBC4_AUX_CH_DATA1) + (i) * 4)
52
53#define   DP_AUX_CH_CTL_SEND_BUSY		REG_BIT(31)
54#define   DP_AUX_CH_CTL_DONE			REG_BIT(30)
55#define   DP_AUX_CH_CTL_INTERRUPT		REG_BIT(29)
56#define   DP_AUX_CH_CTL_TIME_OUT_ERROR		REG_BIT(28)
57
58#define   DP_AUX_CH_CTL_TIME_OUT_MASK		REG_GENMASK(27, 26)
59#define   DP_AUX_CH_CTL_TIME_OUT_400us		REG_FIELD_PREP(DP_AUX_CH_CTL_TIME_OUT_MASK, 0)
60#define   DP_AUX_CH_CTL_TIME_OUT_600us		REG_FIELD_PREP(DP_AUX_CH_CTL_TIME_OUT_MASK, 1)
61#define   DP_AUX_CH_CTL_TIME_OUT_800us		REG_FIELD_PREP(DP_AUX_CH_CTL_TIME_OUT_MASK, 2)
62#define   DP_AUX_CH_CTL_TIME_OUT_MAX		REG_FIELD_PREP(DP_AUX_CH_CTL_TIME_OUT_MASK, 3) /* Varies per platform */
63#define   DP_AUX_CH_CTL_RECEIVE_ERROR		REG_BIT(25)
64#define   DP_AUX_CH_CTL_MESSAGE_SIZE_MASK	REG_GENMASK(24, 20)
65#define   DP_AUX_CH_CTL_MESSAGE_SIZE(x)		REG_FIELD_PREP(DP_AUX_CH_CTL_MESSAGE_SIZE_MASK, (x))
66#define   DP_AUX_CH_CTL_PRECHARGE_2US_MASK	REG_GENMASK(19, 16) /* pre-skl */
67#define   DP_AUX_CH_CTL_PRECHARGE_2US(x)	REG_FIELD_PREP(DP_AUX_CH_CTL_PRECHARGE_2US_MASK, (x))
68#define   XELPDP_DP_AUX_CH_CTL_POWER_REQUEST	REG_BIT(19) /* mtl+ */
69#define   XELPDP_DP_AUX_CH_CTL_POWER_STATUS	REG_BIT(18) /* mtl+ */
70#define   DP_AUX_CH_CTL_AUX_AKSV_SELECT		REG_BIT(15)
71#define   DP_AUX_CH_CTL_MANCHESTER_TEST		REG_BIT(14) /* pre-hsw */
72#define   DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL	REG_BIT(14) /* skl+ */
73#define   DP_AUX_CH_CTL_SYNC_TEST		REG_BIT(13) /* pre-hsw */
74#define   DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL	REG_BIT(13) /* skl+ */
75#define   DP_AUX_CH_CTL_DEGLITCH_TEST		REG_BIT(12) /* pre-hsw */
76#define   DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL	REG_BIT(12) /* skl+ */
77#define   DP_AUX_CH_CTL_PRECHARGE_TEST		REG_BIT(11) /* pre-hsw */
78#define   DP_AUX_CH_CTL_TBT_IO			REG_BIT(11) /* icl+ */
79#define   DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK	REG_GENMASK(10, 0) /* pre-skl */
80#define   DP_AUX_CH_CTL_BIT_CLOCK_2X(x)		REG_FIELD_PREP(DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK, (x))
81#define   DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK	REG_GENMASK(9, 5) /* skl+ */
82#define   DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c)	REG_FIELD_PREP(DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK, (c) - 1)
83#define   DP_AUX_CH_CTL_SYNC_PULSE_SKL_MASK	REG_GENMASK(4, 0) /* skl+ */
84#define   DP_AUX_CH_CTL_SYNC_PULSE_SKL(c)	REG_FIELD_PREP(DP_AUX_CH_CTL_SYNC_PULSE_SKL_MASK, (c) - 1)
85
86#endif /* __INTEL_DP_AUX_REGS_H__ */
87