1/* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23#ifndef SMU71_H 24#define SMU71_H 25 26#if !defined(SMC_MICROCODE) 27#pragma pack(push, 1) 28#endif 29 30#define SMU__NUM_PCIE_DPM_LEVELS 8 31#define SMU__NUM_SCLK_DPM_STATE 8 32#define SMU__NUM_MCLK_DPM_LEVELS 4 33#define SMU__VARIANT__ICELAND 1 34#define SMU__DGPU_ONLY 1 35#define SMU__DYNAMIC_MCARB_SETTINGS 1 36 37enum SID_OPTION { 38 SID_OPTION_HI, 39 SID_OPTION_LO, 40 SID_OPTION_COUNT 41}; 42 43typedef struct { 44 uint32_t high; 45 uint32_t low; 46} data_64_t; 47 48typedef struct { 49 data_64_t high; 50 data_64_t low; 51} data_128_t; 52 53#define SMU7_CONTEXT_ID_SMC 1 54#define SMU7_CONTEXT_ID_VBIOS 2 55 56#define SMU71_MAX_LEVELS_VDDC 8 57#define SMU71_MAX_LEVELS_VDDCI 4 58#define SMU71_MAX_LEVELS_MVDD 4 59#define SMU71_MAX_LEVELS_VDDNB 8 60 61#define SMU71_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE 62#define SMU71_MAX_LEVELS_MEMORY SMU__NUM_MCLK_DPM_LEVELS 63#define SMU71_MAX_LEVELS_GIO SMU__NUM_LCLK_DPM_LEVELS 64#define SMU71_MAX_LEVELS_LINK SMU__NUM_PCIE_DPM_LEVELS 65#define SMU71_MAX_ENTRIES_SMIO 32 66 67#define DPM_NO_LIMIT 0 68#define DPM_NO_UP 1 69#define DPM_GO_DOWN 2 70#define DPM_GO_UP 3 71 72#define SMU7_FIRST_DPM_GRAPHICS_LEVEL 0 73#define SMU7_FIRST_DPM_MEMORY_LEVEL 0 74 75#define GPIO_CLAMP_MODE_VRHOT 1 76#define GPIO_CLAMP_MODE_THERM 2 77#define GPIO_CLAMP_MODE_DC 4 78 79#define SCRATCH_B_TARG_PCIE_INDEX_SHIFT 0 80#define SCRATCH_B_TARG_PCIE_INDEX_MASK (0x7<<SCRATCH_B_TARG_PCIE_INDEX_SHIFT) 81#define SCRATCH_B_CURR_PCIE_INDEX_SHIFT 3 82#define SCRATCH_B_CURR_PCIE_INDEX_MASK (0x7<<SCRATCH_B_CURR_PCIE_INDEX_SHIFT) 83#define SCRATCH_B_TARG_UVD_INDEX_SHIFT 6 84#define SCRATCH_B_TARG_UVD_INDEX_MASK (0x7<<SCRATCH_B_TARG_UVD_INDEX_SHIFT) 85#define SCRATCH_B_CURR_UVD_INDEX_SHIFT 9 86#define SCRATCH_B_CURR_UVD_INDEX_MASK (0x7<<SCRATCH_B_CURR_UVD_INDEX_SHIFT) 87#define SCRATCH_B_TARG_VCE_INDEX_SHIFT 12 88#define SCRATCH_B_TARG_VCE_INDEX_MASK (0x7<<SCRATCH_B_TARG_VCE_INDEX_SHIFT) 89#define SCRATCH_B_CURR_VCE_INDEX_SHIFT 15 90#define SCRATCH_B_CURR_VCE_INDEX_MASK (0x7<<SCRATCH_B_CURR_VCE_INDEX_SHIFT) 91#define SCRATCH_B_TARG_ACP_INDEX_SHIFT 18 92#define SCRATCH_B_TARG_ACP_INDEX_MASK (0x7<<SCRATCH_B_TARG_ACP_INDEX_SHIFT) 93#define SCRATCH_B_CURR_ACP_INDEX_SHIFT 21 94#define SCRATCH_B_CURR_ACP_INDEX_MASK (0x7<<SCRATCH_B_CURR_ACP_INDEX_SHIFT) 95#define SCRATCH_B_TARG_SAMU_INDEX_SHIFT 24 96#define SCRATCH_B_TARG_SAMU_INDEX_MASK (0x7<<SCRATCH_B_TARG_SAMU_INDEX_SHIFT) 97#define SCRATCH_B_CURR_SAMU_INDEX_SHIFT 27 98#define SCRATCH_B_CURR_SAMU_INDEX_MASK (0x7<<SCRATCH_B_CURR_SAMU_INDEX_SHIFT) 99 100 101#if defined SMU__DGPU_ONLY 102#define SMU71_DTE_ITERATIONS 5 103#define SMU71_DTE_SOURCES 3 104#define SMU71_DTE_SINKS 1 105#define SMU71_NUM_CPU_TES 0 106#define SMU71_NUM_GPU_TES 1 107#define SMU71_NUM_NON_TES 2 108 109#endif 110 111#if defined SMU__FUSION_ONLY 112#define SMU7_DTE_ITERATIONS 5 113#define SMU7_DTE_SOURCES 5 114#define SMU7_DTE_SINKS 3 115#define SMU7_NUM_CPU_TES 2 116#define SMU7_NUM_GPU_TES 1 117#define SMU7_NUM_NON_TES 2 118 119#endif 120 121struct SMU71_PIDController { 122 uint32_t Ki; 123 int32_t LFWindupUpperLim; 124 int32_t LFWindupLowerLim; 125 uint32_t StatePrecision; 126 uint32_t LfPrecision; 127 uint32_t LfOffset; 128 uint32_t MaxState; 129 uint32_t MaxLfFraction; 130 uint32_t StateShift; 131}; 132 133typedef struct SMU71_PIDController SMU71_PIDController; 134 135struct SMU7_LocalDpmScoreboard { 136 uint32_t PercentageBusy; 137 138 int32_t PIDError; 139 int32_t PIDIntegral; 140 int32_t PIDOutput; 141 142 uint32_t SigmaDeltaAccum; 143 uint32_t SigmaDeltaOutput; 144 uint32_t SigmaDeltaLevel; 145 146 uint32_t UtilizationSetpoint; 147 148 uint8_t TdpClampMode; 149 uint8_t TdcClampMode; 150 uint8_t ThermClampMode; 151 uint8_t VoltageBusy; 152 153 int8_t CurrLevel; 154 int8_t TargLevel; 155 uint8_t LevelChangeInProgress; 156 uint8_t UpHyst; 157 158 uint8_t DownHyst; 159 uint8_t VoltageDownHyst; 160 uint8_t DpmEnable; 161 uint8_t DpmRunning; 162 163 uint8_t DpmForce; 164 uint8_t DpmForceLevel; 165 uint8_t DisplayWatermark; 166 uint8_t McArbIndex; 167 168 uint32_t MinimumPerfSclk; 169 170 uint8_t AcpiReq; 171 uint8_t AcpiAck; 172 uint8_t GfxClkSlow; 173 uint8_t GpioClampMode; 174 175 uint8_t FpsFilterWeight; 176 uint8_t EnabledLevelsChange; 177 uint8_t DteClampMode; 178 uint8_t FpsClampMode; 179 180 uint16_t LevelResidencyCounters[SMU71_MAX_LEVELS_GRAPHICS]; 181 uint16_t LevelSwitchCounters[SMU71_MAX_LEVELS_GRAPHICS]; 182 183 void (*TargetStateCalculator)(uint8_t); 184 void (*SavedTargetStateCalculator)(uint8_t); 185 186 uint16_t AutoDpmInterval; 187 uint16_t AutoDpmRange; 188 189 uint8_t FpsEnabled; 190 uint8_t MaxPerfLevel; 191 uint8_t AllowLowClkInterruptToHost; 192 uint8_t FpsRunning; 193 194 uint32_t MaxAllowedFrequency; 195}; 196 197typedef struct SMU7_LocalDpmScoreboard SMU7_LocalDpmScoreboard; 198 199#define SMU7_MAX_VOLTAGE_CLIENTS 12 200 201struct SMU7_VoltageScoreboard { 202 uint16_t CurrentVoltage; 203 uint16_t HighestVoltage; 204 uint16_t MaxVid; 205 uint8_t HighestVidOffset; 206 uint8_t CurrentVidOffset; 207#if defined (SMU__DGPU_ONLY) 208 uint8_t CurrentPhases; 209 uint8_t HighestPhases; 210#else 211 uint8_t AvsOffset; 212 uint8_t AvsOffsetApplied; 213#endif 214 uint8_t ControllerBusy; 215 uint8_t CurrentVid; 216 uint16_t RequestedVoltage[SMU7_MAX_VOLTAGE_CLIENTS]; 217#if defined (SMU__DGPU_ONLY) 218 uint8_t RequestedPhases[SMU7_MAX_VOLTAGE_CLIENTS]; 219#endif 220 uint8_t EnabledRequest[SMU7_MAX_VOLTAGE_CLIENTS]; 221 uint8_t TargetIndex; 222 uint8_t Delay; 223 uint8_t ControllerEnable; 224 uint8_t ControllerRunning; 225 uint16_t CurrentStdVoltageHiSidd; 226 uint16_t CurrentStdVoltageLoSidd; 227#if defined (SMU__DGPU_ONLY) 228 uint16_t RequestedVddci; 229 uint16_t CurrentVddci; 230 uint16_t HighestVddci; 231 uint8_t CurrentVddciVid; 232 uint8_t TargetVddciIndex; 233#endif 234}; 235 236typedef struct SMU7_VoltageScoreboard SMU7_VoltageScoreboard; 237 238// ------------------------------------------------------------------------------------------------------------------------- 239#define SMU7_MAX_PCIE_LINK_SPEEDS 3 /* 0:Gen1 1:Gen2 2:Gen3 */ 240 241struct SMU7_PCIeLinkSpeedScoreboard 242{ 243 uint8_t DpmEnable; 244 uint8_t DpmRunning; 245 uint8_t DpmForce; 246 uint8_t DpmForceLevel; 247 248 uint8_t CurrentLinkSpeed; 249 uint8_t EnabledLevelsChange; 250 uint16_t AutoDpmInterval; 251 252 uint16_t AutoDpmRange; 253 uint16_t AutoDpmCount; 254 255 uint8_t DpmMode; 256 uint8_t AcpiReq; 257 uint8_t AcpiAck; 258 uint8_t CurrentLinkLevel; 259 260}; 261 262typedef struct SMU7_PCIeLinkSpeedScoreboard SMU7_PCIeLinkSpeedScoreboard; 263 264// -------------------------------------------------------- CAC table ------------------------------------------------------ 265#define SMU7_LKGE_LUT_NUM_OF_TEMP_ENTRIES 16 266#define SMU7_LKGE_LUT_NUM_OF_VOLT_ENTRIES 16 267 268#define SMU7_SCALE_I 7 269#define SMU7_SCALE_R 12 270 271struct SMU7_PowerScoreboard 272{ 273 uint16_t MinVoltage; 274 uint16_t MaxVoltage; 275 276 uint32_t AvgGpuPower; 277 278 uint16_t VddcLeakagePower[SID_OPTION_COUNT]; 279 uint16_t VddcSclkConstantPower[SID_OPTION_COUNT]; 280 uint16_t VddcSclkDynamicPower[SID_OPTION_COUNT]; 281 uint16_t VddcNonSclkDynamicPower[SID_OPTION_COUNT]; 282 uint16_t VddcTotalPower[SID_OPTION_COUNT]; 283 uint16_t VddcTotalCurrent[SID_OPTION_COUNT]; 284 uint16_t VddcLoadVoltage[SID_OPTION_COUNT]; 285 uint16_t VddcNoLoadVoltage[SID_OPTION_COUNT]; 286 287 uint16_t DisplayPhyPower; 288 uint16_t PciePhyPower; 289 290 uint16_t VddciTotalPower; 291 uint16_t Vddr1TotalPower; 292 293 uint32_t RocPower; 294 295 uint32_t last_power; 296 uint32_t enableWinAvg; 297 298 uint32_t lkg_acc; 299 uint16_t VoltLkgeScaler; 300 uint16_t TempLkgeScaler; 301 302 uint32_t uvd_cac_dclk; 303 uint32_t uvd_cac_vclk; 304 uint32_t vce_cac_eclk; 305 uint32_t samu_cac_samclk; 306 uint32_t display_cac_dispclk; 307 uint32_t acp_cac_aclk; 308 uint32_t unb_cac; 309 310 uint32_t WinTime; 311 312 uint16_t GpuPwr_MAWt; 313 uint16_t FilteredVddcTotalPower; 314 315 uint8_t CalculationRepeats; 316 uint8_t WaterfallUp; 317 uint8_t WaterfallDown; 318 uint8_t WaterfallLimit; 319}; 320 321typedef struct SMU7_PowerScoreboard SMU7_PowerScoreboard; 322 323// -------------------------------------------------------------------------------------------------- 324 325struct SMU7_ThermalScoreboard { 326 int16_t GpuLimit; 327 int16_t GpuHyst; 328 uint16_t CurrGnbTemp; 329 uint16_t FilteredGnbTemp; 330 uint8_t ControllerEnable; 331 uint8_t ControllerRunning; 332 uint8_t WaterfallUp; 333 uint8_t WaterfallDown; 334 uint8_t WaterfallLimit; 335 uint8_t padding[3]; 336}; 337 338typedef struct SMU7_ThermalScoreboard SMU7_ThermalScoreboard; 339 340// For FeatureEnables: 341#define SMU7_SCLK_DPM_CONFIG_MASK 0x01 342#define SMU7_VOLTAGE_CONTROLLER_CONFIG_MASK 0x02 343#define SMU7_THERMAL_CONTROLLER_CONFIG_MASK 0x04 344#define SMU7_MCLK_DPM_CONFIG_MASK 0x08 345#define SMU7_UVD_DPM_CONFIG_MASK 0x10 346#define SMU7_VCE_DPM_CONFIG_MASK 0x20 347#define SMU7_ACP_DPM_CONFIG_MASK 0x40 348#define SMU7_SAMU_DPM_CONFIG_MASK 0x80 349#define SMU7_PCIEGEN_DPM_CONFIG_MASK 0x100 350 351#define SMU7_ACP_MCLK_HANDSHAKE_DISABLE 0x00000001 352#define SMU7_ACP_SCLK_HANDSHAKE_DISABLE 0x00000002 353#define SMU7_UVD_MCLK_HANDSHAKE_DISABLE 0x00000100 354#define SMU7_UVD_SCLK_HANDSHAKE_DISABLE 0x00000200 355#define SMU7_VCE_MCLK_HANDSHAKE_DISABLE 0x00010000 356#define SMU7_VCE_SCLK_HANDSHAKE_DISABLE 0x00020000 357 358// All 'soft registers' should be uint32_t. 359struct SMU71_SoftRegisters { 360 uint32_t RefClockFrequency; 361 uint32_t PmTimerPeriod; 362 uint32_t FeatureEnables; 363#if defined (SMU__DGPU_ONLY) 364 uint32_t PreVBlankGap; 365 uint32_t VBlankTimeout; 366 uint32_t TrainTimeGap; 367 uint32_t MvddSwitchTime; 368 uint32_t LongestAcpiTrainTime; 369 uint32_t AcpiDelay; 370 uint32_t G5TrainTime; 371 uint32_t DelayMpllPwron; 372 uint32_t VoltageChangeTimeout; 373#endif 374 uint32_t HandshakeDisables; 375 376 uint8_t DisplayPhy1Config; 377 uint8_t DisplayPhy2Config; 378 uint8_t DisplayPhy3Config; 379 uint8_t DisplayPhy4Config; 380 381 uint8_t DisplayPhy5Config; 382 uint8_t DisplayPhy6Config; 383 uint8_t DisplayPhy7Config; 384 uint8_t DisplayPhy8Config; 385 386 uint32_t AverageGraphicsActivity; 387 uint32_t AverageMemoryActivity; 388 uint32_t AverageGioActivity; 389 390 uint8_t SClkDpmEnabledLevels; 391 uint8_t MClkDpmEnabledLevels; 392 uint8_t LClkDpmEnabledLevels; 393 uint8_t PCIeDpmEnabledLevels; 394 395 uint32_t DRAM_LOG_ADDR_H; 396 uint32_t DRAM_LOG_ADDR_L; 397 uint32_t DRAM_LOG_PHY_ADDR_H; 398 uint32_t DRAM_LOG_PHY_ADDR_L; 399 uint32_t DRAM_LOG_BUFF_SIZE; 400 uint32_t UlvEnterCount; 401 uint32_t UlvTime; 402 uint32_t UcodeLoadStatus; 403 uint8_t DPMFreezeAndForced; 404 uint8_t Activity_Weight; 405 uint8_t Reserved8[2]; 406 uint32_t Reserved; 407}; 408 409typedef struct SMU71_SoftRegisters SMU71_SoftRegisters; 410 411struct SMU71_Firmware_Header { 412 uint32_t Digest[5]; 413 uint32_t Version; 414 uint32_t HeaderSize; 415 uint32_t Flags; 416 uint32_t EntryPoint; 417 uint32_t CodeSize; 418 uint32_t ImageSize; 419 420 uint32_t Rtos; 421 uint32_t SoftRegisters; 422 uint32_t DpmTable; 423 uint32_t FanTable; 424 uint32_t CacConfigTable; 425 uint32_t CacStatusTable; 426 427 uint32_t mcRegisterTable; 428 429 uint32_t mcArbDramTimingTable; 430 431 uint32_t PmFuseTable; 432 uint32_t Globals; 433 uint32_t UvdDpmTable; 434 uint32_t AcpDpmTable; 435 uint32_t VceDpmTable; 436 uint32_t SamuDpmTable; 437 uint32_t UlvSettings; 438 uint32_t Reserved[37]; 439 uint32_t Signature; 440}; 441 442typedef struct SMU71_Firmware_Header SMU71_Firmware_Header; 443 444struct SMU7_HystController_Data 445{ 446 uint8_t waterfall_up; 447 uint8_t waterfall_down; 448 uint8_t pstate; 449 uint8_t clamp_mode; 450}; 451 452typedef struct SMU7_HystController_Data SMU7_HystController_Data; 453 454#define SMU71_FIRMWARE_HEADER_LOCATION 0x20000 455 456enum DisplayConfig { 457 PowerDown = 1, 458 DP54x4, 459 DP54x2, 460 DP54x1, 461 DP27x4, 462 DP27x2, 463 DP27x1, 464 HDMI297, 465 HDMI162, 466 LVDS, 467 DP324x4, 468 DP324x2, 469 DP324x1 470}; 471 472//#define SX_BLOCK_COUNT 8 473//#define MC_BLOCK_COUNT 1 474//#define CPL_BLOCK_COUNT 27 475 476#if defined SMU__VARIANT__ICELAND 477 #define SX_BLOCK_COUNT 8 478 #define MC_BLOCK_COUNT 1 479 #define CPL_BLOCK_COUNT 29 480#endif 481 482struct SMU7_Local_Cac { 483 uint8_t BlockId; 484 uint8_t SignalId; 485 uint8_t Threshold; 486 uint8_t Padding; 487}; 488 489typedef struct SMU7_Local_Cac SMU7_Local_Cac; 490 491struct SMU7_Local_Cac_Table { 492 SMU7_Local_Cac SxLocalCac[SX_BLOCK_COUNT]; 493 SMU7_Local_Cac CplLocalCac[CPL_BLOCK_COUNT]; 494 SMU7_Local_Cac McLocalCac[MC_BLOCK_COUNT]; 495}; 496 497typedef struct SMU7_Local_Cac_Table SMU7_Local_Cac_Table; 498 499#if !defined(SMC_MICROCODE) 500#pragma pack(pop) 501#endif 502 503#endif 504 505