1/* SPDX-License-Identifier: MIT */ 2/* 3 * Copyright 2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25#ifndef _dcn_3_1_4_OFFSET_HEADER 26#define _dcn_3_1_4_OFFSET_HEADER 27 28 29 30// addressBlock: dce_dc_hda_azcontroller_azdec 31// base address: 0x0 32#define regAZCONTROLLER0_CORB_WRITE_POINTER 0x0000 33#define regAZCONTROLLER0_CORB_WRITE_POINTER_BASE_IDX 0 34#define regAZCONTROLLER0_CORB_READ_POINTER 0x0000 35#define regAZCONTROLLER0_CORB_READ_POINTER_BASE_IDX 0 36#define regAZCONTROLLER0_CORB_CONTROL 0x0001 37#define regAZCONTROLLER0_CORB_CONTROL_BASE_IDX 0 38#define regAZCONTROLLER0_CORB_STATUS 0x0001 39#define regAZCONTROLLER0_CORB_STATUS_BASE_IDX 0 40#define regAZCONTROLLER0_CORB_SIZE 0x0001 41#define regAZCONTROLLER0_CORB_SIZE_BASE_IDX 0 42#define regAZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS 0x0002 43#define regAZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS_BASE_IDX 0 44#define regAZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS 0x0003 45#define regAZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS_BASE_IDX 0 46#define regAZCONTROLLER0_RIRB_WRITE_POINTER 0x0004 47#define regAZCONTROLLER0_RIRB_WRITE_POINTER_BASE_IDX 0 48#define regAZCONTROLLER0_RESPONSE_INTERRUPT_COUNT 0x0004 49#define regAZCONTROLLER0_RESPONSE_INTERRUPT_COUNT_BASE_IDX 0 50#define regAZCONTROLLER0_RIRB_CONTROL 0x0005 51#define regAZCONTROLLER0_RIRB_CONTROL_BASE_IDX 0 52#define regAZCONTROLLER0_RIRB_STATUS 0x0005 53#define regAZCONTROLLER0_RIRB_STATUS_BASE_IDX 0 54#define regAZCONTROLLER0_RIRB_SIZE 0x0005 55#define regAZCONTROLLER0_RIRB_SIZE_BASE_IDX 0 56#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x0006 57#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX 0 58#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006 59#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0 60#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006 61#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0 62#define regAZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE 0x0007 63#define regAZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX 0 64#define regAZCONTROLLER0_IMMEDIATE_COMMAND_STATUS 0x0008 65#define regAZCONTROLLER0_IMMEDIATE_COMMAND_STATUS_BASE_IDX 0 66#define regAZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS 0x000a 67#define regAZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX 0 68#define regAZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS 0x000b 69#define regAZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX 0 70 71 72// addressBlock: vga_vgaseqind 73// base address: 0x0 74#define ixSEQ00 0x0000 75#define ixSEQ01 0x0001 76#define ixSEQ02 0x0002 77#define ixSEQ03 0x0003 78#define ixSEQ04 0x0004 79 80 81// addressBlock: vga_vgacrtind 82// base address: 0x0 83#define ixCRT00 0x0000 84#define ixCRT01 0x0001 85#define ixCRT02 0x0002 86#define ixCRT03 0x0003 87#define ixCRT04 0x0004 88#define ixCRT05 0x0005 89#define ixCRT06 0x0006 90#define ixCRT07 0x0007 91#define ixCRT08 0x0008 92#define ixCRT09 0x0009 93#define ixCRT0A 0x000a 94#define ixCRT0B 0x000b 95#define ixCRT0C 0x000c 96#define ixCRT0D 0x000d 97#define ixCRT0E 0x000e 98#define ixCRT0F 0x000f 99#define ixCRT10 0x0010 100#define ixCRT11 0x0011 101#define ixCRT12 0x0012 102#define ixCRT13 0x0013 103#define ixCRT14 0x0014 104#define ixCRT15 0x0015 105#define ixCRT16 0x0016 106#define ixCRT17 0x0017 107#define ixCRT18 0x0018 108#define ixCRT1E 0x001e 109#define ixCRT1F 0x001f 110#define ixCRT22 0x0022 111 112 113// addressBlock: vga_vgagrphind 114// base address: 0x0 115#define ixGRA00 0x0000 116#define ixGRA01 0x0001 117#define ixGRA02 0x0002 118#define ixGRA03 0x0003 119#define ixGRA04 0x0004 120#define ixGRA05 0x0005 121#define ixGRA06 0x0006 122#define ixGRA07 0x0007 123#define ixGRA08 0x0008 124 125 126// addressBlock: vga_vgaattrind 127// base address: 0x0 128#define ixATTR00 0x0000 129#define ixATTR01 0x0001 130#define ixATTR02 0x0002 131#define ixATTR03 0x0003 132#define ixATTR04 0x0004 133#define ixATTR05 0x0005 134#define ixATTR06 0x0006 135#define ixATTR07 0x0007 136#define ixATTR08 0x0008 137#define ixATTR09 0x0009 138#define ixATTR0A 0x000a 139#define ixATTR0B 0x000b 140#define ixATTR0C 0x000c 141#define ixATTR0D 0x000d 142#define ixATTR0E 0x000e 143#define ixATTR0F 0x000f 144#define ixATTR10 0x0010 145#define ixATTR11 0x0011 146#define ixATTR12 0x0012 147#define ixATTR13 0x0013 148#define ixATTR14 0x0014 149 150 151// addressBlock: azendpoint_sinkinfoind 152// base address: 0x0 153#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0000 154#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x0001 155#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x0002 156#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x0003 157#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x0004 158#define ixSINK_DESCRIPTION0 0x0005 159#define ixSINK_DESCRIPTION1 0x0006 160#define ixSINK_DESCRIPTION2 0x0007 161#define ixSINK_DESCRIPTION3 0x0008 162#define ixSINK_DESCRIPTION4 0x0009 163#define ixSINK_DESCRIPTION5 0x000a 164#define ixSINK_DESCRIPTION6 0x000b 165#define ixSINK_DESCRIPTION7 0x000c 166#define ixSINK_DESCRIPTION8 0x000d 167#define ixSINK_DESCRIPTION9 0x000e 168#define ixSINK_DESCRIPTION10 0x000f 169#define ixSINK_DESCRIPTION11 0x0010 170#define ixSINK_DESCRIPTION12 0x0011 171#define ixSINK_DESCRIPTION13 0x0012 172#define ixSINK_DESCRIPTION14 0x0013 173#define ixSINK_DESCRIPTION15 0x0014 174#define ixSINK_DESCRIPTION16 0x0015 175#define ixSINK_DESCRIPTION17 0x0016 176 177 178// addressBlock: azf0controller_azinputcrc0resultind 179// base address: 0x0 180#define ixAZALIA_INPUT_CRC0_CHANNEL0 0x0000 181#define ixAZALIA_INPUT_CRC0_CHANNEL1 0x0001 182#define ixAZALIA_INPUT_CRC0_CHANNEL2 0x0002 183#define ixAZALIA_INPUT_CRC0_CHANNEL3 0x0003 184#define ixAZALIA_INPUT_CRC0_CHANNEL4 0x0004 185#define ixAZALIA_INPUT_CRC0_CHANNEL5 0x0005 186#define ixAZALIA_INPUT_CRC0_CHANNEL6 0x0006 187#define ixAZALIA_INPUT_CRC0_CHANNEL7 0x0007 188 189 190// addressBlock: azf0controller_azinputcrc1resultind 191// base address: 0x0 192#define ixAZALIA_INPUT_CRC1_CHANNEL0 0x0000 193#define ixAZALIA_INPUT_CRC1_CHANNEL1 0x0001 194#define ixAZALIA_INPUT_CRC1_CHANNEL2 0x0002 195#define ixAZALIA_INPUT_CRC1_CHANNEL3 0x0003 196#define ixAZALIA_INPUT_CRC1_CHANNEL4 0x0004 197#define ixAZALIA_INPUT_CRC1_CHANNEL5 0x0005 198#define ixAZALIA_INPUT_CRC1_CHANNEL6 0x0006 199#define ixAZALIA_INPUT_CRC1_CHANNEL7 0x0007 200 201 202// addressBlock: azf0controller_azcrc0resultind 203// base address: 0x0 204#define ixAZALIA_CRC0_CHANNEL0 0x0000 205#define ixAZALIA_CRC0_CHANNEL1 0x0001 206#define ixAZALIA_CRC0_CHANNEL2 0x0002 207#define ixAZALIA_CRC0_CHANNEL3 0x0003 208#define ixAZALIA_CRC0_CHANNEL4 0x0004 209#define ixAZALIA_CRC0_CHANNEL5 0x0005 210#define ixAZALIA_CRC0_CHANNEL6 0x0006 211#define ixAZALIA_CRC0_CHANNEL7 0x0007 212 213 214// addressBlock: azf0controller_azcrc1resultind 215// base address: 0x0 216#define ixAZALIA_CRC1_CHANNEL0 0x0000 217#define ixAZALIA_CRC1_CHANNEL1 0x0001 218#define ixAZALIA_CRC1_CHANNEL2 0x0002 219#define ixAZALIA_CRC1_CHANNEL3 0x0003 220#define ixAZALIA_CRC1_CHANNEL4 0x0004 221#define ixAZALIA_CRC1_CHANNEL5 0x0005 222#define ixAZALIA_CRC1_CHANNEL6 0x0006 223#define ixAZALIA_CRC1_CHANNEL7 0x0007 224 225 226// addressBlock: azf0stream0_streamind 227// base address: 0x0 228#define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL 0x0000 229#define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 230#define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 231#define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 232#define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 233 234 235// addressBlock: azf0stream1_streamind 236// base address: 0x0 237#define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL 0x0000 238#define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 239#define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 240#define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 241#define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 242 243 244// addressBlock: azf0stream2_streamind 245// base address: 0x0 246#define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL 0x0000 247#define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 248#define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 249#define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 250#define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 251 252 253// addressBlock: azf0stream3_streamind 254// base address: 0x0 255#define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL 0x0000 256#define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 257#define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 258#define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 259#define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 260 261 262// addressBlock: azf0stream4_streamind 263// base address: 0x0 264#define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL 0x0000 265#define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 266#define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 267#define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 268#define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 269 270 271// addressBlock: azf0stream5_streamind 272// base address: 0x0 273#define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL 0x0000 274#define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 275#define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 276#define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 277#define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 278 279 280// addressBlock: azf0stream6_streamind 281// base address: 0x0 282#define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL 0x0000 283#define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 284#define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 285#define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 286#define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 287 288 289// addressBlock: azf0stream7_streamind 290// base address: 0x0 291#define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL 0x0000 292#define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 293#define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 294#define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 295#define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 296 297 298// addressBlock: azf0stream8_streamind 299// base address: 0x0 300#define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL 0x0000 301#define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 302#define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 303#define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 304#define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 305 306 307// addressBlock: azf0stream9_streamind 308// base address: 0x0 309#define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL 0x0000 310#define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 311#define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 312#define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 313#define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 314 315 316// addressBlock: azf0stream10_streamind 317// base address: 0x0 318#define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL 0x0000 319#define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 320#define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 321#define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 322#define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 323 324 325// addressBlock: azf0stream11_streamind 326// base address: 0x0 327#define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL 0x0000 328#define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 329#define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 330#define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 331#define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 332 333 334// addressBlock: azf0stream12_streamind 335// base address: 0x0 336#define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL 0x0000 337#define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 338#define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 339#define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 340#define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 341 342 343// addressBlock: azf0stream13_streamind 344// base address: 0x0 345#define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL 0x0000 346#define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 347#define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 348#define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 349#define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 350 351 352// addressBlock: azf0stream14_streamind 353// base address: 0x0 354#define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL 0x0000 355#define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 356#define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 357#define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 358#define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 359 360 361// addressBlock: azf0stream15_streamind 362// base address: 0x0 363#define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL 0x0000 364#define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 365#define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 366#define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 367#define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 368 369 370// addressBlock: azf0endpoint0_endpointind 371// base address: 0x0 372#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 373#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 374#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 375#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 376#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 377#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 378#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 379#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 380#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 381#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 382#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 383#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 384#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 385#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 386#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 387#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 388#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 389#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 390#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 391#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 392#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 393#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 394#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 395#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 396#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 397#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 398#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 399#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 400#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 401#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 402#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 403#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 404#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 405#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 406#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 407#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 408#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 409#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 410#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 411#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 412#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 413#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 414#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 415#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 416#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 417#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 418#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 419#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 420#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 421#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 422#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 423#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 424#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 425#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 426#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 427#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 428#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 429#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 430#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 431#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 432#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 433#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 434#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 435#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 436#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 437#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 438#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 439#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 440#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 441#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 442#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 443 444 445// addressBlock: azf0endpoint1_endpointind 446// base address: 0x0 447#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 448#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 449#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 450#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 451#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 452#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 453#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 454#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 455#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 456#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 457#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 458#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 459#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 460#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 461#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 462#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 463#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 464#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 465#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 466#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 467#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 468#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 469#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 470#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 471#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 472#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 473#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 474#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 475#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 476#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 477#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 478#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 479#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 480#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 481#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 482#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 483#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 484#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 485#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 486#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 487#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 488#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 489#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 490#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 491#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 492#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 493#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 494#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 495#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 496#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 497#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 498#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 499#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 500#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 501#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 502#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 503#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 504#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 505#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 506#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 507#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 508#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 509#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 510#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 511#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 512#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 513#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 514#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 515#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 516#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 517#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 518 519 520// addressBlock: azf0endpoint2_endpointind 521// base address: 0x0 522#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 523#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 524#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 525#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 526#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 527#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 528#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 529#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 530#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 531#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 532#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 533#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 534#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 535#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 536#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 537#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 538#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 539#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 540#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 541#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 542#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 543#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 544#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 545#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 546#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 547#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 548#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 549#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 550#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 551#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 552#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 553#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 554#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 555#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 556#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 557#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 558#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 559#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 560#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 561#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 562#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 563#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 564#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 565#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 566#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 567#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 568#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 569#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 570#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 571#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 572#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 573#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 574#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 575#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 576#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 577#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 578#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 579#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 580#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 581#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 582#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 583#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 584#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 585#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 586#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 587#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 588#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 589#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 590#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 591#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 592#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 593 594 595// addressBlock: azf0endpoint3_endpointind 596// base address: 0x0 597#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 598#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 599#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 600#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 601#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 602#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 603#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 604#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 605#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 606#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 607#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 608#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 609#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 610#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 611#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 612#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 613#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 614#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 615#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 616#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 617#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 618#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 619#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 620#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 621#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 622#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 623#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 624#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 625#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 626#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 627#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 628#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 629#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 630#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 631#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 632#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 633#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 634#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 635#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 636#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 637#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 638#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 639#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 640#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 641#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 642#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 643#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 644#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 645#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 646#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 647#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 648#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 649#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 650#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 651#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 652#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 653#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 654#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 655#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 656#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 657#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 658#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 659#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 660#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 661#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 662#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 663#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 664#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 665#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 666#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 667#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 668 669 670// addressBlock: azf0endpoint4_endpointind 671// base address: 0x0 672#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 673#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 674#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 675#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 676#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 677#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 678#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 679#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 680#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 681#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 682#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 683#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 684#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 685#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 686#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 687#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 688#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 689#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 690#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 691#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 692#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 693#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 694#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 695#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 696#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 697#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 698#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 699#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 700#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 701#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 702#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 703#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 704#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 705#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 706#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 707#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 708#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 709#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 710#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 711#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 712#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 713#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 714#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 715#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 716#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 717#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 718#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 719#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 720#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 721#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 722#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 723#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 724#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 725#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 726#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 727#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 728#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 729#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 730#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 731#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 732#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 733#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 734#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 735#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 736#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 737#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 738#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 739#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 740#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 741#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 742#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 743 744 745// addressBlock: azf0endpoint5_endpointind 746// base address: 0x0 747#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 748#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 749#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 750#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 751#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 752#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 753#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 754#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 755#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 756#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 757#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 758#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 759#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 760#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 761#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 762#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 763#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 764#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 765#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 766#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 767#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 768#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 769#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 770#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 771#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 772#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 773#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 774#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 775#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 776#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 777#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 778#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 779#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 780#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 781#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 782#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 783#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 784#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 785#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 786#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 787#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 788#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 789#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 790#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 791#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 792#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 793#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 794#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 795#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 796#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 797#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 798#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 799#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 800#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 801#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 802#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 803#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 804#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 805#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 806#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 807#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 808#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 809#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 810#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 811#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 812#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 813#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 814#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 815#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 816#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 817#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 818 819 820// addressBlock: azf0endpoint6_endpointind 821// base address: 0x0 822#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 823#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 824#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 825#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 826#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 827#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 828#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 829#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 830#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 831#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 832#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 833#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 834#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 835#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 836#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 837#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 838#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 839#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 840#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 841#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 842#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 843#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 844#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 845#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 846#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 847#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 848#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 849#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 850#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 851#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 852#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 853#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 854#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 855#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 856#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 857#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 858#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 859#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 860#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 861#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 862#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 863#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 864#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 865#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 866#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 867#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 868#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 869#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 870#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 871#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 872#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 873#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 874#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 875#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 876#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 877#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 878#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 879#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 880#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 881#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 882#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 883#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 884#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 885#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 886#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 887#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 888#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 889#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 890#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 891#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 892#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 893 894 895// addressBlock: azf0endpoint7_endpointind 896// base address: 0x0 897#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 898#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 899#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 900#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 901#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 902#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 903#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 904#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 905#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 906#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 907#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 908#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 909#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 910#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 911#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 912#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 913#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 914#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 915#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 916#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 917#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 918#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 919#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 920#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 921#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 922#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 923#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 924#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 925#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 926#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 927#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 928#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 929#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 930#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 931#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 932#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 933#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 934#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 935#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 936#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 937#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 938#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 939#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 940#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 941#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 942#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 943#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 944#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 945#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 946#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 947#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 948#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 949#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 950#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 951#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 952#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 953#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 954#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 955#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 956#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 957#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 958#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 959#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 960#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 961#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 962#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 963#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 964#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 965#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 966#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 967#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 968 969 970// addressBlock: azf0inputendpoint0_inputendpointind 971// base address: 0x0 972#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 973#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 974#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 975#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 976#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 977#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 978#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 979#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 980#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 981#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 982#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 983#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 984#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 985#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 986#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 987#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 988#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 989#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 990#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 991#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 992#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 993#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 994#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 995 996 997// addressBlock: azf0inputendpoint1_inputendpointind 998// base address: 0x0 999#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 1000#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 1001#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 1002#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 1003#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 1004#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 1005#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 1006#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 1007#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 1008#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 1009#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 1010#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 1011#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 1012#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 1013#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 1014#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 1015#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 1016#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 1017#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 1018#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 1019#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 1020#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 1021#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 1022 1023 1024// addressBlock: azf0inputendpoint2_inputendpointind 1025// base address: 0x0 1026#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 1027#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 1028#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 1029#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 1030#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 1031#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 1032#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 1033#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 1034#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 1035#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 1036#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 1037#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 1038#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 1039#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 1040#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 1041#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 1042#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 1043#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 1044#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 1045#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 1046#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 1047#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 1048#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 1049 1050 1051// addressBlock: azf0inputendpoint3_inputendpointind 1052// base address: 0x0 1053#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 1054#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 1055#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 1056#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 1057#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 1058#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 1059#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 1060#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 1061#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 1062#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 1063#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 1064#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 1065#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 1066#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 1067#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 1068#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 1069#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 1070#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 1071#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 1072#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 1073#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 1074#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 1075#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 1076 1077 1078// addressBlock: azf0inputendpoint4_inputendpointind 1079// base address: 0x0 1080#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 1081#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 1082#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 1083#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 1084#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 1085#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 1086#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 1087#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 1088#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 1089#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 1090#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 1091#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 1092#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 1093#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 1094#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 1095#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 1096#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 1097#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 1098#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 1099#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 1100#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 1101#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 1102#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 1103 1104 1105// addressBlock: azf0inputendpoint5_inputendpointind 1106// base address: 0x0 1107#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 1108#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 1109#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 1110#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 1111#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 1112#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 1113#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 1114#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 1115#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 1116#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 1117#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 1118#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 1119#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 1120#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 1121#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 1122#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 1123#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 1124#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 1125#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 1126#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 1127#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 1128#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 1129#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 1130 1131 1132// addressBlock: azf0inputendpoint6_inputendpointind 1133// base address: 0x0 1134#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 1135#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 1136#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 1137#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 1138#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 1139#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 1140#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 1141#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 1142#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 1143#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 1144#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 1145#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 1146#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 1147#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 1148#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 1149#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 1150#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 1151#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 1152#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 1153#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 1154#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 1155#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 1156#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 1157 1158 1159// addressBlock: azf0inputendpoint7_inputendpointind 1160// base address: 0x0 1161#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 1162#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 1163#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 1164#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 1165#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 1166#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 1167#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 1168#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 1169#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 1170#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 1171#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 1172#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 1173#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 1174#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 1175#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 1176#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 1177#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 1178#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 1179#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 1180#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 1181#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 1182#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 1183#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 1184 1185 1186// addressBlock: azendpoint_descriptorind 1187// base address: 0x0 1188#define ixAUDIO_DESCRIPTOR0 0x0001 1189#define ixAUDIO_DESCRIPTOR1 0x0002 1190#define ixAUDIO_DESCRIPTOR2 0x0003 1191#define ixAUDIO_DESCRIPTOR3 0x0004 1192#define ixAUDIO_DESCRIPTOR4 0x0005 1193#define ixAUDIO_DESCRIPTOR5 0x0006 1194#define ixAUDIO_DESCRIPTOR6 0x0007 1195#define ixAUDIO_DESCRIPTOR7 0x0008 1196#define ixAUDIO_DESCRIPTOR8 0x0009 1197#define ixAUDIO_DESCRIPTOR9 0x000a 1198#define ixAUDIO_DESCRIPTOR10 0x000b 1199#define ixAUDIO_DESCRIPTOR11 0x000c 1200#define ixAUDIO_DESCRIPTOR12 0x000d 1201#define ixAUDIO_DESCRIPTOR13 0x000e 1202 1203 1204// addressBlock: dce_dc_mmhubbub_vga_dispdec[72..76] 1205// base address: 0x48 1206#define regVGA_MEM_WRITE_PAGE_ADDR 0x0000 1207#define regVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0 1208#define regVGA_MEM_READ_PAGE_ADDR 0x0001 1209#define regVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0 1210 1211 1212// addressBlock: dce_dc_mmhubbub_vga_dispdec 1213// base address: 0x0 1214#define regVGA_RENDER_CONTROL 0x0000 1215#define regVGA_RENDER_CONTROL_BASE_IDX 1 1216#define regVGA_SEQUENCER_RESET_CONTROL 0x0001 1217#define regVGA_SEQUENCER_RESET_CONTROL_BASE_IDX 1 1218#define regVGA_MODE_CONTROL 0x0002 1219#define regVGA_MODE_CONTROL_BASE_IDX 1 1220#define regVGA_SURFACE_PITCH_SELECT 0x0003 1221#define regVGA_SURFACE_PITCH_SELECT_BASE_IDX 1 1222#define regVGA_MEMORY_BASE_ADDRESS 0x0004 1223#define regVGA_MEMORY_BASE_ADDRESS_BASE_IDX 1 1224#define regVGA_DISPBUF1_SURFACE_ADDR 0x0006 1225#define regVGA_DISPBUF1_SURFACE_ADDR_BASE_IDX 1 1226#define regVGA_DISPBUF2_SURFACE_ADDR 0x0008 1227#define regVGA_DISPBUF2_SURFACE_ADDR_BASE_IDX 1 1228#define regVGA_MEMORY_BASE_ADDRESS_HIGH 0x0009 1229#define regVGA_MEMORY_BASE_ADDRESS_HIGH_BASE_IDX 1 1230#define regVGA_HDP_CONTROL 0x000a 1231#define regVGA_HDP_CONTROL_BASE_IDX 1 1232#define regVGA_CACHE_CONTROL 0x000b 1233#define regVGA_CACHE_CONTROL_BASE_IDX 1 1234#define regD1VGA_CONTROL 0x000c 1235#define regD1VGA_CONTROL_BASE_IDX 1 1236#define regD2VGA_CONTROL 0x000e 1237#define regD2VGA_CONTROL_BASE_IDX 1 1238#define regVGA_STATUS 0x0010 1239#define regVGA_STATUS_BASE_IDX 1 1240#define regVGA_INTERRUPT_CONTROL 0x0011 1241#define regVGA_INTERRUPT_CONTROL_BASE_IDX 1 1242#define regVGA_STATUS_CLEAR 0x0012 1243#define regVGA_STATUS_CLEAR_BASE_IDX 1 1244#define regVGA_INTERRUPT_STATUS 0x0013 1245#define regVGA_INTERRUPT_STATUS_BASE_IDX 1 1246#define regVGA_MAIN_CONTROL 0x0014 1247#define regVGA_MAIN_CONTROL_BASE_IDX 1 1248#define regVGA_TEST_CONTROL 0x0015 1249#define regVGA_TEST_CONTROL_BASE_IDX 1 1250#define regVGA_QOS_CTRL 0x0018 1251#define regVGA_QOS_CTRL_BASE_IDX 1 1252#define regCRTC8_IDX 0x002d 1253#define regCRTC8_IDX_BASE_IDX 1 1254#define regCRTC8_DATA 0x002d 1255#define regCRTC8_DATA_BASE_IDX 1 1256#define regGENFC_WT 0x002e 1257#define regGENFC_WT_BASE_IDX 1 1258#define regGENS1 0x002e 1259#define regGENS1_BASE_IDX 1 1260#define regATTRDW 0x0030 1261#define regATTRDW_BASE_IDX 1 1262#define regATTRX 0x0030 1263#define regATTRX_BASE_IDX 1 1264#define regATTRDR 0x0030 1265#define regATTRDR_BASE_IDX 1 1266#define regGENMO_WT 0x0030 1267#define regGENMO_WT_BASE_IDX 1 1268#define regGENS0 0x0030 1269#define regGENS0_BASE_IDX 1 1270#define regGENENB 0x0030 1271#define regSEQ8_IDX 0x0031 1272#define regSEQ8_IDX_BASE_IDX 1 1273#define regSEQ8_DATA 0x0031 1274#define regSEQ8_DATA_BASE_IDX 1 1275#define regDAC_MASK 0x0031 1276#define regDAC_MASK_BASE_IDX 1 1277#define regDAC_R_INDEX 0x0031 1278#define regDAC_R_INDEX_BASE_IDX 1 1279#define regDAC_W_INDEX 0x0032 1280#define regDAC_W_INDEX_BASE_IDX 1 1281#define regDAC_DATA 0x0032 1282#define regDAC_DATA_BASE_IDX 1 1283#define regGENFC_RD 0x0032 1284#define regGENFC_RD_BASE_IDX 1 1285#define regGENMO_RD 0x0033 1286#define regGENMO_RD_BASE_IDX 1 1287#define regGRPH8_IDX 0x0033 1288#define regGRPH8_IDX_BASE_IDX 1 1289#define regGRPH8_DATA 0x0033 1290#define regGRPH8_DATA_BASE_IDX 1 1291#define regCRTC8_IDX_1 0x0035 1292#define regCRTC8_IDX_1_BASE_IDX 1 1293#define regCRTC8_DATA_1 0x0035 1294#define regCRTC8_DATA_1_BASE_IDX 1 1295#define regGENFC_WT_1 0x0036 1296#define regGENFC_WT_1_BASE_IDX 1 1297#define regGENS1_1 0x0036 1298#define regGENS1_1_BASE_IDX 1 1299#define regD3VGA_CONTROL 0x0038 1300#define regD3VGA_CONTROL_BASE_IDX 1 1301#define regD4VGA_CONTROL 0x0039 1302#define regD4VGA_CONTROL_BASE_IDX 1 1303#define regD5VGA_CONTROL 0x003a 1304#define regD5VGA_CONTROL_BASE_IDX 1 1305#define regD6VGA_CONTROL 0x003b 1306#define regD6VGA_CONTROL_BASE_IDX 1 1307#define regVGA_SOURCE_SELECT 0x003c 1308#define regVGA_SOURCE_SELECT_BASE_IDX 1 1309 1310 1311// addressBlock: dce_dc_hda_azendpoint_azdec 1312// base address: 0x0 1313#define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006 1314#define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0 1315#define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006 1316#define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0 1317 1318 1319// addressBlock: dce_dc_hda_azinputendpoint_azdec 1320// base address: 0x0 1321#define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0x0006 1322#define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX 0 1323#define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0x0006 1324#define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX 0 1325 1326 1327// addressBlock: dce_dc_dccg_dccg_dispdec 1328// base address: 0x0 1329#define regPHYPLLA_PIXCLK_RESYNC_CNTL 0x0040 1330#define regPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX 1 1331#define regPHYPLLB_PIXCLK_RESYNC_CNTL 0x0041 1332#define regPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX 1 1333#define regPHYPLLC_PIXCLK_RESYNC_CNTL 0x0042 1334#define regPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX 1 1335#define regPHYPLLD_PIXCLK_RESYNC_CNTL 0x0043 1336#define regPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX 1 1337#define regDP_DTO_DBUF_EN 0x0044 1338#define regDP_DTO_DBUF_EN_BASE_IDX 1 1339#define regDSCCLK3_DTO_PARAM 0x0045 1340#define regDSCCLK3_DTO_PARAM_BASE_IDX 1 1341#define regDPREFCLK_CGTT_BLK_CTRL_REG 0x0048 1342#define regDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 1343#define regDCCG_GATE_DISABLE_CNTL4 0x0049 1344#define regDCCG_GATE_DISABLE_CNTL4_BASE_IDX 1 1345#define regDPSTREAMCLK_CNTL 0x004a 1346#define regDPSTREAMCLK_CNTL_BASE_IDX 1 1347#define regREFCLK_CGTT_BLK_CTRL_REG 0x004b 1348#define regREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 1349#define regPHYPLLE_PIXCLK_RESYNC_CNTL 0x004c 1350#define regPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX 1 1351#define regDCCG_PERFMON_CNTL2 0x004e 1352#define regDCCG_PERFMON_CNTL2_BASE_IDX 1 1353#define regDCCG_GLOBAL_FGCG_REP_CNTL 0x0050 1354#define regDCCG_GLOBAL_FGCG_REP_CNTL_BASE_IDX 1 1355#define regDCCG_DS_DTO_INCR 0x0053 1356#define regDCCG_DS_DTO_INCR_BASE_IDX 1 1357#define regDCCG_DS_DTO_MODULO 0x0054 1358#define regDCCG_DS_DTO_MODULO_BASE_IDX 1 1359#define regDCCG_DS_CNTL 0x0055 1360#define regDCCG_DS_CNTL_BASE_IDX 1 1361#define regDCCG_DS_HW_CAL_INTERVAL 0x0056 1362#define regDCCG_DS_HW_CAL_INTERVAL_BASE_IDX 1 1363#define regDPREFCLK_CNTL 0x0058 1364#define regDPREFCLK_CNTL_BASE_IDX 1 1365#define regDCE_VERSION 0x005e 1366#define regDCE_VERSION_BASE_IDX 1 1367#define regDCCG_GTC_CNTL 0x0060 1368#define regDCCG_GTC_CNTL_BASE_IDX 1 1369#define regDCCG_GTC_DTO_INCR 0x0061 1370#define regDCCG_GTC_DTO_INCR_BASE_IDX 1 1371#define regDCCG_GTC_DTO_MODULO 0x0062 1372#define regDCCG_GTC_DTO_MODULO_BASE_IDX 1 1373#define regDCCG_GTC_CURRENT 0x0063 1374#define regDCCG_GTC_CURRENT_BASE_IDX 1 1375#define regSYMCLK32_SE_CNTL 0x0065 1376#define regSYMCLK32_SE_CNTL_BASE_IDX 1 1377#define regSYMCLK32_LE_CNTL 0x0066 1378#define regSYMCLK32_LE_CNTL_BASE_IDX 1 1379#define regDTBCLK_P_CNTL 0x0068 1380#define regDTBCLK_P_CNTL_BASE_IDX 1 1381#define regDCCG_GATE_DISABLE_CNTL5 0x0069 1382#define regDCCG_GATE_DISABLE_CNTL5_BASE_IDX 1 1383#define regDSCCLK0_DTO_PARAM 0x006c 1384#define regDSCCLK0_DTO_PARAM_BASE_IDX 1 1385#define regDSCCLK1_DTO_PARAM 0x006d 1386#define regDSCCLK1_DTO_PARAM_BASE_IDX 1 1387#define regDSCCLK2_DTO_PARAM 0x006e 1388#define regDSCCLK2_DTO_PARAM_BASE_IDX 1 1389#define regOTG_PIXEL_RATE_DIV 0x006f 1390#define regOTG_PIXEL_RATE_DIV_BASE_IDX 1 1391#define regMILLISECOND_TIME_BASE_DIV 0x0070 1392#define regMILLISECOND_TIME_BASE_DIV_BASE_IDX 1 1393#define regDISPCLK_FREQ_CHANGE_CNTL 0x0071 1394#define regDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX 1 1395#define regDC_MEM_GLOBAL_PWR_REQ_CNTL 0x0072 1396#define regDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX 1 1397#define regDCCG_PERFMON_CNTL 0x0073 1398#define regDCCG_PERFMON_CNTL_BASE_IDX 1 1399#define regDCCG_GATE_DISABLE_CNTL 0x0074 1400#define regDCCG_GATE_DISABLE_CNTL_BASE_IDX 1 1401#define regDISPCLK_CGTT_BLK_CTRL_REG 0x0075 1402#define regDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 1403#define regSOCCLK_CGTT_BLK_CTRL_REG 0x0076 1404#define regSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 1405#define regDCCG_CAC_STATUS 0x0077 1406#define regDCCG_CAC_STATUS_BASE_IDX 1 1407#define regMICROSECOND_TIME_BASE_DIV 0x007b 1408#define regMICROSECOND_TIME_BASE_DIV_BASE_IDX 1 1409#define regDCCG_GATE_DISABLE_CNTL2 0x007c 1410#define regDCCG_GATE_DISABLE_CNTL2_BASE_IDX 1 1411#define regSYMCLK_CGTT_BLK_CTRL_REG 0x007d 1412#define regSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 1413#define regDCCG_DISP_CNTL_REG 0x007f 1414#define regDCCG_DISP_CNTL_REG_BASE_IDX 1 1415#define regOTG0_PIXEL_RATE_CNTL 0x0080 1416#define regOTG0_PIXEL_RATE_CNTL_BASE_IDX 1 1417#define regDP_DTO0_PHASE 0x0081 1418#define regDP_DTO0_PHASE_BASE_IDX 1 1419#define regDP_DTO0_MODULO 0x0082 1420#define regDP_DTO0_MODULO_BASE_IDX 1 1421#define regOTG0_PHYPLL_PIXEL_RATE_CNTL 0x0083 1422#define regOTG0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 1423#define regOTG1_PIXEL_RATE_CNTL 0x0084 1424#define regOTG1_PIXEL_RATE_CNTL_BASE_IDX 1 1425#define regDP_DTO1_PHASE 0x0085 1426#define regDP_DTO1_PHASE_BASE_IDX 1 1427#define regDP_DTO1_MODULO 0x0086 1428#define regDP_DTO1_MODULO_BASE_IDX 1 1429#define regOTG1_PHYPLL_PIXEL_RATE_CNTL 0x0087 1430#define regOTG1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 1431#define regOTG2_PIXEL_RATE_CNTL 0x0088 1432#define regOTG2_PIXEL_RATE_CNTL_BASE_IDX 1 1433#define regDP_DTO2_PHASE 0x0089 1434#define regDP_DTO2_PHASE_BASE_IDX 1 1435#define regDP_DTO2_MODULO 0x008a 1436#define regDP_DTO2_MODULO_BASE_IDX 1 1437#define regOTG2_PHYPLL_PIXEL_RATE_CNTL 0x008b 1438#define regOTG2_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 1439#define regOTG3_PIXEL_RATE_CNTL 0x008c 1440#define regOTG3_PIXEL_RATE_CNTL_BASE_IDX 1 1441#define regDP_DTO3_PHASE 0x008d 1442#define regDP_DTO3_PHASE_BASE_IDX 1 1443#define regDP_DTO3_MODULO 0x008e 1444#define regDP_DTO3_MODULO_BASE_IDX 1 1445#define regOTG3_PHYPLL_PIXEL_RATE_CNTL 0x008f 1446#define regOTG3_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 1447#define regDPPCLK_CGTT_BLK_CTRL_REG 0x0098 1448#define regDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 1449#define regDPPCLK0_DTO_PARAM 0x0099 1450#define regDPPCLK0_DTO_PARAM_BASE_IDX 1 1451#define regDPPCLK1_DTO_PARAM 0x009a 1452#define regDPPCLK1_DTO_PARAM_BASE_IDX 1 1453#define regDPPCLK2_DTO_PARAM 0x009b 1454#define regDPPCLK2_DTO_PARAM_BASE_IDX 1 1455#define regDPPCLK3_DTO_PARAM 0x009c 1456#define regDPPCLK3_DTO_PARAM_BASE_IDX 1 1457#define regDCCG_CAC_STATUS2 0x009f 1458#define regDCCG_CAC_STATUS2_BASE_IDX 1 1459#define regSYMCLKA_CLOCK_ENABLE 0x00a0 1460#define regSYMCLKA_CLOCK_ENABLE_BASE_IDX 1 1461#define regSYMCLKB_CLOCK_ENABLE 0x00a1 1462#define regSYMCLKB_CLOCK_ENABLE_BASE_IDX 1 1463#define regSYMCLKC_CLOCK_ENABLE 0x00a2 1464#define regSYMCLKC_CLOCK_ENABLE_BASE_IDX 1 1465#define regSYMCLKD_CLOCK_ENABLE 0x00a3 1466#define regSYMCLKD_CLOCK_ENABLE_BASE_IDX 1 1467#define regSYMCLKE_CLOCK_ENABLE 0x00a4 1468#define regSYMCLKE_CLOCK_ENABLE_BASE_IDX 1 1469#define regDCCG_SOFT_RESET 0x00a6 1470#define regDCCG_SOFT_RESET_BASE_IDX 1 1471#define regDSCCLK_DTO_CTRL 0x00a7 1472#define regDSCCLK_DTO_CTRL_BASE_IDX 1 1473#define regDCCG_AUDIO_DTO_SOURCE 0x00ab 1474#define regDCCG_AUDIO_DTO_SOURCE_BASE_IDX 1 1475#define regDCCG_AUDIO_DTO0_PHASE 0x00ac 1476#define regDCCG_AUDIO_DTO0_PHASE_BASE_IDX 1 1477#define regDCCG_AUDIO_DTO0_MODULE 0x00ad 1478#define regDCCG_AUDIO_DTO0_MODULE_BASE_IDX 1 1479#define regDCCG_AUDIO_DTO1_PHASE 0x00ae 1480#define regDCCG_AUDIO_DTO1_PHASE_BASE_IDX 1 1481#define regDCCG_AUDIO_DTO1_MODULE 0x00af 1482#define regDCCG_AUDIO_DTO1_MODULE_BASE_IDX 1 1483#define regDCCG_VSYNC_OTG0_LATCH_VALUE 0x00b0 1484#define regDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX 1 1485#define regDCCG_VSYNC_OTG1_LATCH_VALUE 0x00b1 1486#define regDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX 1 1487#define regDCCG_VSYNC_OTG2_LATCH_VALUE 0x00b2 1488#define regDCCG_VSYNC_OTG2_LATCH_VALUE_BASE_IDX 1 1489#define regDCCG_VSYNC_OTG3_LATCH_VALUE 0x00b3 1490#define regDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX 1 1491#define regDCCG_VSYNC_OTG4_LATCH_VALUE 0x00b4 1492#define regDCCG_VSYNC_OTG4_LATCH_VALUE_BASE_IDX 1 1493#define regDCCG_VSYNC_OTG5_LATCH_VALUE 0x00b5 1494#define regDCCG_VSYNC_OTG5_LATCH_VALUE_BASE_IDX 1 1495#define regDPPCLK_DTO_CTRL 0x00b6 1496#define regDPPCLK_DTO_CTRL_BASE_IDX 1 1497#define regDCCG_VSYNC_CNT_CTRL 0x00b8 1498#define regDCCG_VSYNC_CNT_CTRL_BASE_IDX 1 1499#define regDCCG_VSYNC_CNT_INT_CTRL 0x00b9 1500#define regDCCG_VSYNC_CNT_INT_CTRL_BASE_IDX 1 1501#define regFORCE_SYMCLK_DISABLE 0x00ba 1502#define regFORCE_SYMCLK_DISABLE_BASE_IDX 1 1503#define regDTBCLK_DTO0_PHASE 0x0018 1504#define regDTBCLK_DTO0_PHASE_BASE_IDX 2 1505#define regDTBCLK_DTO1_PHASE 0x0019 1506#define regDTBCLK_DTO1_PHASE_BASE_IDX 2 1507#define regDTBCLK_DTO2_PHASE 0x001a 1508#define regDTBCLK_DTO2_PHASE_BASE_IDX 2 1509#define regDTBCLK_DTO3_PHASE 0x001b 1510#define regDTBCLK_DTO3_PHASE_BASE_IDX 2 1511#define regDTBCLK_DTO0_MODULO 0x001f 1512#define regDTBCLK_DTO0_MODULO_BASE_IDX 2 1513#define regDTBCLK_DTO1_MODULO 0x0020 1514#define regDTBCLK_DTO1_MODULO_BASE_IDX 2 1515#define regDTBCLK_DTO2_MODULO 0x0021 1516#define regDTBCLK_DTO2_MODULO_BASE_IDX 2 1517#define regDTBCLK_DTO3_MODULO 0x0022 1518#define regDTBCLK_DTO3_MODULO_BASE_IDX 2 1519#define regHDMICHARCLK0_CLOCK_CNTL 0x004a 1520#define regHDMICHARCLK0_CLOCK_CNTL_BASE_IDX 2 1521#define regPHYASYMCLK_CLOCK_CNTL 0x0052 1522#define regPHYASYMCLK_CLOCK_CNTL_BASE_IDX 2 1523#define regPHYBSYMCLK_CLOCK_CNTL 0x0053 1524#define regPHYBSYMCLK_CLOCK_CNTL_BASE_IDX 2 1525#define regPHYCSYMCLK_CLOCK_CNTL 0x0054 1526#define regPHYCSYMCLK_CLOCK_CNTL_BASE_IDX 2 1527#define regPHYDSYMCLK_CLOCK_CNTL 0x0055 1528#define regPHYDSYMCLK_CLOCK_CNTL_BASE_IDX 2 1529#define regPHYESYMCLK_CLOCK_CNTL 0x0056 1530#define regPHYESYMCLK_CLOCK_CNTL_BASE_IDX 2 1531#define regHDMISTREAMCLK_CNTL 0x0059 1532#define regHDMISTREAMCLK_CNTL_BASE_IDX 2 1533#define regDCCG_GATE_DISABLE_CNTL3 0x005a 1534#define regDCCG_GATE_DISABLE_CNTL3_BASE_IDX 2 1535#define regHDMISTREAMCLK0_DTO_PARAM 0x005b 1536#define regHDMISTREAMCLK0_DTO_PARAM_BASE_IDX 2 1537#define regDCCG_AUDIO_DTBCLK_DTO_PHASE 0x0061 1538#define regDCCG_AUDIO_DTBCLK_DTO_PHASE_BASE_IDX 2 1539#define regDCCG_AUDIO_DTBCLK_DTO_MODULO 0x0062 1540#define regDCCG_AUDIO_DTBCLK_DTO_MODULO_BASE_IDX 2 1541#define regDTBCLK_DTO_DBUF_EN 0x0063 1542#define regDTBCLK_DTO_DBUF_EN_BASE_IDX 2 1543#define regDMCUBCLK_CNTL 0x0067 1544#define regDMCUBCLK_CNTL_BASE_IDX 2 1545 1546 1547// addressBlock: dce_dc_dccg_dccg_dfs_dispdec 1548// base address: 0x0 1549#define regDENTIST_DISPCLK_CNTL 0x0064 1550#define regDENTIST_DISPCLK_CNTL_BASE_IDX 1 1551 1552 1553// addressBlock: azroot_f2codecind 1554// base address: 0x0 1555#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0f00 1556#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0x0f02 1557#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0x0f04 1558#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705 1559#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720 1560#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721 1561#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722 1562#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723 1563#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770 1564#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17ff 1565#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1f04 1566#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1f05 1567#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1f0a 1568#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1f0b 1569#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1f0f 1570 1571 1572// addressBlock: azendpoint_f2codecind 1573// base address: 0x0 1574#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200 1575#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706 1576#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270d 1577#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270e 1578#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724 1579#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273e 1580#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770 1581#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x2771 1582#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2f09 1583#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2f0a 1584#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2f0b 1585#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702 1586#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707 1587#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708 1588#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709 1589#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371c 1590#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371d 1591#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371e 1592#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371f 1593#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770 1594#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771 1595#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772 1596#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776 1597#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776 1598#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777 1599#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778 1600#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779 1601#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377a 1602#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377b 1603#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377c 1604#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780 1605#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781 1606#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785 1607#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786 1608#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787 1609#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788 1610#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789 1611#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378a 1612#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378b 1613#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378c 1614#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378d 1615#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378e 1616#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378f 1617#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790 1618#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791 1619#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792 1620#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793 1621#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x3797 1622#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x3798 1623#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB 0x3799 1624#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x379a 1625#define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE 0x379b 1626#define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x379c 1627#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x379d 1628#define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x379e 1629#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3f09 1630#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3f0c 1631#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3f0e 1632 1633 1634// addressBlock: azinputendpoint_f2codecind 1635// base address: 0x0 1636#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x6200 1637#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x6706 1638#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x670d 1639#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x6f09 1640#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6f0a 1641#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x6f0b 1642#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x7707 1643#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x7708 1644#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE 0x7709 1645#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x771c 1646#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x771d 1647#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x771e 1648#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x771f 1649#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x7771 1650#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE 0x7777 1651#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE 0x7778 1652#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE 0x7779 1653#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE 0x777a 1654#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR 0x777c 1655#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x7785 1656#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x7786 1657#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x7787 1658#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x7788 1659#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x7798 1660#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB 0x7799 1661#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x779a 1662#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x779b 1663#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x779c 1664#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L 0x779d 1665#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H 0x779e 1666#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x7f09 1667#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x7f0c 1668 1669 1670// addressBlock: dce_dc_dccg_dccg_dcperfmon0_dc_perfmon_dispdec 1671// base address: 0x0 1672#define regDC_PERFMON0_PERFCOUNTER_CNTL 0x0000 1673#define regDC_PERFMON0_PERFCOUNTER_CNTL_BASE_IDX 2 1674#define regDC_PERFMON0_PERFCOUNTER_CNTL2 0x0001 1675#define regDC_PERFMON0_PERFCOUNTER_CNTL2_BASE_IDX 2 1676#define regDC_PERFMON0_PERFCOUNTER_STATE 0x0002 1677#define regDC_PERFMON0_PERFCOUNTER_STATE_BASE_IDX 2 1678#define regDC_PERFMON0_PERFMON_CNTL 0x0003 1679#define regDC_PERFMON0_PERFMON_CNTL_BASE_IDX 2 1680#define regDC_PERFMON0_PERFMON_CNTL2 0x0004 1681#define regDC_PERFMON0_PERFMON_CNTL2_BASE_IDX 2 1682#define regDC_PERFMON0_PERFMON_CVALUE_INT_MISC 0x0005 1683#define regDC_PERFMON0_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 1684#define regDC_PERFMON0_PERFMON_CVALUE_LOW 0x0006 1685#define regDC_PERFMON0_PERFMON_CVALUE_LOW_BASE_IDX 2 1686#define regDC_PERFMON0_PERFMON_HI 0x0007 1687#define regDC_PERFMON0_PERFMON_HI_BASE_IDX 2 1688#define regDC_PERFMON0_PERFMON_LOW 0x0008 1689#define regDC_PERFMON0_PERFMON_LOW_BASE_IDX 2 1690 1691 1692// addressBlock: dce_dc_dccg_dccg_dcperfmon1_dc_perfmon_dispdec 1693// base address: 0x30 1694#define regDC_PERFMON1_PERFCOUNTER_CNTL 0x000c 1695#define regDC_PERFMON1_PERFCOUNTER_CNTL_BASE_IDX 2 1696#define regDC_PERFMON1_PERFCOUNTER_CNTL2 0x000d 1697#define regDC_PERFMON1_PERFCOUNTER_CNTL2_BASE_IDX 2 1698#define regDC_PERFMON1_PERFCOUNTER_STATE 0x000e 1699#define regDC_PERFMON1_PERFCOUNTER_STATE_BASE_IDX 2 1700#define regDC_PERFMON1_PERFMON_CNTL 0x000f 1701#define regDC_PERFMON1_PERFMON_CNTL_BASE_IDX 2 1702#define regDC_PERFMON1_PERFMON_CNTL2 0x0010 1703#define regDC_PERFMON1_PERFMON_CNTL2_BASE_IDX 2 1704#define regDC_PERFMON1_PERFMON_CVALUE_INT_MISC 0x0011 1705#define regDC_PERFMON1_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 1706#define regDC_PERFMON1_PERFMON_CVALUE_LOW 0x0012 1707#define regDC_PERFMON1_PERFMON_CVALUE_LOW_BASE_IDX 2 1708#define regDC_PERFMON1_PERFMON_HI 0x0013 1709#define regDC_PERFMON1_PERFMON_HI_BASE_IDX 2 1710#define regDC_PERFMON1_PERFMON_LOW 0x0014 1711#define regDC_PERFMON1_PERFMON_LOW_BASE_IDX 2 1712 1713 1714// addressBlock: dce_dc_dmu_dc_pg_dispdec 1715// base address: 0x0 1716#define regDOMAIN0_PG_CONFIG 0x0080 1717#define regDOMAIN0_PG_CONFIG_BASE_IDX 2 1718#define regDOMAIN0_PG_STATUS 0x0081 1719#define regDOMAIN0_PG_STATUS_BASE_IDX 2 1720#define regDOMAIN1_PG_CONFIG 0x0082 1721#define regDOMAIN1_PG_CONFIG_BASE_IDX 2 1722#define regDOMAIN1_PG_STATUS 0x0083 1723#define regDOMAIN1_PG_STATUS_BASE_IDX 2 1724#define regDOMAIN2_PG_CONFIG 0x0084 1725#define regDOMAIN2_PG_CONFIG_BASE_IDX 2 1726#define regDOMAIN2_PG_STATUS 0x0085 1727#define regDOMAIN2_PG_STATUS_BASE_IDX 2 1728#define regDOMAIN3_PG_CONFIG 0x0086 1729#define regDOMAIN3_PG_CONFIG_BASE_IDX 2 1730#define regDOMAIN3_PG_STATUS 0x0087 1731#define regDOMAIN3_PG_STATUS_BASE_IDX 2 1732#define regDOMAIN16_PG_CONFIG 0x0089 1733#define regDOMAIN16_PG_CONFIG_BASE_IDX 2 1734#define regDOMAIN16_PG_STATUS 0x008a 1735#define regDOMAIN16_PG_STATUS_BASE_IDX 2 1736#define regDOMAIN17_PG_CONFIG 0x008b 1737#define regDOMAIN17_PG_CONFIG_BASE_IDX 2 1738#define regDOMAIN17_PG_STATUS 0x008c 1739#define regDOMAIN17_PG_STATUS_BASE_IDX 2 1740#define regDOMAIN18_PG_CONFIG 0x008d 1741#define regDOMAIN18_PG_CONFIG_BASE_IDX 2 1742#define regDOMAIN18_PG_STATUS 0x008e 1743#define regDOMAIN18_PG_STATUS_BASE_IDX 2 1744#define regDOMAIN19_PG_CONFIG 0x008f 1745#define regDOMAIN19_PG_CONFIG_BASE_IDX 2 1746#define regDOMAIN19_PG_STATUS 0x0090 1747#define regDOMAIN19_PG_STATUS_BASE_IDX 2 1748#define regDCPG_INTERRUPT_STATUS 0x0091 1749#define regDCPG_INTERRUPT_STATUS_BASE_IDX 2 1750#define regDCPG_INTERRUPT_STATUS_2 0x0092 1751#define regDCPG_INTERRUPT_STATUS_2_BASE_IDX 2 1752#define regDCPG_INTERRUPT_CONTROL_1 0x0093 1753#define regDCPG_INTERRUPT_CONTROL_1_BASE_IDX 2 1754#define regDCPG_INTERRUPT_CONTROL_3 0x0094 1755#define regDCPG_INTERRUPT_CONTROL_3_BASE_IDX 2 1756#define regDC_IP_REQUEST_CNTL 0x0095 1757#define regDC_IP_REQUEST_CNTL_BASE_IDX 2 1758 1759 1760// addressBlock: dce_dc_dmu_dmu_dcperfmon_dc_perfmon_dispdec 1761// base address: 0x2f8 1762#define regDC_PERFMON2_PERFCOUNTER_CNTL 0x00be 1763#define regDC_PERFMON2_PERFCOUNTER_CNTL_BASE_IDX 2 1764#define regDC_PERFMON2_PERFCOUNTER_CNTL2 0x00bf 1765#define regDC_PERFMON2_PERFCOUNTER_CNTL2_BASE_IDX 2 1766#define regDC_PERFMON2_PERFCOUNTER_STATE 0x00c0 1767#define regDC_PERFMON2_PERFCOUNTER_STATE_BASE_IDX 2 1768#define regDC_PERFMON2_PERFMON_CNTL 0x00c1 1769#define regDC_PERFMON2_PERFMON_CNTL_BASE_IDX 2 1770#define regDC_PERFMON2_PERFMON_CNTL2 0x00c2 1771#define regDC_PERFMON2_PERFMON_CNTL2_BASE_IDX 2 1772#define regDC_PERFMON2_PERFMON_CVALUE_INT_MISC 0x00c3 1773#define regDC_PERFMON2_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 1774#define regDC_PERFMON2_PERFMON_CVALUE_LOW 0x00c4 1775#define regDC_PERFMON2_PERFMON_CVALUE_LOW_BASE_IDX 2 1776#define regDC_PERFMON2_PERFMON_HI 0x00c5 1777#define regDC_PERFMON2_PERFMON_HI_BASE_IDX 2 1778#define regDC_PERFMON2_PERFMON_LOW 0x00c6 1779#define regDC_PERFMON2_PERFMON_LOW_BASE_IDX 2 1780 1781 1782// addressBlock: dce_dc_dmu_dmu_misc_dispdec 1783// base address: 0x0 1784#define regCC_DC_PIPE_DIS 0x00ca 1785#define regCC_DC_PIPE_DIS_BASE_IDX 2 1786#define regDMU_CLK_CNTL 0x00cb 1787#define regDMU_CLK_CNTL_BASE_IDX 2 1788#define regDMU_MEM_PWR_CNTL 0x00cc 1789#define regDMU_MEM_PWR_CNTL_BASE_IDX 2 1790#define regDMCU_SMU_INTERRUPT_CNTL 0x00cd 1791#define regDMCU_SMU_INTERRUPT_CNTL_BASE_IDX 2 1792#define regSMU_INTERRUPT_CONTROL 0x00ce 1793#define regSMU_INTERRUPT_CONTROL_BASE_IDX 2 1794#define regZSC_CNTL 0x00cf 1795#define regZSC_CNTL_BASE_IDX 2 1796#define regZSC_CNTL2 0x00d0 1797#define regZSC_CNTL2_BASE_IDX 2 1798#define regDMU_MISC_ALLOW_DS_FORCE 0x00d6 1799#define regDMU_MISC_ALLOW_DS_FORCE_BASE_IDX 2 1800#define regZSC_STATUS 0x00d7 1801#define regZSC_STATUS_BASE_IDX 2 1802 1803 1804// addressBlock: dce_dc_dmu_dmcu_dispdec 1805// base address: 0x0 1806#define regDMCU_CTRL 0x00da 1807#define regDMCU_CTRL_BASE_IDX 2 1808#define regDMCU_STATUS 0x00db 1809#define regDMCU_STATUS_BASE_IDX 2 1810#define regDMCU_PC_START_ADDR 0x00dc 1811#define regDMCU_PC_START_ADDR_BASE_IDX 2 1812#define regDMCU_FW_START_ADDR 0x00dd 1813#define regDMCU_FW_START_ADDR_BASE_IDX 2 1814#define regDMCU_FW_END_ADDR 0x00de 1815#define regDMCU_FW_END_ADDR_BASE_IDX 2 1816#define regDMCU_FW_ISR_START_ADDR 0x00df 1817#define regDMCU_FW_ISR_START_ADDR_BASE_IDX 2 1818#define regDMCU_FW_CS_HI 0x00e0 1819#define regDMCU_FW_CS_HI_BASE_IDX 2 1820#define regDMCU_FW_CS_LO 0x00e1 1821#define regDMCU_FW_CS_LO_BASE_IDX 2 1822#define regDMCU_RAM_ACCESS_CTRL 0x00e2 1823#define regDMCU_RAM_ACCESS_CTRL_BASE_IDX 2 1824#define regDMCU_ERAM_WR_CTRL 0x00e3 1825#define regDMCU_ERAM_WR_CTRL_BASE_IDX 2 1826#define regDMCU_ERAM_WR_DATA 0x00e4 1827#define regDMCU_ERAM_WR_DATA_BASE_IDX 2 1828#define regDMCU_ERAM_RD_CTRL 0x00e5 1829#define regDMCU_ERAM_RD_CTRL_BASE_IDX 2 1830#define regDMCU_ERAM_RD_DATA 0x00e6 1831#define regDMCU_ERAM_RD_DATA_BASE_IDX 2 1832#define regDMCU_IRAM_WR_CTRL 0x00e7 1833#define regDMCU_IRAM_WR_CTRL_BASE_IDX 2 1834#define regDMCU_IRAM_WR_DATA 0x00e8 1835#define regDMCU_IRAM_WR_DATA_BASE_IDX 2 1836#define regDMCU_IRAM_RD_CTRL 0x00e9 1837#define regDMCU_IRAM_RD_CTRL_BASE_IDX 2 1838#define regDMCU_IRAM_RD_DATA 0x00ea 1839#define regDMCU_IRAM_RD_DATA_BASE_IDX 2 1840#define regDMCU_EVENT_TRIGGER 0x00eb 1841#define regDMCU_EVENT_TRIGGER_BASE_IDX 2 1842#define regDMCU_UC_INTERNAL_INT_STATUS 0x00ec 1843#define regDMCU_UC_INTERNAL_INT_STATUS_BASE_IDX 2 1844#define regDMCU_SS_INTERRUPT_CNTL_STATUS 0x00ed 1845#define regDMCU_SS_INTERRUPT_CNTL_STATUS_BASE_IDX 2 1846#define regDMCU_INTERRUPT_STATUS 0x00ee 1847#define regDMCU_INTERRUPT_STATUS_BASE_IDX 2 1848#define regDMCU_INTERRUPT_STATUS_1 0x00ef 1849#define regDMCU_INTERRUPT_STATUS_1_BASE_IDX 2 1850#define regDMCU_INTERRUPT_TO_HOST_EN_MASK 0x00f0 1851#define regDMCU_INTERRUPT_TO_HOST_EN_MASK_BASE_IDX 2 1852#define regDMCU_INTERRUPT_TO_UC_EN_MASK 0x00f1 1853#define regDMCU_INTERRUPT_TO_UC_EN_MASK_BASE_IDX 2 1854#define regDMCU_INTERRUPT_TO_UC_EN_MASK_1 0x00f2 1855#define regDMCU_INTERRUPT_TO_UC_EN_MASK_1_BASE_IDX 2 1856#define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL 0x00f3 1857#define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_BASE_IDX 2 1858#define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1 0x00f4 1859#define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1_BASE_IDX 2 1860#define regDC_DMCU_SCRATCH 0x00f5 1861#define regDC_DMCU_SCRATCH_BASE_IDX 2 1862#define regDMCU_INT_CNT 0x00f6 1863#define regDMCU_INT_CNT_BASE_IDX 2 1864#define regDMCU_FW_CHECKSUM_SMPL_BYTE_POS 0x00f7 1865#define regDMCU_FW_CHECKSUM_SMPL_BYTE_POS_BASE_IDX 2 1866#define regDMCU_UC_CLK_GATING_CNTL 0x00f8 1867#define regDMCU_UC_CLK_GATING_CNTL_BASE_IDX 2 1868#define regMASTER_COMM_DATA_REG1 0x00f9 1869#define regMASTER_COMM_DATA_REG1_BASE_IDX 2 1870#define regMASTER_COMM_DATA_REG2 0x00fa 1871#define regMASTER_COMM_DATA_REG2_BASE_IDX 2 1872#define regMASTER_COMM_DATA_REG3 0x00fb 1873#define regMASTER_COMM_DATA_REG3_BASE_IDX 2 1874#define regMASTER_COMM_CMD_REG 0x00fc 1875#define regMASTER_COMM_CMD_REG_BASE_IDX 2 1876#define regMASTER_COMM_CNTL_REG 0x00fd 1877#define regMASTER_COMM_CNTL_REG_BASE_IDX 2 1878#define regSLAVE_COMM_DATA_REG1 0x00fe 1879#define regSLAVE_COMM_DATA_REG1_BASE_IDX 2 1880#define regSLAVE_COMM_DATA_REG2 0x00ff 1881#define regSLAVE_COMM_DATA_REG2_BASE_IDX 2 1882#define regSLAVE_COMM_DATA_REG3 0x0100 1883#define regSLAVE_COMM_DATA_REG3_BASE_IDX 2 1884#define regSLAVE_COMM_CMD_REG 0x0101 1885#define regSLAVE_COMM_CMD_REG_BASE_IDX 2 1886#define regSLAVE_COMM_CNTL_REG 0x0102 1887#define regSLAVE_COMM_CNTL_REG_BASE_IDX 2 1888#define regDMCU_PERFMON_INTERRUPT_STATUS1 0x0105 1889#define regDMCU_PERFMON_INTERRUPT_STATUS1_BASE_IDX 2 1890#define regDMCU_PERFMON_INTERRUPT_STATUS2 0x0106 1891#define regDMCU_PERFMON_INTERRUPT_STATUS2_BASE_IDX 2 1892#define regDMCU_PERFMON_INTERRUPT_STATUS3 0x0107 1893#define regDMCU_PERFMON_INTERRUPT_STATUS3_BASE_IDX 2 1894#define regDMCU_PERFMON_INTERRUPT_STATUS4 0x0108 1895#define regDMCU_PERFMON_INTERRUPT_STATUS4_BASE_IDX 2 1896#define regDMCU_PERFMON_INTERRUPT_STATUS5 0x0109 1897#define regDMCU_PERFMON_INTERRUPT_STATUS5_BASE_IDX 2 1898#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 0x010a 1899#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX 2 1900#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 0x010b 1901#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2_BASE_IDX 2 1902#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 0x010c 1903#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3_BASE_IDX 2 1904#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 0x010d 1905#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4_BASE_IDX 2 1906#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5 0x010e 1907#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5_BASE_IDX 2 1908#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x010f 1909#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX 2 1910#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 0x0110 1911#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2_BASE_IDX 2 1912#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 0x0111 1913#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3_BASE_IDX 2 1914#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 0x0112 1915#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4_BASE_IDX 2 1916#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5 0x0113 1917#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5_BASE_IDX 2 1918#define regDMCU_DPRX_INTERRUPT_STATUS1 0x0114 1919#define regDMCU_DPRX_INTERRUPT_STATUS1_BASE_IDX 2 1920#define regDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1 0x0115 1921#define regDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX 2 1922#define regDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x0116 1923#define regDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX 2 1924#define regDMCU_INTERRUPT_STATUS_CONTINUE 0x0119 1925#define regDMCU_INTERRUPT_STATUS_CONTINUE_BASE_IDX 2 1926#define regDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE 0x011a 1927#define regDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE_BASE_IDX 2 1928#define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE 0x011b 1929#define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE_BASE_IDX 2 1930#define regDMCU_INT_CNT_CONTINUE 0x011c 1931#define regDMCU_INT_CNT_CONTINUE_BASE_IDX 2 1932#define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2 0x011d 1933#define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2_BASE_IDX 2 1934#define regDMCU_INTERRUPT_STATUS_2 0x011e 1935#define regDMCU_INTERRUPT_STATUS_2_BASE_IDX 2 1936#define regDMCU_INTERRUPT_TO_UC_EN_MASK_2 0x011f 1937#define regDMCU_INTERRUPT_TO_UC_EN_MASK_2_BASE_IDX 2 1938#define regDMCU_INT_CNT_CONT2 0x0120 1939#define regDMCU_INT_CNT_CONT2_BASE_IDX 2 1940#define regDMCU_INT_CNT_CONT3 0x0121 1941#define regDMCU_INT_CNT_CONT3_BASE_IDX 2 1942 1943 1944// addressBlock: dce_dc_dmu_ihc_dispdec 1945// base address: 0x0 1946#define regDC_GPU_TIMER_START_POSITION_V_UPDATE 0x0126 1947#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_BASE_IDX 2 1948#define regDC_GPU_TIMER_START_POSITION_VSTARTUP 0x0127 1949#define regDC_GPU_TIMER_START_POSITION_VSTARTUP_BASE_IDX 2 1950#define regDC_GPU_TIMER_READ 0x0128 1951#define regDC_GPU_TIMER_READ_BASE_IDX 2 1952#define regDC_GPU_TIMER_READ_CNTL 0x0129 1953#define regDC_GPU_TIMER_READ_CNTL_BASE_IDX 2 1954#define regDISP_INTERRUPT_STATUS 0x012a 1955#define regDISP_INTERRUPT_STATUS_BASE_IDX 2 1956#define regDISP_INTERRUPT_STATUS_CONTINUE 0x012b 1957#define regDISP_INTERRUPT_STATUS_CONTINUE_BASE_IDX 2 1958#define regDISP_INTERRUPT_STATUS_CONTINUE2 0x012c 1959#define regDISP_INTERRUPT_STATUS_CONTINUE2_BASE_IDX 2 1960#define regDISP_INTERRUPT_STATUS_CONTINUE3 0x012d 1961#define regDISP_INTERRUPT_STATUS_CONTINUE3_BASE_IDX 2 1962#define regDISP_INTERRUPT_STATUS_CONTINUE4 0x012e 1963#define regDISP_INTERRUPT_STATUS_CONTINUE4_BASE_IDX 2 1964#define regDISP_INTERRUPT_STATUS_CONTINUE5 0x012f 1965#define regDISP_INTERRUPT_STATUS_CONTINUE5_BASE_IDX 2 1966#define regDISP_INTERRUPT_STATUS_CONTINUE6 0x0130 1967#define regDISP_INTERRUPT_STATUS_CONTINUE6_BASE_IDX 2 1968#define regDISP_INTERRUPT_STATUS_CONTINUE7 0x0131 1969#define regDISP_INTERRUPT_STATUS_CONTINUE7_BASE_IDX 2 1970#define regDISP_INTERRUPT_STATUS_CONTINUE8 0x0132 1971#define regDISP_INTERRUPT_STATUS_CONTINUE8_BASE_IDX 2 1972#define regDISP_INTERRUPT_STATUS_CONTINUE9 0x0133 1973#define regDISP_INTERRUPT_STATUS_CONTINUE9_BASE_IDX 2 1974#define regDISP_INTERRUPT_STATUS_CONTINUE10 0x0134 1975#define regDISP_INTERRUPT_STATUS_CONTINUE10_BASE_IDX 2 1976#define regDISP_INTERRUPT_STATUS_CONTINUE11 0x0135 1977#define regDISP_INTERRUPT_STATUS_CONTINUE11_BASE_IDX 2 1978#define regDISP_INTERRUPT_STATUS_CONTINUE12 0x0136 1979#define regDISP_INTERRUPT_STATUS_CONTINUE12_BASE_IDX 2 1980#define regDISP_INTERRUPT_STATUS_CONTINUE13 0x0137 1981#define regDISP_INTERRUPT_STATUS_CONTINUE13_BASE_IDX 2 1982#define regDISP_INTERRUPT_STATUS_CONTINUE14 0x0138 1983#define regDISP_INTERRUPT_STATUS_CONTINUE14_BASE_IDX 2 1984#define regDISP_INTERRUPT_STATUS_CONTINUE15 0x0139 1985#define regDISP_INTERRUPT_STATUS_CONTINUE15_BASE_IDX 2 1986#define regDISP_INTERRUPT_STATUS_CONTINUE16 0x013a 1987#define regDISP_INTERRUPT_STATUS_CONTINUE16_BASE_IDX 2 1988#define regDISP_INTERRUPT_STATUS_CONTINUE17 0x013b 1989#define regDISP_INTERRUPT_STATUS_CONTINUE17_BASE_IDX 2 1990#define regDISP_INTERRUPT_STATUS_CONTINUE18 0x013c 1991#define regDISP_INTERRUPT_STATUS_CONTINUE18_BASE_IDX 2 1992#define regDISP_INTERRUPT_STATUS_CONTINUE19 0x013d 1993#define regDISP_INTERRUPT_STATUS_CONTINUE19_BASE_IDX 2 1994#define regDISP_INTERRUPT_STATUS_CONTINUE20 0x013e 1995#define regDISP_INTERRUPT_STATUS_CONTINUE20_BASE_IDX 2 1996#define regDISP_INTERRUPT_STATUS_CONTINUE21 0x013f 1997#define regDISP_INTERRUPT_STATUS_CONTINUE21_BASE_IDX 2 1998#define regDISP_INTERRUPT_STATUS_CONTINUE22 0x0140 1999#define regDISP_INTERRUPT_STATUS_CONTINUE22_BASE_IDX 2 2000#define regDC_GPU_TIMER_START_POSITION_VREADY 0x0141 2001#define regDC_GPU_TIMER_START_POSITION_VREADY_BASE_IDX 2 2002#define regDC_GPU_TIMER_START_POSITION_FLIP 0x0142 2003#define regDC_GPU_TIMER_START_POSITION_FLIP_BASE_IDX 2 2004#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK 0x0143 2005#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK_BASE_IDX 2 2006#define regDC_GPU_TIMER_START_POSITION_FLIP_AWAY 0x0144 2007#define regDC_GPU_TIMER_START_POSITION_FLIP_AWAY_BASE_IDX 2 2008#define regDISP_INTERRUPT_STATUS_CONTINUE23 0x0145 2009#define regDISP_INTERRUPT_STATUS_CONTINUE23_BASE_IDX 2 2010#define regDISP_INTERRUPT_STATUS_CONTINUE24 0x0146 2011#define regDISP_INTERRUPT_STATUS_CONTINUE24_BASE_IDX 2 2012#define regDISP_INTERRUPT_STATUS_CONTINUE25 0x0147 2013#define regDISP_INTERRUPT_STATUS_CONTINUE25_BASE_IDX 2 2014#define regDCCG_INTERRUPT_DEST 0x0148 2015#define regDCCG_INTERRUPT_DEST_BASE_IDX 2 2016#define regDMU_INTERRUPT_DEST 0x0149 2017#define regDMU_INTERRUPT_DEST_BASE_IDX 2 2018#define regDMU_INTERRUPT_DEST2 0x014a 2019#define regDMU_INTERRUPT_DEST2_BASE_IDX 2 2020#define regDCPG_INTERRUPT_DEST 0x014b 2021#define regDCPG_INTERRUPT_DEST_BASE_IDX 2 2022#define regDCPG_INTERRUPT_DEST2 0x014c 2023#define regDCPG_INTERRUPT_DEST2_BASE_IDX 2 2024#define regMMHUBBUB_INTERRUPT_DEST 0x014d 2025#define regMMHUBBUB_INTERRUPT_DEST_BASE_IDX 2 2026#define regWB_INTERRUPT_DEST 0x014e 2027#define regWB_INTERRUPT_DEST_BASE_IDX 2 2028#define regDCHUB_INTERRUPT_DEST 0x014f 2029#define regDCHUB_INTERRUPT_DEST_BASE_IDX 2 2030#define regDCHUB_PERFCOUNTER_INTERRUPT_DEST 0x0150 2031#define regDCHUB_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX 2 2032#define regDCHUB_INTERRUPT_DEST2 0x0151 2033#define regDCHUB_INTERRUPT_DEST2_BASE_IDX 2 2034#define regDPP_PERFCOUNTER_INTERRUPT_DEST 0x0152 2035#define regDPP_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX 2 2036#define regMPC_INTERRUPT_DEST 0x0153 2037#define regMPC_INTERRUPT_DEST_BASE_IDX 2 2038#define regOPP_INTERRUPT_DEST 0x0154 2039#define regOPP_INTERRUPT_DEST_BASE_IDX 2 2040#define regOPTC_INTERRUPT_DEST 0x0155 2041#define regOPTC_INTERRUPT_DEST_BASE_IDX 2 2042#define regOTG0_INTERRUPT_DEST 0x0156 2043#define regOTG0_INTERRUPT_DEST_BASE_IDX 2 2044#define regOTG1_INTERRUPT_DEST 0x0157 2045#define regOTG1_INTERRUPT_DEST_BASE_IDX 2 2046#define regOTG2_INTERRUPT_DEST 0x0158 2047#define regOTG2_INTERRUPT_DEST_BASE_IDX 2 2048#define regOTG3_INTERRUPT_DEST 0x0159 2049#define regOTG3_INTERRUPT_DEST_BASE_IDX 2 2050#define regOTG4_INTERRUPT_DEST 0x015a 2051#define regOTG4_INTERRUPT_DEST_BASE_IDX 2 2052#define regOTG5_INTERRUPT_DEST 0x015b 2053#define regOTG5_INTERRUPT_DEST_BASE_IDX 2 2054#define regDIG_INTERRUPT_DEST 0x015c 2055#define regDIG_INTERRUPT_DEST_BASE_IDX 2 2056#define regI2C_DDC_HPD_INTERRUPT_DEST 0x015d 2057#define regI2C_DDC_HPD_INTERRUPT_DEST_BASE_IDX 2 2058#define regDIO_INTERRUPT_DEST 0x015f 2059#define regDIO_INTERRUPT_DEST_BASE_IDX 2 2060#define regDCIO_INTERRUPT_DEST 0x0160 2061#define regDCIO_INTERRUPT_DEST_BASE_IDX 2 2062#define regHPD_INTERRUPT_DEST 0x0161 2063#define regHPD_INTERRUPT_DEST_BASE_IDX 2 2064#define regAZ_INTERRUPT_DEST 0x0162 2065#define regAZ_INTERRUPT_DEST_BASE_IDX 2 2066#define regAUX_INTERRUPT_DEST 0x0163 2067#define regAUX_INTERRUPT_DEST_BASE_IDX 2 2068#define regDSC_INTERRUPT_DEST 0x0164 2069#define regDSC_INTERRUPT_DEST_BASE_IDX 2 2070#define regHPO_INTERRUPT_DEST 0x0165 2071#define regHPO_INTERRUPT_DEST_BASE_IDX 2 2072 2073 2074// addressBlock: dce_dc_dmu_fgsec_dispdec 2075// base address: 0x0 2076#define regDMCUB_RBBMIF_SEC_CNTL 0x017a 2077#define regDMCUB_RBBMIF_SEC_CNTL_BASE_IDX 2 2078 2079 2080// addressBlock: dce_dc_dmu_rbbmif_dispdec 2081// base address: 0x0 2082#define regRBBMIF_TIMEOUT 0x017f 2083#define regRBBMIF_TIMEOUT_BASE_IDX 2 2084#define regRBBMIF_STATUS 0x0180 2085#define regRBBMIF_STATUS_BASE_IDX 2 2086#define regRBBMIF_STATUS_2 0x0181 2087#define regRBBMIF_STATUS_2_BASE_IDX 2 2088#define regRBBMIF_INT_STATUS 0x0182 2089#define regRBBMIF_INT_STATUS_BASE_IDX 2 2090#define regRBBMIF_TIMEOUT_DIS 0x0183 2091#define regRBBMIF_TIMEOUT_DIS_BASE_IDX 2 2092#define regRBBMIF_TIMEOUT_DIS_2 0x0184 2093#define regRBBMIF_TIMEOUT_DIS_2_BASE_IDX 2 2094#define regRBBMIF_STATUS_FLAG 0x0185 2095#define regRBBMIF_STATUS_FLAG_BASE_IDX 2 2096 2097 2098// addressBlock: dce_dc_dmu_dmcub_dispdec 2099// base address: 0x0 2100#define regDMCUB_REGION0_OFFSET 0x018e 2101#define regDMCUB_REGION0_OFFSET_BASE_IDX 2 2102#define regDMCUB_REGION0_OFFSET_HIGH 0x018f 2103#define regDMCUB_REGION0_OFFSET_HIGH_BASE_IDX 2 2104#define regDMCUB_REGION1_OFFSET 0x0190 2105#define regDMCUB_REGION1_OFFSET_BASE_IDX 2 2106#define regDMCUB_REGION1_OFFSET_HIGH 0x0191 2107#define regDMCUB_REGION1_OFFSET_HIGH_BASE_IDX 2 2108#define regDMCUB_REGION2_OFFSET 0x0192 2109#define regDMCUB_REGION2_OFFSET_BASE_IDX 2 2110#define regDMCUB_REGION2_OFFSET_HIGH 0x0193 2111#define regDMCUB_REGION2_OFFSET_HIGH_BASE_IDX 2 2112#define regDMCUB_REGION4_OFFSET 0x0196 2113#define regDMCUB_REGION4_OFFSET_BASE_IDX 2 2114#define regDMCUB_REGION4_OFFSET_HIGH 0x0197 2115#define regDMCUB_REGION4_OFFSET_HIGH_BASE_IDX 2 2116#define regDMCUB_REGION5_OFFSET 0x0198 2117#define regDMCUB_REGION5_OFFSET_BASE_IDX 2 2118#define regDMCUB_REGION5_OFFSET_HIGH 0x0199 2119#define regDMCUB_REGION5_OFFSET_HIGH_BASE_IDX 2 2120#define regDMCUB_REGION6_OFFSET 0x019a 2121#define regDMCUB_REGION6_OFFSET_BASE_IDX 2 2122#define regDMCUB_REGION6_OFFSET_HIGH 0x019b 2123#define regDMCUB_REGION6_OFFSET_HIGH_BASE_IDX 2 2124#define regDMCUB_REGION7_OFFSET 0x019c 2125#define regDMCUB_REGION7_OFFSET_BASE_IDX 2 2126#define regDMCUB_REGION7_OFFSET_HIGH 0x019d 2127#define regDMCUB_REGION7_OFFSET_HIGH_BASE_IDX 2 2128#define regDMCUB_REGION0_TOP_ADDRESS 0x019e 2129#define regDMCUB_REGION0_TOP_ADDRESS_BASE_IDX 2 2130#define regDMCUB_REGION1_TOP_ADDRESS 0x019f 2131#define regDMCUB_REGION1_TOP_ADDRESS_BASE_IDX 2 2132#define regDMCUB_REGION2_TOP_ADDRESS 0x01a0 2133#define regDMCUB_REGION2_TOP_ADDRESS_BASE_IDX 2 2134#define regDMCUB_REGION4_TOP_ADDRESS 0x01a1 2135#define regDMCUB_REGION4_TOP_ADDRESS_BASE_IDX 2 2136#define regDMCUB_REGION5_TOP_ADDRESS 0x01a2 2137#define regDMCUB_REGION5_TOP_ADDRESS_BASE_IDX 2 2138#define regDMCUB_REGION6_TOP_ADDRESS 0x01a3 2139#define regDMCUB_REGION6_TOP_ADDRESS_BASE_IDX 2 2140#define regDMCUB_REGION7_TOP_ADDRESS 0x01a4 2141#define regDMCUB_REGION7_TOP_ADDRESS_BASE_IDX 2 2142#define regDMCUB_REGION3_CW0_BASE_ADDRESS 0x01a5 2143#define regDMCUB_REGION3_CW0_BASE_ADDRESS_BASE_IDX 2 2144#define regDMCUB_REGION3_CW1_BASE_ADDRESS 0x01a6 2145#define regDMCUB_REGION3_CW1_BASE_ADDRESS_BASE_IDX 2 2146#define regDMCUB_REGION3_CW2_BASE_ADDRESS 0x01a7 2147#define regDMCUB_REGION3_CW2_BASE_ADDRESS_BASE_IDX 2 2148#define regDMCUB_REGION3_CW3_BASE_ADDRESS 0x01a8 2149#define regDMCUB_REGION3_CW3_BASE_ADDRESS_BASE_IDX 2 2150#define regDMCUB_REGION3_CW4_BASE_ADDRESS 0x01a9 2151#define regDMCUB_REGION3_CW4_BASE_ADDRESS_BASE_IDX 2 2152#define regDMCUB_REGION3_CW5_BASE_ADDRESS 0x01aa 2153#define regDMCUB_REGION3_CW5_BASE_ADDRESS_BASE_IDX 2 2154#define regDMCUB_REGION3_CW6_BASE_ADDRESS 0x01ab 2155#define regDMCUB_REGION3_CW6_BASE_ADDRESS_BASE_IDX 2 2156#define regDMCUB_REGION3_CW7_BASE_ADDRESS 0x01ac 2157#define regDMCUB_REGION3_CW7_BASE_ADDRESS_BASE_IDX 2 2158#define regDMCUB_REGION3_CW0_TOP_ADDRESS 0x01ad 2159#define regDMCUB_REGION3_CW0_TOP_ADDRESS_BASE_IDX 2 2160#define regDMCUB_REGION3_CW1_TOP_ADDRESS 0x01ae 2161#define regDMCUB_REGION3_CW1_TOP_ADDRESS_BASE_IDX 2 2162#define regDMCUB_REGION3_CW2_TOP_ADDRESS 0x01af 2163#define regDMCUB_REGION3_CW2_TOP_ADDRESS_BASE_IDX 2 2164#define regDMCUB_REGION3_CW3_TOP_ADDRESS 0x01b0 2165#define regDMCUB_REGION3_CW3_TOP_ADDRESS_BASE_IDX 2 2166#define regDMCUB_REGION3_CW4_TOP_ADDRESS 0x01b1 2167#define regDMCUB_REGION3_CW4_TOP_ADDRESS_BASE_IDX 2 2168#define regDMCUB_REGION3_CW5_TOP_ADDRESS 0x01b2 2169#define regDMCUB_REGION3_CW5_TOP_ADDRESS_BASE_IDX 2 2170#define regDMCUB_REGION3_CW6_TOP_ADDRESS 0x01b3 2171#define regDMCUB_REGION3_CW6_TOP_ADDRESS_BASE_IDX 2 2172#define regDMCUB_REGION3_CW7_TOP_ADDRESS 0x01b4 2173#define regDMCUB_REGION3_CW7_TOP_ADDRESS_BASE_IDX 2 2174#define regDMCUB_REGION3_CW0_OFFSET 0x01b5 2175#define regDMCUB_REGION3_CW0_OFFSET_BASE_IDX 2 2176#define regDMCUB_REGION3_CW0_OFFSET_HIGH 0x01b6 2177#define regDMCUB_REGION3_CW0_OFFSET_HIGH_BASE_IDX 2 2178#define regDMCUB_REGION3_CW1_OFFSET 0x01b7 2179#define regDMCUB_REGION3_CW1_OFFSET_BASE_IDX 2 2180#define regDMCUB_REGION3_CW1_OFFSET_HIGH 0x01b8 2181#define regDMCUB_REGION3_CW1_OFFSET_HIGH_BASE_IDX 2 2182#define regDMCUB_REGION3_CW2_OFFSET 0x01b9 2183#define regDMCUB_REGION3_CW2_OFFSET_BASE_IDX 2 2184#define regDMCUB_REGION3_CW2_OFFSET_HIGH 0x01ba 2185#define regDMCUB_REGION3_CW2_OFFSET_HIGH_BASE_IDX 2 2186#define regDMCUB_REGION3_CW3_OFFSET 0x01bb 2187#define regDMCUB_REGION3_CW3_OFFSET_BASE_IDX 2 2188#define regDMCUB_REGION3_CW3_OFFSET_HIGH 0x01bc 2189#define regDMCUB_REGION3_CW3_OFFSET_HIGH_BASE_IDX 2 2190#define regDMCUB_REGION3_CW4_OFFSET 0x01bd 2191#define regDMCUB_REGION3_CW4_OFFSET_BASE_IDX 2 2192#define regDMCUB_REGION3_CW4_OFFSET_HIGH 0x01be 2193#define regDMCUB_REGION3_CW4_OFFSET_HIGH_BASE_IDX 2 2194#define regDMCUB_REGION3_CW5_OFFSET 0x01bf 2195#define regDMCUB_REGION3_CW5_OFFSET_BASE_IDX 2 2196#define regDMCUB_REGION3_CW5_OFFSET_HIGH 0x01c0 2197#define regDMCUB_REGION3_CW5_OFFSET_HIGH_BASE_IDX 2 2198#define regDMCUB_REGION3_CW6_OFFSET 0x01c1 2199#define regDMCUB_REGION3_CW6_OFFSET_BASE_IDX 2 2200#define regDMCUB_REGION3_CW6_OFFSET_HIGH 0x01c2 2201#define regDMCUB_REGION3_CW6_OFFSET_HIGH_BASE_IDX 2 2202#define regDMCUB_REGION3_CW7_OFFSET 0x01c3 2203#define regDMCUB_REGION3_CW7_OFFSET_BASE_IDX 2 2204#define regDMCUB_REGION3_CW7_OFFSET_HIGH 0x01c4 2205#define regDMCUB_REGION3_CW7_OFFSET_HIGH_BASE_IDX 2 2206#define regDMCUB_INTERRUPT_ENABLE 0x01c5 2207#define regDMCUB_INTERRUPT_ENABLE_BASE_IDX 2 2208#define regDMCUB_INTERRUPT_ACK 0x01c6 2209#define regDMCUB_INTERRUPT_ACK_BASE_IDX 2 2210#define regDMCUB_INTERRUPT_STATUS 0x01c7 2211#define regDMCUB_INTERRUPT_STATUS_BASE_IDX 2 2212#define regDMCUB_INTERRUPT_TYPE 0x01c8 2213#define regDMCUB_INTERRUPT_TYPE_BASE_IDX 2 2214#define regDMCUB_EXT_INTERRUPT_STATUS 0x01c9 2215#define regDMCUB_EXT_INTERRUPT_STATUS_BASE_IDX 2 2216#define regDMCUB_EXT_INTERRUPT_CTXID 0x01ca 2217#define regDMCUB_EXT_INTERRUPT_CTXID_BASE_IDX 2 2218#define regDMCUB_EXT_INTERRUPT_ACK 0x01cb 2219#define regDMCUB_EXT_INTERRUPT_ACK_BASE_IDX 2 2220#define regDMCUB_INST_FETCH_FAULT_ADDR 0x01cc 2221#define regDMCUB_INST_FETCH_FAULT_ADDR_BASE_IDX 2 2222#define regDMCUB_DATA_WRITE_FAULT_ADDR 0x01cd 2223#define regDMCUB_DATA_WRITE_FAULT_ADDR_BASE_IDX 2 2224#define regDMCUB_SEC_CNTL 0x01ce 2225#define regDMCUB_SEC_CNTL_BASE_IDX 2 2226#define regDMCUB_MEM_CNTL 0x01cf 2227#define regDMCUB_MEM_CNTL_BASE_IDX 2 2228#define regDMCUB_INBOX0_BASE_ADDRESS 0x01d0 2229#define regDMCUB_INBOX0_BASE_ADDRESS_BASE_IDX 2 2230#define regDMCUB_INBOX0_SIZE 0x01d1 2231#define regDMCUB_INBOX0_SIZE_BASE_IDX 2 2232#define regDMCUB_INBOX0_WPTR 0x01d2 2233#define regDMCUB_INBOX0_WPTR_BASE_IDX 2 2234#define regDMCUB_INBOX0_RPTR 0x01d3 2235#define regDMCUB_INBOX0_RPTR_BASE_IDX 2 2236#define regDMCUB_INBOX1_BASE_ADDRESS 0x01d4 2237#define regDMCUB_INBOX1_BASE_ADDRESS_BASE_IDX 2 2238#define regDMCUB_INBOX1_SIZE 0x01d5 2239#define regDMCUB_INBOX1_SIZE_BASE_IDX 2 2240#define regDMCUB_INBOX1_WPTR 0x01d6 2241#define regDMCUB_INBOX1_WPTR_BASE_IDX 2 2242#define regDMCUB_INBOX1_RPTR 0x01d7 2243#define regDMCUB_INBOX1_RPTR_BASE_IDX 2 2244#define regDMCUB_OUTBOX0_BASE_ADDRESS 0x01d8 2245#define regDMCUB_OUTBOX0_BASE_ADDRESS_BASE_IDX 2 2246#define regDMCUB_OUTBOX0_SIZE 0x01d9 2247#define regDMCUB_OUTBOX0_SIZE_BASE_IDX 2 2248#define regDMCUB_OUTBOX0_WPTR 0x01da 2249#define regDMCUB_OUTBOX0_WPTR_BASE_IDX 2 2250#define regDMCUB_OUTBOX0_RPTR 0x01db 2251#define regDMCUB_OUTBOX0_RPTR_BASE_IDX 2 2252#define regDMCUB_OUTBOX1_BASE_ADDRESS 0x01dc 2253#define regDMCUB_OUTBOX1_BASE_ADDRESS_BASE_IDX 2 2254#define regDMCUB_OUTBOX1_SIZE 0x01dd 2255#define regDMCUB_OUTBOX1_SIZE_BASE_IDX 2 2256#define regDMCUB_OUTBOX1_WPTR 0x01de 2257#define regDMCUB_OUTBOX1_WPTR_BASE_IDX 2 2258#define regDMCUB_OUTBOX1_RPTR 0x01df 2259#define regDMCUB_OUTBOX1_RPTR_BASE_IDX 2 2260#define regDMCUB_TIMER_TRIGGER0 0x01e0 2261#define regDMCUB_TIMER_TRIGGER0_BASE_IDX 2 2262#define regDMCUB_TIMER_TRIGGER1 0x01e1 2263#define regDMCUB_TIMER_TRIGGER1_BASE_IDX 2 2264#define regDMCUB_TIMER_WINDOW 0x01e2 2265#define regDMCUB_TIMER_WINDOW_BASE_IDX 2 2266#define regDMCUB_SCRATCH0 0x01e3 2267#define regDMCUB_SCRATCH0_BASE_IDX 2 2268#define regDMCUB_SCRATCH1 0x01e4 2269#define regDMCUB_SCRATCH1_BASE_IDX 2 2270#define regDMCUB_SCRATCH2 0x01e5 2271#define regDMCUB_SCRATCH2_BASE_IDX 2 2272#define regDMCUB_SCRATCH3 0x01e6 2273#define regDMCUB_SCRATCH3_BASE_IDX 2 2274#define regDMCUB_SCRATCH4 0x01e7 2275#define regDMCUB_SCRATCH4_BASE_IDX 2 2276#define regDMCUB_SCRATCH5 0x01e8 2277#define regDMCUB_SCRATCH5_BASE_IDX 2 2278#define regDMCUB_SCRATCH6 0x01e9 2279#define regDMCUB_SCRATCH6_BASE_IDX 2 2280#define regDMCUB_SCRATCH7 0x01ea 2281#define regDMCUB_SCRATCH7_BASE_IDX 2 2282#define regDMCUB_SCRATCH8 0x01eb 2283#define regDMCUB_SCRATCH8_BASE_IDX 2 2284#define regDMCUB_SCRATCH9 0x01ec 2285#define regDMCUB_SCRATCH9_BASE_IDX 2 2286#define regDMCUB_SCRATCH10 0x01ed 2287#define regDMCUB_SCRATCH10_BASE_IDX 2 2288#define regDMCUB_SCRATCH11 0x01ee 2289#define regDMCUB_SCRATCH11_BASE_IDX 2 2290#define regDMCUB_SCRATCH12 0x01ef 2291#define regDMCUB_SCRATCH12_BASE_IDX 2 2292#define regDMCUB_SCRATCH13 0x01f0 2293#define regDMCUB_SCRATCH13_BASE_IDX 2 2294#define regDMCUB_SCRATCH14 0x01f1 2295#define regDMCUB_SCRATCH14_BASE_IDX 2 2296#define regDMCUB_SCRATCH15 0x01f2 2297#define regDMCUB_SCRATCH15_BASE_IDX 2 2298#define regDMCUB_CNTL 0x01f6 2299#define regDMCUB_CNTL_BASE_IDX 2 2300#define regDMCUB_GPINT_DATAIN0 0x01f7 2301#define regDMCUB_GPINT_DATAIN0_BASE_IDX 2 2302#define regDMCUB_GPINT_DATAIN1 0x01f8 2303#define regDMCUB_GPINT_DATAIN1_BASE_IDX 2 2304#define regDMCUB_GPINT_DATAOUT 0x01f9 2305#define regDMCUB_GPINT_DATAOUT_BASE_IDX 2 2306#define regDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR 0x01fa 2307#define regDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_BASE_IDX 2 2308#define regDMCUB_LS_WAKE_INT_ENABLE 0x01fb 2309#define regDMCUB_LS_WAKE_INT_ENABLE_BASE_IDX 2 2310#define regDMCUB_MEM_PWR_CNTL 0x01fc 2311#define regDMCUB_MEM_PWR_CNTL_BASE_IDX 2 2312#define regDMCUB_TIMER_CURRENT 0x01fd 2313#define regDMCUB_TIMER_CURRENT_BASE_IDX 2 2314#define regDMCUB_PROC_ID 0x01ff 2315#define regDMCUB_PROC_ID_BASE_IDX 2 2316#define regDMCUB_CNTL2 0x0200 2317#define regDMCUB_CNTL2_BASE_IDX 2 2318#define regDMCUB_GPINT_DATAIN2 0x0215 2319#define regDMCUB_GPINT_DATAIN2_BASE_IDX 2 2320#define regDMCUB_GPINT_DATAIN3 0x0216 2321#define regDMCUB_GPINT_DATAIN3_BASE_IDX 2 2322#define regDMCUB_GPINT_DATAIN4 0x0217 2323#define regDMCUB_GPINT_DATAIN4_BASE_IDX 2 2324#define regDMCUB_GPINT_DATAIN5 0x0218 2325#define regDMCUB_GPINT_DATAIN5_BASE_IDX 2 2326#define regDMCUB_GPINT_DATAIN6 0x0219 2327#define regDMCUB_GPINT_DATAIN6_BASE_IDX 2 2328 2329 2330// addressBlock: dce_dc_mmhubbub_mcif_wb0_dispdec 2331// base address: 0x0 2332#define regMCIF_WB_BUFMGR_SW_CONTROL 0x0272 2333#define regMCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2 2334#define regMCIF_WB_BUFMGR_STATUS 0x0274 2335#define regMCIF_WB_BUFMGR_STATUS_BASE_IDX 2 2336#define regMCIF_WB_BUF_PITCH 0x0275 2337#define regMCIF_WB_BUF_PITCH_BASE_IDX 2 2338#define regMCIF_WB_BUF_1_STATUS 0x0276 2339#define regMCIF_WB_BUF_1_STATUS_BASE_IDX 2 2340#define regMCIF_WB_BUF_1_STATUS2 0x0277 2341#define regMCIF_WB_BUF_1_STATUS2_BASE_IDX 2 2342#define regMCIF_WB_BUF_2_STATUS 0x0278 2343#define regMCIF_WB_BUF_2_STATUS_BASE_IDX 2 2344#define regMCIF_WB_BUF_2_STATUS2 0x0279 2345#define regMCIF_WB_BUF_2_STATUS2_BASE_IDX 2 2346#define regMCIF_WB_BUF_3_STATUS 0x027a 2347#define regMCIF_WB_BUF_3_STATUS_BASE_IDX 2 2348#define regMCIF_WB_BUF_3_STATUS2 0x027b 2349#define regMCIF_WB_BUF_3_STATUS2_BASE_IDX 2 2350#define regMCIF_WB_BUF_4_STATUS 0x027c 2351#define regMCIF_WB_BUF_4_STATUS_BASE_IDX 2 2352#define regMCIF_WB_BUF_4_STATUS2 0x027d 2353#define regMCIF_WB_BUF_4_STATUS2_BASE_IDX 2 2354#define regMCIF_WB_ARBITRATION_CONTROL 0x027e 2355#define regMCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2 2356#define regMCIF_WB_SCLK_CHANGE 0x027f 2357#define regMCIF_WB_SCLK_CHANGE_BASE_IDX 2 2358#define regMCIF_WB_TEST_DEBUG_INDEX 0x0280 2359#define regMCIF_WB_TEST_DEBUG_INDEX_BASE_IDX 2 2360#define regMCIF_WB_TEST_DEBUG_DATA 0x0281 2361#define regMCIF_WB_TEST_DEBUG_DATA_BASE_IDX 2 2362#define regMCIF_WB_BUF_1_ADDR_Y 0x0282 2363#define regMCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2 2364#define regMCIF_WB_BUF_1_ADDR_C 0x0284 2365#define regMCIF_WB_BUF_1_ADDR_C_BASE_IDX 2 2366#define regMCIF_WB_BUF_2_ADDR_Y 0x0286 2367#define regMCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2 2368#define regMCIF_WB_BUF_2_ADDR_C 0x0288 2369#define regMCIF_WB_BUF_2_ADDR_C_BASE_IDX 2 2370#define regMCIF_WB_BUF_3_ADDR_Y 0x028a 2371#define regMCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2 2372#define regMCIF_WB_BUF_3_ADDR_C 0x028c 2373#define regMCIF_WB_BUF_3_ADDR_C_BASE_IDX 2 2374#define regMCIF_WB_BUF_4_ADDR_Y 0x028e 2375#define regMCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2 2376#define regMCIF_WB_BUF_4_ADDR_C 0x0290 2377#define regMCIF_WB_BUF_4_ADDR_C_BASE_IDX 2 2378#define regMCIF_WB_BUFMGR_VCE_CONTROL 0x0292 2379#define regMCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2 2380#define regMCIF_WB_NB_PSTATE_CONTROL 0x0293 2381#define regMCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2 2382#define regMCIF_WB_CLOCK_GATER_CONTROL 0x0294 2383#define regMCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2 2384#define regMCIF_WB_SELF_REFRESH_CONTROL 0x0296 2385#define regMCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2 2386#define regMULTI_LEVEL_QOS_CTRL 0x0297 2387#define regMULTI_LEVEL_QOS_CTRL_BASE_IDX 2 2388#define regMCIF_WB_BUF_LUMA_SIZE 0x0299 2389#define regMCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2 2390#define regMCIF_WB_BUF_CHROMA_SIZE 0x029a 2391#define regMCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2 2392#define regMCIF_WB_BUF_1_ADDR_Y_HIGH 0x029b 2393#define regMCIF_WB_BUF_1_ADDR_Y_HIGH_BASE_IDX 2 2394#define regMCIF_WB_BUF_1_ADDR_C_HIGH 0x029c 2395#define regMCIF_WB_BUF_1_ADDR_C_HIGH_BASE_IDX 2 2396#define regMCIF_WB_BUF_2_ADDR_Y_HIGH 0x029d 2397#define regMCIF_WB_BUF_2_ADDR_Y_HIGH_BASE_IDX 2 2398#define regMCIF_WB_BUF_2_ADDR_C_HIGH 0x029e 2399#define regMCIF_WB_BUF_2_ADDR_C_HIGH_BASE_IDX 2 2400#define regMCIF_WB_BUF_3_ADDR_Y_HIGH 0x029f 2401#define regMCIF_WB_BUF_3_ADDR_Y_HIGH_BASE_IDX 2 2402#define regMCIF_WB_BUF_3_ADDR_C_HIGH 0x02a0 2403#define regMCIF_WB_BUF_3_ADDR_C_HIGH_BASE_IDX 2 2404#define regMCIF_WB_BUF_4_ADDR_Y_HIGH 0x02a1 2405#define regMCIF_WB_BUF_4_ADDR_Y_HIGH_BASE_IDX 2 2406#define regMCIF_WB_BUF_4_ADDR_C_HIGH 0x02a2 2407#define regMCIF_WB_BUF_4_ADDR_C_HIGH_BASE_IDX 2 2408#define regMCIF_WB_BUF_1_RESOLUTION 0x02a3 2409#define regMCIF_WB_BUF_1_RESOLUTION_BASE_IDX 2 2410#define regMCIF_WB_BUF_2_RESOLUTION 0x02a4 2411#define regMCIF_WB_BUF_2_RESOLUTION_BASE_IDX 2 2412#define regMCIF_WB_BUF_3_RESOLUTION 0x02a5 2413#define regMCIF_WB_BUF_3_RESOLUTION_BASE_IDX 2 2414#define regMCIF_WB_BUF_4_RESOLUTION 0x02a6 2415#define regMCIF_WB_BUF_4_RESOLUTION_BASE_IDX 2 2416#define regMCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI 0x02a7 2417#define regMCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI_BASE_IDX 2 2418#define regMCIF_WB_VMID_CONTROL 0x02a8 2419#define regMCIF_WB_VMID_CONTROL_BASE_IDX 2 2420#define regMCIF_WB_MIN_TTO 0x02a9 2421#define regMCIF_WB_MIN_TTO_BASE_IDX 2 2422 2423 2424// addressBlock: dce_dc_mmhubbub_mmhubbub_dispdec 2425// base address: 0x0 2426#define regMCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x02aa 2427#define regMCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2 2428#define regMCIF_WB_WATERMARK 0x02ab 2429#define regMCIF_WB_WATERMARK_BASE_IDX 2 2430#define regMMHUBBUB_WARMUP_CONFIG 0x02ac 2431#define regMMHUBBUB_WARMUP_CONFIG_BASE_IDX 2 2432#define regMMHUBBUB_WARMUP_CONTROL_STATUS 0x02ad 2433#define regMMHUBBUB_WARMUP_CONTROL_STATUS_BASE_IDX 2 2434#define regMMHUBBUB_WARMUP_BASE_ADDR_LOW 0x02ae 2435#define regMMHUBBUB_WARMUP_BASE_ADDR_LOW_BASE_IDX 2 2436#define regMMHUBBUB_WARMUP_BASE_ADDR_HIGH 0x02af 2437#define regMMHUBBUB_WARMUP_BASE_ADDR_HIGH_BASE_IDX 2 2438#define regMMHUBBUB_WARMUP_ADDR_REGION 0x02b0 2439#define regMMHUBBUB_WARMUP_ADDR_REGION_BASE_IDX 2 2440#define regMMHUBBUB_MIN_TTO 0x02b1 2441#define regMMHUBBUB_MIN_TTO_BASE_IDX 2 2442#define regMMHUBBUB_CTRL 0x0333 2443#define regMMHUBBUB_CTRL_BASE_IDX 2 2444#define regWBIF_SMU_WM_CONTROL 0x0334 2445#define regWBIF_SMU_WM_CONTROL_BASE_IDX 2 2446#define regWBIF0_MISC_CTRL 0x0335 2447#define regWBIF0_MISC_CTRL_BASE_IDX 2 2448#define regWBIF0_PHASE0_OUTSTANDING_COUNTER 0x0336 2449#define regWBIF0_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2 2450#define regWBIF0_PHASE1_OUTSTANDING_COUNTER 0x0337 2451#define regWBIF0_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2 2452#define regVGA_SRC_SPLIT_CNTL 0x033e 2453#define regVGA_SRC_SPLIT_CNTL_BASE_IDX 2 2454#define regMMHUBBUB_MEM_PWR_STATUS 0x033f 2455#define regMMHUBBUB_MEM_PWR_STATUS_BASE_IDX 2 2456#define regMMHUBBUB_MEM_PWR_CNTL 0x0340 2457#define regMMHUBBUB_MEM_PWR_CNTL_BASE_IDX 2 2458#define regMMHUBBUB_CLOCK_CNTL 0x0341 2459#define regMMHUBBUB_CLOCK_CNTL_BASE_IDX 2 2460#define regMMHUBBUB_SOFT_RESET 0x0342 2461#define regMMHUBBUB_SOFT_RESET_BASE_IDX 2 2462#define regDMU_IF_ERR_STATUS 0x0346 2463#define regDMU_IF_ERR_STATUS_BASE_IDX 2 2464#define regMMHUBBUB_CLIENT_UNIT_ID 0x0347 2465#define regMMHUBBUB_CLIENT_UNIT_ID_BASE_IDX 2 2466#define regMMHUBBUB_WARMUP_VMID_CONTROL 0x0349 2467#define regMMHUBBUB_WARMUP_VMID_CONTROL_BASE_IDX 2 2468 2469 2470// addressBlock: dce_dc_mmhubbub_vgaif_dispdec 2471// base address: 0x0 2472#define regMCIF_CONTROL 0x034a 2473#define regMCIF_CONTROL_BASE_IDX 2 2474#define regMCIF_WRITE_COMBINE_CONTROL 0x034b 2475#define regMCIF_WRITE_COMBINE_CONTROL_BASE_IDX 2 2476#define regMCIF_PHASE0_OUTSTANDING_COUNTER 0x034e 2477#define regMCIF_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2 2478#define regMCIF_PHASE1_OUTSTANDING_COUNTER 0x034f 2479#define regMCIF_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2 2480#define regMCIF_PHASE2_OUTSTANDING_COUNTER 0x0350 2481#define regMCIF_PHASE2_OUTSTANDING_COUNTER_BASE_IDX 2 2482 2483 2484// addressBlock: dce_dc_mmhubbub_mmhubbub_dcperfmon_dc_perfmon_dispdec 2485// base address: 0xd48 2486#define regDC_PERFMON3_PERFCOUNTER_CNTL 0x0352 2487#define regDC_PERFMON3_PERFCOUNTER_CNTL_BASE_IDX 2 2488#define regDC_PERFMON3_PERFCOUNTER_CNTL2 0x0353 2489#define regDC_PERFMON3_PERFCOUNTER_CNTL2_BASE_IDX 2 2490#define regDC_PERFMON3_PERFCOUNTER_STATE 0x0354 2491#define regDC_PERFMON3_PERFCOUNTER_STATE_BASE_IDX 2 2492#define regDC_PERFMON3_PERFMON_CNTL 0x0355 2493#define regDC_PERFMON3_PERFMON_CNTL_BASE_IDX 2 2494#define regDC_PERFMON3_PERFMON_CNTL2 0x0356 2495#define regDC_PERFMON3_PERFMON_CNTL2_BASE_IDX 2 2496#define regDC_PERFMON3_PERFMON_CVALUE_INT_MISC 0x0357 2497#define regDC_PERFMON3_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 2498#define regDC_PERFMON3_PERFMON_CVALUE_LOW 0x0358 2499#define regDC_PERFMON3_PERFMON_CVALUE_LOW_BASE_IDX 2 2500#define regDC_PERFMON3_PERFMON_HI 0x0359 2501#define regDC_PERFMON3_PERFMON_HI_BASE_IDX 2 2502#define regDC_PERFMON3_PERFMON_LOW 0x035a 2503#define regDC_PERFMON3_PERFMON_LOW_BASE_IDX 2 2504 2505 2506// addressBlock: dce_dc_hda_azf0stream0_dispdec 2507// base address: 0x0 2508#define regAZF0STREAM0_AZALIA_STREAM_INDEX 0x035e 2509#define regAZF0STREAM0_AZALIA_STREAM_INDEX_BASE_IDX 2 2510#define regAZF0STREAM0_AZALIA_STREAM_DATA 0x035f 2511#define regAZF0STREAM0_AZALIA_STREAM_DATA_BASE_IDX 2 2512 2513 2514// addressBlock: dce_dc_hda_azf0stream1_dispdec 2515// base address: 0x8 2516#define regAZF0STREAM1_AZALIA_STREAM_INDEX 0x0360 2517#define regAZF0STREAM1_AZALIA_STREAM_INDEX_BASE_IDX 2 2518#define regAZF0STREAM1_AZALIA_STREAM_DATA 0x0361 2519#define regAZF0STREAM1_AZALIA_STREAM_DATA_BASE_IDX 2 2520 2521 2522// addressBlock: dce_dc_hda_azf0stream2_dispdec 2523// base address: 0x10 2524#define regAZF0STREAM2_AZALIA_STREAM_INDEX 0x0362 2525#define regAZF0STREAM2_AZALIA_STREAM_INDEX_BASE_IDX 2 2526#define regAZF0STREAM2_AZALIA_STREAM_DATA 0x0363 2527#define regAZF0STREAM2_AZALIA_STREAM_DATA_BASE_IDX 2 2528 2529 2530// addressBlock: dce_dc_hda_azf0stream3_dispdec 2531// base address: 0x18 2532#define regAZF0STREAM3_AZALIA_STREAM_INDEX 0x0364 2533#define regAZF0STREAM3_AZALIA_STREAM_INDEX_BASE_IDX 2 2534#define regAZF0STREAM3_AZALIA_STREAM_DATA 0x0365 2535#define regAZF0STREAM3_AZALIA_STREAM_DATA_BASE_IDX 2 2536 2537 2538// addressBlock: dce_dc_hda_azf0stream4_dispdec 2539// base address: 0x20 2540#define regAZF0STREAM4_AZALIA_STREAM_INDEX 0x0366 2541#define regAZF0STREAM4_AZALIA_STREAM_INDEX_BASE_IDX 2 2542#define regAZF0STREAM4_AZALIA_STREAM_DATA 0x0367 2543#define regAZF0STREAM4_AZALIA_STREAM_DATA_BASE_IDX 2 2544 2545 2546// addressBlock: dce_dc_hda_azf0stream5_dispdec 2547// base address: 0x28 2548#define regAZF0STREAM5_AZALIA_STREAM_INDEX 0x0368 2549#define regAZF0STREAM5_AZALIA_STREAM_INDEX_BASE_IDX 2 2550#define regAZF0STREAM5_AZALIA_STREAM_DATA 0x0369 2551#define regAZF0STREAM5_AZALIA_STREAM_DATA_BASE_IDX 2 2552 2553 2554// addressBlock: dce_dc_hda_azf0stream6_dispdec 2555// base address: 0x30 2556#define regAZF0STREAM6_AZALIA_STREAM_INDEX 0x036a 2557#define regAZF0STREAM6_AZALIA_STREAM_INDEX_BASE_IDX 2 2558#define regAZF0STREAM6_AZALIA_STREAM_DATA 0x036b 2559#define regAZF0STREAM6_AZALIA_STREAM_DATA_BASE_IDX 2 2560 2561 2562// addressBlock: dce_dc_hda_azf0stream7_dispdec 2563// base address: 0x38 2564#define regAZF0STREAM7_AZALIA_STREAM_INDEX 0x036c 2565#define regAZF0STREAM7_AZALIA_STREAM_INDEX_BASE_IDX 2 2566#define regAZF0STREAM7_AZALIA_STREAM_DATA 0x036d 2567#define regAZF0STREAM7_AZALIA_STREAM_DATA_BASE_IDX 2 2568 2569 2570// addressBlock: dce_dc_hda_az_misc_dispdec 2571// base address: 0x0 2572#define regAZ_CLOCK_CNTL 0x0372 2573#define regAZ_CLOCK_CNTL_BASE_IDX 2 2574 2575 2576// addressBlock: dce_dc_hda_az_dcperfmon_dc_perfmon_dispdec 2577// base address: 0xde8 2578#define regDC_PERFMON4_PERFCOUNTER_CNTL 0x037a 2579#define regDC_PERFMON4_PERFCOUNTER_CNTL_BASE_IDX 2 2580#define regDC_PERFMON4_PERFCOUNTER_CNTL2 0x037b 2581#define regDC_PERFMON4_PERFCOUNTER_CNTL2_BASE_IDX 2 2582#define regDC_PERFMON4_PERFCOUNTER_STATE 0x037c 2583#define regDC_PERFMON4_PERFCOUNTER_STATE_BASE_IDX 2 2584#define regDC_PERFMON4_PERFMON_CNTL 0x037d 2585#define regDC_PERFMON4_PERFMON_CNTL_BASE_IDX 2 2586#define regDC_PERFMON4_PERFMON_CNTL2 0x037e 2587#define regDC_PERFMON4_PERFMON_CNTL2_BASE_IDX 2 2588#define regDC_PERFMON4_PERFMON_CVALUE_INT_MISC 0x037f 2589#define regDC_PERFMON4_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 2590#define regDC_PERFMON4_PERFMON_CVALUE_LOW 0x0380 2591#define regDC_PERFMON4_PERFMON_CVALUE_LOW_BASE_IDX 2 2592#define regDC_PERFMON4_PERFMON_HI 0x0381 2593#define regDC_PERFMON4_PERFMON_HI_BASE_IDX 2 2594#define regDC_PERFMON4_PERFMON_LOW 0x0382 2595#define regDC_PERFMON4_PERFMON_LOW_BASE_IDX 2 2596 2597 2598// addressBlock: dce_dc_hda_azf0endpoint0_dispdec 2599// base address: 0x0 2600#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0386 2601#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 2602#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0387 2603#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 2604 2605 2606// addressBlock: dce_dc_hda_azf0endpoint1_dispdec 2607// base address: 0x18 2608#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x038c 2609#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 2610#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x038d 2611#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 2612 2613 2614// addressBlock: dce_dc_hda_azf0endpoint2_dispdec 2615// base address: 0x30 2616#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0392 2617#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 2618#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0393 2619#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 2620 2621 2622// addressBlock: dce_dc_hda_azf0endpoint3_dispdec 2623// base address: 0x48 2624#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0398 2625#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 2626#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0399 2627#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 2628 2629 2630// addressBlock: dce_dc_hda_azf0endpoint4_dispdec 2631// base address: 0x60 2632#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x039e 2633#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 2634#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x039f 2635#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 2636 2637 2638// addressBlock: dce_dc_hda_azf0endpoint5_dispdec 2639// base address: 0x78 2640#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03a4 2641#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 2642#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03a5 2643#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 2644 2645 2646// addressBlock: dce_dc_hda_azf0endpoint6_dispdec 2647// base address: 0x90 2648#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03aa 2649#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 2650#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03ab 2651#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 2652 2653 2654// addressBlock: dce_dc_hda_azf0endpoint7_dispdec 2655// base address: 0xa8 2656#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03b0 2657#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 2658#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03b1 2659#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 2660 2661 2662// addressBlock: dce_dc_hda_azf0controller_dispdec 2663// base address: 0x0 2664#define regAZALIA_CONTROLLER_CLOCK_GATING 0x03c2 2665#define regAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX 2 2666#define regAZALIA_AUDIO_DTO 0x03c3 2667#define regAZALIA_AUDIO_DTO_BASE_IDX 2 2668#define regAZALIA_AUDIO_DTO_CONTROL 0x03c4 2669#define regAZALIA_AUDIO_DTO_CONTROL_BASE_IDX 2 2670#define regAZALIA_SOCCLK_CONTROL 0x03c5 2671#define regAZALIA_SOCCLK_CONTROL_BASE_IDX 2 2672#define regAZALIA_UNDERFLOW_FILLER_SAMPLE 0x03c6 2673#define regAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX 2 2674#define regAZALIA_DATA_DMA_CONTROL 0x03c7 2675#define regAZALIA_DATA_DMA_CONTROL_BASE_IDX 2 2676#define regAZALIA_BDL_DMA_CONTROL 0x03c8 2677#define regAZALIA_BDL_DMA_CONTROL_BASE_IDX 2 2678#define regAZALIA_RIRB_AND_DP_CONTROL 0x03c9 2679#define regAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX 2 2680#define regAZALIA_CORB_DMA_CONTROL 0x03ca 2681#define regAZALIA_CORB_DMA_CONTROL_BASE_IDX 2 2682#define regAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0x03d1 2683#define regAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER_BASE_IDX 2 2684#define regAZALIA_CYCLIC_BUFFER_SYNC 0x03d2 2685#define regAZALIA_CYCLIC_BUFFER_SYNC_BASE_IDX 2 2686#define regAZALIA_GLOBAL_CAPABILITIES 0x03d3 2687#define regAZALIA_GLOBAL_CAPABILITIES_BASE_IDX 2 2688#define regAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x03d5 2689#define regAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX 2 2690#define regAZALIA_INPUT_CRC0_CONTROL0 0x03d9 2691#define regAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX 2 2692#define regAZALIA_INPUT_CRC0_CONTROL1 0x03da 2693#define regAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX 2 2694#define regAZALIA_INPUT_CRC0_CONTROL2 0x03db 2695#define regAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX 2 2696#define regAZALIA_INPUT_CRC0_CONTROL3 0x03dc 2697#define regAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX 2 2698#define regAZALIA_INPUT_CRC0_RESULT 0x03dd 2699#define regAZALIA_INPUT_CRC0_RESULT_BASE_IDX 2 2700#define regAZALIA_INPUT_CRC1_CONTROL0 0x03de 2701#define regAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX 2 2702#define regAZALIA_INPUT_CRC1_CONTROL1 0x03df 2703#define regAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX 2 2704#define regAZALIA_INPUT_CRC1_CONTROL2 0x03e0 2705#define regAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX 2 2706#define regAZALIA_INPUT_CRC1_CONTROL3 0x03e1 2707#define regAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX 2 2708#define regAZALIA_INPUT_CRC1_RESULT 0x03e2 2709#define regAZALIA_INPUT_CRC1_RESULT_BASE_IDX 2 2710#define regAZALIA_CRC0_CONTROL0 0x03e3 2711#define regAZALIA_CRC0_CONTROL0_BASE_IDX 2 2712#define regAZALIA_CRC0_CONTROL1 0x03e4 2713#define regAZALIA_CRC0_CONTROL1_BASE_IDX 2 2714#define regAZALIA_CRC0_CONTROL2 0x03e5 2715#define regAZALIA_CRC0_CONTROL2_BASE_IDX 2 2716#define regAZALIA_CRC0_CONTROL3 0x03e6 2717#define regAZALIA_CRC0_CONTROL3_BASE_IDX 2 2718#define regAZALIA_CRC0_RESULT 0x03e7 2719#define regAZALIA_CRC0_RESULT_BASE_IDX 2 2720#define regAZALIA_CRC1_CONTROL0 0x03e8 2721#define regAZALIA_CRC1_CONTROL0_BASE_IDX 2 2722#define regAZALIA_CRC1_CONTROL1 0x03e9 2723#define regAZALIA_CRC1_CONTROL1_BASE_IDX 2 2724#define regAZALIA_CRC1_CONTROL2 0x03ea 2725#define regAZALIA_CRC1_CONTROL2_BASE_IDX 2 2726#define regAZALIA_CRC1_CONTROL3 0x03eb 2727#define regAZALIA_CRC1_CONTROL3_BASE_IDX 2 2728#define regAZALIA_CRC1_RESULT 0x03ec 2729#define regAZALIA_CRC1_RESULT_BASE_IDX 2 2730#define regAZALIA_MEM_PWR_CTRL 0x03ee 2731#define regAZALIA_MEM_PWR_CTRL_BASE_IDX 2 2732#define regAZALIA_MEM_PWR_STATUS 0x03ef 2733#define regAZALIA_MEM_PWR_STATUS_BASE_IDX 2 2734 2735 2736// addressBlock: dce_dc_hda_azf0root_dispdec 2737// base address: 0x0 2738#define regAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0406 2739#define regAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX 2 2740#define regAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x0407 2741#define regAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX 2 2742#define regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x0408 2743#define regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX 2 2744#define regAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x0409 2745#define regAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX 2 2746#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x040a 2747#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX 2 2748#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x040b 2749#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX 2 2750#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x040c 2751#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX 2 2752#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x040d 2753#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX 2 2754#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x040e 2755#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX 2 2756#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x040f 2757#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX 2 2758#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x0410 2759#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX 2 2760#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x0411 2761#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX 2 2762#define regCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x0412 2763#define regCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2 2764#define regCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x0413 2765#define regCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2 2766#define regAZALIA_F0_GTC_GROUP_OFFSET0 0x0415 2767#define regAZALIA_F0_GTC_GROUP_OFFSET0_BASE_IDX 2 2768#define regAZALIA_F0_GTC_GROUP_OFFSET1 0x0416 2769#define regAZALIA_F0_GTC_GROUP_OFFSET1_BASE_IDX 2 2770#define regAZALIA_F0_GTC_GROUP_OFFSET2 0x0417 2771#define regAZALIA_F0_GTC_GROUP_OFFSET2_BASE_IDX 2 2772#define regAZALIA_F0_GTC_GROUP_OFFSET3 0x0418 2773#define regAZALIA_F0_GTC_GROUP_OFFSET3_BASE_IDX 2 2774#define regAZALIA_F0_GTC_GROUP_OFFSET4 0x0419 2775#define regAZALIA_F0_GTC_GROUP_OFFSET4_BASE_IDX 2 2776#define regAZALIA_F0_GTC_GROUP_OFFSET5 0x041a 2777#define regAZALIA_F0_GTC_GROUP_OFFSET5_BASE_IDX 2 2778#define regAZALIA_F0_GTC_GROUP_OFFSET6 0x041b 2779#define regAZALIA_F0_GTC_GROUP_OFFSET6_BASE_IDX 2 2780#define regREG_DC_AUDIO_PORT_CONNECTIVITY 0x041c 2781#define regREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2 2782#define regREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x041d 2783#define regREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2 2784 2785 2786// addressBlock: dce_dc_hda_azf0stream8_dispdec 2787// base address: 0x320 2788#define regAZF0STREAM8_AZALIA_STREAM_INDEX 0x0426 2789#define regAZF0STREAM8_AZALIA_STREAM_INDEX_BASE_IDX 2 2790#define regAZF0STREAM8_AZALIA_STREAM_DATA 0x0427 2791#define regAZF0STREAM8_AZALIA_STREAM_DATA_BASE_IDX 2 2792 2793 2794// addressBlock: dce_dc_hda_azf0stream9_dispdec 2795// base address: 0x328 2796#define regAZF0STREAM9_AZALIA_STREAM_INDEX 0x0428 2797#define regAZF0STREAM9_AZALIA_STREAM_INDEX_BASE_IDX 2 2798#define regAZF0STREAM9_AZALIA_STREAM_DATA 0x0429 2799#define regAZF0STREAM9_AZALIA_STREAM_DATA_BASE_IDX 2 2800 2801 2802// addressBlock: dce_dc_hda_azf0stream10_dispdec 2803// base address: 0x330 2804#define regAZF0STREAM10_AZALIA_STREAM_INDEX 0x042a 2805#define regAZF0STREAM10_AZALIA_STREAM_INDEX_BASE_IDX 2 2806#define regAZF0STREAM10_AZALIA_STREAM_DATA 0x042b 2807#define regAZF0STREAM10_AZALIA_STREAM_DATA_BASE_IDX 2 2808 2809 2810// addressBlock: dce_dc_hda_azf0stream11_dispdec 2811// base address: 0x338 2812#define regAZF0STREAM11_AZALIA_STREAM_INDEX 0x042c 2813#define regAZF0STREAM11_AZALIA_STREAM_INDEX_BASE_IDX 2 2814#define regAZF0STREAM11_AZALIA_STREAM_DATA 0x042d 2815#define regAZF0STREAM11_AZALIA_STREAM_DATA_BASE_IDX 2 2816 2817 2818// addressBlock: dce_dc_hda_azf0stream12_dispdec 2819// base address: 0x340 2820#define regAZF0STREAM12_AZALIA_STREAM_INDEX 0x042e 2821#define regAZF0STREAM12_AZALIA_STREAM_INDEX_BASE_IDX 2 2822#define regAZF0STREAM12_AZALIA_STREAM_DATA 0x042f 2823#define regAZF0STREAM12_AZALIA_STREAM_DATA_BASE_IDX 2 2824 2825 2826// addressBlock: dce_dc_hda_azf0stream13_dispdec 2827// base address: 0x348 2828#define regAZF0STREAM13_AZALIA_STREAM_INDEX 0x0430 2829#define regAZF0STREAM13_AZALIA_STREAM_INDEX_BASE_IDX 2 2830#define regAZF0STREAM13_AZALIA_STREAM_DATA 0x0431 2831#define regAZF0STREAM13_AZALIA_STREAM_DATA_BASE_IDX 2 2832 2833 2834// addressBlock: dce_dc_hda_azf0stream14_dispdec 2835// base address: 0x350 2836#define regAZF0STREAM14_AZALIA_STREAM_INDEX 0x0432 2837#define regAZF0STREAM14_AZALIA_STREAM_INDEX_BASE_IDX 2 2838#define regAZF0STREAM14_AZALIA_STREAM_DATA 0x0433 2839#define regAZF0STREAM14_AZALIA_STREAM_DATA_BASE_IDX 2 2840 2841 2842// addressBlock: dce_dc_hda_azf0stream15_dispdec 2843// base address: 0x358 2844#define regAZF0STREAM15_AZALIA_STREAM_INDEX 0x0434 2845#define regAZF0STREAM15_AZALIA_STREAM_INDEX_BASE_IDX 2 2846#define regAZF0STREAM15_AZALIA_STREAM_DATA 0x0435 2847#define regAZF0STREAM15_AZALIA_STREAM_DATA_BASE_IDX 2 2848 2849 2850// addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec 2851// base address: 0x0 2852#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043a 2853#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 2854#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043b 2855#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 2856 2857 2858// addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec 2859// base address: 0x10 2860#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043e 2861#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 2862#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043f 2863#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 2864 2865 2866// addressBlock: dce_dc_hda_azf0inputendpoint2_dispdec 2867// base address: 0x20 2868#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0442 2869#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 2870#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0443 2871#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 2872 2873 2874// addressBlock: dce_dc_hda_azf0inputendpoint3_dispdec 2875// base address: 0x30 2876#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0446 2877#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 2878#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0447 2879#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 2880 2881 2882// addressBlock: dce_dc_hda_azf0inputendpoint4_dispdec 2883// base address: 0x40 2884#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044a 2885#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 2886#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044b 2887#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 2888 2889 2890// addressBlock: dce_dc_hda_azf0inputendpoint5_dispdec 2891// base address: 0x50 2892#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044e 2893#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 2894#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044f 2895#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 2896 2897 2898// addressBlock: dce_dc_hda_azf0inputendpoint6_dispdec 2899// base address: 0x60 2900#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0452 2901#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 2902#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0453 2903#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 2904 2905 2906// addressBlock: dce_dc_hda_azf0inputendpoint7_dispdec 2907// base address: 0x70 2908#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0456 2909#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 2910#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0457 2911#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 2912 2913 2914// addressBlock: dce_dc_dchubbubl_hubbub_sdpif_dispdec 2915// base address: 0x0 2916#define regDCHUBBUB_SDPIF_CFG0 0x046f 2917#define regDCHUBBUB_SDPIF_CFG0_BASE_IDX 2 2918#define regDCHUBBUB_SDPIF_CFG1 0x0470 2919#define regDCHUBBUB_SDPIF_CFG1_BASE_IDX 2 2920#define regDCHUBBUB_SDPIF_CFG2 0x0471 2921#define regDCHUBBUB_SDPIF_CFG2_BASE_IDX 2 2922#define regVM_REQUEST_PHYSICAL 0x0472 2923#define regVM_REQUEST_PHYSICAL_BASE_IDX 2 2924#define regDCHUBBUB_FORCE_IO_STATUS_0 0x0473 2925#define regDCHUBBUB_FORCE_IO_STATUS_0_BASE_IDX 2 2926#define regDCHUBBUB_FORCE_IO_STATUS_1 0x0474 2927#define regDCHUBBUB_FORCE_IO_STATUS_1_BASE_IDX 2 2928#define regDCN_VM_FB_LOCATION_BASE 0x0475 2929#define regDCN_VM_FB_LOCATION_BASE_BASE_IDX 2 2930#define regDCN_VM_FB_LOCATION_TOP 0x0476 2931#define regDCN_VM_FB_LOCATION_TOP_BASE_IDX 2 2932#define regDCN_VM_FB_OFFSET 0x0477 2933#define regDCN_VM_FB_OFFSET_BASE_IDX 2 2934#define regDCN_VM_AGP_BOT 0x0478 2935#define regDCN_VM_AGP_BOT_BASE_IDX 2 2936#define regDCN_VM_AGP_TOP 0x0479 2937#define regDCN_VM_AGP_TOP_BASE_IDX 2 2938#define regDCN_VM_AGP_BASE 0x047a 2939#define regDCN_VM_AGP_BASE_BASE_IDX 2 2940#define regDCN_VM_LOCAL_HBM_ADDRESS_START 0x047b 2941#define regDCN_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 2 2942#define regDCN_VM_LOCAL_HBM_ADDRESS_END 0x047c 2943#define regDCN_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 2 2944#define regDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x047d 2945#define regDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 2 2946#define regDCHUBBUB_SDPIF_MEM_PWR_CTRL 0x0483 2947#define regDCHUBBUB_SDPIF_MEM_PWR_CTRL_BASE_IDX 2 2948#define regDCHUBBUB_SDPIF_MEM_PWR_STATUS 0x0484 2949#define regDCHUBBUB_SDPIF_MEM_PWR_STATUS_BASE_IDX 2 2950 2951 2952// addressBlock: dce_dc_dchubbubl_hubbub_ret_path_dispdec 2953// base address: 0x0 2954#define regDCHUBBUB_RET_PATH_MEM_PWR_CTRL 0x04af 2955#define regDCHUBBUB_RET_PATH_MEM_PWR_CTRL_BASE_IDX 2 2956#define regDCHUBBUB_RET_PATH_MEM_PWR_STATUS 0x04b0 2957#define regDCHUBBUB_RET_PATH_MEM_PWR_STATUS_BASE_IDX 2 2958#define regDCHUBBUB_CRC_CTRL 0x04b1 2959#define regDCHUBBUB_CRC_CTRL_BASE_IDX 2 2960#define regDCHUBBUB_CRC0_VAL_R_G 0x04b2 2961#define regDCHUBBUB_CRC0_VAL_R_G_BASE_IDX 2 2962#define regDCHUBBUB_CRC0_VAL_B_A 0x04b3 2963#define regDCHUBBUB_CRC0_VAL_B_A_BASE_IDX 2 2964#define regDCHUBBUB_CRC1_VAL_R_G 0x04b4 2965#define regDCHUBBUB_CRC1_VAL_R_G_BASE_IDX 2 2966#define regDCHUBBUB_CRC1_VAL_B_A 0x04b5 2967#define regDCHUBBUB_CRC1_VAL_B_A_BASE_IDX 2 2968#define regDCHUBBUB_DCC_STAT_CNTL 0x04b6 2969#define regDCHUBBUB_DCC_STAT_CNTL_BASE_IDX 2 2970#define regDCHUBBUB_DCC_STAT0 0x04b7 2971#define regDCHUBBUB_DCC_STAT0_BASE_IDX 2 2972#define regDCHUBBUB_DCC_STAT1 0x04b8 2973#define regDCHUBBUB_DCC_STAT1_BASE_IDX 2 2974#define regDCHUBBUB_DCC_STAT2 0x04b9 2975#define regDCHUBBUB_DCC_STAT2_BASE_IDX 2 2976#define regDCHUBBUB_COMPBUF_CTRL 0x04ba 2977#define regDCHUBBUB_COMPBUF_CTRL_BASE_IDX 2 2978#define regDCHUBBUB_DET0_CTRL 0x04bb 2979#define regDCHUBBUB_DET0_CTRL_BASE_IDX 2 2980#define regDCHUBBUB_DET1_CTRL 0x04bc 2981#define regDCHUBBUB_DET1_CTRL_BASE_IDX 2 2982#define regDCHUBBUB_DET2_CTRL 0x04bd 2983#define regDCHUBBUB_DET2_CTRL_BASE_IDX 2 2984#define regDCHUBBUB_DET3_CTRL 0x04be 2985#define regDCHUBBUB_DET3_CTRL_BASE_IDX 2 2986#define regDCHUBBUB_MEM_PWR_MODE_CTRL 0x04c0 2987#define regDCHUBBUB_MEM_PWR_MODE_CTRL_BASE_IDX 2 2988#define regCOMPBUF_MEM_PWR_CTRL_1 0x04c1 2989#define regCOMPBUF_MEM_PWR_CTRL_1_BASE_IDX 2 2990#define regCOMPBUF_MEM_PWR_CTRL_2 0x04c2 2991#define regCOMPBUF_MEM_PWR_CTRL_2_BASE_IDX 2 2992#define regDCHUBBUB_MEM_PWR_STATUS 0x04c3 2993#define regDCHUBBUB_MEM_PWR_STATUS_BASE_IDX 2 2994#define regCOMPBUF_RESERVED_SPACE 0x04c4 2995#define regCOMPBUF_RESERVED_SPACE_BASE_IDX 2 2996#define regDCHUBBUB_DEBUG_CTRL_0 0x04c5 2997#define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX 2 2998 2999 3000// addressBlock: dce_dc_dchubbubl_hubbub_dispdec 3001// base address: 0x0 3002#define regDCHUBBUB_ARB_DF_REQ_OUTSTAND 0x04f9 3003#define regDCHUBBUB_ARB_DF_REQ_OUTSTAND_BASE_IDX 2 3004#define regDCHUBBUB_ARB_SAT_LEVEL 0x04fa 3005#define regDCHUBBUB_ARB_SAT_LEVEL_BASE_IDX 2 3006#define regDCHUBBUB_ARB_QOS_FORCE 0x04fb 3007#define regDCHUBBUB_ARB_QOS_FORCE_BASE_IDX 2 3008#define regDCHUBBUB_ARB_DRAM_STATE_CNTL 0x04fc 3009#define regDCHUBBUB_ARB_DRAM_STATE_CNTL_BASE_IDX 2 3010#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A 0x04fd 3011#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_BASE_IDX 2 3012#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A 0x04fe 3013#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A_BASE_IDX 2 3014#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A 0x04ff 3015#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_BASE_IDX 2 3016#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A 0x0500 3017#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A_BASE_IDX 2 3018#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A 0x0501 3019#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_BASE_IDX 2 3020#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A 0x0502 3021#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A_BASE_IDX 2 3022#define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A 0x0503 3023#define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A_BASE_IDX 2 3024#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_A 0x0504 3025#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_A_BASE_IDX 2 3026#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A 0x0505 3027#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A_BASE_IDX 2 3028#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B 0x0506 3029#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_BASE_IDX 2 3030#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B 0x0507 3031#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B_BASE_IDX 2 3032#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B 0x0508 3033#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_BASE_IDX 2 3034#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B 0x0509 3035#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B_BASE_IDX 2 3036#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B 0x050a 3037#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_BASE_IDX 2 3038#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B 0x050b 3039#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B_BASE_IDX 2 3040#define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B 0x050c 3041#define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B_BASE_IDX 2 3042#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_B 0x050d 3043#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_B_BASE_IDX 2 3044#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B 0x050e 3045#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B_BASE_IDX 2 3046#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C 0x050f 3047#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_BASE_IDX 2 3048#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C 0x0510 3049#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C_BASE_IDX 2 3050#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C 0x0511 3051#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_BASE_IDX 2 3052#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C 0x0512 3053#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C_BASE_IDX 2 3054#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C 0x0513 3055#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_BASE_IDX 2 3056#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C 0x0514 3057#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C_BASE_IDX 2 3058#define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C 0x0515 3059#define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C_BASE_IDX 2 3060#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_C 0x0516 3061#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_C_BASE_IDX 2 3062#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C 0x0517 3063#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C_BASE_IDX 2 3064#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D 0x0518 3065#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_BASE_IDX 2 3066#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D 0x0519 3067#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D_BASE_IDX 2 3068#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D 0x051a 3069#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_BASE_IDX 2 3070#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D 0x051b 3071#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D_BASE_IDX 2 3072#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D 0x051c 3073#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_BASE_IDX 2 3074#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D 0x051d 3075#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D_BASE_IDX 2 3076#define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D 0x051e 3077#define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D_BASE_IDX 2 3078#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_D 0x051f 3079#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_D_BASE_IDX 2 3080#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D 0x0520 3081#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D_BASE_IDX 2 3082#define regDCHUBBUB_ARB_HOSTVM_CNTL 0x0521 3083#define regDCHUBBUB_ARB_HOSTVM_CNTL_BASE_IDX 2 3084#define regDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL 0x0522 3085#define regDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL_BASE_IDX 2 3086#define regDCHUBBUB_ARB_TIMEOUT_ENABLE 0x0523 3087#define regDCHUBBUB_ARB_TIMEOUT_ENABLE_BASE_IDX 2 3088#define regDCHUBBUB_GLOBAL_TIMER_CNTL 0x0524 3089#define regDCHUBBUB_GLOBAL_TIMER_CNTL_BASE_IDX 2 3090#define regSURFACE_CHECK0_ADDRESS_LSB 0x0525 3091#define regSURFACE_CHECK0_ADDRESS_LSB_BASE_IDX 2 3092#define regSURFACE_CHECK0_ADDRESS_MSB 0x0526 3093#define regSURFACE_CHECK0_ADDRESS_MSB_BASE_IDX 2 3094#define regSURFACE_CHECK1_ADDRESS_LSB 0x0527 3095#define regSURFACE_CHECK1_ADDRESS_LSB_BASE_IDX 2 3096#define regSURFACE_CHECK1_ADDRESS_MSB 0x0528 3097#define regSURFACE_CHECK1_ADDRESS_MSB_BASE_IDX 2 3098#define regSURFACE_CHECK2_ADDRESS_LSB 0x0529 3099#define regSURFACE_CHECK2_ADDRESS_LSB_BASE_IDX 2 3100#define regSURFACE_CHECK2_ADDRESS_MSB 0x052a 3101#define regSURFACE_CHECK2_ADDRESS_MSB_BASE_IDX 2 3102#define regSURFACE_CHECK3_ADDRESS_LSB 0x052b 3103#define regSURFACE_CHECK3_ADDRESS_LSB_BASE_IDX 2 3104#define regSURFACE_CHECK3_ADDRESS_MSB 0x052c 3105#define regSURFACE_CHECK3_ADDRESS_MSB_BASE_IDX 2 3106#define regVTG0_CONTROL 0x052d 3107#define regVTG0_CONTROL_BASE_IDX 2 3108#define regVTG1_CONTROL 0x052e 3109#define regVTG1_CONTROL_BASE_IDX 2 3110#define regVTG2_CONTROL 0x052f 3111#define regVTG2_CONTROL_BASE_IDX 2 3112#define regVTG3_CONTROL 0x0530 3113#define regVTG3_CONTROL_BASE_IDX 2 3114#define regDCHUBBUB_SOFT_RESET 0x0531 3115#define regDCHUBBUB_SOFT_RESET_BASE_IDX 2 3116#define regDCHUBBUB_CLOCK_CNTL 0x0532 3117#define regDCHUBBUB_CLOCK_CNTL_BASE_IDX 2 3118#define regDCFCLK_CNTL 0x0533 3119#define regDCFCLK_CNTL_BASE_IDX 2 3120#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL 0x0534 3121#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL_BASE_IDX 2 3122#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2 0x0535 3123#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2_BASE_IDX 2 3124#define regDCHUBBUB_VLINE_SNAPSHOT 0x0536 3125#define regDCHUBBUB_VLINE_SNAPSHOT_BASE_IDX 2 3126#define regDCHUBBUB_CTRL_STATUS 0x0537 3127#define regDCHUBBUB_CTRL_STATUS_BASE_IDX 2 3128#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL1 0x053d 3129#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL1_BASE_IDX 2 3130#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL2 0x053e 3131#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL2_BASE_IDX 2 3132#define regDCHUBBUB_TIMEOUT_INTERRUPT_STATUS 0x053f 3133#define regDCHUBBUB_TIMEOUT_INTERRUPT_STATUS_BASE_IDX 2 3134#define regFMON_CTRL 0x0540 3135#define regFMON_CTRL_BASE_IDX 2 3136#define regDCHUBBUB_TEST_DEBUG_INDEX 0x0541 3137#define regDCHUBBUB_TEST_DEBUG_INDEX_BASE_IDX 2 3138#define regDCHUBBUB_TEST_DEBUG_DATA 0x0542 3139#define regDCHUBBUB_TEST_DEBUG_DATA_BASE_IDX 2 3140 3141 3142// addressBlock: dce_dc_dchubbubl_dchubbub_dcperfmon_dc_perfmon_dispdec 3143// base address: 0x1534 3144#define regDC_PERFMON5_PERFCOUNTER_CNTL 0x054d 3145#define regDC_PERFMON5_PERFCOUNTER_CNTL_BASE_IDX 2 3146#define regDC_PERFMON5_PERFCOUNTER_CNTL2 0x054e 3147#define regDC_PERFMON5_PERFCOUNTER_CNTL2_BASE_IDX 2 3148#define regDC_PERFMON5_PERFCOUNTER_STATE 0x054f 3149#define regDC_PERFMON5_PERFCOUNTER_STATE_BASE_IDX 2 3150#define regDC_PERFMON5_PERFMON_CNTL 0x0550 3151#define regDC_PERFMON5_PERFMON_CNTL_BASE_IDX 2 3152#define regDC_PERFMON5_PERFMON_CNTL2 0x0551 3153#define regDC_PERFMON5_PERFMON_CNTL2_BASE_IDX 2 3154#define regDC_PERFMON5_PERFMON_CVALUE_INT_MISC 0x0552 3155#define regDC_PERFMON5_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 3156#define regDC_PERFMON5_PERFMON_CVALUE_LOW 0x0553 3157#define regDC_PERFMON5_PERFMON_CVALUE_LOW_BASE_IDX 2 3158#define regDC_PERFMON5_PERFMON_HI 0x0554 3159#define regDC_PERFMON5_PERFMON_HI_BASE_IDX 2 3160#define regDC_PERFMON5_PERFMON_LOW 0x0555 3161#define regDC_PERFMON5_PERFMON_LOW_BASE_IDX 2 3162 3163 3164// addressBlock: dce_dc_dchubbubl_hubbub_vmrq_if_dispdec 3165// base address: 0x0 3166#define regDCN_VM_CONTEXT0_CNTL 0x0559 3167#define regDCN_VM_CONTEXT0_CNTL_BASE_IDX 2 3168#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x055a 3169#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 3170#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x055b 3171#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 3172#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x055c 3173#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 3174#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x055d 3175#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 3176#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x055e 3177#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 3178#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x055f 3179#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 3180#define regDCN_VM_CONTEXT1_CNTL 0x0560 3181#define regDCN_VM_CONTEXT1_CNTL_BASE_IDX 2 3182#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x0561 3183#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 3184#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x0562 3185#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 3186#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x0563 3187#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 3188#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x0564 3189#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 3190#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x0565 3191#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 3192#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x0566 3193#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 3194#define regDCN_VM_CONTEXT2_CNTL 0x0567 3195#define regDCN_VM_CONTEXT2_CNTL_BASE_IDX 2 3196#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x0568 3197#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 3198#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x0569 3199#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 3200#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x056a 3201#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 3202#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x056b 3203#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 3204#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x056c 3205#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 3206#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x056d 3207#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 3208#define regDCN_VM_CONTEXT3_CNTL 0x056e 3209#define regDCN_VM_CONTEXT3_CNTL_BASE_IDX 2 3210#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x056f 3211#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 3212#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x0570 3213#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 3214#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x0571 3215#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 3216#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x0572 3217#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 3218#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x0573 3219#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 3220#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x0574 3221#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 3222#define regDCN_VM_CONTEXT4_CNTL 0x0575 3223#define regDCN_VM_CONTEXT4_CNTL_BASE_IDX 2 3224#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x0576 3225#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 3226#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x0577 3227#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 3228#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x0578 3229#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 3230#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x0579 3231#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 3232#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x057a 3233#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 3234#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x057b 3235#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 3236#define regDCN_VM_CONTEXT5_CNTL 0x057c 3237#define regDCN_VM_CONTEXT5_CNTL_BASE_IDX 2 3238#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x057d 3239#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 3240#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x057e 3241#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 3242#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x057f 3243#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 3244#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x0580 3245#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 3246#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x0581 3247#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 3248#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x0582 3249#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 3250#define regDCN_VM_CONTEXT6_CNTL 0x0583 3251#define regDCN_VM_CONTEXT6_CNTL_BASE_IDX 2 3252#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x0584 3253#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 3254#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x0585 3255#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 3256#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x0586 3257#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 3258#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x0587 3259#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 3260#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x0588 3261#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 3262#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x0589 3263#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 3264#define regDCN_VM_CONTEXT7_CNTL 0x058a 3265#define regDCN_VM_CONTEXT7_CNTL_BASE_IDX 2 3266#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x058b 3267#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 3268#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x058c 3269#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 3270#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x058d 3271#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 3272#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x058e 3273#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 3274#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x058f 3275#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 3276#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x0590 3277#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 3278#define regDCN_VM_CONTEXT8_CNTL 0x0591 3279#define regDCN_VM_CONTEXT8_CNTL_BASE_IDX 2 3280#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x0592 3281#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 3282#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x0593 3283#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 3284#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x0594 3285#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 3286#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x0595 3287#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 3288#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x0596 3289#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 3290#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x0597 3291#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 3292#define regDCN_VM_CONTEXT9_CNTL 0x0598 3293#define regDCN_VM_CONTEXT9_CNTL_BASE_IDX 2 3294#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x0599 3295#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 3296#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x059a 3297#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 3298#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x059b 3299#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 3300#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x059c 3301#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 3302#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x059d 3303#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 3304#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x059e 3305#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 3306#define regDCN_VM_CONTEXT10_CNTL 0x059f 3307#define regDCN_VM_CONTEXT10_CNTL_BASE_IDX 2 3308#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x05a0 3309#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 3310#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x05a1 3311#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 3312#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x05a2 3313#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 3314#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x05a3 3315#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 3316#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x05a4 3317#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 3318#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x05a5 3319#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 3320#define regDCN_VM_CONTEXT11_CNTL 0x05a6 3321#define regDCN_VM_CONTEXT11_CNTL_BASE_IDX 2 3322#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x05a7 3323#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 3324#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x05a8 3325#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 3326#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x05a9 3327#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 3328#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x05aa 3329#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 3330#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x05ab 3331#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 3332#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x05ac 3333#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 3334#define regDCN_VM_CONTEXT12_CNTL 0x05ad 3335#define regDCN_VM_CONTEXT12_CNTL_BASE_IDX 2 3336#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x05ae 3337#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 3338#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x05af 3339#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 3340#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x05b0 3341#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 3342#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x05b1 3343#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 3344#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x05b2 3345#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 3346#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x05b3 3347#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 3348#define regDCN_VM_CONTEXT13_CNTL 0x05b4 3349#define regDCN_VM_CONTEXT13_CNTL_BASE_IDX 2 3350#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x05b5 3351#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 3352#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x05b6 3353#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 3354#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x05b7 3355#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 3356#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x05b8 3357#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 3358#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x05b9 3359#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 3360#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x05ba 3361#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 3362#define regDCN_VM_CONTEXT14_CNTL 0x05bb 3363#define regDCN_VM_CONTEXT14_CNTL_BASE_IDX 2 3364#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x05bc 3365#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 3366#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x05bd 3367#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 3368#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x05be 3369#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 3370#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x05bf 3371#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 3372#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x05c0 3373#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 3374#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x05c1 3375#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 3376#define regDCN_VM_CONTEXT15_CNTL 0x05c2 3377#define regDCN_VM_CONTEXT15_CNTL_BASE_IDX 2 3378#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x05c3 3379#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 3380#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x05c4 3381#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 3382#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x05c5 3383#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 3384#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x05c6 3385#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 3386#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x05c7 3387#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 3388#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x05c8 3389#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 3390#define regDCN_VM_DEFAULT_ADDR_MSB 0x05c9 3391#define regDCN_VM_DEFAULT_ADDR_MSB_BASE_IDX 2 3392#define regDCN_VM_DEFAULT_ADDR_LSB 0x05ca 3393#define regDCN_VM_DEFAULT_ADDR_LSB_BASE_IDX 2 3394#define regDCN_VM_FAULT_CNTL 0x05cb 3395#define regDCN_VM_FAULT_CNTL_BASE_IDX 2 3396#define regDCN_VM_FAULT_STATUS 0x05cc 3397#define regDCN_VM_FAULT_STATUS_BASE_IDX 2 3398#define regDCN_VM_FAULT_ADDR_MSB 0x05cd 3399#define regDCN_VM_FAULT_ADDR_MSB_BASE_IDX 2 3400#define regDCN_VM_FAULT_ADDR_LSB 0x05ce 3401#define regDCN_VM_FAULT_ADDR_LSB_BASE_IDX 2 3402 3403 3404// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec 3405// base address: 0x0 3406#define regHUBP0_DCSURF_SURFACE_CONFIG 0x05e5 3407#define regHUBP0_DCSURF_SURFACE_CONFIG_BASE_IDX 2 3408#define regHUBP0_DCSURF_ADDR_CONFIG 0x05e6 3409#define regHUBP0_DCSURF_ADDR_CONFIG_BASE_IDX 2 3410#define regHUBP0_DCSURF_TILING_CONFIG 0x05e7 3411#define regHUBP0_DCSURF_TILING_CONFIG_BASE_IDX 2 3412#define regHUBP0_DCSURF_PRI_VIEWPORT_START 0x05e9 3413#define regHUBP0_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 3414#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x05ea 3415#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 3416#define regHUBP0_DCSURF_PRI_VIEWPORT_START_C 0x05eb 3417#define regHUBP0_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 3418#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x05ec 3419#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 3420#define regHUBP0_DCSURF_SEC_VIEWPORT_START 0x05ed 3421#define regHUBP0_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 3422#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION 0x05ee 3423#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 3424#define regHUBP0_DCSURF_SEC_VIEWPORT_START_C 0x05ef 3425#define regHUBP0_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 3426#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x05f0 3427#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 3428#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG 0x05f1 3429#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 3430#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_C 0x05f2 3431#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 3432#define regHUBP0_DCHUBP_CNTL 0x05f3 3433#define regHUBP0_DCHUBP_CNTL_BASE_IDX 2 3434#define regHUBP0_HUBP_CLK_CNTL 0x05f4 3435#define regHUBP0_HUBP_CLK_CNTL_BASE_IDX 2 3436#define regHUBP0_DCHUBP_VMPG_CONFIG 0x05f5 3437#define regHUBP0_DCHUBP_VMPG_CONFIG_BASE_IDX 2 3438#define regHUBP0_HUBPREQ_DEBUG_DB 0x05f6 3439#define regHUBP0_HUBPREQ_DEBUG_DB_BASE_IDX 2 3440#define regHUBP0_HUBPREQ_DEBUG 0x05f7 3441#define regHUBP0_HUBPREQ_DEBUG_BASE_IDX 2 3442#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x05fb 3443#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 3444#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x05fc 3445#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 3446 3447 3448// addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec 3449// base address: 0x0 3450#define regHUBPREQ0_DCSURF_SURFACE_PITCH 0x0607 3451#define regHUBPREQ0_DCSURF_SURFACE_PITCH_BASE_IDX 2 3452#define regHUBPREQ0_DCSURF_SURFACE_PITCH_C 0x0608 3453#define regHUBPREQ0_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 3454#define regHUBPREQ0_VMID_SETTINGS_0 0x0609 3455#define regHUBPREQ0_VMID_SETTINGS_0_BASE_IDX 2 3456#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS 0x060a 3457#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 3458#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x060b 3459#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3460#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x060c 3461#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 3462#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x060d 3463#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3464#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS 0x060e 3465#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 3466#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x060f 3467#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3468#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x0610 3469#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 3470#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x0611 3471#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3472#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x0612 3473#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 3474#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x0613 3475#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3476#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x0614 3477#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 3478#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x0615 3479#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3480#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x0616 3481#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 3482#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x0617 3483#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3484#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x0618 3485#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 3486#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x0619 3487#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3488#define regHUBPREQ0_DCSURF_SURFACE_CONTROL 0x061a 3489#define regHUBPREQ0_DCSURF_SURFACE_CONTROL_BASE_IDX 2 3490#define regHUBPREQ0_DCSURF_FLIP_CONTROL 0x061b 3491#define regHUBPREQ0_DCSURF_FLIP_CONTROL_BASE_IDX 2 3492#define regHUBPREQ0_DCSURF_FLIP_CONTROL2 0x061c 3493#define regHUBPREQ0_DCSURF_FLIP_CONTROL2_BASE_IDX 2 3494#define regHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT 0x0620 3495#define regHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 3496#define regHUBPREQ0_DCSURF_SURFACE_INUSE 0x0621 3497#define regHUBPREQ0_DCSURF_SURFACE_INUSE_BASE_IDX 2 3498#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH 0x0622 3499#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 3500#define regHUBPREQ0_DCSURF_SURFACE_INUSE_C 0x0623 3501#define regHUBPREQ0_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 3502#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C 0x0624 3503#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 3504#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE 0x0625 3505#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 3506#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0626 3507#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 3508#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0627 3509#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 3510#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0628 3511#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 3512#define regHUBPREQ0_DCN_EXPANSION_MODE 0x0629 3513#define regHUBPREQ0_DCN_EXPANSION_MODE_BASE_IDX 2 3514#define regHUBPREQ0_DCN_TTU_QOS_WM 0x062a 3515#define regHUBPREQ0_DCN_TTU_QOS_WM_BASE_IDX 2 3516#define regHUBPREQ0_DCN_GLOBAL_TTU_CNTL 0x062b 3517#define regHUBPREQ0_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 3518#define regHUBPREQ0_DCN_SURF0_TTU_CNTL0 0x062c 3519#define regHUBPREQ0_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 3520#define regHUBPREQ0_DCN_SURF0_TTU_CNTL1 0x062d 3521#define regHUBPREQ0_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 3522#define regHUBPREQ0_DCN_SURF1_TTU_CNTL0 0x062e 3523#define regHUBPREQ0_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 3524#define regHUBPREQ0_DCN_SURF1_TTU_CNTL1 0x062f 3525#define regHUBPREQ0_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 3526#define regHUBPREQ0_DCN_CUR0_TTU_CNTL0 0x0630 3527#define regHUBPREQ0_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 3528#define regHUBPREQ0_DCN_CUR0_TTU_CNTL1 0x0631 3529#define regHUBPREQ0_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 3530#define regHUBPREQ0_DCN_CUR1_TTU_CNTL0 0x0632 3531#define regHUBPREQ0_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 3532#define regHUBPREQ0_DCN_CUR1_TTU_CNTL1 0x0633 3533#define regHUBPREQ0_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 3534#define regHUBPREQ0_DCN_DMDATA_VM_CNTL 0x0634 3535#define regHUBPREQ0_DCN_DMDATA_VM_CNTL_BASE_IDX 2 3536#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x0635 3537#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 3538#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0636 3539#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 3540#define regHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL 0x0643 3541#define regHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 3542#define regHUBPREQ0_BLANK_OFFSET_0 0x0644 3543#define regHUBPREQ0_BLANK_OFFSET_0_BASE_IDX 2 3544#define regHUBPREQ0_BLANK_OFFSET_1 0x0645 3545#define regHUBPREQ0_BLANK_OFFSET_1_BASE_IDX 2 3546#define regHUBPREQ0_DST_DIMENSIONS 0x0646 3547#define regHUBPREQ0_DST_DIMENSIONS_BASE_IDX 2 3548#define regHUBPREQ0_DST_AFTER_SCALER 0x0647 3549#define regHUBPREQ0_DST_AFTER_SCALER_BASE_IDX 2 3550#define regHUBPREQ0_PREFETCH_SETTINGS 0x0648 3551#define regHUBPREQ0_PREFETCH_SETTINGS_BASE_IDX 2 3552#define regHUBPREQ0_PREFETCH_SETTINGS_C 0x0649 3553#define regHUBPREQ0_PREFETCH_SETTINGS_C_BASE_IDX 2 3554#define regHUBPREQ0_VBLANK_PARAMETERS_0 0x064a 3555#define regHUBPREQ0_VBLANK_PARAMETERS_0_BASE_IDX 2 3556#define regHUBPREQ0_VBLANK_PARAMETERS_1 0x064b 3557#define regHUBPREQ0_VBLANK_PARAMETERS_1_BASE_IDX 2 3558#define regHUBPREQ0_VBLANK_PARAMETERS_2 0x064c 3559#define regHUBPREQ0_VBLANK_PARAMETERS_2_BASE_IDX 2 3560#define regHUBPREQ0_VBLANK_PARAMETERS_3 0x064d 3561#define regHUBPREQ0_VBLANK_PARAMETERS_3_BASE_IDX 2 3562#define regHUBPREQ0_VBLANK_PARAMETERS_4 0x064e 3563#define regHUBPREQ0_VBLANK_PARAMETERS_4_BASE_IDX 2 3564#define regHUBPREQ0_FLIP_PARAMETERS_0 0x064f 3565#define regHUBPREQ0_FLIP_PARAMETERS_0_BASE_IDX 2 3566#define regHUBPREQ0_FLIP_PARAMETERS_1 0x0650 3567#define regHUBPREQ0_FLIP_PARAMETERS_1_BASE_IDX 2 3568#define regHUBPREQ0_FLIP_PARAMETERS_2 0x0651 3569#define regHUBPREQ0_FLIP_PARAMETERS_2_BASE_IDX 2 3570#define regHUBPREQ0_NOM_PARAMETERS_0 0x0652 3571#define regHUBPREQ0_NOM_PARAMETERS_0_BASE_IDX 2 3572#define regHUBPREQ0_NOM_PARAMETERS_1 0x0653 3573#define regHUBPREQ0_NOM_PARAMETERS_1_BASE_IDX 2 3574#define regHUBPREQ0_NOM_PARAMETERS_2 0x0654 3575#define regHUBPREQ0_NOM_PARAMETERS_2_BASE_IDX 2 3576#define regHUBPREQ0_NOM_PARAMETERS_3 0x0655 3577#define regHUBPREQ0_NOM_PARAMETERS_3_BASE_IDX 2 3578#define regHUBPREQ0_NOM_PARAMETERS_4 0x0656 3579#define regHUBPREQ0_NOM_PARAMETERS_4_BASE_IDX 2 3580#define regHUBPREQ0_NOM_PARAMETERS_5 0x0657 3581#define regHUBPREQ0_NOM_PARAMETERS_5_BASE_IDX 2 3582#define regHUBPREQ0_NOM_PARAMETERS_6 0x0658 3583#define regHUBPREQ0_NOM_PARAMETERS_6_BASE_IDX 2 3584#define regHUBPREQ0_NOM_PARAMETERS_7 0x0659 3585#define regHUBPREQ0_NOM_PARAMETERS_7_BASE_IDX 2 3586#define regHUBPREQ0_PER_LINE_DELIVERY_PRE 0x065a 3587#define regHUBPREQ0_PER_LINE_DELIVERY_PRE_BASE_IDX 2 3588#define regHUBPREQ0_PER_LINE_DELIVERY 0x065b 3589#define regHUBPREQ0_PER_LINE_DELIVERY_BASE_IDX 2 3590#define regHUBPREQ0_CURSOR_SETTINGS 0x065c 3591#define regHUBPREQ0_CURSOR_SETTINGS_BASE_IDX 2 3592#define regHUBPREQ0_REF_FREQ_TO_PIX_FREQ 0x065d 3593#define regHUBPREQ0_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 3594#define regHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT 0x065e 3595#define regHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 3596#define regHUBPREQ0_HUBPREQ_MEM_PWR_CTRL 0x065f 3597#define regHUBPREQ0_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 3598#define regHUBPREQ0_HUBPREQ_MEM_PWR_STATUS 0x0660 3599#define regHUBPREQ0_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 3600#define regHUBPREQ0_VBLANK_PARAMETERS_5 0x0663 3601#define regHUBPREQ0_VBLANK_PARAMETERS_5_BASE_IDX 2 3602#define regHUBPREQ0_VBLANK_PARAMETERS_6 0x0664 3603#define regHUBPREQ0_VBLANK_PARAMETERS_6_BASE_IDX 2 3604#define regHUBPREQ0_FLIP_PARAMETERS_3 0x0665 3605#define regHUBPREQ0_FLIP_PARAMETERS_3_BASE_IDX 2 3606#define regHUBPREQ0_FLIP_PARAMETERS_4 0x0666 3607#define regHUBPREQ0_FLIP_PARAMETERS_4_BASE_IDX 2 3608#define regHUBPREQ0_FLIP_PARAMETERS_5 0x0667 3609#define regHUBPREQ0_FLIP_PARAMETERS_5_BASE_IDX 2 3610#define regHUBPREQ0_FLIP_PARAMETERS_6 0x0668 3611#define regHUBPREQ0_FLIP_PARAMETERS_6_BASE_IDX 2 3612 3613 3614// addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec 3615// base address: 0x0 3616#define regHUBPRET0_HUBPRET_CONTROL 0x066c 3617#define regHUBPRET0_HUBPRET_CONTROL_BASE_IDX 2 3618#define regHUBPRET0_HUBPRET_MEM_PWR_CTRL 0x066d 3619#define regHUBPRET0_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 3620#define regHUBPRET0_HUBPRET_MEM_PWR_STATUS 0x066e 3621#define regHUBPRET0_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 3622#define regHUBPRET0_HUBPRET_READ_LINE_CTRL0 0x066f 3623#define regHUBPRET0_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 3624#define regHUBPRET0_HUBPRET_READ_LINE_CTRL1 0x0670 3625#define regHUBPRET0_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 3626#define regHUBPRET0_HUBPRET_READ_LINE0 0x0671 3627#define regHUBPRET0_HUBPRET_READ_LINE0_BASE_IDX 2 3628#define regHUBPRET0_HUBPRET_READ_LINE1 0x0672 3629#define regHUBPRET0_HUBPRET_READ_LINE1_BASE_IDX 2 3630#define regHUBPRET0_HUBPRET_INTERRUPT 0x0673 3631#define regHUBPRET0_HUBPRET_INTERRUPT_BASE_IDX 2 3632#define regHUBPRET0_HUBPRET_READ_LINE_VALUE 0x0674 3633#define regHUBPRET0_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 3634#define regHUBPRET0_HUBPRET_READ_LINE_STATUS 0x0675 3635#define regHUBPRET0_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 3636 3637 3638// addressBlock: dce_dc_dcbubp0_dispdec_cursor0_dispdec 3639// base address: 0x0 3640#define regCURSOR0_0_CURSOR_CONTROL 0x0678 3641#define regCURSOR0_0_CURSOR_CONTROL_BASE_IDX 2 3642#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS 0x0679 3643#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 3644#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH 0x067a 3645#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3646#define regCURSOR0_0_CURSOR_SIZE 0x067b 3647#define regCURSOR0_0_CURSOR_SIZE_BASE_IDX 2 3648#define regCURSOR0_0_CURSOR_POSITION 0x067c 3649#define regCURSOR0_0_CURSOR_POSITION_BASE_IDX 2 3650#define regCURSOR0_0_CURSOR_HOT_SPOT 0x067d 3651#define regCURSOR0_0_CURSOR_HOT_SPOT_BASE_IDX 2 3652#define regCURSOR0_0_CURSOR_STEREO_CONTROL 0x067e 3653#define regCURSOR0_0_CURSOR_STEREO_CONTROL_BASE_IDX 2 3654#define regCURSOR0_0_CURSOR_DST_OFFSET 0x067f 3655#define regCURSOR0_0_CURSOR_DST_OFFSET_BASE_IDX 2 3656#define regCURSOR0_0_CURSOR_MEM_PWR_CTRL 0x0680 3657#define regCURSOR0_0_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 3658#define regCURSOR0_0_CURSOR_MEM_PWR_STATUS 0x0681 3659#define regCURSOR0_0_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 3660#define regCURSOR0_0_DMDATA_ADDRESS_HIGH 0x0682 3661#define regCURSOR0_0_DMDATA_ADDRESS_HIGH_BASE_IDX 2 3662#define regCURSOR0_0_DMDATA_ADDRESS_LOW 0x0683 3663#define regCURSOR0_0_DMDATA_ADDRESS_LOW_BASE_IDX 2 3664#define regCURSOR0_0_DMDATA_CNTL 0x0684 3665#define regCURSOR0_0_DMDATA_CNTL_BASE_IDX 2 3666#define regCURSOR0_0_DMDATA_QOS_CNTL 0x0685 3667#define regCURSOR0_0_DMDATA_QOS_CNTL_BASE_IDX 2 3668#define regCURSOR0_0_DMDATA_STATUS 0x0686 3669#define regCURSOR0_0_DMDATA_STATUS_BASE_IDX 2 3670#define regCURSOR0_0_DMDATA_SW_CNTL 0x0687 3671#define regCURSOR0_0_DMDATA_SW_CNTL_BASE_IDX 2 3672#define regCURSOR0_0_DMDATA_SW_DATA 0x0688 3673#define regCURSOR0_0_DMDATA_SW_DATA_BASE_IDX 2 3674 3675 3676// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dcperfmon_dc_perfmon_dispdec 3677// base address: 0x1a74 3678#define regDC_PERFMON6_PERFCOUNTER_CNTL 0x069d 3679#define regDC_PERFMON6_PERFCOUNTER_CNTL_BASE_IDX 2 3680#define regDC_PERFMON6_PERFCOUNTER_CNTL2 0x069e 3681#define regDC_PERFMON6_PERFCOUNTER_CNTL2_BASE_IDX 2 3682#define regDC_PERFMON6_PERFCOUNTER_STATE 0x069f 3683#define regDC_PERFMON6_PERFCOUNTER_STATE_BASE_IDX 2 3684#define regDC_PERFMON6_PERFMON_CNTL 0x06a0 3685#define regDC_PERFMON6_PERFMON_CNTL_BASE_IDX 2 3686#define regDC_PERFMON6_PERFMON_CNTL2 0x06a1 3687#define regDC_PERFMON6_PERFMON_CNTL2_BASE_IDX 2 3688#define regDC_PERFMON6_PERFMON_CVALUE_INT_MISC 0x06a2 3689#define regDC_PERFMON6_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 3690#define regDC_PERFMON6_PERFMON_CVALUE_LOW 0x06a3 3691#define regDC_PERFMON6_PERFMON_CVALUE_LOW_BASE_IDX 2 3692#define regDC_PERFMON6_PERFMON_HI 0x06a4 3693#define regDC_PERFMON6_PERFMON_HI_BASE_IDX 2 3694#define regDC_PERFMON6_PERFMON_LOW 0x06a5 3695#define regDC_PERFMON6_PERFMON_LOW_BASE_IDX 2 3696 3697 3698// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec 3699// base address: 0x370 3700#define regHUBP1_DCSURF_SURFACE_CONFIG 0x06c1 3701#define regHUBP1_DCSURF_SURFACE_CONFIG_BASE_IDX 2 3702#define regHUBP1_DCSURF_ADDR_CONFIG 0x06c2 3703#define regHUBP1_DCSURF_ADDR_CONFIG_BASE_IDX 2 3704#define regHUBP1_DCSURF_TILING_CONFIG 0x06c3 3705#define regHUBP1_DCSURF_TILING_CONFIG_BASE_IDX 2 3706#define regHUBP1_DCSURF_PRI_VIEWPORT_START 0x06c5 3707#define regHUBP1_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 3708#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION 0x06c6 3709#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 3710#define regHUBP1_DCSURF_PRI_VIEWPORT_START_C 0x06c7 3711#define regHUBP1_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 3712#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x06c8 3713#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 3714#define regHUBP1_DCSURF_SEC_VIEWPORT_START 0x06c9 3715#define regHUBP1_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 3716#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION 0x06ca 3717#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 3718#define regHUBP1_DCSURF_SEC_VIEWPORT_START_C 0x06cb 3719#define regHUBP1_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 3720#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x06cc 3721#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 3722#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG 0x06cd 3723#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 3724#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_C 0x06ce 3725#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 3726#define regHUBP1_DCHUBP_CNTL 0x06cf 3727#define regHUBP1_DCHUBP_CNTL_BASE_IDX 2 3728#define regHUBP1_HUBP_CLK_CNTL 0x06d0 3729#define regHUBP1_HUBP_CLK_CNTL_BASE_IDX 2 3730#define regHUBP1_DCHUBP_VMPG_CONFIG 0x06d1 3731#define regHUBP1_DCHUBP_VMPG_CONFIG_BASE_IDX 2 3732#define regHUBP1_HUBPREQ_DEBUG_DB 0x06d2 3733#define regHUBP1_HUBPREQ_DEBUG_DB_BASE_IDX 2 3734#define regHUBP1_HUBPREQ_DEBUG 0x06d3 3735#define regHUBP1_HUBPREQ_DEBUG_BASE_IDX 2 3736#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x06d7 3737#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 3738#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x06d8 3739#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 3740 3741 3742// addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec 3743// base address: 0x370 3744#define regHUBPREQ1_DCSURF_SURFACE_PITCH 0x06e3 3745#define regHUBPREQ1_DCSURF_SURFACE_PITCH_BASE_IDX 2 3746#define regHUBPREQ1_DCSURF_SURFACE_PITCH_C 0x06e4 3747#define regHUBPREQ1_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 3748#define regHUBPREQ1_VMID_SETTINGS_0 0x06e5 3749#define regHUBPREQ1_VMID_SETTINGS_0_BASE_IDX 2 3750#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS 0x06e6 3751#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 3752#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x06e7 3753#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3754#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x06e8 3755#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 3756#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x06e9 3757#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3758#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS 0x06ea 3759#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 3760#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x06eb 3761#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3762#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x06ec 3763#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 3764#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x06ed 3765#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3766#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x06ee 3767#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 3768#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x06ef 3769#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3770#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x06f0 3771#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 3772#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x06f1 3773#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3774#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x06f2 3775#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 3776#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x06f3 3777#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3778#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x06f4 3779#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 3780#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x06f5 3781#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3782#define regHUBPREQ1_DCSURF_SURFACE_CONTROL 0x06f6 3783#define regHUBPREQ1_DCSURF_SURFACE_CONTROL_BASE_IDX 2 3784#define regHUBPREQ1_DCSURF_FLIP_CONTROL 0x06f7 3785#define regHUBPREQ1_DCSURF_FLIP_CONTROL_BASE_IDX 2 3786#define regHUBPREQ1_DCSURF_FLIP_CONTROL2 0x06f8 3787#define regHUBPREQ1_DCSURF_FLIP_CONTROL2_BASE_IDX 2 3788#define regHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT 0x06fc 3789#define regHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 3790#define regHUBPREQ1_DCSURF_SURFACE_INUSE 0x06fd 3791#define regHUBPREQ1_DCSURF_SURFACE_INUSE_BASE_IDX 2 3792#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH 0x06fe 3793#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 3794#define regHUBPREQ1_DCSURF_SURFACE_INUSE_C 0x06ff 3795#define regHUBPREQ1_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 3796#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C 0x0700 3797#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 3798#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE 0x0701 3799#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 3800#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0702 3801#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 3802#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0703 3803#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 3804#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0704 3805#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 3806#define regHUBPREQ1_DCN_EXPANSION_MODE 0x0705 3807#define regHUBPREQ1_DCN_EXPANSION_MODE_BASE_IDX 2 3808#define regHUBPREQ1_DCN_TTU_QOS_WM 0x0706 3809#define regHUBPREQ1_DCN_TTU_QOS_WM_BASE_IDX 2 3810#define regHUBPREQ1_DCN_GLOBAL_TTU_CNTL 0x0707 3811#define regHUBPREQ1_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 3812#define regHUBPREQ1_DCN_SURF0_TTU_CNTL0 0x0708 3813#define regHUBPREQ1_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 3814#define regHUBPREQ1_DCN_SURF0_TTU_CNTL1 0x0709 3815#define regHUBPREQ1_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 3816#define regHUBPREQ1_DCN_SURF1_TTU_CNTL0 0x070a 3817#define regHUBPREQ1_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 3818#define regHUBPREQ1_DCN_SURF1_TTU_CNTL1 0x070b 3819#define regHUBPREQ1_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 3820#define regHUBPREQ1_DCN_CUR0_TTU_CNTL0 0x070c 3821#define regHUBPREQ1_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 3822#define regHUBPREQ1_DCN_CUR0_TTU_CNTL1 0x070d 3823#define regHUBPREQ1_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 3824#define regHUBPREQ1_DCN_CUR1_TTU_CNTL0 0x070e 3825#define regHUBPREQ1_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 3826#define regHUBPREQ1_DCN_CUR1_TTU_CNTL1 0x070f 3827#define regHUBPREQ1_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 3828#define regHUBPREQ1_DCN_DMDATA_VM_CNTL 0x0710 3829#define regHUBPREQ1_DCN_DMDATA_VM_CNTL_BASE_IDX 2 3830#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x0711 3831#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 3832#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0712 3833#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 3834#define regHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL 0x071f 3835#define regHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 3836#define regHUBPREQ1_BLANK_OFFSET_0 0x0720 3837#define regHUBPREQ1_BLANK_OFFSET_0_BASE_IDX 2 3838#define regHUBPREQ1_BLANK_OFFSET_1 0x0721 3839#define regHUBPREQ1_BLANK_OFFSET_1_BASE_IDX 2 3840#define regHUBPREQ1_DST_DIMENSIONS 0x0722 3841#define regHUBPREQ1_DST_DIMENSIONS_BASE_IDX 2 3842#define regHUBPREQ1_DST_AFTER_SCALER 0x0723 3843#define regHUBPREQ1_DST_AFTER_SCALER_BASE_IDX 2 3844#define regHUBPREQ1_PREFETCH_SETTINGS 0x0724 3845#define regHUBPREQ1_PREFETCH_SETTINGS_BASE_IDX 2 3846#define regHUBPREQ1_PREFETCH_SETTINGS_C 0x0725 3847#define regHUBPREQ1_PREFETCH_SETTINGS_C_BASE_IDX 2 3848#define regHUBPREQ1_VBLANK_PARAMETERS_0 0x0726 3849#define regHUBPREQ1_VBLANK_PARAMETERS_0_BASE_IDX 2 3850#define regHUBPREQ1_VBLANK_PARAMETERS_1 0x0727 3851#define regHUBPREQ1_VBLANK_PARAMETERS_1_BASE_IDX 2 3852#define regHUBPREQ1_VBLANK_PARAMETERS_2 0x0728 3853#define regHUBPREQ1_VBLANK_PARAMETERS_2_BASE_IDX 2 3854#define regHUBPREQ1_VBLANK_PARAMETERS_3 0x0729 3855#define regHUBPREQ1_VBLANK_PARAMETERS_3_BASE_IDX 2 3856#define regHUBPREQ1_VBLANK_PARAMETERS_4 0x072a 3857#define regHUBPREQ1_VBLANK_PARAMETERS_4_BASE_IDX 2 3858#define regHUBPREQ1_FLIP_PARAMETERS_0 0x072b 3859#define regHUBPREQ1_FLIP_PARAMETERS_0_BASE_IDX 2 3860#define regHUBPREQ1_FLIP_PARAMETERS_1 0x072c 3861#define regHUBPREQ1_FLIP_PARAMETERS_1_BASE_IDX 2 3862#define regHUBPREQ1_FLIP_PARAMETERS_2 0x072d 3863#define regHUBPREQ1_FLIP_PARAMETERS_2_BASE_IDX 2 3864#define regHUBPREQ1_NOM_PARAMETERS_0 0x072e 3865#define regHUBPREQ1_NOM_PARAMETERS_0_BASE_IDX 2 3866#define regHUBPREQ1_NOM_PARAMETERS_1 0x072f 3867#define regHUBPREQ1_NOM_PARAMETERS_1_BASE_IDX 2 3868#define regHUBPREQ1_NOM_PARAMETERS_2 0x0730 3869#define regHUBPREQ1_NOM_PARAMETERS_2_BASE_IDX 2 3870#define regHUBPREQ1_NOM_PARAMETERS_3 0x0731 3871#define regHUBPREQ1_NOM_PARAMETERS_3_BASE_IDX 2 3872#define regHUBPREQ1_NOM_PARAMETERS_4 0x0732 3873#define regHUBPREQ1_NOM_PARAMETERS_4_BASE_IDX 2 3874#define regHUBPREQ1_NOM_PARAMETERS_5 0x0733 3875#define regHUBPREQ1_NOM_PARAMETERS_5_BASE_IDX 2 3876#define regHUBPREQ1_NOM_PARAMETERS_6 0x0734 3877#define regHUBPREQ1_NOM_PARAMETERS_6_BASE_IDX 2 3878#define regHUBPREQ1_NOM_PARAMETERS_7 0x0735 3879#define regHUBPREQ1_NOM_PARAMETERS_7_BASE_IDX 2 3880#define regHUBPREQ1_PER_LINE_DELIVERY_PRE 0x0736 3881#define regHUBPREQ1_PER_LINE_DELIVERY_PRE_BASE_IDX 2 3882#define regHUBPREQ1_PER_LINE_DELIVERY 0x0737 3883#define regHUBPREQ1_PER_LINE_DELIVERY_BASE_IDX 2 3884#define regHUBPREQ1_CURSOR_SETTINGS 0x0738 3885#define regHUBPREQ1_CURSOR_SETTINGS_BASE_IDX 2 3886#define regHUBPREQ1_REF_FREQ_TO_PIX_FREQ 0x0739 3887#define regHUBPREQ1_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 3888#define regHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT 0x073a 3889#define regHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 3890#define regHUBPREQ1_HUBPREQ_MEM_PWR_CTRL 0x073b 3891#define regHUBPREQ1_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 3892#define regHUBPREQ1_HUBPREQ_MEM_PWR_STATUS 0x073c 3893#define regHUBPREQ1_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 3894#define regHUBPREQ1_VBLANK_PARAMETERS_5 0x073f 3895#define regHUBPREQ1_VBLANK_PARAMETERS_5_BASE_IDX 2 3896#define regHUBPREQ1_VBLANK_PARAMETERS_6 0x0740 3897#define regHUBPREQ1_VBLANK_PARAMETERS_6_BASE_IDX 2 3898#define regHUBPREQ1_FLIP_PARAMETERS_3 0x0741 3899#define regHUBPREQ1_FLIP_PARAMETERS_3_BASE_IDX 2 3900#define regHUBPREQ1_FLIP_PARAMETERS_4 0x0742 3901#define regHUBPREQ1_FLIP_PARAMETERS_4_BASE_IDX 2 3902#define regHUBPREQ1_FLIP_PARAMETERS_5 0x0743 3903#define regHUBPREQ1_FLIP_PARAMETERS_5_BASE_IDX 2 3904#define regHUBPREQ1_FLIP_PARAMETERS_6 0x0744 3905#define regHUBPREQ1_FLIP_PARAMETERS_6_BASE_IDX 2 3906 3907 3908// addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec 3909// base address: 0x370 3910#define regHUBPRET1_HUBPRET_CONTROL 0x0748 3911#define regHUBPRET1_HUBPRET_CONTROL_BASE_IDX 2 3912#define regHUBPRET1_HUBPRET_MEM_PWR_CTRL 0x0749 3913#define regHUBPRET1_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 3914#define regHUBPRET1_HUBPRET_MEM_PWR_STATUS 0x074a 3915#define regHUBPRET1_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 3916#define regHUBPRET1_HUBPRET_READ_LINE_CTRL0 0x074b 3917#define regHUBPRET1_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 3918#define regHUBPRET1_HUBPRET_READ_LINE_CTRL1 0x074c 3919#define regHUBPRET1_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 3920#define regHUBPRET1_HUBPRET_READ_LINE0 0x074d 3921#define regHUBPRET1_HUBPRET_READ_LINE0_BASE_IDX 2 3922#define regHUBPRET1_HUBPRET_READ_LINE1 0x074e 3923#define regHUBPRET1_HUBPRET_READ_LINE1_BASE_IDX 2 3924#define regHUBPRET1_HUBPRET_INTERRUPT 0x074f 3925#define regHUBPRET1_HUBPRET_INTERRUPT_BASE_IDX 2 3926#define regHUBPRET1_HUBPRET_READ_LINE_VALUE 0x0750 3927#define regHUBPRET1_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 3928#define regHUBPRET1_HUBPRET_READ_LINE_STATUS 0x0751 3929#define regHUBPRET1_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 3930 3931 3932// addressBlock: dce_dc_dcbubp1_dispdec_cursor0_dispdec 3933// base address: 0x370 3934#define regCURSOR0_1_CURSOR_CONTROL 0x0754 3935#define regCURSOR0_1_CURSOR_CONTROL_BASE_IDX 2 3936#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS 0x0755 3937#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 3938#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH 0x0756 3939#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3940#define regCURSOR0_1_CURSOR_SIZE 0x0757 3941#define regCURSOR0_1_CURSOR_SIZE_BASE_IDX 2 3942#define regCURSOR0_1_CURSOR_POSITION 0x0758 3943#define regCURSOR0_1_CURSOR_POSITION_BASE_IDX 2 3944#define regCURSOR0_1_CURSOR_HOT_SPOT 0x0759 3945#define regCURSOR0_1_CURSOR_HOT_SPOT_BASE_IDX 2 3946#define regCURSOR0_1_CURSOR_STEREO_CONTROL 0x075a 3947#define regCURSOR0_1_CURSOR_STEREO_CONTROL_BASE_IDX 2 3948#define regCURSOR0_1_CURSOR_DST_OFFSET 0x075b 3949#define regCURSOR0_1_CURSOR_DST_OFFSET_BASE_IDX 2 3950#define regCURSOR0_1_CURSOR_MEM_PWR_CTRL 0x075c 3951#define regCURSOR0_1_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 3952#define regCURSOR0_1_CURSOR_MEM_PWR_STATUS 0x075d 3953#define regCURSOR0_1_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 3954#define regCURSOR0_1_DMDATA_ADDRESS_HIGH 0x075e 3955#define regCURSOR0_1_DMDATA_ADDRESS_HIGH_BASE_IDX 2 3956#define regCURSOR0_1_DMDATA_ADDRESS_LOW 0x075f 3957#define regCURSOR0_1_DMDATA_ADDRESS_LOW_BASE_IDX 2 3958#define regCURSOR0_1_DMDATA_CNTL 0x0760 3959#define regCURSOR0_1_DMDATA_CNTL_BASE_IDX 2 3960#define regCURSOR0_1_DMDATA_QOS_CNTL 0x0761 3961#define regCURSOR0_1_DMDATA_QOS_CNTL_BASE_IDX 2 3962#define regCURSOR0_1_DMDATA_STATUS 0x0762 3963#define regCURSOR0_1_DMDATA_STATUS_BASE_IDX 2 3964#define regCURSOR0_1_DMDATA_SW_CNTL 0x0763 3965#define regCURSOR0_1_DMDATA_SW_CNTL_BASE_IDX 2 3966#define regCURSOR0_1_DMDATA_SW_DATA 0x0764 3967#define regCURSOR0_1_DMDATA_SW_DATA_BASE_IDX 2 3968 3969 3970// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dcperfmon_dc_perfmon_dispdec 3971// base address: 0x1de4 3972#define regDC_PERFMON7_PERFCOUNTER_CNTL 0x0779 3973#define regDC_PERFMON7_PERFCOUNTER_CNTL_BASE_IDX 2 3974#define regDC_PERFMON7_PERFCOUNTER_CNTL2 0x077a 3975#define regDC_PERFMON7_PERFCOUNTER_CNTL2_BASE_IDX 2 3976#define regDC_PERFMON7_PERFCOUNTER_STATE 0x077b 3977#define regDC_PERFMON7_PERFCOUNTER_STATE_BASE_IDX 2 3978#define regDC_PERFMON7_PERFMON_CNTL 0x077c 3979#define regDC_PERFMON7_PERFMON_CNTL_BASE_IDX 2 3980#define regDC_PERFMON7_PERFMON_CNTL2 0x077d 3981#define regDC_PERFMON7_PERFMON_CNTL2_BASE_IDX 2 3982#define regDC_PERFMON7_PERFMON_CVALUE_INT_MISC 0x077e 3983#define regDC_PERFMON7_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 3984#define regDC_PERFMON7_PERFMON_CVALUE_LOW 0x077f 3985#define regDC_PERFMON7_PERFMON_CVALUE_LOW_BASE_IDX 2 3986#define regDC_PERFMON7_PERFMON_HI 0x0780 3987#define regDC_PERFMON7_PERFMON_HI_BASE_IDX 2 3988#define regDC_PERFMON7_PERFMON_LOW 0x0781 3989#define regDC_PERFMON7_PERFMON_LOW_BASE_IDX 2 3990 3991 3992// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dispdec 3993// base address: 0x6e0 3994#define regHUBP2_DCSURF_SURFACE_CONFIG 0x079d 3995#define regHUBP2_DCSURF_SURFACE_CONFIG_BASE_IDX 2 3996#define regHUBP2_DCSURF_ADDR_CONFIG 0x079e 3997#define regHUBP2_DCSURF_ADDR_CONFIG_BASE_IDX 2 3998#define regHUBP2_DCSURF_TILING_CONFIG 0x079f 3999#define regHUBP2_DCSURF_TILING_CONFIG_BASE_IDX 2 4000#define regHUBP2_DCSURF_PRI_VIEWPORT_START 0x07a1 4001#define regHUBP2_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 4002#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION 0x07a2 4003#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 4004#define regHUBP2_DCSURF_PRI_VIEWPORT_START_C 0x07a3 4005#define regHUBP2_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 4006#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x07a4 4007#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 4008#define regHUBP2_DCSURF_SEC_VIEWPORT_START 0x07a5 4009#define regHUBP2_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 4010#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION 0x07a6 4011#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 4012#define regHUBP2_DCSURF_SEC_VIEWPORT_START_C 0x07a7 4013#define regHUBP2_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 4014#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x07a8 4015#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 4016#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG 0x07a9 4017#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 4018#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_C 0x07aa 4019#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 4020#define regHUBP2_DCHUBP_CNTL 0x07ab 4021#define regHUBP2_DCHUBP_CNTL_BASE_IDX 2 4022#define regHUBP2_HUBP_CLK_CNTL 0x07ac 4023#define regHUBP2_HUBP_CLK_CNTL_BASE_IDX 2 4024#define regHUBP2_DCHUBP_VMPG_CONFIG 0x07ad 4025#define regHUBP2_DCHUBP_VMPG_CONFIG_BASE_IDX 2 4026#define regHUBP2_HUBPREQ_DEBUG_DB 0x07ae 4027#define regHUBP2_HUBPREQ_DEBUG_DB_BASE_IDX 2 4028#define regHUBP2_HUBPREQ_DEBUG 0x07af 4029#define regHUBP2_HUBPREQ_DEBUG_BASE_IDX 2 4030#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x07b3 4031#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 4032#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x07b4 4033#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 4034 4035 4036// addressBlock: dce_dc_dcbubp2_dispdec_hubpreq_dispdec 4037// base address: 0x6e0 4038#define regHUBPREQ2_DCSURF_SURFACE_PITCH 0x07bf 4039#define regHUBPREQ2_DCSURF_SURFACE_PITCH_BASE_IDX 2 4040#define regHUBPREQ2_DCSURF_SURFACE_PITCH_C 0x07c0 4041#define regHUBPREQ2_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 4042#define regHUBPREQ2_VMID_SETTINGS_0 0x07c1 4043#define regHUBPREQ2_VMID_SETTINGS_0_BASE_IDX 2 4044#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS 0x07c2 4045#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 4046#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x07c3 4047#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 4048#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x07c4 4049#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 4050#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x07c5 4051#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 4052#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS 0x07c6 4053#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 4054#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x07c7 4055#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 4056#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x07c8 4057#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 4058#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x07c9 4059#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 4060#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x07ca 4061#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 4062#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x07cb 4063#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 4064#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x07cc 4065#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 4066#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x07cd 4067#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 4068#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x07ce 4069#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 4070#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x07cf 4071#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 4072#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x07d0 4073#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 4074#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x07d1 4075#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 4076#define regHUBPREQ2_DCSURF_SURFACE_CONTROL 0x07d2 4077#define regHUBPREQ2_DCSURF_SURFACE_CONTROL_BASE_IDX 2 4078#define regHUBPREQ2_DCSURF_FLIP_CONTROL 0x07d3 4079#define regHUBPREQ2_DCSURF_FLIP_CONTROL_BASE_IDX 2 4080#define regHUBPREQ2_DCSURF_FLIP_CONTROL2 0x07d4 4081#define regHUBPREQ2_DCSURF_FLIP_CONTROL2_BASE_IDX 2 4082#define regHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT 0x07d8 4083#define regHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 4084#define regHUBPREQ2_DCSURF_SURFACE_INUSE 0x07d9 4085#define regHUBPREQ2_DCSURF_SURFACE_INUSE_BASE_IDX 2 4086#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH 0x07da 4087#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 4088#define regHUBPREQ2_DCSURF_SURFACE_INUSE_C 0x07db 4089#define regHUBPREQ2_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 4090#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C 0x07dc 4091#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 4092#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE 0x07dd 4093#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 4094#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x07de 4095#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 4096#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C 0x07df 4097#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 4098#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x07e0 4099#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 4100#define regHUBPREQ2_DCN_EXPANSION_MODE 0x07e1 4101#define regHUBPREQ2_DCN_EXPANSION_MODE_BASE_IDX 2 4102#define regHUBPREQ2_DCN_TTU_QOS_WM 0x07e2 4103#define regHUBPREQ2_DCN_TTU_QOS_WM_BASE_IDX 2 4104#define regHUBPREQ2_DCN_GLOBAL_TTU_CNTL 0x07e3 4105#define regHUBPREQ2_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 4106#define regHUBPREQ2_DCN_SURF0_TTU_CNTL0 0x07e4 4107#define regHUBPREQ2_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 4108#define regHUBPREQ2_DCN_SURF0_TTU_CNTL1 0x07e5 4109#define regHUBPREQ2_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 4110#define regHUBPREQ2_DCN_SURF1_TTU_CNTL0 0x07e6 4111#define regHUBPREQ2_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 4112#define regHUBPREQ2_DCN_SURF1_TTU_CNTL1 0x07e7 4113#define regHUBPREQ2_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 4114#define regHUBPREQ2_DCN_CUR0_TTU_CNTL0 0x07e8 4115#define regHUBPREQ2_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 4116#define regHUBPREQ2_DCN_CUR0_TTU_CNTL1 0x07e9 4117#define regHUBPREQ2_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 4118#define regHUBPREQ2_DCN_CUR1_TTU_CNTL0 0x07ea 4119#define regHUBPREQ2_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 4120#define regHUBPREQ2_DCN_CUR1_TTU_CNTL1 0x07eb 4121#define regHUBPREQ2_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 4122#define regHUBPREQ2_DCN_DMDATA_VM_CNTL 0x07ec 4123#define regHUBPREQ2_DCN_DMDATA_VM_CNTL_BASE_IDX 2 4124#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x07ed 4125#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 4126#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x07ee 4127#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 4128#define regHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL 0x07fb 4129#define regHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 4130#define regHUBPREQ2_BLANK_OFFSET_0 0x07fc 4131#define regHUBPREQ2_BLANK_OFFSET_0_BASE_IDX 2 4132#define regHUBPREQ2_BLANK_OFFSET_1 0x07fd 4133#define regHUBPREQ2_BLANK_OFFSET_1_BASE_IDX 2 4134#define regHUBPREQ2_DST_DIMENSIONS 0x07fe 4135#define regHUBPREQ2_DST_DIMENSIONS_BASE_IDX 2 4136#define regHUBPREQ2_DST_AFTER_SCALER 0x07ff 4137#define regHUBPREQ2_DST_AFTER_SCALER_BASE_IDX 2 4138#define regHUBPREQ2_PREFETCH_SETTINGS 0x0800 4139#define regHUBPREQ2_PREFETCH_SETTINGS_BASE_IDX 2 4140#define regHUBPREQ2_PREFETCH_SETTINGS_C 0x0801 4141#define regHUBPREQ2_PREFETCH_SETTINGS_C_BASE_IDX 2 4142#define regHUBPREQ2_VBLANK_PARAMETERS_0 0x0802 4143#define regHUBPREQ2_VBLANK_PARAMETERS_0_BASE_IDX 2 4144#define regHUBPREQ2_VBLANK_PARAMETERS_1 0x0803 4145#define regHUBPREQ2_VBLANK_PARAMETERS_1_BASE_IDX 2 4146#define regHUBPREQ2_VBLANK_PARAMETERS_2 0x0804 4147#define regHUBPREQ2_VBLANK_PARAMETERS_2_BASE_IDX 2 4148#define regHUBPREQ2_VBLANK_PARAMETERS_3 0x0805 4149#define regHUBPREQ2_VBLANK_PARAMETERS_3_BASE_IDX 2 4150#define regHUBPREQ2_VBLANK_PARAMETERS_4 0x0806 4151#define regHUBPREQ2_VBLANK_PARAMETERS_4_BASE_IDX 2 4152#define regHUBPREQ2_FLIP_PARAMETERS_0 0x0807 4153#define regHUBPREQ2_FLIP_PARAMETERS_0_BASE_IDX 2 4154#define regHUBPREQ2_FLIP_PARAMETERS_1 0x0808 4155#define regHUBPREQ2_FLIP_PARAMETERS_1_BASE_IDX 2 4156#define regHUBPREQ2_FLIP_PARAMETERS_2 0x0809 4157#define regHUBPREQ2_FLIP_PARAMETERS_2_BASE_IDX 2 4158#define regHUBPREQ2_NOM_PARAMETERS_0 0x080a 4159#define regHUBPREQ2_NOM_PARAMETERS_0_BASE_IDX 2 4160#define regHUBPREQ2_NOM_PARAMETERS_1 0x080b 4161#define regHUBPREQ2_NOM_PARAMETERS_1_BASE_IDX 2 4162#define regHUBPREQ2_NOM_PARAMETERS_2 0x080c 4163#define regHUBPREQ2_NOM_PARAMETERS_2_BASE_IDX 2 4164#define regHUBPREQ2_NOM_PARAMETERS_3 0x080d 4165#define regHUBPREQ2_NOM_PARAMETERS_3_BASE_IDX 2 4166#define regHUBPREQ2_NOM_PARAMETERS_4 0x080e 4167#define regHUBPREQ2_NOM_PARAMETERS_4_BASE_IDX 2 4168#define regHUBPREQ2_NOM_PARAMETERS_5 0x080f 4169#define regHUBPREQ2_NOM_PARAMETERS_5_BASE_IDX 2 4170#define regHUBPREQ2_NOM_PARAMETERS_6 0x0810 4171#define regHUBPREQ2_NOM_PARAMETERS_6_BASE_IDX 2 4172#define regHUBPREQ2_NOM_PARAMETERS_7 0x0811 4173#define regHUBPREQ2_NOM_PARAMETERS_7_BASE_IDX 2 4174#define regHUBPREQ2_PER_LINE_DELIVERY_PRE 0x0812 4175#define regHUBPREQ2_PER_LINE_DELIVERY_PRE_BASE_IDX 2 4176#define regHUBPREQ2_PER_LINE_DELIVERY 0x0813 4177#define regHUBPREQ2_PER_LINE_DELIVERY_BASE_IDX 2 4178#define regHUBPREQ2_CURSOR_SETTINGS 0x0814 4179#define regHUBPREQ2_CURSOR_SETTINGS_BASE_IDX 2 4180#define regHUBPREQ2_REF_FREQ_TO_PIX_FREQ 0x0815 4181#define regHUBPREQ2_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 4182#define regHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT 0x0816 4183#define regHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 4184#define regHUBPREQ2_HUBPREQ_MEM_PWR_CTRL 0x0817 4185#define regHUBPREQ2_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 4186#define regHUBPREQ2_HUBPREQ_MEM_PWR_STATUS 0x0818 4187#define regHUBPREQ2_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 4188#define regHUBPREQ2_VBLANK_PARAMETERS_5 0x081b 4189#define regHUBPREQ2_VBLANK_PARAMETERS_5_BASE_IDX 2 4190#define regHUBPREQ2_VBLANK_PARAMETERS_6 0x081c 4191#define regHUBPREQ2_VBLANK_PARAMETERS_6_BASE_IDX 2 4192#define regHUBPREQ2_FLIP_PARAMETERS_3 0x081d 4193#define regHUBPREQ2_FLIP_PARAMETERS_3_BASE_IDX 2 4194#define regHUBPREQ2_FLIP_PARAMETERS_4 0x081e 4195#define regHUBPREQ2_FLIP_PARAMETERS_4_BASE_IDX 2 4196#define regHUBPREQ2_FLIP_PARAMETERS_5 0x081f 4197#define regHUBPREQ2_FLIP_PARAMETERS_5_BASE_IDX 2 4198#define regHUBPREQ2_FLIP_PARAMETERS_6 0x0820 4199#define regHUBPREQ2_FLIP_PARAMETERS_6_BASE_IDX 2 4200 4201 4202// addressBlock: dce_dc_dcbubp2_dispdec_hubpret_dispdec 4203// base address: 0x6e0 4204#define regHUBPRET2_HUBPRET_CONTROL 0x0824 4205#define regHUBPRET2_HUBPRET_CONTROL_BASE_IDX 2 4206#define regHUBPRET2_HUBPRET_MEM_PWR_CTRL 0x0825 4207#define regHUBPRET2_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 4208#define regHUBPRET2_HUBPRET_MEM_PWR_STATUS 0x0826 4209#define regHUBPRET2_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 4210#define regHUBPRET2_HUBPRET_READ_LINE_CTRL0 0x0827 4211#define regHUBPRET2_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 4212#define regHUBPRET2_HUBPRET_READ_LINE_CTRL1 0x0828 4213#define regHUBPRET2_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 4214#define regHUBPRET2_HUBPRET_READ_LINE0 0x0829 4215#define regHUBPRET2_HUBPRET_READ_LINE0_BASE_IDX 2 4216#define regHUBPRET2_HUBPRET_READ_LINE1 0x082a 4217#define regHUBPRET2_HUBPRET_READ_LINE1_BASE_IDX 2 4218#define regHUBPRET2_HUBPRET_INTERRUPT 0x082b 4219#define regHUBPRET2_HUBPRET_INTERRUPT_BASE_IDX 2 4220#define regHUBPRET2_HUBPRET_READ_LINE_VALUE 0x082c 4221#define regHUBPRET2_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 4222#define regHUBPRET2_HUBPRET_READ_LINE_STATUS 0x082d 4223#define regHUBPRET2_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 4224 4225 4226// addressBlock: dce_dc_dcbubp2_dispdec_cursor0_dispdec 4227// base address: 0x6e0 4228#define regCURSOR0_2_CURSOR_CONTROL 0x0830 4229#define regCURSOR0_2_CURSOR_CONTROL_BASE_IDX 2 4230#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS 0x0831 4231#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 4232#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH 0x0832 4233#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 4234#define regCURSOR0_2_CURSOR_SIZE 0x0833 4235#define regCURSOR0_2_CURSOR_SIZE_BASE_IDX 2 4236#define regCURSOR0_2_CURSOR_POSITION 0x0834 4237#define regCURSOR0_2_CURSOR_POSITION_BASE_IDX 2 4238#define regCURSOR0_2_CURSOR_HOT_SPOT 0x0835 4239#define regCURSOR0_2_CURSOR_HOT_SPOT_BASE_IDX 2 4240#define regCURSOR0_2_CURSOR_STEREO_CONTROL 0x0836 4241#define regCURSOR0_2_CURSOR_STEREO_CONTROL_BASE_IDX 2 4242#define regCURSOR0_2_CURSOR_DST_OFFSET 0x0837 4243#define regCURSOR0_2_CURSOR_DST_OFFSET_BASE_IDX 2 4244#define regCURSOR0_2_CURSOR_MEM_PWR_CTRL 0x0838 4245#define regCURSOR0_2_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 4246#define regCURSOR0_2_CURSOR_MEM_PWR_STATUS 0x0839 4247#define regCURSOR0_2_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 4248#define regCURSOR0_2_DMDATA_ADDRESS_HIGH 0x083a 4249#define regCURSOR0_2_DMDATA_ADDRESS_HIGH_BASE_IDX 2 4250#define regCURSOR0_2_DMDATA_ADDRESS_LOW 0x083b 4251#define regCURSOR0_2_DMDATA_ADDRESS_LOW_BASE_IDX 2 4252#define regCURSOR0_2_DMDATA_CNTL 0x083c 4253#define regCURSOR0_2_DMDATA_CNTL_BASE_IDX 2 4254#define regCURSOR0_2_DMDATA_QOS_CNTL 0x083d 4255#define regCURSOR0_2_DMDATA_QOS_CNTL_BASE_IDX 2 4256#define regCURSOR0_2_DMDATA_STATUS 0x083e 4257#define regCURSOR0_2_DMDATA_STATUS_BASE_IDX 2 4258#define regCURSOR0_2_DMDATA_SW_CNTL 0x083f 4259#define regCURSOR0_2_DMDATA_SW_CNTL_BASE_IDX 2 4260#define regCURSOR0_2_DMDATA_SW_DATA 0x0840 4261#define regCURSOR0_2_DMDATA_SW_DATA_BASE_IDX 2 4262 4263 4264// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dcperfmon_dc_perfmon_dispdec 4265// base address: 0x2154 4266#define regDC_PERFMON8_PERFCOUNTER_CNTL 0x0855 4267#define regDC_PERFMON8_PERFCOUNTER_CNTL_BASE_IDX 2 4268#define regDC_PERFMON8_PERFCOUNTER_CNTL2 0x0856 4269#define regDC_PERFMON8_PERFCOUNTER_CNTL2_BASE_IDX 2 4270#define regDC_PERFMON8_PERFCOUNTER_STATE 0x0857 4271#define regDC_PERFMON8_PERFCOUNTER_STATE_BASE_IDX 2 4272#define regDC_PERFMON8_PERFMON_CNTL 0x0858 4273#define regDC_PERFMON8_PERFMON_CNTL_BASE_IDX 2 4274#define regDC_PERFMON8_PERFMON_CNTL2 0x0859 4275#define regDC_PERFMON8_PERFMON_CNTL2_BASE_IDX 2 4276#define regDC_PERFMON8_PERFMON_CVALUE_INT_MISC 0x085a 4277#define regDC_PERFMON8_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 4278#define regDC_PERFMON8_PERFMON_CVALUE_LOW 0x085b 4279#define regDC_PERFMON8_PERFMON_CVALUE_LOW_BASE_IDX 2 4280#define regDC_PERFMON8_PERFMON_HI 0x085c 4281#define regDC_PERFMON8_PERFMON_HI_BASE_IDX 2 4282#define regDC_PERFMON8_PERFMON_LOW 0x085d 4283#define regDC_PERFMON8_PERFMON_LOW_BASE_IDX 2 4284 4285 4286// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dispdec 4287// base address: 0xa50 4288#define regHUBP3_DCSURF_SURFACE_CONFIG 0x0879 4289#define regHUBP3_DCSURF_SURFACE_CONFIG_BASE_IDX 2 4290#define regHUBP3_DCSURF_ADDR_CONFIG 0x087a 4291#define regHUBP3_DCSURF_ADDR_CONFIG_BASE_IDX 2 4292#define regHUBP3_DCSURF_TILING_CONFIG 0x087b 4293#define regHUBP3_DCSURF_TILING_CONFIG_BASE_IDX 2 4294#define regHUBP3_DCSURF_PRI_VIEWPORT_START 0x087d 4295#define regHUBP3_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 4296#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION 0x087e 4297#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 4298#define regHUBP3_DCSURF_PRI_VIEWPORT_START_C 0x087f 4299#define regHUBP3_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 4300#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x0880 4301#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 4302#define regHUBP3_DCSURF_SEC_VIEWPORT_START 0x0881 4303#define regHUBP3_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 4304#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION 0x0882 4305#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 4306#define regHUBP3_DCSURF_SEC_VIEWPORT_START_C 0x0883 4307#define regHUBP3_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 4308#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x0884 4309#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 4310#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG 0x0885 4311#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 4312#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_C 0x0886 4313#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 4314#define regHUBP3_DCHUBP_CNTL 0x0887 4315#define regHUBP3_DCHUBP_CNTL_BASE_IDX 2 4316#define regHUBP3_HUBP_CLK_CNTL 0x0888 4317#define regHUBP3_HUBP_CLK_CNTL_BASE_IDX 2 4318#define regHUBP3_DCHUBP_VMPG_CONFIG 0x0889 4319#define regHUBP3_DCHUBP_VMPG_CONFIG_BASE_IDX 2 4320#define regHUBP3_HUBPREQ_DEBUG_DB 0x088a 4321#define regHUBP3_HUBPREQ_DEBUG_DB_BASE_IDX 2 4322#define regHUBP3_HUBPREQ_DEBUG 0x088b 4323#define regHUBP3_HUBPREQ_DEBUG_BASE_IDX 2 4324#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x088f 4325#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 4326#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x0890 4327#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 4328 4329 4330// addressBlock: dce_dc_dcbubp3_dispdec_hubpreq_dispdec 4331// base address: 0xa50 4332#define regHUBPREQ3_DCSURF_SURFACE_PITCH 0x089b 4333#define regHUBPREQ3_DCSURF_SURFACE_PITCH_BASE_IDX 2 4334#define regHUBPREQ3_DCSURF_SURFACE_PITCH_C 0x089c 4335#define regHUBPREQ3_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 4336#define regHUBPREQ3_VMID_SETTINGS_0 0x089d 4337#define regHUBPREQ3_VMID_SETTINGS_0_BASE_IDX 2 4338#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS 0x089e 4339#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 4340#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x089f 4341#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 4342#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x08a0 4343#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 4344#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x08a1 4345#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 4346#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS 0x08a2 4347#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 4348#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x08a3 4349#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 4350#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x08a4 4351#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 4352#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x08a5 4353#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 4354#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x08a6 4355#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 4356#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x08a7 4357#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 4358#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x08a8 4359#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 4360#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x08a9 4361#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 4362#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x08aa 4363#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 4364#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x08ab 4365#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 4366#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x08ac 4367#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 4368#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x08ad 4369#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 4370#define regHUBPREQ3_DCSURF_SURFACE_CONTROL 0x08ae 4371#define regHUBPREQ3_DCSURF_SURFACE_CONTROL_BASE_IDX 2 4372#define regHUBPREQ3_DCSURF_FLIP_CONTROL 0x08af 4373#define regHUBPREQ3_DCSURF_FLIP_CONTROL_BASE_IDX 2 4374#define regHUBPREQ3_DCSURF_FLIP_CONTROL2 0x08b0 4375#define regHUBPREQ3_DCSURF_FLIP_CONTROL2_BASE_IDX 2 4376#define regHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT 0x08b4 4377#define regHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 4378#define regHUBPREQ3_DCSURF_SURFACE_INUSE 0x08b5 4379#define regHUBPREQ3_DCSURF_SURFACE_INUSE_BASE_IDX 2 4380#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH 0x08b6 4381#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 4382#define regHUBPREQ3_DCSURF_SURFACE_INUSE_C 0x08b7 4383#define regHUBPREQ3_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 4384#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C 0x08b8 4385#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 4386#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE 0x08b9 4387#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 4388#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x08ba 4389#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 4390#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C 0x08bb 4391#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 4392#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x08bc 4393#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 4394#define regHUBPREQ3_DCN_EXPANSION_MODE 0x08bd 4395#define regHUBPREQ3_DCN_EXPANSION_MODE_BASE_IDX 2 4396#define regHUBPREQ3_DCN_TTU_QOS_WM 0x08be 4397#define regHUBPREQ3_DCN_TTU_QOS_WM_BASE_IDX 2 4398#define regHUBPREQ3_DCN_GLOBAL_TTU_CNTL 0x08bf 4399#define regHUBPREQ3_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 4400#define regHUBPREQ3_DCN_SURF0_TTU_CNTL0 0x08c0 4401#define regHUBPREQ3_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 4402#define regHUBPREQ3_DCN_SURF0_TTU_CNTL1 0x08c1 4403#define regHUBPREQ3_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 4404#define regHUBPREQ3_DCN_SURF1_TTU_CNTL0 0x08c2 4405#define regHUBPREQ3_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 4406#define regHUBPREQ3_DCN_SURF1_TTU_CNTL1 0x08c3 4407#define regHUBPREQ3_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 4408#define regHUBPREQ3_DCN_CUR0_TTU_CNTL0 0x08c4 4409#define regHUBPREQ3_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 4410#define regHUBPREQ3_DCN_CUR0_TTU_CNTL1 0x08c5 4411#define regHUBPREQ3_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 4412#define regHUBPREQ3_DCN_CUR1_TTU_CNTL0 0x08c6 4413#define regHUBPREQ3_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 4414#define regHUBPREQ3_DCN_CUR1_TTU_CNTL1 0x08c7 4415#define regHUBPREQ3_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 4416#define regHUBPREQ3_DCN_DMDATA_VM_CNTL 0x08c8 4417#define regHUBPREQ3_DCN_DMDATA_VM_CNTL_BASE_IDX 2 4418#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x08c9 4419#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 4420#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x08ca 4421#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 4422#define regHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL 0x08d7 4423#define regHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 4424#define regHUBPREQ3_BLANK_OFFSET_0 0x08d8 4425#define regHUBPREQ3_BLANK_OFFSET_0_BASE_IDX 2 4426#define regHUBPREQ3_BLANK_OFFSET_1 0x08d9 4427#define regHUBPREQ3_BLANK_OFFSET_1_BASE_IDX 2 4428#define regHUBPREQ3_DST_DIMENSIONS 0x08da 4429#define regHUBPREQ3_DST_DIMENSIONS_BASE_IDX 2 4430#define regHUBPREQ3_DST_AFTER_SCALER 0x08db 4431#define regHUBPREQ3_DST_AFTER_SCALER_BASE_IDX 2 4432#define regHUBPREQ3_PREFETCH_SETTINGS 0x08dc 4433#define regHUBPREQ3_PREFETCH_SETTINGS_BASE_IDX 2 4434#define regHUBPREQ3_PREFETCH_SETTINGS_C 0x08dd 4435#define regHUBPREQ3_PREFETCH_SETTINGS_C_BASE_IDX 2 4436#define regHUBPREQ3_VBLANK_PARAMETERS_0 0x08de 4437#define regHUBPREQ3_VBLANK_PARAMETERS_0_BASE_IDX 2 4438#define regHUBPREQ3_VBLANK_PARAMETERS_1 0x08df 4439#define regHUBPREQ3_VBLANK_PARAMETERS_1_BASE_IDX 2 4440#define regHUBPREQ3_VBLANK_PARAMETERS_2 0x08e0 4441#define regHUBPREQ3_VBLANK_PARAMETERS_2_BASE_IDX 2 4442#define regHUBPREQ3_VBLANK_PARAMETERS_3 0x08e1 4443#define regHUBPREQ3_VBLANK_PARAMETERS_3_BASE_IDX 2 4444#define regHUBPREQ3_VBLANK_PARAMETERS_4 0x08e2 4445#define regHUBPREQ3_VBLANK_PARAMETERS_4_BASE_IDX 2 4446#define regHUBPREQ3_FLIP_PARAMETERS_0 0x08e3 4447#define regHUBPREQ3_FLIP_PARAMETERS_0_BASE_IDX 2 4448#define regHUBPREQ3_FLIP_PARAMETERS_1 0x08e4 4449#define regHUBPREQ3_FLIP_PARAMETERS_1_BASE_IDX 2 4450#define regHUBPREQ3_FLIP_PARAMETERS_2 0x08e5 4451#define regHUBPREQ3_FLIP_PARAMETERS_2_BASE_IDX 2 4452#define regHUBPREQ3_NOM_PARAMETERS_0 0x08e6 4453#define regHUBPREQ3_NOM_PARAMETERS_0_BASE_IDX 2 4454#define regHUBPREQ3_NOM_PARAMETERS_1 0x08e7 4455#define regHUBPREQ3_NOM_PARAMETERS_1_BASE_IDX 2 4456#define regHUBPREQ3_NOM_PARAMETERS_2 0x08e8 4457#define regHUBPREQ3_NOM_PARAMETERS_2_BASE_IDX 2 4458#define regHUBPREQ3_NOM_PARAMETERS_3 0x08e9 4459#define regHUBPREQ3_NOM_PARAMETERS_3_BASE_IDX 2 4460#define regHUBPREQ3_NOM_PARAMETERS_4 0x08ea 4461#define regHUBPREQ3_NOM_PARAMETERS_4_BASE_IDX 2 4462#define regHUBPREQ3_NOM_PARAMETERS_5 0x08eb 4463#define regHUBPREQ3_NOM_PARAMETERS_5_BASE_IDX 2 4464#define regHUBPREQ3_NOM_PARAMETERS_6 0x08ec 4465#define regHUBPREQ3_NOM_PARAMETERS_6_BASE_IDX 2 4466#define regHUBPREQ3_NOM_PARAMETERS_7 0x08ed 4467#define regHUBPREQ3_NOM_PARAMETERS_7_BASE_IDX 2 4468#define regHUBPREQ3_PER_LINE_DELIVERY_PRE 0x08ee 4469#define regHUBPREQ3_PER_LINE_DELIVERY_PRE_BASE_IDX 2 4470#define regHUBPREQ3_PER_LINE_DELIVERY 0x08ef 4471#define regHUBPREQ3_PER_LINE_DELIVERY_BASE_IDX 2 4472#define regHUBPREQ3_CURSOR_SETTINGS 0x08f0 4473#define regHUBPREQ3_CURSOR_SETTINGS_BASE_IDX 2 4474#define regHUBPREQ3_REF_FREQ_TO_PIX_FREQ 0x08f1 4475#define regHUBPREQ3_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 4476#define regHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT 0x08f2 4477#define regHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 4478#define regHUBPREQ3_HUBPREQ_MEM_PWR_CTRL 0x08f3 4479#define regHUBPREQ3_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 4480#define regHUBPREQ3_HUBPREQ_MEM_PWR_STATUS 0x08f4 4481#define regHUBPREQ3_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 4482#define regHUBPREQ3_VBLANK_PARAMETERS_5 0x08f7 4483#define regHUBPREQ3_VBLANK_PARAMETERS_5_BASE_IDX 2 4484#define regHUBPREQ3_VBLANK_PARAMETERS_6 0x08f8 4485#define regHUBPREQ3_VBLANK_PARAMETERS_6_BASE_IDX 2 4486#define regHUBPREQ3_FLIP_PARAMETERS_3 0x08f9 4487#define regHUBPREQ3_FLIP_PARAMETERS_3_BASE_IDX 2 4488#define regHUBPREQ3_FLIP_PARAMETERS_4 0x08fa 4489#define regHUBPREQ3_FLIP_PARAMETERS_4_BASE_IDX 2 4490#define regHUBPREQ3_FLIP_PARAMETERS_5 0x08fb 4491#define regHUBPREQ3_FLIP_PARAMETERS_5_BASE_IDX 2 4492#define regHUBPREQ3_FLIP_PARAMETERS_6 0x08fc 4493#define regHUBPREQ3_FLIP_PARAMETERS_6_BASE_IDX 2 4494 4495 4496// addressBlock: dce_dc_dcbubp3_dispdec_hubpret_dispdec 4497// base address: 0xa50 4498#define regHUBPRET3_HUBPRET_CONTROL 0x0900 4499#define regHUBPRET3_HUBPRET_CONTROL_BASE_IDX 2 4500#define regHUBPRET3_HUBPRET_MEM_PWR_CTRL 0x0901 4501#define regHUBPRET3_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 4502#define regHUBPRET3_HUBPRET_MEM_PWR_STATUS 0x0902 4503#define regHUBPRET3_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 4504#define regHUBPRET3_HUBPRET_READ_LINE_CTRL0 0x0903 4505#define regHUBPRET3_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 4506#define regHUBPRET3_HUBPRET_READ_LINE_CTRL1 0x0904 4507#define regHUBPRET3_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 4508#define regHUBPRET3_HUBPRET_READ_LINE0 0x0905 4509#define regHUBPRET3_HUBPRET_READ_LINE0_BASE_IDX 2 4510#define regHUBPRET3_HUBPRET_READ_LINE1 0x0906 4511#define regHUBPRET3_HUBPRET_READ_LINE1_BASE_IDX 2 4512#define regHUBPRET3_HUBPRET_INTERRUPT 0x0907 4513#define regHUBPRET3_HUBPRET_INTERRUPT_BASE_IDX 2 4514#define regHUBPRET3_HUBPRET_READ_LINE_VALUE 0x0908 4515#define regHUBPRET3_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 4516#define regHUBPRET3_HUBPRET_READ_LINE_STATUS 0x0909 4517#define regHUBPRET3_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 4518 4519 4520// addressBlock: dce_dc_dcbubp3_dispdec_cursor0_dispdec 4521// base address: 0xa50 4522#define regCURSOR0_3_CURSOR_CONTROL 0x090c 4523#define regCURSOR0_3_CURSOR_CONTROL_BASE_IDX 2 4524#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS 0x090d 4525#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 4526#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH 0x090e 4527#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 4528#define regCURSOR0_3_CURSOR_SIZE 0x090f 4529#define regCURSOR0_3_CURSOR_SIZE_BASE_IDX 2 4530#define regCURSOR0_3_CURSOR_POSITION 0x0910 4531#define regCURSOR0_3_CURSOR_POSITION_BASE_IDX 2 4532#define regCURSOR0_3_CURSOR_HOT_SPOT 0x0911 4533#define regCURSOR0_3_CURSOR_HOT_SPOT_BASE_IDX 2 4534#define regCURSOR0_3_CURSOR_STEREO_CONTROL 0x0912 4535#define regCURSOR0_3_CURSOR_STEREO_CONTROL_BASE_IDX 2 4536#define regCURSOR0_3_CURSOR_DST_OFFSET 0x0913 4537#define regCURSOR0_3_CURSOR_DST_OFFSET_BASE_IDX 2 4538#define regCURSOR0_3_CURSOR_MEM_PWR_CTRL 0x0914 4539#define regCURSOR0_3_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 4540#define regCURSOR0_3_CURSOR_MEM_PWR_STATUS 0x0915 4541#define regCURSOR0_3_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 4542#define regCURSOR0_3_DMDATA_ADDRESS_HIGH 0x0916 4543#define regCURSOR0_3_DMDATA_ADDRESS_HIGH_BASE_IDX 2 4544#define regCURSOR0_3_DMDATA_ADDRESS_LOW 0x0917 4545#define regCURSOR0_3_DMDATA_ADDRESS_LOW_BASE_IDX 2 4546#define regCURSOR0_3_DMDATA_CNTL 0x0918 4547#define regCURSOR0_3_DMDATA_CNTL_BASE_IDX 2 4548#define regCURSOR0_3_DMDATA_QOS_CNTL 0x0919 4549#define regCURSOR0_3_DMDATA_QOS_CNTL_BASE_IDX 2 4550#define regCURSOR0_3_DMDATA_STATUS 0x091a 4551#define regCURSOR0_3_DMDATA_STATUS_BASE_IDX 2 4552#define regCURSOR0_3_DMDATA_SW_CNTL 0x091b 4553#define regCURSOR0_3_DMDATA_SW_CNTL_BASE_IDX 2 4554#define regCURSOR0_3_DMDATA_SW_DATA 0x091c 4555#define regCURSOR0_3_DMDATA_SW_DATA_BASE_IDX 2 4556 4557 4558// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dcperfmon_dc_perfmon_dispdec 4559// base address: 0x24c4 4560#define regDC_PERFMON9_PERFCOUNTER_CNTL 0x0931 4561#define regDC_PERFMON9_PERFCOUNTER_CNTL_BASE_IDX 2 4562#define regDC_PERFMON9_PERFCOUNTER_CNTL2 0x0932 4563#define regDC_PERFMON9_PERFCOUNTER_CNTL2_BASE_IDX 2 4564#define regDC_PERFMON9_PERFCOUNTER_STATE 0x0933 4565#define regDC_PERFMON9_PERFCOUNTER_STATE_BASE_IDX 2 4566#define regDC_PERFMON9_PERFMON_CNTL 0x0934 4567#define regDC_PERFMON9_PERFMON_CNTL_BASE_IDX 2 4568#define regDC_PERFMON9_PERFMON_CNTL2 0x0935 4569#define regDC_PERFMON9_PERFMON_CNTL2_BASE_IDX 2 4570#define regDC_PERFMON9_PERFMON_CVALUE_INT_MISC 0x0936 4571#define regDC_PERFMON9_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 4572#define regDC_PERFMON9_PERFMON_CVALUE_LOW 0x0937 4573#define regDC_PERFMON9_PERFMON_CVALUE_LOW_BASE_IDX 2 4574#define regDC_PERFMON9_PERFMON_HI 0x0938 4575#define regDC_PERFMON9_PERFMON_HI_BASE_IDX 2 4576#define regDC_PERFMON9_PERFMON_LOW 0x0939 4577#define regDC_PERFMON9_PERFMON_LOW_BASE_IDX 2 4578 4579 4580// addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec 4581// base address: 0x0 4582#define regDPP_TOP0_DPP_CONTROL 0x0cc5 4583#define regDPP_TOP0_DPP_CONTROL_BASE_IDX 2 4584#define regDPP_TOP0_DPP_SOFT_RESET 0x0cc6 4585#define regDPP_TOP0_DPP_SOFT_RESET_BASE_IDX 2 4586#define regDPP_TOP0_DPP_CRC_VAL_R_G 0x0cc7 4587#define regDPP_TOP0_DPP_CRC_VAL_R_G_BASE_IDX 2 4588#define regDPP_TOP0_DPP_CRC_VAL_B_A 0x0cc8 4589#define regDPP_TOP0_DPP_CRC_VAL_B_A_BASE_IDX 2 4590#define regDPP_TOP0_DPP_CRC_CTRL 0x0cc9 4591#define regDPP_TOP0_DPP_CRC_CTRL_BASE_IDX 2 4592#define regDPP_TOP0_HOST_READ_CONTROL 0x0cca 4593#define regDPP_TOP0_HOST_READ_CONTROL_BASE_IDX 2 4594 4595 4596// addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec 4597// base address: 0x0 4598#define regCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT 0x0ccf 4599#define regCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 4600#define regCNVC_CFG0_FORMAT_CONTROL 0x0cd0 4601#define regCNVC_CFG0_FORMAT_CONTROL_BASE_IDX 2 4602#define regCNVC_CFG0_FCNV_FP_BIAS_R 0x0cd1 4603#define regCNVC_CFG0_FCNV_FP_BIAS_R_BASE_IDX 2 4604#define regCNVC_CFG0_FCNV_FP_BIAS_G 0x0cd2 4605#define regCNVC_CFG0_FCNV_FP_BIAS_G_BASE_IDX 2 4606#define regCNVC_CFG0_FCNV_FP_BIAS_B 0x0cd3 4607#define regCNVC_CFG0_FCNV_FP_BIAS_B_BASE_IDX 2 4608#define regCNVC_CFG0_FCNV_FP_SCALE_R 0x0cd4 4609#define regCNVC_CFG0_FCNV_FP_SCALE_R_BASE_IDX 2 4610#define regCNVC_CFG0_FCNV_FP_SCALE_G 0x0cd5 4611#define regCNVC_CFG0_FCNV_FP_SCALE_G_BASE_IDX 2 4612#define regCNVC_CFG0_FCNV_FP_SCALE_B 0x0cd6 4613#define regCNVC_CFG0_FCNV_FP_SCALE_B_BASE_IDX 2 4614#define regCNVC_CFG0_COLOR_KEYER_CONTROL 0x0cd7 4615#define regCNVC_CFG0_COLOR_KEYER_CONTROL_BASE_IDX 2 4616#define regCNVC_CFG0_COLOR_KEYER_ALPHA 0x0cd8 4617#define regCNVC_CFG0_COLOR_KEYER_ALPHA_BASE_IDX 2 4618#define regCNVC_CFG0_COLOR_KEYER_RED 0x0cd9 4619#define regCNVC_CFG0_COLOR_KEYER_RED_BASE_IDX 2 4620#define regCNVC_CFG0_COLOR_KEYER_GREEN 0x0cda 4621#define regCNVC_CFG0_COLOR_KEYER_GREEN_BASE_IDX 2 4622#define regCNVC_CFG0_COLOR_KEYER_BLUE 0x0cdb 4623#define regCNVC_CFG0_COLOR_KEYER_BLUE_BASE_IDX 2 4624#define regCNVC_CFG0_ALPHA_2BIT_LUT 0x0cdd 4625#define regCNVC_CFG0_ALPHA_2BIT_LUT_BASE_IDX 2 4626#define regCNVC_CFG0_PRE_DEALPHA 0x0cde 4627#define regCNVC_CFG0_PRE_DEALPHA_BASE_IDX 2 4628#define regCNVC_CFG0_PRE_CSC_MODE 0x0cdf 4629#define regCNVC_CFG0_PRE_CSC_MODE_BASE_IDX 2 4630#define regCNVC_CFG0_PRE_CSC_C11_C12 0x0ce0 4631#define regCNVC_CFG0_PRE_CSC_C11_C12_BASE_IDX 2 4632#define regCNVC_CFG0_PRE_CSC_C13_C14 0x0ce1 4633#define regCNVC_CFG0_PRE_CSC_C13_C14_BASE_IDX 2 4634#define regCNVC_CFG0_PRE_CSC_C21_C22 0x0ce2 4635#define regCNVC_CFG0_PRE_CSC_C21_C22_BASE_IDX 2 4636#define regCNVC_CFG0_PRE_CSC_C23_C24 0x0ce3 4637#define regCNVC_CFG0_PRE_CSC_C23_C24_BASE_IDX 2 4638#define regCNVC_CFG0_PRE_CSC_C31_C32 0x0ce4 4639#define regCNVC_CFG0_PRE_CSC_C31_C32_BASE_IDX 2 4640#define regCNVC_CFG0_PRE_CSC_C33_C34 0x0ce5 4641#define regCNVC_CFG0_PRE_CSC_C33_C34_BASE_IDX 2 4642#define regCNVC_CFG0_PRE_CSC_B_C11_C12 0x0ce6 4643#define regCNVC_CFG0_PRE_CSC_B_C11_C12_BASE_IDX 2 4644#define regCNVC_CFG0_PRE_CSC_B_C13_C14 0x0ce7 4645#define regCNVC_CFG0_PRE_CSC_B_C13_C14_BASE_IDX 2 4646#define regCNVC_CFG0_PRE_CSC_B_C21_C22 0x0ce8 4647#define regCNVC_CFG0_PRE_CSC_B_C21_C22_BASE_IDX 2 4648#define regCNVC_CFG0_PRE_CSC_B_C23_C24 0x0ce9 4649#define regCNVC_CFG0_PRE_CSC_B_C23_C24_BASE_IDX 2 4650#define regCNVC_CFG0_PRE_CSC_B_C31_C32 0x0cea 4651#define regCNVC_CFG0_PRE_CSC_B_C31_C32_BASE_IDX 2 4652#define regCNVC_CFG0_PRE_CSC_B_C33_C34 0x0ceb 4653#define regCNVC_CFG0_PRE_CSC_B_C33_C34_BASE_IDX 2 4654#define regCNVC_CFG0_CNVC_COEF_FORMAT 0x0cec 4655#define regCNVC_CFG0_CNVC_COEF_FORMAT_BASE_IDX 2 4656#define regCNVC_CFG0_PRE_DEGAM 0x0ced 4657#define regCNVC_CFG0_PRE_DEGAM_BASE_IDX 2 4658#define regCNVC_CFG0_PRE_REALPHA 0x0cee 4659#define regCNVC_CFG0_PRE_REALPHA_BASE_IDX 2 4660 4661 4662// addressBlock: dce_dc_dpp0_dispdec_cnvc_cur_dispdec 4663// base address: 0x0 4664#define regCNVC_CUR0_CURSOR0_CONTROL 0x0cf1 4665#define regCNVC_CUR0_CURSOR0_CONTROL_BASE_IDX 2 4666#define regCNVC_CUR0_CURSOR0_COLOR0 0x0cf2 4667#define regCNVC_CUR0_CURSOR0_COLOR0_BASE_IDX 2 4668#define regCNVC_CUR0_CURSOR0_COLOR1 0x0cf3 4669#define regCNVC_CUR0_CURSOR0_COLOR1_BASE_IDX 2 4670#define regCNVC_CUR0_CURSOR0_FP_SCALE_BIAS 0x0cf4 4671#define regCNVC_CUR0_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 4672 4673 4674// addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec 4675// base address: 0x0 4676#define regDSCL0_SCL_COEF_RAM_TAP_SELECT 0x0cf9 4677#define regDSCL0_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 4678#define regDSCL0_SCL_COEF_RAM_TAP_DATA 0x0cfa 4679#define regDSCL0_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 4680#define regDSCL0_SCL_MODE 0x0cfb 4681#define regDSCL0_SCL_MODE_BASE_IDX 2 4682#define regDSCL0_SCL_TAP_CONTROL 0x0cfc 4683#define regDSCL0_SCL_TAP_CONTROL_BASE_IDX 2 4684#define regDSCL0_DSCL_CONTROL 0x0cfd 4685#define regDSCL0_DSCL_CONTROL_BASE_IDX 2 4686#define regDSCL0_DSCL_2TAP_CONTROL 0x0cfe 4687#define regDSCL0_DSCL_2TAP_CONTROL_BASE_IDX 2 4688#define regDSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x0cff 4689#define regDSCL0_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 4690#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x0d00 4691#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 4692#define regDSCL0_SCL_HORZ_FILTER_INIT 0x0d01 4693#define regDSCL0_SCL_HORZ_FILTER_INIT_BASE_IDX 2 4694#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0d02 4695#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 4696#define regDSCL0_SCL_HORZ_FILTER_INIT_C 0x0d03 4697#define regDSCL0_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 4698#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x0d04 4699#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 4700#define regDSCL0_SCL_VERT_FILTER_INIT 0x0d05 4701#define regDSCL0_SCL_VERT_FILTER_INIT_BASE_IDX 2 4702#define regDSCL0_SCL_VERT_FILTER_INIT_BOT 0x0d06 4703#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 4704#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C 0x0d07 4705#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 4706#define regDSCL0_SCL_VERT_FILTER_INIT_C 0x0d08 4707#define regDSCL0_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 4708#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_C 0x0d09 4709#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 4710#define regDSCL0_SCL_BLACK_COLOR 0x0d0a 4711#define regDSCL0_SCL_BLACK_COLOR_BASE_IDX 2 4712#define regDSCL0_DSCL_UPDATE 0x0d0b 4713#define regDSCL0_DSCL_UPDATE_BASE_IDX 2 4714#define regDSCL0_DSCL_AUTOCAL 0x0d0c 4715#define regDSCL0_DSCL_AUTOCAL_BASE_IDX 2 4716#define regDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0d0d 4717#define regDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 4718#define regDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0d0e 4719#define regDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 4720#define regDSCL0_OTG_H_BLANK 0x0d0f 4721#define regDSCL0_OTG_H_BLANK_BASE_IDX 2 4722#define regDSCL0_OTG_V_BLANK 0x0d10 4723#define regDSCL0_OTG_V_BLANK_BASE_IDX 2 4724#define regDSCL0_RECOUT_START 0x0d11 4725#define regDSCL0_RECOUT_START_BASE_IDX 2 4726#define regDSCL0_RECOUT_SIZE 0x0d12 4727#define regDSCL0_RECOUT_SIZE_BASE_IDX 2 4728#define regDSCL0_MPC_SIZE 0x0d13 4729#define regDSCL0_MPC_SIZE_BASE_IDX 2 4730#define regDSCL0_LB_DATA_FORMAT 0x0d14 4731#define regDSCL0_LB_DATA_FORMAT_BASE_IDX 2 4732#define regDSCL0_LB_MEMORY_CTRL 0x0d15 4733#define regDSCL0_LB_MEMORY_CTRL_BASE_IDX 2 4734#define regDSCL0_LB_V_COUNTER 0x0d16 4735#define regDSCL0_LB_V_COUNTER_BASE_IDX 2 4736#define regDSCL0_DSCL_MEM_PWR_CTRL 0x0d17 4737#define regDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX 2 4738#define regDSCL0_DSCL_MEM_PWR_STATUS 0x0d18 4739#define regDSCL0_DSCL_MEM_PWR_STATUS_BASE_IDX 2 4740#define regDSCL0_OBUF_CONTROL 0x0d19 4741#define regDSCL0_OBUF_CONTROL_BASE_IDX 2 4742#define regDSCL0_OBUF_MEM_PWR_CTRL 0x0d1a 4743#define regDSCL0_OBUF_MEM_PWR_CTRL_BASE_IDX 2 4744 4745 4746// addressBlock: dce_dc_dpp0_dispdec_cm_dispdec 4747// base address: 0x0 4748#define regCM0_CM_CONTROL 0x0d20 4749#define regCM0_CM_CONTROL_BASE_IDX 2 4750#define regCM0_CM_POST_CSC_CONTROL 0x0d21 4751#define regCM0_CM_POST_CSC_CONTROL_BASE_IDX 2 4752#define regCM0_CM_POST_CSC_C11_C12 0x0d22 4753#define regCM0_CM_POST_CSC_C11_C12_BASE_IDX 2 4754#define regCM0_CM_POST_CSC_C13_C14 0x0d23 4755#define regCM0_CM_POST_CSC_C13_C14_BASE_IDX 2 4756#define regCM0_CM_POST_CSC_C21_C22 0x0d24 4757#define regCM0_CM_POST_CSC_C21_C22_BASE_IDX 2 4758#define regCM0_CM_POST_CSC_C23_C24 0x0d25 4759#define regCM0_CM_POST_CSC_C23_C24_BASE_IDX 2 4760#define regCM0_CM_POST_CSC_C31_C32 0x0d26 4761#define regCM0_CM_POST_CSC_C31_C32_BASE_IDX 2 4762#define regCM0_CM_POST_CSC_C33_C34 0x0d27 4763#define regCM0_CM_POST_CSC_C33_C34_BASE_IDX 2 4764#define regCM0_CM_POST_CSC_B_C11_C12 0x0d28 4765#define regCM0_CM_POST_CSC_B_C11_C12_BASE_IDX 2 4766#define regCM0_CM_POST_CSC_B_C13_C14 0x0d29 4767#define regCM0_CM_POST_CSC_B_C13_C14_BASE_IDX 2 4768#define regCM0_CM_POST_CSC_B_C21_C22 0x0d2a 4769#define regCM0_CM_POST_CSC_B_C21_C22_BASE_IDX 2 4770#define regCM0_CM_POST_CSC_B_C23_C24 0x0d2b 4771#define regCM0_CM_POST_CSC_B_C23_C24_BASE_IDX 2 4772#define regCM0_CM_POST_CSC_B_C31_C32 0x0d2c 4773#define regCM0_CM_POST_CSC_B_C31_C32_BASE_IDX 2 4774#define regCM0_CM_POST_CSC_B_C33_C34 0x0d2d 4775#define regCM0_CM_POST_CSC_B_C33_C34_BASE_IDX 2 4776#define regCM0_CM_GAMUT_REMAP_CONTROL 0x0d2e 4777#define regCM0_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 4778#define regCM0_CM_GAMUT_REMAP_C11_C12 0x0d2f 4779#define regCM0_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 4780#define regCM0_CM_GAMUT_REMAP_C13_C14 0x0d30 4781#define regCM0_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 4782#define regCM0_CM_GAMUT_REMAP_C21_C22 0x0d31 4783#define regCM0_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 4784#define regCM0_CM_GAMUT_REMAP_C23_C24 0x0d32 4785#define regCM0_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 4786#define regCM0_CM_GAMUT_REMAP_C31_C32 0x0d33 4787#define regCM0_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 4788#define regCM0_CM_GAMUT_REMAP_C33_C34 0x0d34 4789#define regCM0_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 4790#define regCM0_CM_GAMUT_REMAP_B_C11_C12 0x0d35 4791#define regCM0_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 4792#define regCM0_CM_GAMUT_REMAP_B_C13_C14 0x0d36 4793#define regCM0_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 4794#define regCM0_CM_GAMUT_REMAP_B_C21_C22 0x0d37 4795#define regCM0_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 4796#define regCM0_CM_GAMUT_REMAP_B_C23_C24 0x0d38 4797#define regCM0_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 4798#define regCM0_CM_GAMUT_REMAP_B_C31_C32 0x0d39 4799#define regCM0_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 4800#define regCM0_CM_GAMUT_REMAP_B_C33_C34 0x0d3a 4801#define regCM0_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 4802#define regCM0_CM_BIAS_CR_R 0x0d3b 4803#define regCM0_CM_BIAS_CR_R_BASE_IDX 2 4804#define regCM0_CM_BIAS_Y_G_CB_B 0x0d3c 4805#define regCM0_CM_BIAS_Y_G_CB_B_BASE_IDX 2 4806#define regCM0_CM_GAMCOR_CONTROL 0x0d3d 4807#define regCM0_CM_GAMCOR_CONTROL_BASE_IDX 2 4808#define regCM0_CM_GAMCOR_LUT_INDEX 0x0d3e 4809#define regCM0_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 4810#define regCM0_CM_GAMCOR_LUT_DATA 0x0d3f 4811#define regCM0_CM_GAMCOR_LUT_DATA_BASE_IDX 2 4812#define regCM0_CM_GAMCOR_LUT_CONTROL 0x0d40 4813#define regCM0_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 4814#define regCM0_CM_GAMCOR_RAMA_START_CNTL_B 0x0d41 4815#define regCM0_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 4816#define regCM0_CM_GAMCOR_RAMA_START_CNTL_G 0x0d42 4817#define regCM0_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 4818#define regCM0_CM_GAMCOR_RAMA_START_CNTL_R 0x0d43 4819#define regCM0_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 4820#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x0d44 4821#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 4822#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x0d45 4823#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 4824#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x0d46 4825#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 4826#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x0d47 4827#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 4828#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x0d48 4829#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 4830#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x0d49 4831#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 4832#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_B 0x0d4a 4833#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 4834#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_B 0x0d4b 4835#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 4836#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_G 0x0d4c 4837#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 4838#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_G 0x0d4d 4839#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 4840#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_R 0x0d4e 4841#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 4842#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_R 0x0d4f 4843#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 4844#define regCM0_CM_GAMCOR_RAMA_OFFSET_B 0x0d50 4845#define regCM0_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 4846#define regCM0_CM_GAMCOR_RAMA_OFFSET_G 0x0d51 4847#define regCM0_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 4848#define regCM0_CM_GAMCOR_RAMA_OFFSET_R 0x0d52 4849#define regCM0_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 4850#define regCM0_CM_GAMCOR_RAMA_REGION_0_1 0x0d53 4851#define regCM0_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 4852#define regCM0_CM_GAMCOR_RAMA_REGION_2_3 0x0d54 4853#define regCM0_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 4854#define regCM0_CM_GAMCOR_RAMA_REGION_4_5 0x0d55 4855#define regCM0_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 4856#define regCM0_CM_GAMCOR_RAMA_REGION_6_7 0x0d56 4857#define regCM0_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 4858#define regCM0_CM_GAMCOR_RAMA_REGION_8_9 0x0d57 4859#define regCM0_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 4860#define regCM0_CM_GAMCOR_RAMA_REGION_10_11 0x0d58 4861#define regCM0_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 4862#define regCM0_CM_GAMCOR_RAMA_REGION_12_13 0x0d59 4863#define regCM0_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 4864#define regCM0_CM_GAMCOR_RAMA_REGION_14_15 0x0d5a 4865#define regCM0_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 4866#define regCM0_CM_GAMCOR_RAMA_REGION_16_17 0x0d5b 4867#define regCM0_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 4868#define regCM0_CM_GAMCOR_RAMA_REGION_18_19 0x0d5c 4869#define regCM0_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 4870#define regCM0_CM_GAMCOR_RAMA_REGION_20_21 0x0d5d 4871#define regCM0_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 4872#define regCM0_CM_GAMCOR_RAMA_REGION_22_23 0x0d5e 4873#define regCM0_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 4874#define regCM0_CM_GAMCOR_RAMA_REGION_24_25 0x0d5f 4875#define regCM0_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 4876#define regCM0_CM_GAMCOR_RAMA_REGION_26_27 0x0d60 4877#define regCM0_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 4878#define regCM0_CM_GAMCOR_RAMA_REGION_28_29 0x0d61 4879#define regCM0_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 4880#define regCM0_CM_GAMCOR_RAMA_REGION_30_31 0x0d62 4881#define regCM0_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 4882#define regCM0_CM_GAMCOR_RAMA_REGION_32_33 0x0d63 4883#define regCM0_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 4884#define regCM0_CM_GAMCOR_RAMB_START_CNTL_B 0x0d64 4885#define regCM0_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 4886#define regCM0_CM_GAMCOR_RAMB_START_CNTL_G 0x0d65 4887#define regCM0_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 4888#define regCM0_CM_GAMCOR_RAMB_START_CNTL_R 0x0d66 4889#define regCM0_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 4890#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x0d67 4891#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 4892#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x0d68 4893#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 4894#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x0d69 4895#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 4896#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x0d6a 4897#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 4898#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x0d6b 4899#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 4900#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x0d6c 4901#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 4902#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_B 0x0d6d 4903#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 4904#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_B 0x0d6e 4905#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 4906#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_G 0x0d6f 4907#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 4908#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_G 0x0d70 4909#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 4910#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_R 0x0d71 4911#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 4912#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_R 0x0d72 4913#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 4914#define regCM0_CM_GAMCOR_RAMB_OFFSET_B 0x0d73 4915#define regCM0_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 4916#define regCM0_CM_GAMCOR_RAMB_OFFSET_G 0x0d74 4917#define regCM0_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 4918#define regCM0_CM_GAMCOR_RAMB_OFFSET_R 0x0d75 4919#define regCM0_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 4920#define regCM0_CM_GAMCOR_RAMB_REGION_0_1 0x0d76 4921#define regCM0_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 4922#define regCM0_CM_GAMCOR_RAMB_REGION_2_3 0x0d77 4923#define regCM0_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 4924#define regCM0_CM_GAMCOR_RAMB_REGION_4_5 0x0d78 4925#define regCM0_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 4926#define regCM0_CM_GAMCOR_RAMB_REGION_6_7 0x0d79 4927#define regCM0_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 4928#define regCM0_CM_GAMCOR_RAMB_REGION_8_9 0x0d7a 4929#define regCM0_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 4930#define regCM0_CM_GAMCOR_RAMB_REGION_10_11 0x0d7b 4931#define regCM0_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 4932#define regCM0_CM_GAMCOR_RAMB_REGION_12_13 0x0d7c 4933#define regCM0_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 4934#define regCM0_CM_GAMCOR_RAMB_REGION_14_15 0x0d7d 4935#define regCM0_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 4936#define regCM0_CM_GAMCOR_RAMB_REGION_16_17 0x0d7e 4937#define regCM0_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 4938#define regCM0_CM_GAMCOR_RAMB_REGION_18_19 0x0d7f 4939#define regCM0_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 4940#define regCM0_CM_GAMCOR_RAMB_REGION_20_21 0x0d80 4941#define regCM0_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 4942#define regCM0_CM_GAMCOR_RAMB_REGION_22_23 0x0d81 4943#define regCM0_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 4944#define regCM0_CM_GAMCOR_RAMB_REGION_24_25 0x0d82 4945#define regCM0_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 4946#define regCM0_CM_GAMCOR_RAMB_REGION_26_27 0x0d83 4947#define regCM0_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 4948#define regCM0_CM_GAMCOR_RAMB_REGION_28_29 0x0d84 4949#define regCM0_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 4950#define regCM0_CM_GAMCOR_RAMB_REGION_30_31 0x0d85 4951#define regCM0_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 4952#define regCM0_CM_GAMCOR_RAMB_REGION_32_33 0x0d86 4953#define regCM0_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 4954#define regCM0_CM_BLNDGAM_CONTROL 0x0d87 4955#define regCM0_CM_BLNDGAM_CONTROL_BASE_IDX 2 4956#define regCM0_CM_BLNDGAM_LUT_INDEX 0x0d88 4957#define regCM0_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2 4958#define regCM0_CM_BLNDGAM_LUT_DATA 0x0d89 4959#define regCM0_CM_BLNDGAM_LUT_DATA_BASE_IDX 2 4960#define regCM0_CM_BLNDGAM_LUT_CONTROL 0x0d8a 4961#define regCM0_CM_BLNDGAM_LUT_CONTROL_BASE_IDX 2 4962#define regCM0_CM_BLNDGAM_RAMA_START_CNTL_B 0x0d8b 4963#define regCM0_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2 4964#define regCM0_CM_BLNDGAM_RAMA_START_CNTL_G 0x0d8c 4965#define regCM0_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2 4966#define regCM0_CM_BLNDGAM_RAMA_START_CNTL_R 0x0d8d 4967#define regCM0_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2 4968#define regCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B 0x0d8e 4969#define regCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 4970#define regCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G 0x0d8f 4971#define regCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 4972#define regCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R 0x0d90 4973#define regCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 4974#define regCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_B 0x0d91 4975#define regCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2 4976#define regCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_G 0x0d92 4977#define regCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2 4978#define regCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_R 0x0d93 4979#define regCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2 4980#define regCM0_CM_BLNDGAM_RAMA_END_CNTL1_B 0x0d94 4981#define regCM0_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2 4982#define regCM0_CM_BLNDGAM_RAMA_END_CNTL2_B 0x0d95 4983#define regCM0_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2 4984#define regCM0_CM_BLNDGAM_RAMA_END_CNTL1_G 0x0d96 4985#define regCM0_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2 4986#define regCM0_CM_BLNDGAM_RAMA_END_CNTL2_G 0x0d97 4987#define regCM0_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2 4988#define regCM0_CM_BLNDGAM_RAMA_END_CNTL1_R 0x0d98 4989#define regCM0_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2 4990#define regCM0_CM_BLNDGAM_RAMA_END_CNTL2_R 0x0d99 4991#define regCM0_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2 4992#define regCM0_CM_BLNDGAM_RAMA_OFFSET_B 0x0d9a 4993#define regCM0_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX 2 4994#define regCM0_CM_BLNDGAM_RAMA_OFFSET_G 0x0d9b 4995#define regCM0_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX 2 4996#define regCM0_CM_BLNDGAM_RAMA_OFFSET_R 0x0d9c 4997#define regCM0_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX 2 4998#define regCM0_CM_BLNDGAM_RAMA_REGION_0_1 0x0d9d 4999#define regCM0_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2 5000#define regCM0_CM_BLNDGAM_RAMA_REGION_2_3 0x0d9e 5001#define regCM0_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2 5002#define regCM0_CM_BLNDGAM_RAMA_REGION_4_5 0x0d9f 5003#define regCM0_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2 5004#define regCM0_CM_BLNDGAM_RAMA_REGION_6_7 0x0da0 5005#define regCM0_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2 5006#define regCM0_CM_BLNDGAM_RAMA_REGION_8_9 0x0da1 5007#define regCM0_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2 5008#define regCM0_CM_BLNDGAM_RAMA_REGION_10_11 0x0da2 5009#define regCM0_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2 5010#define regCM0_CM_BLNDGAM_RAMA_REGION_12_13 0x0da3 5011#define regCM0_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2 5012#define regCM0_CM_BLNDGAM_RAMA_REGION_14_15 0x0da4 5013#define regCM0_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2 5014#define regCM0_CM_BLNDGAM_RAMA_REGION_16_17 0x0da5 5015#define regCM0_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2 5016#define regCM0_CM_BLNDGAM_RAMA_REGION_18_19 0x0da6 5017#define regCM0_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2 5018#define regCM0_CM_BLNDGAM_RAMA_REGION_20_21 0x0da7 5019#define regCM0_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2 5020#define regCM0_CM_BLNDGAM_RAMA_REGION_22_23 0x0da8 5021#define regCM0_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2 5022#define regCM0_CM_BLNDGAM_RAMA_REGION_24_25 0x0da9 5023#define regCM0_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2 5024#define regCM0_CM_BLNDGAM_RAMA_REGION_26_27 0x0daa 5025#define regCM0_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2 5026#define regCM0_CM_BLNDGAM_RAMA_REGION_28_29 0x0dab 5027#define regCM0_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2 5028#define regCM0_CM_BLNDGAM_RAMA_REGION_30_31 0x0dac 5029#define regCM0_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2 5030#define regCM0_CM_BLNDGAM_RAMA_REGION_32_33 0x0dad 5031#define regCM0_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2 5032#define regCM0_CM_BLNDGAM_RAMB_START_CNTL_B 0x0dae 5033#define regCM0_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2 5034#define regCM0_CM_BLNDGAM_RAMB_START_CNTL_G 0x0daf 5035#define regCM0_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2 5036#define regCM0_CM_BLNDGAM_RAMB_START_CNTL_R 0x0db0 5037#define regCM0_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2 5038#define regCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B 0x0db1 5039#define regCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 5040#define regCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G 0x0db2 5041#define regCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 5042#define regCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R 0x0db3 5043#define regCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 5044#define regCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_B 0x0db4 5045#define regCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2 5046#define regCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_G 0x0db5 5047#define regCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2 5048#define regCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_R 0x0db6 5049#define regCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2 5050#define regCM0_CM_BLNDGAM_RAMB_END_CNTL1_B 0x0db7 5051#define regCM0_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2 5052#define regCM0_CM_BLNDGAM_RAMB_END_CNTL2_B 0x0db8 5053#define regCM0_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2 5054#define regCM0_CM_BLNDGAM_RAMB_END_CNTL1_G 0x0db9 5055#define regCM0_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2 5056#define regCM0_CM_BLNDGAM_RAMB_END_CNTL2_G 0x0dba 5057#define regCM0_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2 5058#define regCM0_CM_BLNDGAM_RAMB_END_CNTL1_R 0x0dbb 5059#define regCM0_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2 5060#define regCM0_CM_BLNDGAM_RAMB_END_CNTL2_R 0x0dbc 5061#define regCM0_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2 5062#define regCM0_CM_BLNDGAM_RAMB_OFFSET_B 0x0dbd 5063#define regCM0_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX 2 5064#define regCM0_CM_BLNDGAM_RAMB_OFFSET_G 0x0dbe 5065#define regCM0_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX 2 5066#define regCM0_CM_BLNDGAM_RAMB_OFFSET_R 0x0dbf 5067#define regCM0_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX 2 5068#define regCM0_CM_BLNDGAM_RAMB_REGION_0_1 0x0dc0 5069#define regCM0_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2 5070#define regCM0_CM_BLNDGAM_RAMB_REGION_2_3 0x0dc1 5071#define regCM0_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2 5072#define regCM0_CM_BLNDGAM_RAMB_REGION_4_5 0x0dc2 5073#define regCM0_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2 5074#define regCM0_CM_BLNDGAM_RAMB_REGION_6_7 0x0dc3 5075#define regCM0_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2 5076#define regCM0_CM_BLNDGAM_RAMB_REGION_8_9 0x0dc4 5077#define regCM0_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2 5078#define regCM0_CM_BLNDGAM_RAMB_REGION_10_11 0x0dc5 5079#define regCM0_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2 5080#define regCM0_CM_BLNDGAM_RAMB_REGION_12_13 0x0dc6 5081#define regCM0_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2 5082#define regCM0_CM_BLNDGAM_RAMB_REGION_14_15 0x0dc7 5083#define regCM0_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2 5084#define regCM0_CM_BLNDGAM_RAMB_REGION_16_17 0x0dc8 5085#define regCM0_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2 5086#define regCM0_CM_BLNDGAM_RAMB_REGION_18_19 0x0dc9 5087#define regCM0_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2 5088#define regCM0_CM_BLNDGAM_RAMB_REGION_20_21 0x0dca 5089#define regCM0_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2 5090#define regCM0_CM_BLNDGAM_RAMB_REGION_22_23 0x0dcb 5091#define regCM0_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2 5092#define regCM0_CM_BLNDGAM_RAMB_REGION_24_25 0x0dcc 5093#define regCM0_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2 5094#define regCM0_CM_BLNDGAM_RAMB_REGION_26_27 0x0dcd 5095#define regCM0_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2 5096#define regCM0_CM_BLNDGAM_RAMB_REGION_28_29 0x0dce 5097#define regCM0_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2 5098#define regCM0_CM_BLNDGAM_RAMB_REGION_30_31 0x0dcf 5099#define regCM0_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2 5100#define regCM0_CM_BLNDGAM_RAMB_REGION_32_33 0x0dd0 5101#define regCM0_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2 5102#define regCM0_CM_HDR_MULT_COEF 0x0dd1 5103#define regCM0_CM_HDR_MULT_COEF_BASE_IDX 2 5104#define regCM0_CM_MEM_PWR_CTRL 0x0dd2 5105#define regCM0_CM_MEM_PWR_CTRL_BASE_IDX 2 5106#define regCM0_CM_MEM_PWR_STATUS 0x0dd3 5107#define regCM0_CM_MEM_PWR_STATUS_BASE_IDX 2 5108#define regCM0_CM_DEALPHA 0x0dd5 5109#define regCM0_CM_DEALPHA_BASE_IDX 2 5110#define regCM0_CM_COEF_FORMAT 0x0dd6 5111#define regCM0_CM_COEF_FORMAT_BASE_IDX 2 5112#define regCM0_CM_SHAPER_CONTROL 0x0dd7 5113#define regCM0_CM_SHAPER_CONTROL_BASE_IDX 2 5114#define regCM0_CM_SHAPER_OFFSET_R 0x0dd8 5115#define regCM0_CM_SHAPER_OFFSET_R_BASE_IDX 2 5116#define regCM0_CM_SHAPER_OFFSET_G 0x0dd9 5117#define regCM0_CM_SHAPER_OFFSET_G_BASE_IDX 2 5118#define regCM0_CM_SHAPER_OFFSET_B 0x0dda 5119#define regCM0_CM_SHAPER_OFFSET_B_BASE_IDX 2 5120#define regCM0_CM_SHAPER_SCALE_R 0x0ddb 5121#define regCM0_CM_SHAPER_SCALE_R_BASE_IDX 2 5122#define regCM0_CM_SHAPER_SCALE_G_B 0x0ddc 5123#define regCM0_CM_SHAPER_SCALE_G_B_BASE_IDX 2 5124#define regCM0_CM_SHAPER_LUT_INDEX 0x0ddd 5125#define regCM0_CM_SHAPER_LUT_INDEX_BASE_IDX 2 5126#define regCM0_CM_SHAPER_LUT_DATA 0x0dde 5127#define regCM0_CM_SHAPER_LUT_DATA_BASE_IDX 2 5128#define regCM0_CM_SHAPER_LUT_WRITE_EN_MASK 0x0ddf 5129#define regCM0_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2 5130#define regCM0_CM_SHAPER_RAMA_START_CNTL_B 0x0de0 5131#define regCM0_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2 5132#define regCM0_CM_SHAPER_RAMA_START_CNTL_G 0x0de1 5133#define regCM0_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2 5134#define regCM0_CM_SHAPER_RAMA_START_CNTL_R 0x0de2 5135#define regCM0_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2 5136#define regCM0_CM_SHAPER_RAMA_END_CNTL_B 0x0de3 5137#define regCM0_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2 5138#define regCM0_CM_SHAPER_RAMA_END_CNTL_G 0x0de4 5139#define regCM0_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2 5140#define regCM0_CM_SHAPER_RAMA_END_CNTL_R 0x0de5 5141#define regCM0_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2 5142#define regCM0_CM_SHAPER_RAMA_REGION_0_1 0x0de6 5143#define regCM0_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2 5144#define regCM0_CM_SHAPER_RAMA_REGION_2_3 0x0de7 5145#define regCM0_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2 5146#define regCM0_CM_SHAPER_RAMA_REGION_4_5 0x0de8 5147#define regCM0_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2 5148#define regCM0_CM_SHAPER_RAMA_REGION_6_7 0x0de9 5149#define regCM0_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2 5150#define regCM0_CM_SHAPER_RAMA_REGION_8_9 0x0dea 5151#define regCM0_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2 5152#define regCM0_CM_SHAPER_RAMA_REGION_10_11 0x0deb 5153#define regCM0_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2 5154#define regCM0_CM_SHAPER_RAMA_REGION_12_13 0x0dec 5155#define regCM0_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2 5156#define regCM0_CM_SHAPER_RAMA_REGION_14_15 0x0ded 5157#define regCM0_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2 5158#define regCM0_CM_SHAPER_RAMA_REGION_16_17 0x0dee 5159#define regCM0_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2 5160#define regCM0_CM_SHAPER_RAMA_REGION_18_19 0x0def 5161#define regCM0_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2 5162#define regCM0_CM_SHAPER_RAMA_REGION_20_21 0x0df0 5163#define regCM0_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2 5164#define regCM0_CM_SHAPER_RAMA_REGION_22_23 0x0df1 5165#define regCM0_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2 5166#define regCM0_CM_SHAPER_RAMA_REGION_24_25 0x0df2 5167#define regCM0_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2 5168#define regCM0_CM_SHAPER_RAMA_REGION_26_27 0x0df3 5169#define regCM0_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2 5170#define regCM0_CM_SHAPER_RAMA_REGION_28_29 0x0df4 5171#define regCM0_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2 5172#define regCM0_CM_SHAPER_RAMA_REGION_30_31 0x0df5 5173#define regCM0_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2 5174#define regCM0_CM_SHAPER_RAMA_REGION_32_33 0x0df6 5175#define regCM0_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2 5176#define regCM0_CM_SHAPER_RAMB_START_CNTL_B 0x0df7 5177#define regCM0_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2 5178#define regCM0_CM_SHAPER_RAMB_START_CNTL_G 0x0df8 5179#define regCM0_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2 5180#define regCM0_CM_SHAPER_RAMB_START_CNTL_R 0x0df9 5181#define regCM0_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2 5182#define regCM0_CM_SHAPER_RAMB_END_CNTL_B 0x0dfa 5183#define regCM0_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2 5184#define regCM0_CM_SHAPER_RAMB_END_CNTL_G 0x0dfb 5185#define regCM0_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2 5186#define regCM0_CM_SHAPER_RAMB_END_CNTL_R 0x0dfc 5187#define regCM0_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2 5188#define regCM0_CM_SHAPER_RAMB_REGION_0_1 0x0dfd 5189#define regCM0_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2 5190#define regCM0_CM_SHAPER_RAMB_REGION_2_3 0x0dfe 5191#define regCM0_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2 5192#define regCM0_CM_SHAPER_RAMB_REGION_4_5 0x0dff 5193#define regCM0_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2 5194#define regCM0_CM_SHAPER_RAMB_REGION_6_7 0x0e00 5195#define regCM0_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2 5196#define regCM0_CM_SHAPER_RAMB_REGION_8_9 0x0e01 5197#define regCM0_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2 5198#define regCM0_CM_SHAPER_RAMB_REGION_10_11 0x0e02 5199#define regCM0_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2 5200#define regCM0_CM_SHAPER_RAMB_REGION_12_13 0x0e03 5201#define regCM0_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2 5202#define regCM0_CM_SHAPER_RAMB_REGION_14_15 0x0e04 5203#define regCM0_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2 5204#define regCM0_CM_SHAPER_RAMB_REGION_16_17 0x0e05 5205#define regCM0_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2 5206#define regCM0_CM_SHAPER_RAMB_REGION_18_19 0x0e06 5207#define regCM0_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2 5208#define regCM0_CM_SHAPER_RAMB_REGION_20_21 0x0e07 5209#define regCM0_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2 5210#define regCM0_CM_SHAPER_RAMB_REGION_22_23 0x0e08 5211#define regCM0_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2 5212#define regCM0_CM_SHAPER_RAMB_REGION_24_25 0x0e09 5213#define regCM0_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2 5214#define regCM0_CM_SHAPER_RAMB_REGION_26_27 0x0e0a 5215#define regCM0_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2 5216#define regCM0_CM_SHAPER_RAMB_REGION_28_29 0x0e0b 5217#define regCM0_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2 5218#define regCM0_CM_SHAPER_RAMB_REGION_30_31 0x0e0c 5219#define regCM0_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2 5220#define regCM0_CM_SHAPER_RAMB_REGION_32_33 0x0e0d 5221#define regCM0_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2 5222#define regCM0_CM_MEM_PWR_CTRL2 0x0e0e 5223#define regCM0_CM_MEM_PWR_CTRL2_BASE_IDX 2 5224#define regCM0_CM_MEM_PWR_STATUS2 0x0e0f 5225#define regCM0_CM_MEM_PWR_STATUS2_BASE_IDX 2 5226#define regCM0_CM_3DLUT_MODE 0x0e10 5227#define regCM0_CM_3DLUT_MODE_BASE_IDX 2 5228#define regCM0_CM_3DLUT_INDEX 0x0e11 5229#define regCM0_CM_3DLUT_INDEX_BASE_IDX 2 5230#define regCM0_CM_3DLUT_DATA 0x0e12 5231#define regCM0_CM_3DLUT_DATA_BASE_IDX 2 5232#define regCM0_CM_3DLUT_DATA_30BIT 0x0e13 5233#define regCM0_CM_3DLUT_DATA_30BIT_BASE_IDX 2 5234#define regCM0_CM_3DLUT_READ_WRITE_CONTROL 0x0e14 5235#define regCM0_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2 5236#define regCM0_CM_3DLUT_OUT_NORM_FACTOR 0x0e15 5237#define regCM0_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2 5238#define regCM0_CM_3DLUT_OUT_OFFSET_R 0x0e16 5239#define regCM0_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2 5240#define regCM0_CM_3DLUT_OUT_OFFSET_G 0x0e17 5241#define regCM0_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2 5242#define regCM0_CM_3DLUT_OUT_OFFSET_B 0x0e18 5243#define regCM0_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2 5244#define regCM0_CM_TEST_DEBUG_INDEX 0x0e19 5245#define regCM0_CM_TEST_DEBUG_INDEX_BASE_IDX 2 5246#define regCM0_CM_TEST_DEBUG_DATA 0x0e1a 5247#define regCM0_CM_TEST_DEBUG_DATA_BASE_IDX 2 5248 5249 5250// addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec 5251// base address: 0x3890 5252#define regDC_PERFMON10_PERFCOUNTER_CNTL 0x0e24 5253#define regDC_PERFMON10_PERFCOUNTER_CNTL_BASE_IDX 2 5254#define regDC_PERFMON10_PERFCOUNTER_CNTL2 0x0e25 5255#define regDC_PERFMON10_PERFCOUNTER_CNTL2_BASE_IDX 2 5256#define regDC_PERFMON10_PERFCOUNTER_STATE 0x0e26 5257#define regDC_PERFMON10_PERFCOUNTER_STATE_BASE_IDX 2 5258#define regDC_PERFMON10_PERFMON_CNTL 0x0e27 5259#define regDC_PERFMON10_PERFMON_CNTL_BASE_IDX 2 5260#define regDC_PERFMON10_PERFMON_CNTL2 0x0e28 5261#define regDC_PERFMON10_PERFMON_CNTL2_BASE_IDX 2 5262#define regDC_PERFMON10_PERFMON_CVALUE_INT_MISC 0x0e29 5263#define regDC_PERFMON10_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 5264#define regDC_PERFMON10_PERFMON_CVALUE_LOW 0x0e2a 5265#define regDC_PERFMON10_PERFMON_CVALUE_LOW_BASE_IDX 2 5266#define regDC_PERFMON10_PERFMON_HI 0x0e2b 5267#define regDC_PERFMON10_PERFMON_HI_BASE_IDX 2 5268#define regDC_PERFMON10_PERFMON_LOW 0x0e2c 5269#define regDC_PERFMON10_PERFMON_LOW_BASE_IDX 2 5270 5271 5272// addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec 5273// base address: 0x5ac 5274#define regDPP_TOP1_DPP_CONTROL 0x0e30 5275#define regDPP_TOP1_DPP_CONTROL_BASE_IDX 2 5276#define regDPP_TOP1_DPP_SOFT_RESET 0x0e31 5277#define regDPP_TOP1_DPP_SOFT_RESET_BASE_IDX 2 5278#define regDPP_TOP1_DPP_CRC_VAL_R_G 0x0e32 5279#define regDPP_TOP1_DPP_CRC_VAL_R_G_BASE_IDX 2 5280#define regDPP_TOP1_DPP_CRC_VAL_B_A 0x0e33 5281#define regDPP_TOP1_DPP_CRC_VAL_B_A_BASE_IDX 2 5282#define regDPP_TOP1_DPP_CRC_CTRL 0x0e34 5283#define regDPP_TOP1_DPP_CRC_CTRL_BASE_IDX 2 5284#define regDPP_TOP1_HOST_READ_CONTROL 0x0e35 5285#define regDPP_TOP1_HOST_READ_CONTROL_BASE_IDX 2 5286 5287 5288// addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec 5289// base address: 0x5ac 5290#define regCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT 0x0e3a 5291#define regCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 5292#define regCNVC_CFG1_FORMAT_CONTROL 0x0e3b 5293#define regCNVC_CFG1_FORMAT_CONTROL_BASE_IDX 2 5294#define regCNVC_CFG1_FCNV_FP_BIAS_R 0x0e3c 5295#define regCNVC_CFG1_FCNV_FP_BIAS_R_BASE_IDX 2 5296#define regCNVC_CFG1_FCNV_FP_BIAS_G 0x0e3d 5297#define regCNVC_CFG1_FCNV_FP_BIAS_G_BASE_IDX 2 5298#define regCNVC_CFG1_FCNV_FP_BIAS_B 0x0e3e 5299#define regCNVC_CFG1_FCNV_FP_BIAS_B_BASE_IDX 2 5300#define regCNVC_CFG1_FCNV_FP_SCALE_R 0x0e3f 5301#define regCNVC_CFG1_FCNV_FP_SCALE_R_BASE_IDX 2 5302#define regCNVC_CFG1_FCNV_FP_SCALE_G 0x0e40 5303#define regCNVC_CFG1_FCNV_FP_SCALE_G_BASE_IDX 2 5304#define regCNVC_CFG1_FCNV_FP_SCALE_B 0x0e41 5305#define regCNVC_CFG1_FCNV_FP_SCALE_B_BASE_IDX 2 5306#define regCNVC_CFG1_COLOR_KEYER_CONTROL 0x0e42 5307#define regCNVC_CFG1_COLOR_KEYER_CONTROL_BASE_IDX 2 5308#define regCNVC_CFG1_COLOR_KEYER_ALPHA 0x0e43 5309#define regCNVC_CFG1_COLOR_KEYER_ALPHA_BASE_IDX 2 5310#define regCNVC_CFG1_COLOR_KEYER_RED 0x0e44 5311#define regCNVC_CFG1_COLOR_KEYER_RED_BASE_IDX 2 5312#define regCNVC_CFG1_COLOR_KEYER_GREEN 0x0e45 5313#define regCNVC_CFG1_COLOR_KEYER_GREEN_BASE_IDX 2 5314#define regCNVC_CFG1_COLOR_KEYER_BLUE 0x0e46 5315#define regCNVC_CFG1_COLOR_KEYER_BLUE_BASE_IDX 2 5316#define regCNVC_CFG1_ALPHA_2BIT_LUT 0x0e48 5317#define regCNVC_CFG1_ALPHA_2BIT_LUT_BASE_IDX 2 5318#define regCNVC_CFG1_PRE_DEALPHA 0x0e49 5319#define regCNVC_CFG1_PRE_DEALPHA_BASE_IDX 2 5320#define regCNVC_CFG1_PRE_CSC_MODE 0x0e4a 5321#define regCNVC_CFG1_PRE_CSC_MODE_BASE_IDX 2 5322#define regCNVC_CFG1_PRE_CSC_C11_C12 0x0e4b 5323#define regCNVC_CFG1_PRE_CSC_C11_C12_BASE_IDX 2 5324#define regCNVC_CFG1_PRE_CSC_C13_C14 0x0e4c 5325#define regCNVC_CFG1_PRE_CSC_C13_C14_BASE_IDX 2 5326#define regCNVC_CFG1_PRE_CSC_C21_C22 0x0e4d 5327#define regCNVC_CFG1_PRE_CSC_C21_C22_BASE_IDX 2 5328#define regCNVC_CFG1_PRE_CSC_C23_C24 0x0e4e 5329#define regCNVC_CFG1_PRE_CSC_C23_C24_BASE_IDX 2 5330#define regCNVC_CFG1_PRE_CSC_C31_C32 0x0e4f 5331#define regCNVC_CFG1_PRE_CSC_C31_C32_BASE_IDX 2 5332#define regCNVC_CFG1_PRE_CSC_C33_C34 0x0e50 5333#define regCNVC_CFG1_PRE_CSC_C33_C34_BASE_IDX 2 5334#define regCNVC_CFG1_PRE_CSC_B_C11_C12 0x0e51 5335#define regCNVC_CFG1_PRE_CSC_B_C11_C12_BASE_IDX 2 5336#define regCNVC_CFG1_PRE_CSC_B_C13_C14 0x0e52 5337#define regCNVC_CFG1_PRE_CSC_B_C13_C14_BASE_IDX 2 5338#define regCNVC_CFG1_PRE_CSC_B_C21_C22 0x0e53 5339#define regCNVC_CFG1_PRE_CSC_B_C21_C22_BASE_IDX 2 5340#define regCNVC_CFG1_PRE_CSC_B_C23_C24 0x0e54 5341#define regCNVC_CFG1_PRE_CSC_B_C23_C24_BASE_IDX 2 5342#define regCNVC_CFG1_PRE_CSC_B_C31_C32 0x0e55 5343#define regCNVC_CFG1_PRE_CSC_B_C31_C32_BASE_IDX 2 5344#define regCNVC_CFG1_PRE_CSC_B_C33_C34 0x0e56 5345#define regCNVC_CFG1_PRE_CSC_B_C33_C34_BASE_IDX 2 5346#define regCNVC_CFG1_CNVC_COEF_FORMAT 0x0e57 5347#define regCNVC_CFG1_CNVC_COEF_FORMAT_BASE_IDX 2 5348#define regCNVC_CFG1_PRE_DEGAM 0x0e58 5349#define regCNVC_CFG1_PRE_DEGAM_BASE_IDX 2 5350#define regCNVC_CFG1_PRE_REALPHA 0x0e59 5351#define regCNVC_CFG1_PRE_REALPHA_BASE_IDX 2 5352 5353 5354// addressBlock: dce_dc_dpp1_dispdec_cnvc_cur_dispdec 5355// base address: 0x5ac 5356#define regCNVC_CUR1_CURSOR0_CONTROL 0x0e5c 5357#define regCNVC_CUR1_CURSOR0_CONTROL_BASE_IDX 2 5358#define regCNVC_CUR1_CURSOR0_COLOR0 0x0e5d 5359#define regCNVC_CUR1_CURSOR0_COLOR0_BASE_IDX 2 5360#define regCNVC_CUR1_CURSOR0_COLOR1 0x0e5e 5361#define regCNVC_CUR1_CURSOR0_COLOR1_BASE_IDX 2 5362#define regCNVC_CUR1_CURSOR0_FP_SCALE_BIAS 0x0e5f 5363#define regCNVC_CUR1_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 5364 5365 5366// addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec 5367// base address: 0x5ac 5368#define regDSCL1_SCL_COEF_RAM_TAP_SELECT 0x0e64 5369#define regDSCL1_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 5370#define regDSCL1_SCL_COEF_RAM_TAP_DATA 0x0e65 5371#define regDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 5372#define regDSCL1_SCL_MODE 0x0e66 5373#define regDSCL1_SCL_MODE_BASE_IDX 2 5374#define regDSCL1_SCL_TAP_CONTROL 0x0e67 5375#define regDSCL1_SCL_TAP_CONTROL_BASE_IDX 2 5376#define regDSCL1_DSCL_CONTROL 0x0e68 5377#define regDSCL1_DSCL_CONTROL_BASE_IDX 2 5378#define regDSCL1_DSCL_2TAP_CONTROL 0x0e69 5379#define regDSCL1_DSCL_2TAP_CONTROL_BASE_IDX 2 5380#define regDSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x0e6a 5381#define regDSCL1_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 5382#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x0e6b 5383#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 5384#define regDSCL1_SCL_HORZ_FILTER_INIT 0x0e6c 5385#define regDSCL1_SCL_HORZ_FILTER_INIT_BASE_IDX 2 5386#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0e6d 5387#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 5388#define regDSCL1_SCL_HORZ_FILTER_INIT_C 0x0e6e 5389#define regDSCL1_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 5390#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x0e6f 5391#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 5392#define regDSCL1_SCL_VERT_FILTER_INIT 0x0e70 5393#define regDSCL1_SCL_VERT_FILTER_INIT_BASE_IDX 2 5394#define regDSCL1_SCL_VERT_FILTER_INIT_BOT 0x0e71 5395#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 5396#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C 0x0e72 5397#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 5398#define regDSCL1_SCL_VERT_FILTER_INIT_C 0x0e73 5399#define regDSCL1_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 5400#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_C 0x0e74 5401#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 5402#define regDSCL1_SCL_BLACK_COLOR 0x0e75 5403#define regDSCL1_SCL_BLACK_COLOR_BASE_IDX 2 5404#define regDSCL1_DSCL_UPDATE 0x0e76 5405#define regDSCL1_DSCL_UPDATE_BASE_IDX 2 5406#define regDSCL1_DSCL_AUTOCAL 0x0e77 5407#define regDSCL1_DSCL_AUTOCAL_BASE_IDX 2 5408#define regDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0e78 5409#define regDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 5410#define regDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0e79 5411#define regDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 5412#define regDSCL1_OTG_H_BLANK 0x0e7a 5413#define regDSCL1_OTG_H_BLANK_BASE_IDX 2 5414#define regDSCL1_OTG_V_BLANK 0x0e7b 5415#define regDSCL1_OTG_V_BLANK_BASE_IDX 2 5416#define regDSCL1_RECOUT_START 0x0e7c 5417#define regDSCL1_RECOUT_START_BASE_IDX 2 5418#define regDSCL1_RECOUT_SIZE 0x0e7d 5419#define regDSCL1_RECOUT_SIZE_BASE_IDX 2 5420#define regDSCL1_MPC_SIZE 0x0e7e 5421#define regDSCL1_MPC_SIZE_BASE_IDX 2 5422#define regDSCL1_LB_DATA_FORMAT 0x0e7f 5423#define regDSCL1_LB_DATA_FORMAT_BASE_IDX 2 5424#define regDSCL1_LB_MEMORY_CTRL 0x0e80 5425#define regDSCL1_LB_MEMORY_CTRL_BASE_IDX 2 5426#define regDSCL1_LB_V_COUNTER 0x0e81 5427#define regDSCL1_LB_V_COUNTER_BASE_IDX 2 5428#define regDSCL1_DSCL_MEM_PWR_CTRL 0x0e82 5429#define regDSCL1_DSCL_MEM_PWR_CTRL_BASE_IDX 2 5430#define regDSCL1_DSCL_MEM_PWR_STATUS 0x0e83 5431#define regDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX 2 5432#define regDSCL1_OBUF_CONTROL 0x0e84 5433#define regDSCL1_OBUF_CONTROL_BASE_IDX 2 5434#define regDSCL1_OBUF_MEM_PWR_CTRL 0x0e85 5435#define regDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX 2 5436 5437 5438// addressBlock: dce_dc_dpp1_dispdec_cm_dispdec 5439// base address: 0x5ac 5440#define regCM1_CM_CONTROL 0x0e8b 5441#define regCM1_CM_CONTROL_BASE_IDX 2 5442#define regCM1_CM_POST_CSC_CONTROL 0x0e8c 5443#define regCM1_CM_POST_CSC_CONTROL_BASE_IDX 2 5444#define regCM1_CM_POST_CSC_C11_C12 0x0e8d 5445#define regCM1_CM_POST_CSC_C11_C12_BASE_IDX 2 5446#define regCM1_CM_POST_CSC_C13_C14 0x0e8e 5447#define regCM1_CM_POST_CSC_C13_C14_BASE_IDX 2 5448#define regCM1_CM_POST_CSC_C21_C22 0x0e8f 5449#define regCM1_CM_POST_CSC_C21_C22_BASE_IDX 2 5450#define regCM1_CM_POST_CSC_C23_C24 0x0e90 5451#define regCM1_CM_POST_CSC_C23_C24_BASE_IDX 2 5452#define regCM1_CM_POST_CSC_C31_C32 0x0e91 5453#define regCM1_CM_POST_CSC_C31_C32_BASE_IDX 2 5454#define regCM1_CM_POST_CSC_C33_C34 0x0e92 5455#define regCM1_CM_POST_CSC_C33_C34_BASE_IDX 2 5456#define regCM1_CM_POST_CSC_B_C11_C12 0x0e93 5457#define regCM1_CM_POST_CSC_B_C11_C12_BASE_IDX 2 5458#define regCM1_CM_POST_CSC_B_C13_C14 0x0e94 5459#define regCM1_CM_POST_CSC_B_C13_C14_BASE_IDX 2 5460#define regCM1_CM_POST_CSC_B_C21_C22 0x0e95 5461#define regCM1_CM_POST_CSC_B_C21_C22_BASE_IDX 2 5462#define regCM1_CM_POST_CSC_B_C23_C24 0x0e96 5463#define regCM1_CM_POST_CSC_B_C23_C24_BASE_IDX 2 5464#define regCM1_CM_POST_CSC_B_C31_C32 0x0e97 5465#define regCM1_CM_POST_CSC_B_C31_C32_BASE_IDX 2 5466#define regCM1_CM_POST_CSC_B_C33_C34 0x0e98 5467#define regCM1_CM_POST_CSC_B_C33_C34_BASE_IDX 2 5468#define regCM1_CM_GAMUT_REMAP_CONTROL 0x0e99 5469#define regCM1_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 5470#define regCM1_CM_GAMUT_REMAP_C11_C12 0x0e9a 5471#define regCM1_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 5472#define regCM1_CM_GAMUT_REMAP_C13_C14 0x0e9b 5473#define regCM1_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 5474#define regCM1_CM_GAMUT_REMAP_C21_C22 0x0e9c 5475#define regCM1_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 5476#define regCM1_CM_GAMUT_REMAP_C23_C24 0x0e9d 5477#define regCM1_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 5478#define regCM1_CM_GAMUT_REMAP_C31_C32 0x0e9e 5479#define regCM1_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 5480#define regCM1_CM_GAMUT_REMAP_C33_C34 0x0e9f 5481#define regCM1_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 5482#define regCM1_CM_GAMUT_REMAP_B_C11_C12 0x0ea0 5483#define regCM1_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 5484#define regCM1_CM_GAMUT_REMAP_B_C13_C14 0x0ea1 5485#define regCM1_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 5486#define regCM1_CM_GAMUT_REMAP_B_C21_C22 0x0ea2 5487#define regCM1_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 5488#define regCM1_CM_GAMUT_REMAP_B_C23_C24 0x0ea3 5489#define regCM1_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 5490#define regCM1_CM_GAMUT_REMAP_B_C31_C32 0x0ea4 5491#define regCM1_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 5492#define regCM1_CM_GAMUT_REMAP_B_C33_C34 0x0ea5 5493#define regCM1_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 5494#define regCM1_CM_BIAS_CR_R 0x0ea6 5495#define regCM1_CM_BIAS_CR_R_BASE_IDX 2 5496#define regCM1_CM_BIAS_Y_G_CB_B 0x0ea7 5497#define regCM1_CM_BIAS_Y_G_CB_B_BASE_IDX 2 5498#define regCM1_CM_GAMCOR_CONTROL 0x0ea8 5499#define regCM1_CM_GAMCOR_CONTROL_BASE_IDX 2 5500#define regCM1_CM_GAMCOR_LUT_INDEX 0x0ea9 5501#define regCM1_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 5502#define regCM1_CM_GAMCOR_LUT_DATA 0x0eaa 5503#define regCM1_CM_GAMCOR_LUT_DATA_BASE_IDX 2 5504#define regCM1_CM_GAMCOR_LUT_CONTROL 0x0eab 5505#define regCM1_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 5506#define regCM1_CM_GAMCOR_RAMA_START_CNTL_B 0x0eac 5507#define regCM1_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 5508#define regCM1_CM_GAMCOR_RAMA_START_CNTL_G 0x0ead 5509#define regCM1_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 5510#define regCM1_CM_GAMCOR_RAMA_START_CNTL_R 0x0eae 5511#define regCM1_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 5512#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x0eaf 5513#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 5514#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x0eb0 5515#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 5516#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x0eb1 5517#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 5518#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x0eb2 5519#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 5520#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x0eb3 5521#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 5522#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x0eb4 5523#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 5524#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_B 0x0eb5 5525#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 5526#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_B 0x0eb6 5527#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 5528#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_G 0x0eb7 5529#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 5530#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_G 0x0eb8 5531#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 5532#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_R 0x0eb9 5533#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 5534#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_R 0x0eba 5535#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 5536#define regCM1_CM_GAMCOR_RAMA_OFFSET_B 0x0ebb 5537#define regCM1_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 5538#define regCM1_CM_GAMCOR_RAMA_OFFSET_G 0x0ebc 5539#define regCM1_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 5540#define regCM1_CM_GAMCOR_RAMA_OFFSET_R 0x0ebd 5541#define regCM1_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 5542#define regCM1_CM_GAMCOR_RAMA_REGION_0_1 0x0ebe 5543#define regCM1_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 5544#define regCM1_CM_GAMCOR_RAMA_REGION_2_3 0x0ebf 5545#define regCM1_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 5546#define regCM1_CM_GAMCOR_RAMA_REGION_4_5 0x0ec0 5547#define regCM1_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 5548#define regCM1_CM_GAMCOR_RAMA_REGION_6_7 0x0ec1 5549#define regCM1_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 5550#define regCM1_CM_GAMCOR_RAMA_REGION_8_9 0x0ec2 5551#define regCM1_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 5552#define regCM1_CM_GAMCOR_RAMA_REGION_10_11 0x0ec3 5553#define regCM1_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 5554#define regCM1_CM_GAMCOR_RAMA_REGION_12_13 0x0ec4 5555#define regCM1_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 5556#define regCM1_CM_GAMCOR_RAMA_REGION_14_15 0x0ec5 5557#define regCM1_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 5558#define regCM1_CM_GAMCOR_RAMA_REGION_16_17 0x0ec6 5559#define regCM1_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 5560#define regCM1_CM_GAMCOR_RAMA_REGION_18_19 0x0ec7 5561#define regCM1_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 5562#define regCM1_CM_GAMCOR_RAMA_REGION_20_21 0x0ec8 5563#define regCM1_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 5564#define regCM1_CM_GAMCOR_RAMA_REGION_22_23 0x0ec9 5565#define regCM1_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 5566#define regCM1_CM_GAMCOR_RAMA_REGION_24_25 0x0eca 5567#define regCM1_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 5568#define regCM1_CM_GAMCOR_RAMA_REGION_26_27 0x0ecb 5569#define regCM1_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 5570#define regCM1_CM_GAMCOR_RAMA_REGION_28_29 0x0ecc 5571#define regCM1_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 5572#define regCM1_CM_GAMCOR_RAMA_REGION_30_31 0x0ecd 5573#define regCM1_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 5574#define regCM1_CM_GAMCOR_RAMA_REGION_32_33 0x0ece 5575#define regCM1_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 5576#define regCM1_CM_GAMCOR_RAMB_START_CNTL_B 0x0ecf 5577#define regCM1_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 5578#define regCM1_CM_GAMCOR_RAMB_START_CNTL_G 0x0ed0 5579#define regCM1_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 5580#define regCM1_CM_GAMCOR_RAMB_START_CNTL_R 0x0ed1 5581#define regCM1_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 5582#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x0ed2 5583#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 5584#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x0ed3 5585#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 5586#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x0ed4 5587#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 5588#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x0ed5 5589#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 5590#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x0ed6 5591#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 5592#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x0ed7 5593#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 5594#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_B 0x0ed8 5595#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 5596#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_B 0x0ed9 5597#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 5598#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_G 0x0eda 5599#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 5600#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_G 0x0edb 5601#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 5602#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_R 0x0edc 5603#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 5604#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_R 0x0edd 5605#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 5606#define regCM1_CM_GAMCOR_RAMB_OFFSET_B 0x0ede 5607#define regCM1_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 5608#define regCM1_CM_GAMCOR_RAMB_OFFSET_G 0x0edf 5609#define regCM1_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 5610#define regCM1_CM_GAMCOR_RAMB_OFFSET_R 0x0ee0 5611#define regCM1_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 5612#define regCM1_CM_GAMCOR_RAMB_REGION_0_1 0x0ee1 5613#define regCM1_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 5614#define regCM1_CM_GAMCOR_RAMB_REGION_2_3 0x0ee2 5615#define regCM1_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 5616#define regCM1_CM_GAMCOR_RAMB_REGION_4_5 0x0ee3 5617#define regCM1_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 5618#define regCM1_CM_GAMCOR_RAMB_REGION_6_7 0x0ee4 5619#define regCM1_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 5620#define regCM1_CM_GAMCOR_RAMB_REGION_8_9 0x0ee5 5621#define regCM1_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 5622#define regCM1_CM_GAMCOR_RAMB_REGION_10_11 0x0ee6 5623#define regCM1_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 5624#define regCM1_CM_GAMCOR_RAMB_REGION_12_13 0x0ee7 5625#define regCM1_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 5626#define regCM1_CM_GAMCOR_RAMB_REGION_14_15 0x0ee8 5627#define regCM1_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 5628#define regCM1_CM_GAMCOR_RAMB_REGION_16_17 0x0ee9 5629#define regCM1_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 5630#define regCM1_CM_GAMCOR_RAMB_REGION_18_19 0x0eea 5631#define regCM1_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 5632#define regCM1_CM_GAMCOR_RAMB_REGION_20_21 0x0eeb 5633#define regCM1_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 5634#define regCM1_CM_GAMCOR_RAMB_REGION_22_23 0x0eec 5635#define regCM1_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 5636#define regCM1_CM_GAMCOR_RAMB_REGION_24_25 0x0eed 5637#define regCM1_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 5638#define regCM1_CM_GAMCOR_RAMB_REGION_26_27 0x0eee 5639#define regCM1_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 5640#define regCM1_CM_GAMCOR_RAMB_REGION_28_29 0x0eef 5641#define regCM1_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 5642#define regCM1_CM_GAMCOR_RAMB_REGION_30_31 0x0ef0 5643#define regCM1_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 5644#define regCM1_CM_GAMCOR_RAMB_REGION_32_33 0x0ef1 5645#define regCM1_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 5646#define regCM1_CM_BLNDGAM_CONTROL 0x0ef2 5647#define regCM1_CM_BLNDGAM_CONTROL_BASE_IDX 2 5648#define regCM1_CM_BLNDGAM_LUT_INDEX 0x0ef3 5649#define regCM1_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2 5650#define regCM1_CM_BLNDGAM_LUT_DATA 0x0ef4 5651#define regCM1_CM_BLNDGAM_LUT_DATA_BASE_IDX 2 5652#define regCM1_CM_BLNDGAM_LUT_CONTROL 0x0ef5 5653#define regCM1_CM_BLNDGAM_LUT_CONTROL_BASE_IDX 2 5654#define regCM1_CM_BLNDGAM_RAMA_START_CNTL_B 0x0ef6 5655#define regCM1_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2 5656#define regCM1_CM_BLNDGAM_RAMA_START_CNTL_G 0x0ef7 5657#define regCM1_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2 5658#define regCM1_CM_BLNDGAM_RAMA_START_CNTL_R 0x0ef8 5659#define regCM1_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2 5660#define regCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B 0x0ef9 5661#define regCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 5662#define regCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G 0x0efa 5663#define regCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 5664#define regCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R 0x0efb 5665#define regCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 5666#define regCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_B 0x0efc 5667#define regCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2 5668#define regCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_G 0x0efd 5669#define regCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2 5670#define regCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_R 0x0efe 5671#define regCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2 5672#define regCM1_CM_BLNDGAM_RAMA_END_CNTL1_B 0x0eff 5673#define regCM1_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2 5674#define regCM1_CM_BLNDGAM_RAMA_END_CNTL2_B 0x0f00 5675#define regCM1_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2 5676#define regCM1_CM_BLNDGAM_RAMA_END_CNTL1_G 0x0f01 5677#define regCM1_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2 5678#define regCM1_CM_BLNDGAM_RAMA_END_CNTL2_G 0x0f02 5679#define regCM1_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2 5680#define regCM1_CM_BLNDGAM_RAMA_END_CNTL1_R 0x0f03 5681#define regCM1_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2 5682#define regCM1_CM_BLNDGAM_RAMA_END_CNTL2_R 0x0f04 5683#define regCM1_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2 5684#define regCM1_CM_BLNDGAM_RAMA_OFFSET_B 0x0f05 5685#define regCM1_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX 2 5686#define regCM1_CM_BLNDGAM_RAMA_OFFSET_G 0x0f06 5687#define regCM1_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX 2 5688#define regCM1_CM_BLNDGAM_RAMA_OFFSET_R 0x0f07 5689#define regCM1_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX 2 5690#define regCM1_CM_BLNDGAM_RAMA_REGION_0_1 0x0f08 5691#define regCM1_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2 5692#define regCM1_CM_BLNDGAM_RAMA_REGION_2_3 0x0f09 5693#define regCM1_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2 5694#define regCM1_CM_BLNDGAM_RAMA_REGION_4_5 0x0f0a 5695#define regCM1_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2 5696#define regCM1_CM_BLNDGAM_RAMA_REGION_6_7 0x0f0b 5697#define regCM1_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2 5698#define regCM1_CM_BLNDGAM_RAMA_REGION_8_9 0x0f0c 5699#define regCM1_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2 5700#define regCM1_CM_BLNDGAM_RAMA_REGION_10_11 0x0f0d 5701#define regCM1_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2 5702#define regCM1_CM_BLNDGAM_RAMA_REGION_12_13 0x0f0e 5703#define regCM1_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2 5704#define regCM1_CM_BLNDGAM_RAMA_REGION_14_15 0x0f0f 5705#define regCM1_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2 5706#define regCM1_CM_BLNDGAM_RAMA_REGION_16_17 0x0f10 5707#define regCM1_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2 5708#define regCM1_CM_BLNDGAM_RAMA_REGION_18_19 0x0f11 5709#define regCM1_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2 5710#define regCM1_CM_BLNDGAM_RAMA_REGION_20_21 0x0f12 5711#define regCM1_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2 5712#define regCM1_CM_BLNDGAM_RAMA_REGION_22_23 0x0f13 5713#define regCM1_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2 5714#define regCM1_CM_BLNDGAM_RAMA_REGION_24_25 0x0f14 5715#define regCM1_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2 5716#define regCM1_CM_BLNDGAM_RAMA_REGION_26_27 0x0f15 5717#define regCM1_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2 5718#define regCM1_CM_BLNDGAM_RAMA_REGION_28_29 0x0f16 5719#define regCM1_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2 5720#define regCM1_CM_BLNDGAM_RAMA_REGION_30_31 0x0f17 5721#define regCM1_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2 5722#define regCM1_CM_BLNDGAM_RAMA_REGION_32_33 0x0f18 5723#define regCM1_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2 5724#define regCM1_CM_BLNDGAM_RAMB_START_CNTL_B 0x0f19 5725#define regCM1_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2 5726#define regCM1_CM_BLNDGAM_RAMB_START_CNTL_G 0x0f1a 5727#define regCM1_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2 5728#define regCM1_CM_BLNDGAM_RAMB_START_CNTL_R 0x0f1b 5729#define regCM1_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2 5730#define regCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B 0x0f1c 5731#define regCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 5732#define regCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G 0x0f1d 5733#define regCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 5734#define regCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R 0x0f1e 5735#define regCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 5736#define regCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_B 0x0f1f 5737#define regCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2 5738#define regCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_G 0x0f20 5739#define regCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2 5740#define regCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_R 0x0f21 5741#define regCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2 5742#define regCM1_CM_BLNDGAM_RAMB_END_CNTL1_B 0x0f22 5743#define regCM1_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2 5744#define regCM1_CM_BLNDGAM_RAMB_END_CNTL2_B 0x0f23 5745#define regCM1_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2 5746#define regCM1_CM_BLNDGAM_RAMB_END_CNTL1_G 0x0f24 5747#define regCM1_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2 5748#define regCM1_CM_BLNDGAM_RAMB_END_CNTL2_G 0x0f25 5749#define regCM1_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2 5750#define regCM1_CM_BLNDGAM_RAMB_END_CNTL1_R 0x0f26 5751#define regCM1_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2 5752#define regCM1_CM_BLNDGAM_RAMB_END_CNTL2_R 0x0f27 5753#define regCM1_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2 5754#define regCM1_CM_BLNDGAM_RAMB_OFFSET_B 0x0f28 5755#define regCM1_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX 2 5756#define regCM1_CM_BLNDGAM_RAMB_OFFSET_G 0x0f29 5757#define regCM1_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX 2 5758#define regCM1_CM_BLNDGAM_RAMB_OFFSET_R 0x0f2a 5759#define regCM1_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX 2 5760#define regCM1_CM_BLNDGAM_RAMB_REGION_0_1 0x0f2b 5761#define regCM1_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2 5762#define regCM1_CM_BLNDGAM_RAMB_REGION_2_3 0x0f2c 5763#define regCM1_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2 5764#define regCM1_CM_BLNDGAM_RAMB_REGION_4_5 0x0f2d 5765#define regCM1_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2 5766#define regCM1_CM_BLNDGAM_RAMB_REGION_6_7 0x0f2e 5767#define regCM1_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2 5768#define regCM1_CM_BLNDGAM_RAMB_REGION_8_9 0x0f2f 5769#define regCM1_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2 5770#define regCM1_CM_BLNDGAM_RAMB_REGION_10_11 0x0f30 5771#define regCM1_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2 5772#define regCM1_CM_BLNDGAM_RAMB_REGION_12_13 0x0f31 5773#define regCM1_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2 5774#define regCM1_CM_BLNDGAM_RAMB_REGION_14_15 0x0f32 5775#define regCM1_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2 5776#define regCM1_CM_BLNDGAM_RAMB_REGION_16_17 0x0f33 5777#define regCM1_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2 5778#define regCM1_CM_BLNDGAM_RAMB_REGION_18_19 0x0f34 5779#define regCM1_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2 5780#define regCM1_CM_BLNDGAM_RAMB_REGION_20_21 0x0f35 5781#define regCM1_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2 5782#define regCM1_CM_BLNDGAM_RAMB_REGION_22_23 0x0f36 5783#define regCM1_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2 5784#define regCM1_CM_BLNDGAM_RAMB_REGION_24_25 0x0f37 5785#define regCM1_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2 5786#define regCM1_CM_BLNDGAM_RAMB_REGION_26_27 0x0f38 5787#define regCM1_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2 5788#define regCM1_CM_BLNDGAM_RAMB_REGION_28_29 0x0f39 5789#define regCM1_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2 5790#define regCM1_CM_BLNDGAM_RAMB_REGION_30_31 0x0f3a 5791#define regCM1_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2 5792#define regCM1_CM_BLNDGAM_RAMB_REGION_32_33 0x0f3b 5793#define regCM1_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2 5794#define regCM1_CM_HDR_MULT_COEF 0x0f3c 5795#define regCM1_CM_HDR_MULT_COEF_BASE_IDX 2 5796#define regCM1_CM_MEM_PWR_CTRL 0x0f3d 5797#define regCM1_CM_MEM_PWR_CTRL_BASE_IDX 2 5798#define regCM1_CM_MEM_PWR_STATUS 0x0f3e 5799#define regCM1_CM_MEM_PWR_STATUS_BASE_IDX 2 5800#define regCM1_CM_DEALPHA 0x0f40 5801#define regCM1_CM_DEALPHA_BASE_IDX 2 5802#define regCM1_CM_COEF_FORMAT 0x0f41 5803#define regCM1_CM_COEF_FORMAT_BASE_IDX 2 5804#define regCM1_CM_SHAPER_CONTROL 0x0f42 5805#define regCM1_CM_SHAPER_CONTROL_BASE_IDX 2 5806#define regCM1_CM_SHAPER_OFFSET_R 0x0f43 5807#define regCM1_CM_SHAPER_OFFSET_R_BASE_IDX 2 5808#define regCM1_CM_SHAPER_OFFSET_G 0x0f44 5809#define regCM1_CM_SHAPER_OFFSET_G_BASE_IDX 2 5810#define regCM1_CM_SHAPER_OFFSET_B 0x0f45 5811#define regCM1_CM_SHAPER_OFFSET_B_BASE_IDX 2 5812#define regCM1_CM_SHAPER_SCALE_R 0x0f46 5813#define regCM1_CM_SHAPER_SCALE_R_BASE_IDX 2 5814#define regCM1_CM_SHAPER_SCALE_G_B 0x0f47 5815#define regCM1_CM_SHAPER_SCALE_G_B_BASE_IDX 2 5816#define regCM1_CM_SHAPER_LUT_INDEX 0x0f48 5817#define regCM1_CM_SHAPER_LUT_INDEX_BASE_IDX 2 5818#define regCM1_CM_SHAPER_LUT_DATA 0x0f49 5819#define regCM1_CM_SHAPER_LUT_DATA_BASE_IDX 2 5820#define regCM1_CM_SHAPER_LUT_WRITE_EN_MASK 0x0f4a 5821#define regCM1_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2 5822#define regCM1_CM_SHAPER_RAMA_START_CNTL_B 0x0f4b 5823#define regCM1_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2 5824#define regCM1_CM_SHAPER_RAMA_START_CNTL_G 0x0f4c 5825#define regCM1_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2 5826#define regCM1_CM_SHAPER_RAMA_START_CNTL_R 0x0f4d 5827#define regCM1_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2 5828#define regCM1_CM_SHAPER_RAMA_END_CNTL_B 0x0f4e 5829#define regCM1_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2 5830#define regCM1_CM_SHAPER_RAMA_END_CNTL_G 0x0f4f 5831#define regCM1_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2 5832#define regCM1_CM_SHAPER_RAMA_END_CNTL_R 0x0f50 5833#define regCM1_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2 5834#define regCM1_CM_SHAPER_RAMA_REGION_0_1 0x0f51 5835#define regCM1_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2 5836#define regCM1_CM_SHAPER_RAMA_REGION_2_3 0x0f52 5837#define regCM1_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2 5838#define regCM1_CM_SHAPER_RAMA_REGION_4_5 0x0f53 5839#define regCM1_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2 5840#define regCM1_CM_SHAPER_RAMA_REGION_6_7 0x0f54 5841#define regCM1_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2 5842#define regCM1_CM_SHAPER_RAMA_REGION_8_9 0x0f55 5843#define regCM1_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2 5844#define regCM1_CM_SHAPER_RAMA_REGION_10_11 0x0f56 5845#define regCM1_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2 5846#define regCM1_CM_SHAPER_RAMA_REGION_12_13 0x0f57 5847#define regCM1_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2 5848#define regCM1_CM_SHAPER_RAMA_REGION_14_15 0x0f58 5849#define regCM1_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2 5850#define regCM1_CM_SHAPER_RAMA_REGION_16_17 0x0f59 5851#define regCM1_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2 5852#define regCM1_CM_SHAPER_RAMA_REGION_18_19 0x0f5a 5853#define regCM1_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2 5854#define regCM1_CM_SHAPER_RAMA_REGION_20_21 0x0f5b 5855#define regCM1_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2 5856#define regCM1_CM_SHAPER_RAMA_REGION_22_23 0x0f5c 5857#define regCM1_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2 5858#define regCM1_CM_SHAPER_RAMA_REGION_24_25 0x0f5d 5859#define regCM1_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2 5860#define regCM1_CM_SHAPER_RAMA_REGION_26_27 0x0f5e 5861#define regCM1_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2 5862#define regCM1_CM_SHAPER_RAMA_REGION_28_29 0x0f5f 5863#define regCM1_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2 5864#define regCM1_CM_SHAPER_RAMA_REGION_30_31 0x0f60 5865#define regCM1_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2 5866#define regCM1_CM_SHAPER_RAMA_REGION_32_33 0x0f61 5867#define regCM1_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2 5868#define regCM1_CM_SHAPER_RAMB_START_CNTL_B 0x0f62 5869#define regCM1_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2 5870#define regCM1_CM_SHAPER_RAMB_START_CNTL_G 0x0f63 5871#define regCM1_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2 5872#define regCM1_CM_SHAPER_RAMB_START_CNTL_R 0x0f64 5873#define regCM1_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2 5874#define regCM1_CM_SHAPER_RAMB_END_CNTL_B 0x0f65 5875#define regCM1_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2 5876#define regCM1_CM_SHAPER_RAMB_END_CNTL_G 0x0f66 5877#define regCM1_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2 5878#define regCM1_CM_SHAPER_RAMB_END_CNTL_R 0x0f67 5879#define regCM1_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2 5880#define regCM1_CM_SHAPER_RAMB_REGION_0_1 0x0f68 5881#define regCM1_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2 5882#define regCM1_CM_SHAPER_RAMB_REGION_2_3 0x0f69 5883#define regCM1_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2 5884#define regCM1_CM_SHAPER_RAMB_REGION_4_5 0x0f6a 5885#define regCM1_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2 5886#define regCM1_CM_SHAPER_RAMB_REGION_6_7 0x0f6b 5887#define regCM1_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2 5888#define regCM1_CM_SHAPER_RAMB_REGION_8_9 0x0f6c 5889#define regCM1_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2 5890#define regCM1_CM_SHAPER_RAMB_REGION_10_11 0x0f6d 5891#define regCM1_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2 5892#define regCM1_CM_SHAPER_RAMB_REGION_12_13 0x0f6e 5893#define regCM1_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2 5894#define regCM1_CM_SHAPER_RAMB_REGION_14_15 0x0f6f 5895#define regCM1_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2 5896#define regCM1_CM_SHAPER_RAMB_REGION_16_17 0x0f70 5897#define regCM1_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2 5898#define regCM1_CM_SHAPER_RAMB_REGION_18_19 0x0f71 5899#define regCM1_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2 5900#define regCM1_CM_SHAPER_RAMB_REGION_20_21 0x0f72 5901#define regCM1_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2 5902#define regCM1_CM_SHAPER_RAMB_REGION_22_23 0x0f73 5903#define regCM1_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2 5904#define regCM1_CM_SHAPER_RAMB_REGION_24_25 0x0f74 5905#define regCM1_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2 5906#define regCM1_CM_SHAPER_RAMB_REGION_26_27 0x0f75 5907#define regCM1_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2 5908#define regCM1_CM_SHAPER_RAMB_REGION_28_29 0x0f76 5909#define regCM1_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2 5910#define regCM1_CM_SHAPER_RAMB_REGION_30_31 0x0f77 5911#define regCM1_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2 5912#define regCM1_CM_SHAPER_RAMB_REGION_32_33 0x0f78 5913#define regCM1_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2 5914#define regCM1_CM_MEM_PWR_CTRL2 0x0f79 5915#define regCM1_CM_MEM_PWR_CTRL2_BASE_IDX 2 5916#define regCM1_CM_MEM_PWR_STATUS2 0x0f7a 5917#define regCM1_CM_MEM_PWR_STATUS2_BASE_IDX 2 5918#define regCM1_CM_3DLUT_MODE 0x0f7b 5919#define regCM1_CM_3DLUT_MODE_BASE_IDX 2 5920#define regCM1_CM_3DLUT_INDEX 0x0f7c 5921#define regCM1_CM_3DLUT_INDEX_BASE_IDX 2 5922#define regCM1_CM_3DLUT_DATA 0x0f7d 5923#define regCM1_CM_3DLUT_DATA_BASE_IDX 2 5924#define regCM1_CM_3DLUT_DATA_30BIT 0x0f7e 5925#define regCM1_CM_3DLUT_DATA_30BIT_BASE_IDX 2 5926#define regCM1_CM_3DLUT_READ_WRITE_CONTROL 0x0f7f 5927#define regCM1_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2 5928#define regCM1_CM_3DLUT_OUT_NORM_FACTOR 0x0f80 5929#define regCM1_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2 5930#define regCM1_CM_3DLUT_OUT_OFFSET_R 0x0f81 5931#define regCM1_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2 5932#define regCM1_CM_3DLUT_OUT_OFFSET_G 0x0f82 5933#define regCM1_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2 5934#define regCM1_CM_3DLUT_OUT_OFFSET_B 0x0f83 5935#define regCM1_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2 5936#define regCM1_CM_TEST_DEBUG_INDEX 0x0f84 5937#define regCM1_CM_TEST_DEBUG_INDEX_BASE_IDX 2 5938#define regCM1_CM_TEST_DEBUG_DATA 0x0f85 5939#define regCM1_CM_TEST_DEBUG_DATA_BASE_IDX 2 5940 5941 5942// addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec 5943// base address: 0x3e3c 5944#define regDC_PERFMON11_PERFCOUNTER_CNTL 0x0f8f 5945#define regDC_PERFMON11_PERFCOUNTER_CNTL_BASE_IDX 2 5946#define regDC_PERFMON11_PERFCOUNTER_CNTL2 0x0f90 5947#define regDC_PERFMON11_PERFCOUNTER_CNTL2_BASE_IDX 2 5948#define regDC_PERFMON11_PERFCOUNTER_STATE 0x0f91 5949#define regDC_PERFMON11_PERFCOUNTER_STATE_BASE_IDX 2 5950#define regDC_PERFMON11_PERFMON_CNTL 0x0f92 5951#define regDC_PERFMON11_PERFMON_CNTL_BASE_IDX 2 5952#define regDC_PERFMON11_PERFMON_CNTL2 0x0f93 5953#define regDC_PERFMON11_PERFMON_CNTL2_BASE_IDX 2 5954#define regDC_PERFMON11_PERFMON_CVALUE_INT_MISC 0x0f94 5955#define regDC_PERFMON11_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 5956#define regDC_PERFMON11_PERFMON_CVALUE_LOW 0x0f95 5957#define regDC_PERFMON11_PERFMON_CVALUE_LOW_BASE_IDX 2 5958#define regDC_PERFMON11_PERFMON_HI 0x0f96 5959#define regDC_PERFMON11_PERFMON_HI_BASE_IDX 2 5960#define regDC_PERFMON11_PERFMON_LOW 0x0f97 5961#define regDC_PERFMON11_PERFMON_LOW_BASE_IDX 2 5962 5963 5964// addressBlock: dce_dc_dpp2_dispdec_dpp_top_dispdec 5965// base address: 0xb58 5966#define regDPP_TOP2_DPP_CONTROL 0x0f9b 5967#define regDPP_TOP2_DPP_CONTROL_BASE_IDX 2 5968#define regDPP_TOP2_DPP_SOFT_RESET 0x0f9c 5969#define regDPP_TOP2_DPP_SOFT_RESET_BASE_IDX 2 5970#define regDPP_TOP2_DPP_CRC_VAL_R_G 0x0f9d 5971#define regDPP_TOP2_DPP_CRC_VAL_R_G_BASE_IDX 2 5972#define regDPP_TOP2_DPP_CRC_VAL_B_A 0x0f9e 5973#define regDPP_TOP2_DPP_CRC_VAL_B_A_BASE_IDX 2 5974#define regDPP_TOP2_DPP_CRC_CTRL 0x0f9f 5975#define regDPP_TOP2_DPP_CRC_CTRL_BASE_IDX 2 5976#define regDPP_TOP2_HOST_READ_CONTROL 0x0fa0 5977#define regDPP_TOP2_HOST_READ_CONTROL_BASE_IDX 2 5978 5979 5980// addressBlock: dce_dc_dpp2_dispdec_cnvc_cfg_dispdec 5981// base address: 0xb58 5982#define regCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT 0x0fa5 5983#define regCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 5984#define regCNVC_CFG2_FORMAT_CONTROL 0x0fa6 5985#define regCNVC_CFG2_FORMAT_CONTROL_BASE_IDX 2 5986#define regCNVC_CFG2_FCNV_FP_BIAS_R 0x0fa7 5987#define regCNVC_CFG2_FCNV_FP_BIAS_R_BASE_IDX 2 5988#define regCNVC_CFG2_FCNV_FP_BIAS_G 0x0fa8 5989#define regCNVC_CFG2_FCNV_FP_BIAS_G_BASE_IDX 2 5990#define regCNVC_CFG2_FCNV_FP_BIAS_B 0x0fa9 5991#define regCNVC_CFG2_FCNV_FP_BIAS_B_BASE_IDX 2 5992#define regCNVC_CFG2_FCNV_FP_SCALE_R 0x0faa 5993#define regCNVC_CFG2_FCNV_FP_SCALE_R_BASE_IDX 2 5994#define regCNVC_CFG2_FCNV_FP_SCALE_G 0x0fab 5995#define regCNVC_CFG2_FCNV_FP_SCALE_G_BASE_IDX 2 5996#define regCNVC_CFG2_FCNV_FP_SCALE_B 0x0fac 5997#define regCNVC_CFG2_FCNV_FP_SCALE_B_BASE_IDX 2 5998#define regCNVC_CFG2_COLOR_KEYER_CONTROL 0x0fad 5999#define regCNVC_CFG2_COLOR_KEYER_CONTROL_BASE_IDX 2 6000#define regCNVC_CFG2_COLOR_KEYER_ALPHA 0x0fae 6001#define regCNVC_CFG2_COLOR_KEYER_ALPHA_BASE_IDX 2 6002#define regCNVC_CFG2_COLOR_KEYER_RED 0x0faf 6003#define regCNVC_CFG2_COLOR_KEYER_RED_BASE_IDX 2 6004#define regCNVC_CFG2_COLOR_KEYER_GREEN 0x0fb0 6005#define regCNVC_CFG2_COLOR_KEYER_GREEN_BASE_IDX 2 6006#define regCNVC_CFG2_COLOR_KEYER_BLUE 0x0fb1 6007#define regCNVC_CFG2_COLOR_KEYER_BLUE_BASE_IDX 2 6008#define regCNVC_CFG2_ALPHA_2BIT_LUT 0x0fb3 6009#define regCNVC_CFG2_ALPHA_2BIT_LUT_BASE_IDX 2 6010#define regCNVC_CFG2_PRE_DEALPHA 0x0fb4 6011#define regCNVC_CFG2_PRE_DEALPHA_BASE_IDX 2 6012#define regCNVC_CFG2_PRE_CSC_MODE 0x0fb5 6013#define regCNVC_CFG2_PRE_CSC_MODE_BASE_IDX 2 6014#define regCNVC_CFG2_PRE_CSC_C11_C12 0x0fb6 6015#define regCNVC_CFG2_PRE_CSC_C11_C12_BASE_IDX 2 6016#define regCNVC_CFG2_PRE_CSC_C13_C14 0x0fb7 6017#define regCNVC_CFG2_PRE_CSC_C13_C14_BASE_IDX 2 6018#define regCNVC_CFG2_PRE_CSC_C21_C22 0x0fb8 6019#define regCNVC_CFG2_PRE_CSC_C21_C22_BASE_IDX 2 6020#define regCNVC_CFG2_PRE_CSC_C23_C24 0x0fb9 6021#define regCNVC_CFG2_PRE_CSC_C23_C24_BASE_IDX 2 6022#define regCNVC_CFG2_PRE_CSC_C31_C32 0x0fba 6023#define regCNVC_CFG2_PRE_CSC_C31_C32_BASE_IDX 2 6024#define regCNVC_CFG2_PRE_CSC_C33_C34 0x0fbb 6025#define regCNVC_CFG2_PRE_CSC_C33_C34_BASE_IDX 2 6026#define regCNVC_CFG2_PRE_CSC_B_C11_C12 0x0fbc 6027#define regCNVC_CFG2_PRE_CSC_B_C11_C12_BASE_IDX 2 6028#define regCNVC_CFG2_PRE_CSC_B_C13_C14 0x0fbd 6029#define regCNVC_CFG2_PRE_CSC_B_C13_C14_BASE_IDX 2 6030#define regCNVC_CFG2_PRE_CSC_B_C21_C22 0x0fbe 6031#define regCNVC_CFG2_PRE_CSC_B_C21_C22_BASE_IDX 2 6032#define regCNVC_CFG2_PRE_CSC_B_C23_C24 0x0fbf 6033#define regCNVC_CFG2_PRE_CSC_B_C23_C24_BASE_IDX 2 6034#define regCNVC_CFG2_PRE_CSC_B_C31_C32 0x0fc0 6035#define regCNVC_CFG2_PRE_CSC_B_C31_C32_BASE_IDX 2 6036#define regCNVC_CFG2_PRE_CSC_B_C33_C34 0x0fc1 6037#define regCNVC_CFG2_PRE_CSC_B_C33_C34_BASE_IDX 2 6038#define regCNVC_CFG2_CNVC_COEF_FORMAT 0x0fc2 6039#define regCNVC_CFG2_CNVC_COEF_FORMAT_BASE_IDX 2 6040#define regCNVC_CFG2_PRE_DEGAM 0x0fc3 6041#define regCNVC_CFG2_PRE_DEGAM_BASE_IDX 2 6042#define regCNVC_CFG2_PRE_REALPHA 0x0fc4 6043#define regCNVC_CFG2_PRE_REALPHA_BASE_IDX 2 6044 6045 6046// addressBlock: dce_dc_dpp2_dispdec_cnvc_cur_dispdec 6047// base address: 0xb58 6048#define regCNVC_CUR2_CURSOR0_CONTROL 0x0fc7 6049#define regCNVC_CUR2_CURSOR0_CONTROL_BASE_IDX 2 6050#define regCNVC_CUR2_CURSOR0_COLOR0 0x0fc8 6051#define regCNVC_CUR2_CURSOR0_COLOR0_BASE_IDX 2 6052#define regCNVC_CUR2_CURSOR0_COLOR1 0x0fc9 6053#define regCNVC_CUR2_CURSOR0_COLOR1_BASE_IDX 2 6054#define regCNVC_CUR2_CURSOR0_FP_SCALE_BIAS 0x0fca 6055#define regCNVC_CUR2_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 6056 6057 6058// addressBlock: dce_dc_dpp2_dispdec_dscl_dispdec 6059// base address: 0xb58 6060#define regDSCL2_SCL_COEF_RAM_TAP_SELECT 0x0fcf 6061#define regDSCL2_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 6062#define regDSCL2_SCL_COEF_RAM_TAP_DATA 0x0fd0 6063#define regDSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 6064#define regDSCL2_SCL_MODE 0x0fd1 6065#define regDSCL2_SCL_MODE_BASE_IDX 2 6066#define regDSCL2_SCL_TAP_CONTROL 0x0fd2 6067#define regDSCL2_SCL_TAP_CONTROL_BASE_IDX 2 6068#define regDSCL2_DSCL_CONTROL 0x0fd3 6069#define regDSCL2_DSCL_CONTROL_BASE_IDX 2 6070#define regDSCL2_DSCL_2TAP_CONTROL 0x0fd4 6071#define regDSCL2_DSCL_2TAP_CONTROL_BASE_IDX 2 6072#define regDSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x0fd5 6073#define regDSCL2_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 6074#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x0fd6 6075#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 6076#define regDSCL2_SCL_HORZ_FILTER_INIT 0x0fd7 6077#define regDSCL2_SCL_HORZ_FILTER_INIT_BASE_IDX 2 6078#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0fd8 6079#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 6080#define regDSCL2_SCL_HORZ_FILTER_INIT_C 0x0fd9 6081#define regDSCL2_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 6082#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x0fda 6083#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 6084#define regDSCL2_SCL_VERT_FILTER_INIT 0x0fdb 6085#define regDSCL2_SCL_VERT_FILTER_INIT_BASE_IDX 2 6086#define regDSCL2_SCL_VERT_FILTER_INIT_BOT 0x0fdc 6087#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 6088#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C 0x0fdd 6089#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 6090#define regDSCL2_SCL_VERT_FILTER_INIT_C 0x0fde 6091#define regDSCL2_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 6092#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_C 0x0fdf 6093#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 6094#define regDSCL2_SCL_BLACK_COLOR 0x0fe0 6095#define regDSCL2_SCL_BLACK_COLOR_BASE_IDX 2 6096#define regDSCL2_DSCL_UPDATE 0x0fe1 6097#define regDSCL2_DSCL_UPDATE_BASE_IDX 2 6098#define regDSCL2_DSCL_AUTOCAL 0x0fe2 6099#define regDSCL2_DSCL_AUTOCAL_BASE_IDX 2 6100#define regDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0fe3 6101#define regDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 6102#define regDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0fe4 6103#define regDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 6104#define regDSCL2_OTG_H_BLANK 0x0fe5 6105#define regDSCL2_OTG_H_BLANK_BASE_IDX 2 6106#define regDSCL2_OTG_V_BLANK 0x0fe6 6107#define regDSCL2_OTG_V_BLANK_BASE_IDX 2 6108#define regDSCL2_RECOUT_START 0x0fe7 6109#define regDSCL2_RECOUT_START_BASE_IDX 2 6110#define regDSCL2_RECOUT_SIZE 0x0fe8 6111#define regDSCL2_RECOUT_SIZE_BASE_IDX 2 6112#define regDSCL2_MPC_SIZE 0x0fe9 6113#define regDSCL2_MPC_SIZE_BASE_IDX 2 6114#define regDSCL2_LB_DATA_FORMAT 0x0fea 6115#define regDSCL2_LB_DATA_FORMAT_BASE_IDX 2 6116#define regDSCL2_LB_MEMORY_CTRL 0x0feb 6117#define regDSCL2_LB_MEMORY_CTRL_BASE_IDX 2 6118#define regDSCL2_LB_V_COUNTER 0x0fec 6119#define regDSCL2_LB_V_COUNTER_BASE_IDX 2 6120#define regDSCL2_DSCL_MEM_PWR_CTRL 0x0fed 6121#define regDSCL2_DSCL_MEM_PWR_CTRL_BASE_IDX 2 6122#define regDSCL2_DSCL_MEM_PWR_STATUS 0x0fee 6123#define regDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX 2 6124#define regDSCL2_OBUF_CONTROL 0x0fef 6125#define regDSCL2_OBUF_CONTROL_BASE_IDX 2 6126#define regDSCL2_OBUF_MEM_PWR_CTRL 0x0ff0 6127#define regDSCL2_OBUF_MEM_PWR_CTRL_BASE_IDX 2 6128 6129 6130// addressBlock: dce_dc_dpp2_dispdec_cm_dispdec 6131// base address: 0xb58 6132#define regCM2_CM_CONTROL 0x0ff6 6133#define regCM2_CM_CONTROL_BASE_IDX 2 6134#define regCM2_CM_POST_CSC_CONTROL 0x0ff7 6135#define regCM2_CM_POST_CSC_CONTROL_BASE_IDX 2 6136#define regCM2_CM_POST_CSC_C11_C12 0x0ff8 6137#define regCM2_CM_POST_CSC_C11_C12_BASE_IDX 2 6138#define regCM2_CM_POST_CSC_C13_C14 0x0ff9 6139#define regCM2_CM_POST_CSC_C13_C14_BASE_IDX 2 6140#define regCM2_CM_POST_CSC_C21_C22 0x0ffa 6141#define regCM2_CM_POST_CSC_C21_C22_BASE_IDX 2 6142#define regCM2_CM_POST_CSC_C23_C24 0x0ffb 6143#define regCM2_CM_POST_CSC_C23_C24_BASE_IDX 2 6144#define regCM2_CM_POST_CSC_C31_C32 0x0ffc 6145#define regCM2_CM_POST_CSC_C31_C32_BASE_IDX 2 6146#define regCM2_CM_POST_CSC_C33_C34 0x0ffd 6147#define regCM2_CM_POST_CSC_C33_C34_BASE_IDX 2 6148#define regCM2_CM_POST_CSC_B_C11_C12 0x0ffe 6149#define regCM2_CM_POST_CSC_B_C11_C12_BASE_IDX 2 6150#define regCM2_CM_POST_CSC_B_C13_C14 0x0fff 6151#define regCM2_CM_POST_CSC_B_C13_C14_BASE_IDX 2 6152#define regCM2_CM_POST_CSC_B_C21_C22 0x1000 6153#define regCM2_CM_POST_CSC_B_C21_C22_BASE_IDX 2 6154#define regCM2_CM_POST_CSC_B_C23_C24 0x1001 6155#define regCM2_CM_POST_CSC_B_C23_C24_BASE_IDX 2 6156#define regCM2_CM_POST_CSC_B_C31_C32 0x1002 6157#define regCM2_CM_POST_CSC_B_C31_C32_BASE_IDX 2 6158#define regCM2_CM_POST_CSC_B_C33_C34 0x1003 6159#define regCM2_CM_POST_CSC_B_C33_C34_BASE_IDX 2 6160#define regCM2_CM_GAMUT_REMAP_CONTROL 0x1004 6161#define regCM2_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 6162#define regCM2_CM_GAMUT_REMAP_C11_C12 0x1005 6163#define regCM2_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 6164#define regCM2_CM_GAMUT_REMAP_C13_C14 0x1006 6165#define regCM2_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 6166#define regCM2_CM_GAMUT_REMAP_C21_C22 0x1007 6167#define regCM2_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 6168#define regCM2_CM_GAMUT_REMAP_C23_C24 0x1008 6169#define regCM2_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 6170#define regCM2_CM_GAMUT_REMAP_C31_C32 0x1009 6171#define regCM2_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 6172#define regCM2_CM_GAMUT_REMAP_C33_C34 0x100a 6173#define regCM2_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 6174#define regCM2_CM_GAMUT_REMAP_B_C11_C12 0x100b 6175#define regCM2_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 6176#define regCM2_CM_GAMUT_REMAP_B_C13_C14 0x100c 6177#define regCM2_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 6178#define regCM2_CM_GAMUT_REMAP_B_C21_C22 0x100d 6179#define regCM2_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 6180#define regCM2_CM_GAMUT_REMAP_B_C23_C24 0x100e 6181#define regCM2_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 6182#define regCM2_CM_GAMUT_REMAP_B_C31_C32 0x100f 6183#define regCM2_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 6184#define regCM2_CM_GAMUT_REMAP_B_C33_C34 0x1010 6185#define regCM2_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 6186#define regCM2_CM_BIAS_CR_R 0x1011 6187#define regCM2_CM_BIAS_CR_R_BASE_IDX 2 6188#define regCM2_CM_BIAS_Y_G_CB_B 0x1012 6189#define regCM2_CM_BIAS_Y_G_CB_B_BASE_IDX 2 6190#define regCM2_CM_GAMCOR_CONTROL 0x1013 6191#define regCM2_CM_GAMCOR_CONTROL_BASE_IDX 2 6192#define regCM2_CM_GAMCOR_LUT_INDEX 0x1014 6193#define regCM2_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 6194#define regCM2_CM_GAMCOR_LUT_DATA 0x1015 6195#define regCM2_CM_GAMCOR_LUT_DATA_BASE_IDX 2 6196#define regCM2_CM_GAMCOR_LUT_CONTROL 0x1016 6197#define regCM2_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 6198#define regCM2_CM_GAMCOR_RAMA_START_CNTL_B 0x1017 6199#define regCM2_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 6200#define regCM2_CM_GAMCOR_RAMA_START_CNTL_G 0x1018 6201#define regCM2_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 6202#define regCM2_CM_GAMCOR_RAMA_START_CNTL_R 0x1019 6203#define regCM2_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 6204#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x101a 6205#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 6206#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x101b 6207#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 6208#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x101c 6209#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 6210#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x101d 6211#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 6212#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x101e 6213#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 6214#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x101f 6215#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 6216#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_B 0x1020 6217#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 6218#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_B 0x1021 6219#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 6220#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_G 0x1022 6221#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 6222#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_G 0x1023 6223#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 6224#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_R 0x1024 6225#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 6226#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_R 0x1025 6227#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 6228#define regCM2_CM_GAMCOR_RAMA_OFFSET_B 0x1026 6229#define regCM2_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 6230#define regCM2_CM_GAMCOR_RAMA_OFFSET_G 0x1027 6231#define regCM2_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 6232#define regCM2_CM_GAMCOR_RAMA_OFFSET_R 0x1028 6233#define regCM2_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 6234#define regCM2_CM_GAMCOR_RAMA_REGION_0_1 0x1029 6235#define regCM2_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 6236#define regCM2_CM_GAMCOR_RAMA_REGION_2_3 0x102a 6237#define regCM2_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 6238#define regCM2_CM_GAMCOR_RAMA_REGION_4_5 0x102b 6239#define regCM2_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 6240#define regCM2_CM_GAMCOR_RAMA_REGION_6_7 0x102c 6241#define regCM2_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 6242#define regCM2_CM_GAMCOR_RAMA_REGION_8_9 0x102d 6243#define regCM2_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 6244#define regCM2_CM_GAMCOR_RAMA_REGION_10_11 0x102e 6245#define regCM2_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 6246#define regCM2_CM_GAMCOR_RAMA_REGION_12_13 0x102f 6247#define regCM2_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 6248#define regCM2_CM_GAMCOR_RAMA_REGION_14_15 0x1030 6249#define regCM2_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 6250#define regCM2_CM_GAMCOR_RAMA_REGION_16_17 0x1031 6251#define regCM2_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 6252#define regCM2_CM_GAMCOR_RAMA_REGION_18_19 0x1032 6253#define regCM2_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 6254#define regCM2_CM_GAMCOR_RAMA_REGION_20_21 0x1033 6255#define regCM2_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 6256#define regCM2_CM_GAMCOR_RAMA_REGION_22_23 0x1034 6257#define regCM2_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 6258#define regCM2_CM_GAMCOR_RAMA_REGION_24_25 0x1035 6259#define regCM2_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 6260#define regCM2_CM_GAMCOR_RAMA_REGION_26_27 0x1036 6261#define regCM2_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 6262#define regCM2_CM_GAMCOR_RAMA_REGION_28_29 0x1037 6263#define regCM2_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 6264#define regCM2_CM_GAMCOR_RAMA_REGION_30_31 0x1038 6265#define regCM2_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 6266#define regCM2_CM_GAMCOR_RAMA_REGION_32_33 0x1039 6267#define regCM2_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 6268#define regCM2_CM_GAMCOR_RAMB_START_CNTL_B 0x103a 6269#define regCM2_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 6270#define regCM2_CM_GAMCOR_RAMB_START_CNTL_G 0x103b 6271#define regCM2_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 6272#define regCM2_CM_GAMCOR_RAMB_START_CNTL_R 0x103c 6273#define regCM2_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 6274#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x103d 6275#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 6276#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x103e 6277#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 6278#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x103f 6279#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 6280#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x1040 6281#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 6282#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x1041 6283#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 6284#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x1042 6285#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 6286#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_B 0x1043 6287#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 6288#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_B 0x1044 6289#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 6290#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_G 0x1045 6291#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 6292#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_G 0x1046 6293#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 6294#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_R 0x1047 6295#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 6296#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_R 0x1048 6297#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 6298#define regCM2_CM_GAMCOR_RAMB_OFFSET_B 0x1049 6299#define regCM2_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 6300#define regCM2_CM_GAMCOR_RAMB_OFFSET_G 0x104a 6301#define regCM2_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 6302#define regCM2_CM_GAMCOR_RAMB_OFFSET_R 0x104b 6303#define regCM2_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 6304#define regCM2_CM_GAMCOR_RAMB_REGION_0_1 0x104c 6305#define regCM2_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 6306#define regCM2_CM_GAMCOR_RAMB_REGION_2_3 0x104d 6307#define regCM2_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 6308#define regCM2_CM_GAMCOR_RAMB_REGION_4_5 0x104e 6309#define regCM2_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 6310#define regCM2_CM_GAMCOR_RAMB_REGION_6_7 0x104f 6311#define regCM2_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 6312#define regCM2_CM_GAMCOR_RAMB_REGION_8_9 0x1050 6313#define regCM2_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 6314#define regCM2_CM_GAMCOR_RAMB_REGION_10_11 0x1051 6315#define regCM2_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 6316#define regCM2_CM_GAMCOR_RAMB_REGION_12_13 0x1052 6317#define regCM2_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 6318#define regCM2_CM_GAMCOR_RAMB_REGION_14_15 0x1053 6319#define regCM2_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 6320#define regCM2_CM_GAMCOR_RAMB_REGION_16_17 0x1054 6321#define regCM2_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 6322#define regCM2_CM_GAMCOR_RAMB_REGION_18_19 0x1055 6323#define regCM2_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 6324#define regCM2_CM_GAMCOR_RAMB_REGION_20_21 0x1056 6325#define regCM2_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 6326#define regCM2_CM_GAMCOR_RAMB_REGION_22_23 0x1057 6327#define regCM2_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 6328#define regCM2_CM_GAMCOR_RAMB_REGION_24_25 0x1058 6329#define regCM2_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 6330#define regCM2_CM_GAMCOR_RAMB_REGION_26_27 0x1059 6331#define regCM2_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 6332#define regCM2_CM_GAMCOR_RAMB_REGION_28_29 0x105a 6333#define regCM2_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 6334#define regCM2_CM_GAMCOR_RAMB_REGION_30_31 0x105b 6335#define regCM2_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 6336#define regCM2_CM_GAMCOR_RAMB_REGION_32_33 0x105c 6337#define regCM2_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 6338#define regCM2_CM_BLNDGAM_CONTROL 0x105d 6339#define regCM2_CM_BLNDGAM_CONTROL_BASE_IDX 2 6340#define regCM2_CM_BLNDGAM_LUT_INDEX 0x105e 6341#define regCM2_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2 6342#define regCM2_CM_BLNDGAM_LUT_DATA 0x105f 6343#define regCM2_CM_BLNDGAM_LUT_DATA_BASE_IDX 2 6344#define regCM2_CM_BLNDGAM_LUT_CONTROL 0x1060 6345#define regCM2_CM_BLNDGAM_LUT_CONTROL_BASE_IDX 2 6346#define regCM2_CM_BLNDGAM_RAMA_START_CNTL_B 0x1061 6347#define regCM2_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2 6348#define regCM2_CM_BLNDGAM_RAMA_START_CNTL_G 0x1062 6349#define regCM2_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2 6350#define regCM2_CM_BLNDGAM_RAMA_START_CNTL_R 0x1063 6351#define regCM2_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2 6352#define regCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B 0x1064 6353#define regCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 6354#define regCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G 0x1065 6355#define regCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 6356#define regCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R 0x1066 6357#define regCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 6358#define regCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_B 0x1067 6359#define regCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2 6360#define regCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_G 0x1068 6361#define regCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2 6362#define regCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_R 0x1069 6363#define regCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2 6364#define regCM2_CM_BLNDGAM_RAMA_END_CNTL1_B 0x106a 6365#define regCM2_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2 6366#define regCM2_CM_BLNDGAM_RAMA_END_CNTL2_B 0x106b 6367#define regCM2_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2 6368#define regCM2_CM_BLNDGAM_RAMA_END_CNTL1_G 0x106c 6369#define regCM2_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2 6370#define regCM2_CM_BLNDGAM_RAMA_END_CNTL2_G 0x106d 6371#define regCM2_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2 6372#define regCM2_CM_BLNDGAM_RAMA_END_CNTL1_R 0x106e 6373#define regCM2_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2 6374#define regCM2_CM_BLNDGAM_RAMA_END_CNTL2_R 0x106f 6375#define regCM2_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2 6376#define regCM2_CM_BLNDGAM_RAMA_OFFSET_B 0x1070 6377#define regCM2_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX 2 6378#define regCM2_CM_BLNDGAM_RAMA_OFFSET_G 0x1071 6379#define regCM2_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX 2 6380#define regCM2_CM_BLNDGAM_RAMA_OFFSET_R 0x1072 6381#define regCM2_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX 2 6382#define regCM2_CM_BLNDGAM_RAMA_REGION_0_1 0x1073 6383#define regCM2_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2 6384#define regCM2_CM_BLNDGAM_RAMA_REGION_2_3 0x1074 6385#define regCM2_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2 6386#define regCM2_CM_BLNDGAM_RAMA_REGION_4_5 0x1075 6387#define regCM2_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2 6388#define regCM2_CM_BLNDGAM_RAMA_REGION_6_7 0x1076 6389#define regCM2_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2 6390#define regCM2_CM_BLNDGAM_RAMA_REGION_8_9 0x1077 6391#define regCM2_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2 6392#define regCM2_CM_BLNDGAM_RAMA_REGION_10_11 0x1078 6393#define regCM2_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2 6394#define regCM2_CM_BLNDGAM_RAMA_REGION_12_13 0x1079 6395#define regCM2_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2 6396#define regCM2_CM_BLNDGAM_RAMA_REGION_14_15 0x107a 6397#define regCM2_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2 6398#define regCM2_CM_BLNDGAM_RAMA_REGION_16_17 0x107b 6399#define regCM2_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2 6400#define regCM2_CM_BLNDGAM_RAMA_REGION_18_19 0x107c 6401#define regCM2_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2 6402#define regCM2_CM_BLNDGAM_RAMA_REGION_20_21 0x107d 6403#define regCM2_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2 6404#define regCM2_CM_BLNDGAM_RAMA_REGION_22_23 0x107e 6405#define regCM2_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2 6406#define regCM2_CM_BLNDGAM_RAMA_REGION_24_25 0x107f 6407#define regCM2_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2 6408#define regCM2_CM_BLNDGAM_RAMA_REGION_26_27 0x1080 6409#define regCM2_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2 6410#define regCM2_CM_BLNDGAM_RAMA_REGION_28_29 0x1081 6411#define regCM2_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2 6412#define regCM2_CM_BLNDGAM_RAMA_REGION_30_31 0x1082 6413#define regCM2_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2 6414#define regCM2_CM_BLNDGAM_RAMA_REGION_32_33 0x1083 6415#define regCM2_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2 6416#define regCM2_CM_BLNDGAM_RAMB_START_CNTL_B 0x1084 6417#define regCM2_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2 6418#define regCM2_CM_BLNDGAM_RAMB_START_CNTL_G 0x1085 6419#define regCM2_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2 6420#define regCM2_CM_BLNDGAM_RAMB_START_CNTL_R 0x1086 6421#define regCM2_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2 6422#define regCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B 0x1087 6423#define regCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 6424#define regCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G 0x1088 6425#define regCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 6426#define regCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R 0x1089 6427#define regCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 6428#define regCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_B 0x108a 6429#define regCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2 6430#define regCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_G 0x108b 6431#define regCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2 6432#define regCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_R 0x108c 6433#define regCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2 6434#define regCM2_CM_BLNDGAM_RAMB_END_CNTL1_B 0x108d 6435#define regCM2_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2 6436#define regCM2_CM_BLNDGAM_RAMB_END_CNTL2_B 0x108e 6437#define regCM2_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2 6438#define regCM2_CM_BLNDGAM_RAMB_END_CNTL1_G 0x108f 6439#define regCM2_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2 6440#define regCM2_CM_BLNDGAM_RAMB_END_CNTL2_G 0x1090 6441#define regCM2_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2 6442#define regCM2_CM_BLNDGAM_RAMB_END_CNTL1_R 0x1091 6443#define regCM2_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2 6444#define regCM2_CM_BLNDGAM_RAMB_END_CNTL2_R 0x1092 6445#define regCM2_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2 6446#define regCM2_CM_BLNDGAM_RAMB_OFFSET_B 0x1093 6447#define regCM2_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX 2 6448#define regCM2_CM_BLNDGAM_RAMB_OFFSET_G 0x1094 6449#define regCM2_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX 2 6450#define regCM2_CM_BLNDGAM_RAMB_OFFSET_R 0x1095 6451#define regCM2_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX 2 6452#define regCM2_CM_BLNDGAM_RAMB_REGION_0_1 0x1096 6453#define regCM2_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2 6454#define regCM2_CM_BLNDGAM_RAMB_REGION_2_3 0x1097 6455#define regCM2_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2 6456#define regCM2_CM_BLNDGAM_RAMB_REGION_4_5 0x1098 6457#define regCM2_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2 6458#define regCM2_CM_BLNDGAM_RAMB_REGION_6_7 0x1099 6459#define regCM2_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2 6460#define regCM2_CM_BLNDGAM_RAMB_REGION_8_9 0x109a 6461#define regCM2_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2 6462#define regCM2_CM_BLNDGAM_RAMB_REGION_10_11 0x109b 6463#define regCM2_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2 6464#define regCM2_CM_BLNDGAM_RAMB_REGION_12_13 0x109c 6465#define regCM2_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2 6466#define regCM2_CM_BLNDGAM_RAMB_REGION_14_15 0x109d 6467#define regCM2_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2 6468#define regCM2_CM_BLNDGAM_RAMB_REGION_16_17 0x109e 6469#define regCM2_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2 6470#define regCM2_CM_BLNDGAM_RAMB_REGION_18_19 0x109f 6471#define regCM2_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2 6472#define regCM2_CM_BLNDGAM_RAMB_REGION_20_21 0x10a0 6473#define regCM2_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2 6474#define regCM2_CM_BLNDGAM_RAMB_REGION_22_23 0x10a1 6475#define regCM2_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2 6476#define regCM2_CM_BLNDGAM_RAMB_REGION_24_25 0x10a2 6477#define regCM2_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2 6478#define regCM2_CM_BLNDGAM_RAMB_REGION_26_27 0x10a3 6479#define regCM2_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2 6480#define regCM2_CM_BLNDGAM_RAMB_REGION_28_29 0x10a4 6481#define regCM2_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2 6482#define regCM2_CM_BLNDGAM_RAMB_REGION_30_31 0x10a5 6483#define regCM2_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2 6484#define regCM2_CM_BLNDGAM_RAMB_REGION_32_33 0x10a6 6485#define regCM2_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2 6486#define regCM2_CM_HDR_MULT_COEF 0x10a7 6487#define regCM2_CM_HDR_MULT_COEF_BASE_IDX 2 6488#define regCM2_CM_MEM_PWR_CTRL 0x10a8 6489#define regCM2_CM_MEM_PWR_CTRL_BASE_IDX 2 6490#define regCM2_CM_MEM_PWR_STATUS 0x10a9 6491#define regCM2_CM_MEM_PWR_STATUS_BASE_IDX 2 6492#define regCM2_CM_DEALPHA 0x10ab 6493#define regCM2_CM_DEALPHA_BASE_IDX 2 6494#define regCM2_CM_COEF_FORMAT 0x10ac 6495#define regCM2_CM_COEF_FORMAT_BASE_IDX 2 6496#define regCM2_CM_SHAPER_CONTROL 0x10ad 6497#define regCM2_CM_SHAPER_CONTROL_BASE_IDX 2 6498#define regCM2_CM_SHAPER_OFFSET_R 0x10ae 6499#define regCM2_CM_SHAPER_OFFSET_R_BASE_IDX 2 6500#define regCM2_CM_SHAPER_OFFSET_G 0x10af 6501#define regCM2_CM_SHAPER_OFFSET_G_BASE_IDX 2 6502#define regCM2_CM_SHAPER_OFFSET_B 0x10b0 6503#define regCM2_CM_SHAPER_OFFSET_B_BASE_IDX 2 6504#define regCM2_CM_SHAPER_SCALE_R 0x10b1 6505#define regCM2_CM_SHAPER_SCALE_R_BASE_IDX 2 6506#define regCM2_CM_SHAPER_SCALE_G_B 0x10b2 6507#define regCM2_CM_SHAPER_SCALE_G_B_BASE_IDX 2 6508#define regCM2_CM_SHAPER_LUT_INDEX 0x10b3 6509#define regCM2_CM_SHAPER_LUT_INDEX_BASE_IDX 2 6510#define regCM2_CM_SHAPER_LUT_DATA 0x10b4 6511#define regCM2_CM_SHAPER_LUT_DATA_BASE_IDX 2 6512#define regCM2_CM_SHAPER_LUT_WRITE_EN_MASK 0x10b5 6513#define regCM2_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2 6514#define regCM2_CM_SHAPER_RAMA_START_CNTL_B 0x10b6 6515#define regCM2_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2 6516#define regCM2_CM_SHAPER_RAMA_START_CNTL_G 0x10b7 6517#define regCM2_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2 6518#define regCM2_CM_SHAPER_RAMA_START_CNTL_R 0x10b8 6519#define regCM2_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2 6520#define regCM2_CM_SHAPER_RAMA_END_CNTL_B 0x10b9 6521#define regCM2_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2 6522#define regCM2_CM_SHAPER_RAMA_END_CNTL_G 0x10ba 6523#define regCM2_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2 6524#define regCM2_CM_SHAPER_RAMA_END_CNTL_R 0x10bb 6525#define regCM2_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2 6526#define regCM2_CM_SHAPER_RAMA_REGION_0_1 0x10bc 6527#define regCM2_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2 6528#define regCM2_CM_SHAPER_RAMA_REGION_2_3 0x10bd 6529#define regCM2_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2 6530#define regCM2_CM_SHAPER_RAMA_REGION_4_5 0x10be 6531#define regCM2_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2 6532#define regCM2_CM_SHAPER_RAMA_REGION_6_7 0x10bf 6533#define regCM2_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2 6534#define regCM2_CM_SHAPER_RAMA_REGION_8_9 0x10c0 6535#define regCM2_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2 6536#define regCM2_CM_SHAPER_RAMA_REGION_10_11 0x10c1 6537#define regCM2_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2 6538#define regCM2_CM_SHAPER_RAMA_REGION_12_13 0x10c2 6539#define regCM2_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2 6540#define regCM2_CM_SHAPER_RAMA_REGION_14_15 0x10c3 6541#define regCM2_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2 6542#define regCM2_CM_SHAPER_RAMA_REGION_16_17 0x10c4 6543#define regCM2_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2 6544#define regCM2_CM_SHAPER_RAMA_REGION_18_19 0x10c5 6545#define regCM2_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2 6546#define regCM2_CM_SHAPER_RAMA_REGION_20_21 0x10c6 6547#define regCM2_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2 6548#define regCM2_CM_SHAPER_RAMA_REGION_22_23 0x10c7 6549#define regCM2_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2 6550#define regCM2_CM_SHAPER_RAMA_REGION_24_25 0x10c8 6551#define regCM2_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2 6552#define regCM2_CM_SHAPER_RAMA_REGION_26_27 0x10c9 6553#define regCM2_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2 6554#define regCM2_CM_SHAPER_RAMA_REGION_28_29 0x10ca 6555#define regCM2_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2 6556#define regCM2_CM_SHAPER_RAMA_REGION_30_31 0x10cb 6557#define regCM2_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2 6558#define regCM2_CM_SHAPER_RAMA_REGION_32_33 0x10cc 6559#define regCM2_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2 6560#define regCM2_CM_SHAPER_RAMB_START_CNTL_B 0x10cd 6561#define regCM2_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2 6562#define regCM2_CM_SHAPER_RAMB_START_CNTL_G 0x10ce 6563#define regCM2_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2 6564#define regCM2_CM_SHAPER_RAMB_START_CNTL_R 0x10cf 6565#define regCM2_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2 6566#define regCM2_CM_SHAPER_RAMB_END_CNTL_B 0x10d0 6567#define regCM2_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2 6568#define regCM2_CM_SHAPER_RAMB_END_CNTL_G 0x10d1 6569#define regCM2_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2 6570#define regCM2_CM_SHAPER_RAMB_END_CNTL_R 0x10d2 6571#define regCM2_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2 6572#define regCM2_CM_SHAPER_RAMB_REGION_0_1 0x10d3 6573#define regCM2_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2 6574#define regCM2_CM_SHAPER_RAMB_REGION_2_3 0x10d4 6575#define regCM2_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2 6576#define regCM2_CM_SHAPER_RAMB_REGION_4_5 0x10d5 6577#define regCM2_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2 6578#define regCM2_CM_SHAPER_RAMB_REGION_6_7 0x10d6 6579#define regCM2_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2 6580#define regCM2_CM_SHAPER_RAMB_REGION_8_9 0x10d7 6581#define regCM2_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2 6582#define regCM2_CM_SHAPER_RAMB_REGION_10_11 0x10d8 6583#define regCM2_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2 6584#define regCM2_CM_SHAPER_RAMB_REGION_12_13 0x10d9 6585#define regCM2_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2 6586#define regCM2_CM_SHAPER_RAMB_REGION_14_15 0x10da 6587#define regCM2_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2 6588#define regCM2_CM_SHAPER_RAMB_REGION_16_17 0x10db 6589#define regCM2_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2 6590#define regCM2_CM_SHAPER_RAMB_REGION_18_19 0x10dc 6591#define regCM2_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2 6592#define regCM2_CM_SHAPER_RAMB_REGION_20_21 0x10dd 6593#define regCM2_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2 6594#define regCM2_CM_SHAPER_RAMB_REGION_22_23 0x10de 6595#define regCM2_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2 6596#define regCM2_CM_SHAPER_RAMB_REGION_24_25 0x10df 6597#define regCM2_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2 6598#define regCM2_CM_SHAPER_RAMB_REGION_26_27 0x10e0 6599#define regCM2_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2 6600#define regCM2_CM_SHAPER_RAMB_REGION_28_29 0x10e1 6601#define regCM2_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2 6602#define regCM2_CM_SHAPER_RAMB_REGION_30_31 0x10e2 6603#define regCM2_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2 6604#define regCM2_CM_SHAPER_RAMB_REGION_32_33 0x10e3 6605#define regCM2_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2 6606#define regCM2_CM_MEM_PWR_CTRL2 0x10e4 6607#define regCM2_CM_MEM_PWR_CTRL2_BASE_IDX 2 6608#define regCM2_CM_MEM_PWR_STATUS2 0x10e5 6609#define regCM2_CM_MEM_PWR_STATUS2_BASE_IDX 2 6610#define regCM2_CM_3DLUT_MODE 0x10e6 6611#define regCM2_CM_3DLUT_MODE_BASE_IDX 2 6612#define regCM2_CM_3DLUT_INDEX 0x10e7 6613#define regCM2_CM_3DLUT_INDEX_BASE_IDX 2 6614#define regCM2_CM_3DLUT_DATA 0x10e8 6615#define regCM2_CM_3DLUT_DATA_BASE_IDX 2 6616#define regCM2_CM_3DLUT_DATA_30BIT 0x10e9 6617#define regCM2_CM_3DLUT_DATA_30BIT_BASE_IDX 2 6618#define regCM2_CM_3DLUT_READ_WRITE_CONTROL 0x10ea 6619#define regCM2_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2 6620#define regCM2_CM_3DLUT_OUT_NORM_FACTOR 0x10eb 6621#define regCM2_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2 6622#define regCM2_CM_3DLUT_OUT_OFFSET_R 0x10ec 6623#define regCM2_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2 6624#define regCM2_CM_3DLUT_OUT_OFFSET_G 0x10ed 6625#define regCM2_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2 6626#define regCM2_CM_3DLUT_OUT_OFFSET_B 0x10ee 6627#define regCM2_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2 6628#define regCM2_CM_TEST_DEBUG_INDEX 0x10ef 6629#define regCM2_CM_TEST_DEBUG_INDEX_BASE_IDX 2 6630#define regCM2_CM_TEST_DEBUG_DATA 0x10f0 6631#define regCM2_CM_TEST_DEBUG_DATA_BASE_IDX 2 6632 6633 6634// addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec 6635// base address: 0x43e8 6636#define regDC_PERFMON12_PERFCOUNTER_CNTL 0x10fa 6637#define regDC_PERFMON12_PERFCOUNTER_CNTL_BASE_IDX 2 6638#define regDC_PERFMON12_PERFCOUNTER_CNTL2 0x10fb 6639#define regDC_PERFMON12_PERFCOUNTER_CNTL2_BASE_IDX 2 6640#define regDC_PERFMON12_PERFCOUNTER_STATE 0x10fc 6641#define regDC_PERFMON12_PERFCOUNTER_STATE_BASE_IDX 2 6642#define regDC_PERFMON12_PERFMON_CNTL 0x10fd 6643#define regDC_PERFMON12_PERFMON_CNTL_BASE_IDX 2 6644#define regDC_PERFMON12_PERFMON_CNTL2 0x10fe 6645#define regDC_PERFMON12_PERFMON_CNTL2_BASE_IDX 2 6646#define regDC_PERFMON12_PERFMON_CVALUE_INT_MISC 0x10ff 6647#define regDC_PERFMON12_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 6648#define regDC_PERFMON12_PERFMON_CVALUE_LOW 0x1100 6649#define regDC_PERFMON12_PERFMON_CVALUE_LOW_BASE_IDX 2 6650#define regDC_PERFMON12_PERFMON_HI 0x1101 6651#define regDC_PERFMON12_PERFMON_HI_BASE_IDX 2 6652#define regDC_PERFMON12_PERFMON_LOW 0x1102 6653#define regDC_PERFMON12_PERFMON_LOW_BASE_IDX 2 6654 6655 6656// addressBlock: dce_dc_dpp3_dispdec_dpp_top_dispdec 6657// base address: 0x1104 6658#define regDPP_TOP3_DPP_CONTROL 0x1106 6659#define regDPP_TOP3_DPP_CONTROL_BASE_IDX 2 6660#define regDPP_TOP3_DPP_SOFT_RESET 0x1107 6661#define regDPP_TOP3_DPP_SOFT_RESET_BASE_IDX 2 6662#define regDPP_TOP3_DPP_CRC_VAL_R_G 0x1108 6663#define regDPP_TOP3_DPP_CRC_VAL_R_G_BASE_IDX 2 6664#define regDPP_TOP3_DPP_CRC_VAL_B_A 0x1109 6665#define regDPP_TOP3_DPP_CRC_VAL_B_A_BASE_IDX 2 6666#define regDPP_TOP3_DPP_CRC_CTRL 0x110a 6667#define regDPP_TOP3_DPP_CRC_CTRL_BASE_IDX 2 6668#define regDPP_TOP3_HOST_READ_CONTROL 0x110b 6669#define regDPP_TOP3_HOST_READ_CONTROL_BASE_IDX 2 6670 6671 6672// addressBlock: dce_dc_dpp3_dispdec_cnvc_cfg_dispdec 6673// base address: 0x1104 6674#define regCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT 0x1110 6675#define regCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 6676#define regCNVC_CFG3_FORMAT_CONTROL 0x1111 6677#define regCNVC_CFG3_FORMAT_CONTROL_BASE_IDX 2 6678#define regCNVC_CFG3_FCNV_FP_BIAS_R 0x1112 6679#define regCNVC_CFG3_FCNV_FP_BIAS_R_BASE_IDX 2 6680#define regCNVC_CFG3_FCNV_FP_BIAS_G 0x1113 6681#define regCNVC_CFG3_FCNV_FP_BIAS_G_BASE_IDX 2 6682#define regCNVC_CFG3_FCNV_FP_BIAS_B 0x1114 6683#define regCNVC_CFG3_FCNV_FP_BIAS_B_BASE_IDX 2 6684#define regCNVC_CFG3_FCNV_FP_SCALE_R 0x1115 6685#define regCNVC_CFG3_FCNV_FP_SCALE_R_BASE_IDX 2 6686#define regCNVC_CFG3_FCNV_FP_SCALE_G 0x1116 6687#define regCNVC_CFG3_FCNV_FP_SCALE_G_BASE_IDX 2 6688#define regCNVC_CFG3_FCNV_FP_SCALE_B 0x1117 6689#define regCNVC_CFG3_FCNV_FP_SCALE_B_BASE_IDX 2 6690#define regCNVC_CFG3_COLOR_KEYER_CONTROL 0x1118 6691#define regCNVC_CFG3_COLOR_KEYER_CONTROL_BASE_IDX 2 6692#define regCNVC_CFG3_COLOR_KEYER_ALPHA 0x1119 6693#define regCNVC_CFG3_COLOR_KEYER_ALPHA_BASE_IDX 2 6694#define regCNVC_CFG3_COLOR_KEYER_RED 0x111a 6695#define regCNVC_CFG3_COLOR_KEYER_RED_BASE_IDX 2 6696#define regCNVC_CFG3_COLOR_KEYER_GREEN 0x111b 6697#define regCNVC_CFG3_COLOR_KEYER_GREEN_BASE_IDX 2 6698#define regCNVC_CFG3_COLOR_KEYER_BLUE 0x111c 6699#define regCNVC_CFG3_COLOR_KEYER_BLUE_BASE_IDX 2 6700#define regCNVC_CFG3_ALPHA_2BIT_LUT 0x111e 6701#define regCNVC_CFG3_ALPHA_2BIT_LUT_BASE_IDX 2 6702#define regCNVC_CFG3_PRE_DEALPHA 0x111f 6703#define regCNVC_CFG3_PRE_DEALPHA_BASE_IDX 2 6704#define regCNVC_CFG3_PRE_CSC_MODE 0x1120 6705#define regCNVC_CFG3_PRE_CSC_MODE_BASE_IDX 2 6706#define regCNVC_CFG3_PRE_CSC_C11_C12 0x1121 6707#define regCNVC_CFG3_PRE_CSC_C11_C12_BASE_IDX 2 6708#define regCNVC_CFG3_PRE_CSC_C13_C14 0x1122 6709#define regCNVC_CFG3_PRE_CSC_C13_C14_BASE_IDX 2 6710#define regCNVC_CFG3_PRE_CSC_C21_C22 0x1123 6711#define regCNVC_CFG3_PRE_CSC_C21_C22_BASE_IDX 2 6712#define regCNVC_CFG3_PRE_CSC_C23_C24 0x1124 6713#define regCNVC_CFG3_PRE_CSC_C23_C24_BASE_IDX 2 6714#define regCNVC_CFG3_PRE_CSC_C31_C32 0x1125 6715#define regCNVC_CFG3_PRE_CSC_C31_C32_BASE_IDX 2 6716#define regCNVC_CFG3_PRE_CSC_C33_C34 0x1126 6717#define regCNVC_CFG3_PRE_CSC_C33_C34_BASE_IDX 2 6718#define regCNVC_CFG3_PRE_CSC_B_C11_C12 0x1127 6719#define regCNVC_CFG3_PRE_CSC_B_C11_C12_BASE_IDX 2 6720#define regCNVC_CFG3_PRE_CSC_B_C13_C14 0x1128 6721#define regCNVC_CFG3_PRE_CSC_B_C13_C14_BASE_IDX 2 6722#define regCNVC_CFG3_PRE_CSC_B_C21_C22 0x1129 6723#define regCNVC_CFG3_PRE_CSC_B_C21_C22_BASE_IDX 2 6724#define regCNVC_CFG3_PRE_CSC_B_C23_C24 0x112a 6725#define regCNVC_CFG3_PRE_CSC_B_C23_C24_BASE_IDX 2 6726#define regCNVC_CFG3_PRE_CSC_B_C31_C32 0x112b 6727#define regCNVC_CFG3_PRE_CSC_B_C31_C32_BASE_IDX 2 6728#define regCNVC_CFG3_PRE_CSC_B_C33_C34 0x112c 6729#define regCNVC_CFG3_PRE_CSC_B_C33_C34_BASE_IDX 2 6730#define regCNVC_CFG3_CNVC_COEF_FORMAT 0x112d 6731#define regCNVC_CFG3_CNVC_COEF_FORMAT_BASE_IDX 2 6732#define regCNVC_CFG3_PRE_DEGAM 0x112e 6733#define regCNVC_CFG3_PRE_DEGAM_BASE_IDX 2 6734#define regCNVC_CFG3_PRE_REALPHA 0x112f 6735#define regCNVC_CFG3_PRE_REALPHA_BASE_IDX 2 6736 6737 6738// addressBlock: dce_dc_dpp3_dispdec_cnvc_cur_dispdec 6739// base address: 0x1104 6740#define regCNVC_CUR3_CURSOR0_CONTROL 0x1132 6741#define regCNVC_CUR3_CURSOR0_CONTROL_BASE_IDX 2 6742#define regCNVC_CUR3_CURSOR0_COLOR0 0x1133 6743#define regCNVC_CUR3_CURSOR0_COLOR0_BASE_IDX 2 6744#define regCNVC_CUR3_CURSOR0_COLOR1 0x1134 6745#define regCNVC_CUR3_CURSOR0_COLOR1_BASE_IDX 2 6746#define regCNVC_CUR3_CURSOR0_FP_SCALE_BIAS 0x1135 6747#define regCNVC_CUR3_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 6748 6749 6750// addressBlock: dce_dc_dpp3_dispdec_dscl_dispdec 6751// base address: 0x1104 6752#define regDSCL3_SCL_COEF_RAM_TAP_SELECT 0x113a 6753#define regDSCL3_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 6754#define regDSCL3_SCL_COEF_RAM_TAP_DATA 0x113b 6755#define regDSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 6756#define regDSCL3_SCL_MODE 0x113c 6757#define regDSCL3_SCL_MODE_BASE_IDX 2 6758#define regDSCL3_SCL_TAP_CONTROL 0x113d 6759#define regDSCL3_SCL_TAP_CONTROL_BASE_IDX 2 6760#define regDSCL3_DSCL_CONTROL 0x113e 6761#define regDSCL3_DSCL_CONTROL_BASE_IDX 2 6762#define regDSCL3_DSCL_2TAP_CONTROL 0x113f 6763#define regDSCL3_DSCL_2TAP_CONTROL_BASE_IDX 2 6764#define regDSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x1140 6765#define regDSCL3_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 6766#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x1141 6767#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 6768#define regDSCL3_SCL_HORZ_FILTER_INIT 0x1142 6769#define regDSCL3_SCL_HORZ_FILTER_INIT_BASE_IDX 2 6770#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C 0x1143 6771#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 6772#define regDSCL3_SCL_HORZ_FILTER_INIT_C 0x1144 6773#define regDSCL3_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 6774#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x1145 6775#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 6776#define regDSCL3_SCL_VERT_FILTER_INIT 0x1146 6777#define regDSCL3_SCL_VERT_FILTER_INIT_BASE_IDX 2 6778#define regDSCL3_SCL_VERT_FILTER_INIT_BOT 0x1147 6779#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 6780#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C 0x1148 6781#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 6782#define regDSCL3_SCL_VERT_FILTER_INIT_C 0x1149 6783#define regDSCL3_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 6784#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_C 0x114a 6785#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 6786#define regDSCL3_SCL_BLACK_COLOR 0x114b 6787#define regDSCL3_SCL_BLACK_COLOR_BASE_IDX 2 6788#define regDSCL3_DSCL_UPDATE 0x114c 6789#define regDSCL3_DSCL_UPDATE_BASE_IDX 2 6790#define regDSCL3_DSCL_AUTOCAL 0x114d 6791#define regDSCL3_DSCL_AUTOCAL_BASE_IDX 2 6792#define regDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x114e 6793#define regDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 6794#define regDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x114f 6795#define regDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 6796#define regDSCL3_OTG_H_BLANK 0x1150 6797#define regDSCL3_OTG_H_BLANK_BASE_IDX 2 6798#define regDSCL3_OTG_V_BLANK 0x1151 6799#define regDSCL3_OTG_V_BLANK_BASE_IDX 2 6800#define regDSCL3_RECOUT_START 0x1152 6801#define regDSCL3_RECOUT_START_BASE_IDX 2 6802#define regDSCL3_RECOUT_SIZE 0x1153 6803#define regDSCL3_RECOUT_SIZE_BASE_IDX 2 6804#define regDSCL3_MPC_SIZE 0x1154 6805#define regDSCL3_MPC_SIZE_BASE_IDX 2 6806#define regDSCL3_LB_DATA_FORMAT 0x1155 6807#define regDSCL3_LB_DATA_FORMAT_BASE_IDX 2 6808#define regDSCL3_LB_MEMORY_CTRL 0x1156 6809#define regDSCL3_LB_MEMORY_CTRL_BASE_IDX 2 6810#define regDSCL3_LB_V_COUNTER 0x1157 6811#define regDSCL3_LB_V_COUNTER_BASE_IDX 2 6812#define regDSCL3_DSCL_MEM_PWR_CTRL 0x1158 6813#define regDSCL3_DSCL_MEM_PWR_CTRL_BASE_IDX 2 6814#define regDSCL3_DSCL_MEM_PWR_STATUS 0x1159 6815#define regDSCL3_DSCL_MEM_PWR_STATUS_BASE_IDX 2 6816#define regDSCL3_OBUF_CONTROL 0x115a 6817#define regDSCL3_OBUF_CONTROL_BASE_IDX 2 6818#define regDSCL3_OBUF_MEM_PWR_CTRL 0x115b 6819#define regDSCL3_OBUF_MEM_PWR_CTRL_BASE_IDX 2 6820 6821 6822// addressBlock: dce_dc_dpp3_dispdec_cm_dispdec 6823// base address: 0x1104 6824#define regCM3_CM_CONTROL 0x1161 6825#define regCM3_CM_CONTROL_BASE_IDX 2 6826#define regCM3_CM_POST_CSC_CONTROL 0x1162 6827#define regCM3_CM_POST_CSC_CONTROL_BASE_IDX 2 6828#define regCM3_CM_POST_CSC_C11_C12 0x1163 6829#define regCM3_CM_POST_CSC_C11_C12_BASE_IDX 2 6830#define regCM3_CM_POST_CSC_C13_C14 0x1164 6831#define regCM3_CM_POST_CSC_C13_C14_BASE_IDX 2 6832#define regCM3_CM_POST_CSC_C21_C22 0x1165 6833#define regCM3_CM_POST_CSC_C21_C22_BASE_IDX 2 6834#define regCM3_CM_POST_CSC_C23_C24 0x1166 6835#define regCM3_CM_POST_CSC_C23_C24_BASE_IDX 2 6836#define regCM3_CM_POST_CSC_C31_C32 0x1167 6837#define regCM3_CM_POST_CSC_C31_C32_BASE_IDX 2 6838#define regCM3_CM_POST_CSC_C33_C34 0x1168 6839#define regCM3_CM_POST_CSC_C33_C34_BASE_IDX 2 6840#define regCM3_CM_POST_CSC_B_C11_C12 0x1169 6841#define regCM3_CM_POST_CSC_B_C11_C12_BASE_IDX 2 6842#define regCM3_CM_POST_CSC_B_C13_C14 0x116a 6843#define regCM3_CM_POST_CSC_B_C13_C14_BASE_IDX 2 6844#define regCM3_CM_POST_CSC_B_C21_C22 0x116b 6845#define regCM3_CM_POST_CSC_B_C21_C22_BASE_IDX 2 6846#define regCM3_CM_POST_CSC_B_C23_C24 0x116c 6847#define regCM3_CM_POST_CSC_B_C23_C24_BASE_IDX 2 6848#define regCM3_CM_POST_CSC_B_C31_C32 0x116d 6849#define regCM3_CM_POST_CSC_B_C31_C32_BASE_IDX 2 6850#define regCM3_CM_POST_CSC_B_C33_C34 0x116e 6851#define regCM3_CM_POST_CSC_B_C33_C34_BASE_IDX 2 6852#define regCM3_CM_GAMUT_REMAP_CONTROL 0x116f 6853#define regCM3_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 6854#define regCM3_CM_GAMUT_REMAP_C11_C12 0x1170 6855#define regCM3_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 6856#define regCM3_CM_GAMUT_REMAP_C13_C14 0x1171 6857#define regCM3_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 6858#define regCM3_CM_GAMUT_REMAP_C21_C22 0x1172 6859#define regCM3_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 6860#define regCM3_CM_GAMUT_REMAP_C23_C24 0x1173 6861#define regCM3_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 6862#define regCM3_CM_GAMUT_REMAP_C31_C32 0x1174 6863#define regCM3_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 6864#define regCM3_CM_GAMUT_REMAP_C33_C34 0x1175 6865#define regCM3_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 6866#define regCM3_CM_GAMUT_REMAP_B_C11_C12 0x1176 6867#define regCM3_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 6868#define regCM3_CM_GAMUT_REMAP_B_C13_C14 0x1177 6869#define regCM3_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 6870#define regCM3_CM_GAMUT_REMAP_B_C21_C22 0x1178 6871#define regCM3_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 6872#define regCM3_CM_GAMUT_REMAP_B_C23_C24 0x1179 6873#define regCM3_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 6874#define regCM3_CM_GAMUT_REMAP_B_C31_C32 0x117a 6875#define regCM3_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 6876#define regCM3_CM_GAMUT_REMAP_B_C33_C34 0x117b 6877#define regCM3_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 6878#define regCM3_CM_BIAS_CR_R 0x117c 6879#define regCM3_CM_BIAS_CR_R_BASE_IDX 2 6880#define regCM3_CM_BIAS_Y_G_CB_B 0x117d 6881#define regCM3_CM_BIAS_Y_G_CB_B_BASE_IDX 2 6882#define regCM3_CM_GAMCOR_CONTROL 0x117e 6883#define regCM3_CM_GAMCOR_CONTROL_BASE_IDX 2 6884#define regCM3_CM_GAMCOR_LUT_INDEX 0x117f 6885#define regCM3_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 6886#define regCM3_CM_GAMCOR_LUT_DATA 0x1180 6887#define regCM3_CM_GAMCOR_LUT_DATA_BASE_IDX 2 6888#define regCM3_CM_GAMCOR_LUT_CONTROL 0x1181 6889#define regCM3_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 6890#define regCM3_CM_GAMCOR_RAMA_START_CNTL_B 0x1182 6891#define regCM3_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 6892#define regCM3_CM_GAMCOR_RAMA_START_CNTL_G 0x1183 6893#define regCM3_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 6894#define regCM3_CM_GAMCOR_RAMA_START_CNTL_R 0x1184 6895#define regCM3_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 6896#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x1185 6897#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 6898#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x1186 6899#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 6900#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x1187 6901#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 6902#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x1188 6903#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 6904#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x1189 6905#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 6906#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x118a 6907#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 6908#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_B 0x118b 6909#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 6910#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_B 0x118c 6911#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 6912#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_G 0x118d 6913#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 6914#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_G 0x118e 6915#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 6916#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_R 0x118f 6917#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 6918#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_R 0x1190 6919#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 6920#define regCM3_CM_GAMCOR_RAMA_OFFSET_B 0x1191 6921#define regCM3_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 6922#define regCM3_CM_GAMCOR_RAMA_OFFSET_G 0x1192 6923#define regCM3_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 6924#define regCM3_CM_GAMCOR_RAMA_OFFSET_R 0x1193 6925#define regCM3_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 6926#define regCM3_CM_GAMCOR_RAMA_REGION_0_1 0x1194 6927#define regCM3_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 6928#define regCM3_CM_GAMCOR_RAMA_REGION_2_3 0x1195 6929#define regCM3_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 6930#define regCM3_CM_GAMCOR_RAMA_REGION_4_5 0x1196 6931#define regCM3_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 6932#define regCM3_CM_GAMCOR_RAMA_REGION_6_7 0x1197 6933#define regCM3_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 6934#define regCM3_CM_GAMCOR_RAMA_REGION_8_9 0x1198 6935#define regCM3_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 6936#define regCM3_CM_GAMCOR_RAMA_REGION_10_11 0x1199 6937#define regCM3_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 6938#define regCM3_CM_GAMCOR_RAMA_REGION_12_13 0x119a 6939#define regCM3_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 6940#define regCM3_CM_GAMCOR_RAMA_REGION_14_15 0x119b 6941#define regCM3_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 6942#define regCM3_CM_GAMCOR_RAMA_REGION_16_17 0x119c 6943#define regCM3_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 6944#define regCM3_CM_GAMCOR_RAMA_REGION_18_19 0x119d 6945#define regCM3_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 6946#define regCM3_CM_GAMCOR_RAMA_REGION_20_21 0x119e 6947#define regCM3_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 6948#define regCM3_CM_GAMCOR_RAMA_REGION_22_23 0x119f 6949#define regCM3_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 6950#define regCM3_CM_GAMCOR_RAMA_REGION_24_25 0x11a0 6951#define regCM3_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 6952#define regCM3_CM_GAMCOR_RAMA_REGION_26_27 0x11a1 6953#define regCM3_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 6954#define regCM3_CM_GAMCOR_RAMA_REGION_28_29 0x11a2 6955#define regCM3_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 6956#define regCM3_CM_GAMCOR_RAMA_REGION_30_31 0x11a3 6957#define regCM3_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 6958#define regCM3_CM_GAMCOR_RAMA_REGION_32_33 0x11a4 6959#define regCM3_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 6960#define regCM3_CM_GAMCOR_RAMB_START_CNTL_B 0x11a5 6961#define regCM3_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 6962#define regCM3_CM_GAMCOR_RAMB_START_CNTL_G 0x11a6 6963#define regCM3_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 6964#define regCM3_CM_GAMCOR_RAMB_START_CNTL_R 0x11a7 6965#define regCM3_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 6966#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x11a8 6967#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 6968#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x11a9 6969#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 6970#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x11aa 6971#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 6972#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x11ab 6973#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 6974#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x11ac 6975#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 6976#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x11ad 6977#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 6978#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_B 0x11ae 6979#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 6980#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_B 0x11af 6981#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 6982#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_G 0x11b0 6983#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 6984#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_G 0x11b1 6985#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 6986#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_R 0x11b2 6987#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 6988#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_R 0x11b3 6989#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 6990#define regCM3_CM_GAMCOR_RAMB_OFFSET_B 0x11b4 6991#define regCM3_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 6992#define regCM3_CM_GAMCOR_RAMB_OFFSET_G 0x11b5 6993#define regCM3_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 6994#define regCM3_CM_GAMCOR_RAMB_OFFSET_R 0x11b6 6995#define regCM3_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 6996#define regCM3_CM_GAMCOR_RAMB_REGION_0_1 0x11b7 6997#define regCM3_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 6998#define regCM3_CM_GAMCOR_RAMB_REGION_2_3 0x11b8 6999#define regCM3_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 7000#define regCM3_CM_GAMCOR_RAMB_REGION_4_5 0x11b9 7001#define regCM3_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 7002#define regCM3_CM_GAMCOR_RAMB_REGION_6_7 0x11ba 7003#define regCM3_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 7004#define regCM3_CM_GAMCOR_RAMB_REGION_8_9 0x11bb 7005#define regCM3_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 7006#define regCM3_CM_GAMCOR_RAMB_REGION_10_11 0x11bc 7007#define regCM3_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 7008#define regCM3_CM_GAMCOR_RAMB_REGION_12_13 0x11bd 7009#define regCM3_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 7010#define regCM3_CM_GAMCOR_RAMB_REGION_14_15 0x11be 7011#define regCM3_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 7012#define regCM3_CM_GAMCOR_RAMB_REGION_16_17 0x11bf 7013#define regCM3_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 7014#define regCM3_CM_GAMCOR_RAMB_REGION_18_19 0x11c0 7015#define regCM3_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 7016#define regCM3_CM_GAMCOR_RAMB_REGION_20_21 0x11c1 7017#define regCM3_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 7018#define regCM3_CM_GAMCOR_RAMB_REGION_22_23 0x11c2 7019#define regCM3_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 7020#define regCM3_CM_GAMCOR_RAMB_REGION_24_25 0x11c3 7021#define regCM3_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 7022#define regCM3_CM_GAMCOR_RAMB_REGION_26_27 0x11c4 7023#define regCM3_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 7024#define regCM3_CM_GAMCOR_RAMB_REGION_28_29 0x11c5 7025#define regCM3_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 7026#define regCM3_CM_GAMCOR_RAMB_REGION_30_31 0x11c6 7027#define regCM3_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 7028#define regCM3_CM_GAMCOR_RAMB_REGION_32_33 0x11c7 7029#define regCM3_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 7030#define regCM3_CM_BLNDGAM_CONTROL 0x11c8 7031#define regCM3_CM_BLNDGAM_CONTROL_BASE_IDX 2 7032#define regCM3_CM_BLNDGAM_LUT_INDEX 0x11c9 7033#define regCM3_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2 7034#define regCM3_CM_BLNDGAM_LUT_DATA 0x11ca 7035#define regCM3_CM_BLNDGAM_LUT_DATA_BASE_IDX 2 7036#define regCM3_CM_BLNDGAM_LUT_CONTROL 0x11cb 7037#define regCM3_CM_BLNDGAM_LUT_CONTROL_BASE_IDX 2 7038#define regCM3_CM_BLNDGAM_RAMA_START_CNTL_B 0x11cc 7039#define regCM3_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2 7040#define regCM3_CM_BLNDGAM_RAMA_START_CNTL_G 0x11cd 7041#define regCM3_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2 7042#define regCM3_CM_BLNDGAM_RAMA_START_CNTL_R 0x11ce 7043#define regCM3_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2 7044#define regCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B 0x11cf 7045#define regCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 7046#define regCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G 0x11d0 7047#define regCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 7048#define regCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R 0x11d1 7049#define regCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 7050#define regCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_B 0x11d2 7051#define regCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2 7052#define regCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_G 0x11d3 7053#define regCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2 7054#define regCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_R 0x11d4 7055#define regCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2 7056#define regCM3_CM_BLNDGAM_RAMA_END_CNTL1_B 0x11d5 7057#define regCM3_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2 7058#define regCM3_CM_BLNDGAM_RAMA_END_CNTL2_B 0x11d6 7059#define regCM3_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2 7060#define regCM3_CM_BLNDGAM_RAMA_END_CNTL1_G 0x11d7 7061#define regCM3_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2 7062#define regCM3_CM_BLNDGAM_RAMA_END_CNTL2_G 0x11d8 7063#define regCM3_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2 7064#define regCM3_CM_BLNDGAM_RAMA_END_CNTL1_R 0x11d9 7065#define regCM3_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2 7066#define regCM3_CM_BLNDGAM_RAMA_END_CNTL2_R 0x11da 7067#define regCM3_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2 7068#define regCM3_CM_BLNDGAM_RAMA_OFFSET_B 0x11db 7069#define regCM3_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX 2 7070#define regCM3_CM_BLNDGAM_RAMA_OFFSET_G 0x11dc 7071#define regCM3_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX 2 7072#define regCM3_CM_BLNDGAM_RAMA_OFFSET_R 0x11dd 7073#define regCM3_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX 2 7074#define regCM3_CM_BLNDGAM_RAMA_REGION_0_1 0x11de 7075#define regCM3_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2 7076#define regCM3_CM_BLNDGAM_RAMA_REGION_2_3 0x11df 7077#define regCM3_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2 7078#define regCM3_CM_BLNDGAM_RAMA_REGION_4_5 0x11e0 7079#define regCM3_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2 7080#define regCM3_CM_BLNDGAM_RAMA_REGION_6_7 0x11e1 7081#define regCM3_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2 7082#define regCM3_CM_BLNDGAM_RAMA_REGION_8_9 0x11e2 7083#define regCM3_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2 7084#define regCM3_CM_BLNDGAM_RAMA_REGION_10_11 0x11e3 7085#define regCM3_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2 7086#define regCM3_CM_BLNDGAM_RAMA_REGION_12_13 0x11e4 7087#define regCM3_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2 7088#define regCM3_CM_BLNDGAM_RAMA_REGION_14_15 0x11e5 7089#define regCM3_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2 7090#define regCM3_CM_BLNDGAM_RAMA_REGION_16_17 0x11e6 7091#define regCM3_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2 7092#define regCM3_CM_BLNDGAM_RAMA_REGION_18_19 0x11e7 7093#define regCM3_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2 7094#define regCM3_CM_BLNDGAM_RAMA_REGION_20_21 0x11e8 7095#define regCM3_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2 7096#define regCM3_CM_BLNDGAM_RAMA_REGION_22_23 0x11e9 7097#define regCM3_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2 7098#define regCM3_CM_BLNDGAM_RAMA_REGION_24_25 0x11ea 7099#define regCM3_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2 7100#define regCM3_CM_BLNDGAM_RAMA_REGION_26_27 0x11eb 7101#define regCM3_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2 7102#define regCM3_CM_BLNDGAM_RAMA_REGION_28_29 0x11ec 7103#define regCM3_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2 7104#define regCM3_CM_BLNDGAM_RAMA_REGION_30_31 0x11ed 7105#define regCM3_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2 7106#define regCM3_CM_BLNDGAM_RAMA_REGION_32_33 0x11ee 7107#define regCM3_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2 7108#define regCM3_CM_BLNDGAM_RAMB_START_CNTL_B 0x11ef 7109#define regCM3_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2 7110#define regCM3_CM_BLNDGAM_RAMB_START_CNTL_G 0x11f0 7111#define regCM3_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2 7112#define regCM3_CM_BLNDGAM_RAMB_START_CNTL_R 0x11f1 7113#define regCM3_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2 7114#define regCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B 0x11f2 7115#define regCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 7116#define regCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G 0x11f3 7117#define regCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 7118#define regCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R 0x11f4 7119#define regCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 7120#define regCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_B 0x11f5 7121#define regCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2 7122#define regCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_G 0x11f6 7123#define regCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2 7124#define regCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_R 0x11f7 7125#define regCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2 7126#define regCM3_CM_BLNDGAM_RAMB_END_CNTL1_B 0x11f8 7127#define regCM3_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2 7128#define regCM3_CM_BLNDGAM_RAMB_END_CNTL2_B 0x11f9 7129#define regCM3_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2 7130#define regCM3_CM_BLNDGAM_RAMB_END_CNTL1_G 0x11fa 7131#define regCM3_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2 7132#define regCM3_CM_BLNDGAM_RAMB_END_CNTL2_G 0x11fb 7133#define regCM3_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2 7134#define regCM3_CM_BLNDGAM_RAMB_END_CNTL1_R 0x11fc 7135#define regCM3_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2 7136#define regCM3_CM_BLNDGAM_RAMB_END_CNTL2_R 0x11fd 7137#define regCM3_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2 7138#define regCM3_CM_BLNDGAM_RAMB_OFFSET_B 0x11fe 7139#define regCM3_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX 2 7140#define regCM3_CM_BLNDGAM_RAMB_OFFSET_G 0x11ff 7141#define regCM3_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX 2 7142#define regCM3_CM_BLNDGAM_RAMB_OFFSET_R 0x1200 7143#define regCM3_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX 2 7144#define regCM3_CM_BLNDGAM_RAMB_REGION_0_1 0x1201 7145#define regCM3_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2 7146#define regCM3_CM_BLNDGAM_RAMB_REGION_2_3 0x1202 7147#define regCM3_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2 7148#define regCM3_CM_BLNDGAM_RAMB_REGION_4_5 0x1203 7149#define regCM3_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2 7150#define regCM3_CM_BLNDGAM_RAMB_REGION_6_7 0x1204 7151#define regCM3_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2 7152#define regCM3_CM_BLNDGAM_RAMB_REGION_8_9 0x1205 7153#define regCM3_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2 7154#define regCM3_CM_BLNDGAM_RAMB_REGION_10_11 0x1206 7155#define regCM3_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2 7156#define regCM3_CM_BLNDGAM_RAMB_REGION_12_13 0x1207 7157#define regCM3_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2 7158#define regCM3_CM_BLNDGAM_RAMB_REGION_14_15 0x1208 7159#define regCM3_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2 7160#define regCM3_CM_BLNDGAM_RAMB_REGION_16_17 0x1209 7161#define regCM3_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2 7162#define regCM3_CM_BLNDGAM_RAMB_REGION_18_19 0x120a 7163#define regCM3_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2 7164#define regCM3_CM_BLNDGAM_RAMB_REGION_20_21 0x120b 7165#define regCM3_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2 7166#define regCM3_CM_BLNDGAM_RAMB_REGION_22_23 0x120c 7167#define regCM3_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2 7168#define regCM3_CM_BLNDGAM_RAMB_REGION_24_25 0x120d 7169#define regCM3_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2 7170#define regCM3_CM_BLNDGAM_RAMB_REGION_26_27 0x120e 7171#define regCM3_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2 7172#define regCM3_CM_BLNDGAM_RAMB_REGION_28_29 0x120f 7173#define regCM3_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2 7174#define regCM3_CM_BLNDGAM_RAMB_REGION_30_31 0x1210 7175#define regCM3_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2 7176#define regCM3_CM_BLNDGAM_RAMB_REGION_32_33 0x1211 7177#define regCM3_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2 7178#define regCM3_CM_HDR_MULT_COEF 0x1212 7179#define regCM3_CM_HDR_MULT_COEF_BASE_IDX 2 7180#define regCM3_CM_MEM_PWR_CTRL 0x1213 7181#define regCM3_CM_MEM_PWR_CTRL_BASE_IDX 2 7182#define regCM3_CM_MEM_PWR_STATUS 0x1214 7183#define regCM3_CM_MEM_PWR_STATUS_BASE_IDX 2 7184#define regCM3_CM_DEALPHA 0x1216 7185#define regCM3_CM_DEALPHA_BASE_IDX 2 7186#define regCM3_CM_COEF_FORMAT 0x1217 7187#define regCM3_CM_COEF_FORMAT_BASE_IDX 2 7188#define regCM3_CM_SHAPER_CONTROL 0x1218 7189#define regCM3_CM_SHAPER_CONTROL_BASE_IDX 2 7190#define regCM3_CM_SHAPER_OFFSET_R 0x1219 7191#define regCM3_CM_SHAPER_OFFSET_R_BASE_IDX 2 7192#define regCM3_CM_SHAPER_OFFSET_G 0x121a 7193#define regCM3_CM_SHAPER_OFFSET_G_BASE_IDX 2 7194#define regCM3_CM_SHAPER_OFFSET_B 0x121b 7195#define regCM3_CM_SHAPER_OFFSET_B_BASE_IDX 2 7196#define regCM3_CM_SHAPER_SCALE_R 0x121c 7197#define regCM3_CM_SHAPER_SCALE_R_BASE_IDX 2 7198#define regCM3_CM_SHAPER_SCALE_G_B 0x121d 7199#define regCM3_CM_SHAPER_SCALE_G_B_BASE_IDX 2 7200#define regCM3_CM_SHAPER_LUT_INDEX 0x121e 7201#define regCM3_CM_SHAPER_LUT_INDEX_BASE_IDX 2 7202#define regCM3_CM_SHAPER_LUT_DATA 0x121f 7203#define regCM3_CM_SHAPER_LUT_DATA_BASE_IDX 2 7204#define regCM3_CM_SHAPER_LUT_WRITE_EN_MASK 0x1220 7205#define regCM3_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2 7206#define regCM3_CM_SHAPER_RAMA_START_CNTL_B 0x1221 7207#define regCM3_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2 7208#define regCM3_CM_SHAPER_RAMA_START_CNTL_G 0x1222 7209#define regCM3_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2 7210#define regCM3_CM_SHAPER_RAMA_START_CNTL_R 0x1223 7211#define regCM3_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2 7212#define regCM3_CM_SHAPER_RAMA_END_CNTL_B 0x1224 7213#define regCM3_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2 7214#define regCM3_CM_SHAPER_RAMA_END_CNTL_G 0x1225 7215#define regCM3_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2 7216#define regCM3_CM_SHAPER_RAMA_END_CNTL_R 0x1226 7217#define regCM3_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2 7218#define regCM3_CM_SHAPER_RAMA_REGION_0_1 0x1227 7219#define regCM3_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2 7220#define regCM3_CM_SHAPER_RAMA_REGION_2_3 0x1228 7221#define regCM3_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2 7222#define regCM3_CM_SHAPER_RAMA_REGION_4_5 0x1229 7223#define regCM3_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2 7224#define regCM3_CM_SHAPER_RAMA_REGION_6_7 0x122a 7225#define regCM3_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2 7226#define regCM3_CM_SHAPER_RAMA_REGION_8_9 0x122b 7227#define regCM3_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2 7228#define regCM3_CM_SHAPER_RAMA_REGION_10_11 0x122c 7229#define regCM3_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2 7230#define regCM3_CM_SHAPER_RAMA_REGION_12_13 0x122d 7231#define regCM3_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2 7232#define regCM3_CM_SHAPER_RAMA_REGION_14_15 0x122e 7233#define regCM3_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2 7234#define regCM3_CM_SHAPER_RAMA_REGION_16_17 0x122f 7235#define regCM3_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2 7236#define regCM3_CM_SHAPER_RAMA_REGION_18_19 0x1230 7237#define regCM3_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2 7238#define regCM3_CM_SHAPER_RAMA_REGION_20_21 0x1231 7239#define regCM3_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2 7240#define regCM3_CM_SHAPER_RAMA_REGION_22_23 0x1232 7241#define regCM3_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2 7242#define regCM3_CM_SHAPER_RAMA_REGION_24_25 0x1233 7243#define regCM3_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2 7244#define regCM3_CM_SHAPER_RAMA_REGION_26_27 0x1234 7245#define regCM3_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2 7246#define regCM3_CM_SHAPER_RAMA_REGION_28_29 0x1235 7247#define regCM3_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2 7248#define regCM3_CM_SHAPER_RAMA_REGION_30_31 0x1236 7249#define regCM3_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2 7250#define regCM3_CM_SHAPER_RAMA_REGION_32_33 0x1237 7251#define regCM3_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2 7252#define regCM3_CM_SHAPER_RAMB_START_CNTL_B 0x1238 7253#define regCM3_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2 7254#define regCM3_CM_SHAPER_RAMB_START_CNTL_G 0x1239 7255#define regCM3_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2 7256#define regCM3_CM_SHAPER_RAMB_START_CNTL_R 0x123a 7257#define regCM3_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2 7258#define regCM3_CM_SHAPER_RAMB_END_CNTL_B 0x123b 7259#define regCM3_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2 7260#define regCM3_CM_SHAPER_RAMB_END_CNTL_G 0x123c 7261#define regCM3_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2 7262#define regCM3_CM_SHAPER_RAMB_END_CNTL_R 0x123d 7263#define regCM3_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2 7264#define regCM3_CM_SHAPER_RAMB_REGION_0_1 0x123e 7265#define regCM3_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2 7266#define regCM3_CM_SHAPER_RAMB_REGION_2_3 0x123f 7267#define regCM3_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2 7268#define regCM3_CM_SHAPER_RAMB_REGION_4_5 0x1240 7269#define regCM3_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2 7270#define regCM3_CM_SHAPER_RAMB_REGION_6_7 0x1241 7271#define regCM3_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2 7272#define regCM3_CM_SHAPER_RAMB_REGION_8_9 0x1242 7273#define regCM3_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2 7274#define regCM3_CM_SHAPER_RAMB_REGION_10_11 0x1243 7275#define regCM3_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2 7276#define regCM3_CM_SHAPER_RAMB_REGION_12_13 0x1244 7277#define regCM3_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2 7278#define regCM3_CM_SHAPER_RAMB_REGION_14_15 0x1245 7279#define regCM3_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2 7280#define regCM3_CM_SHAPER_RAMB_REGION_16_17 0x1246 7281#define regCM3_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2 7282#define regCM3_CM_SHAPER_RAMB_REGION_18_19 0x1247 7283#define regCM3_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2 7284#define regCM3_CM_SHAPER_RAMB_REGION_20_21 0x1248 7285#define regCM3_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2 7286#define regCM3_CM_SHAPER_RAMB_REGION_22_23 0x1249 7287#define regCM3_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2 7288#define regCM3_CM_SHAPER_RAMB_REGION_24_25 0x124a 7289#define regCM3_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2 7290#define regCM3_CM_SHAPER_RAMB_REGION_26_27 0x124b 7291#define regCM3_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2 7292#define regCM3_CM_SHAPER_RAMB_REGION_28_29 0x124c 7293#define regCM3_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2 7294#define regCM3_CM_SHAPER_RAMB_REGION_30_31 0x124d 7295#define regCM3_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2 7296#define regCM3_CM_SHAPER_RAMB_REGION_32_33 0x124e 7297#define regCM3_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2 7298#define regCM3_CM_MEM_PWR_CTRL2 0x124f 7299#define regCM3_CM_MEM_PWR_CTRL2_BASE_IDX 2 7300#define regCM3_CM_MEM_PWR_STATUS2 0x1250 7301#define regCM3_CM_MEM_PWR_STATUS2_BASE_IDX 2 7302#define regCM3_CM_3DLUT_MODE 0x1251 7303#define regCM3_CM_3DLUT_MODE_BASE_IDX 2 7304#define regCM3_CM_3DLUT_INDEX 0x1252 7305#define regCM3_CM_3DLUT_INDEX_BASE_IDX 2 7306#define regCM3_CM_3DLUT_DATA 0x1253 7307#define regCM3_CM_3DLUT_DATA_BASE_IDX 2 7308#define regCM3_CM_3DLUT_DATA_30BIT 0x1254 7309#define regCM3_CM_3DLUT_DATA_30BIT_BASE_IDX 2 7310#define regCM3_CM_3DLUT_READ_WRITE_CONTROL 0x1255 7311#define regCM3_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2 7312#define regCM3_CM_3DLUT_OUT_NORM_FACTOR 0x1256 7313#define regCM3_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2 7314#define regCM3_CM_3DLUT_OUT_OFFSET_R 0x1257 7315#define regCM3_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2 7316#define regCM3_CM_3DLUT_OUT_OFFSET_G 0x1258 7317#define regCM3_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2 7318#define regCM3_CM_3DLUT_OUT_OFFSET_B 0x1259 7319#define regCM3_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2 7320#define regCM3_CM_TEST_DEBUG_INDEX 0x125a 7321#define regCM3_CM_TEST_DEBUG_INDEX_BASE_IDX 2 7322#define regCM3_CM_TEST_DEBUG_DATA 0x125b 7323#define regCM3_CM_TEST_DEBUG_DATA_BASE_IDX 2 7324 7325 7326// addressBlock: dce_dc_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec 7327// base address: 0x4994 7328#define regDC_PERFMON13_PERFCOUNTER_CNTL 0x1265 7329#define regDC_PERFMON13_PERFCOUNTER_CNTL_BASE_IDX 2 7330#define regDC_PERFMON13_PERFCOUNTER_CNTL2 0x1266 7331#define regDC_PERFMON13_PERFCOUNTER_CNTL2_BASE_IDX 2 7332#define regDC_PERFMON13_PERFCOUNTER_STATE 0x1267 7333#define regDC_PERFMON13_PERFCOUNTER_STATE_BASE_IDX 2 7334#define regDC_PERFMON13_PERFMON_CNTL 0x1268 7335#define regDC_PERFMON13_PERFMON_CNTL_BASE_IDX 2 7336#define regDC_PERFMON13_PERFMON_CNTL2 0x1269 7337#define regDC_PERFMON13_PERFMON_CNTL2_BASE_IDX 2 7338#define regDC_PERFMON13_PERFMON_CVALUE_INT_MISC 0x126a 7339#define regDC_PERFMON13_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 7340#define regDC_PERFMON13_PERFMON_CVALUE_LOW 0x126b 7341#define regDC_PERFMON13_PERFMON_CVALUE_LOW_BASE_IDX 2 7342#define regDC_PERFMON13_PERFMON_HI 0x126c 7343#define regDC_PERFMON13_PERFMON_HI_BASE_IDX 2 7344#define regDC_PERFMON13_PERFMON_LOW 0x126d 7345#define regDC_PERFMON13_PERFMON_LOW_BASE_IDX 2 7346 7347 7348// addressBlock: dce_dc_opp_fmt0_dispdec 7349// base address: 0x0 7350#define regFMT0_FMT_CLAMP_COMPONENT_R 0x183c 7351#define regFMT0_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 7352#define regFMT0_FMT_CLAMP_COMPONENT_G 0x183d 7353#define regFMT0_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 7354#define regFMT0_FMT_CLAMP_COMPONENT_B 0x183e 7355#define regFMT0_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 7356#define regFMT0_FMT_DYNAMIC_EXP_CNTL 0x183f 7357#define regFMT0_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 7358#define regFMT0_FMT_CONTROL 0x1840 7359#define regFMT0_FMT_CONTROL_BASE_IDX 2 7360#define regFMT0_FMT_BIT_DEPTH_CONTROL 0x1841 7361#define regFMT0_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 7362#define regFMT0_FMT_DITHER_RAND_R_SEED 0x1842 7363#define regFMT0_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 7364#define regFMT0_FMT_DITHER_RAND_G_SEED 0x1843 7365#define regFMT0_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 7366#define regFMT0_FMT_DITHER_RAND_B_SEED 0x1844 7367#define regFMT0_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 7368#define regFMT0_FMT_CLAMP_CNTL 0x1845 7369#define regFMT0_FMT_CLAMP_CNTL_BASE_IDX 2 7370#define regFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1846 7371#define regFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 7372#define regFMT0_FMT_MAP420_MEMORY_CONTROL 0x1847 7373#define regFMT0_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 7374#define regFMT0_FMT_422_CONTROL 0x1849 7375#define regFMT0_FMT_422_CONTROL_BASE_IDX 2 7376 7377 7378// addressBlock: dce_dc_opp_dpg0_dispdec 7379// base address: 0x0 7380#define regDPG0_DPG_CONTROL 0x1854 7381#define regDPG0_DPG_CONTROL_BASE_IDX 2 7382#define regDPG0_DPG_RAMP_CONTROL 0x1855 7383#define regDPG0_DPG_RAMP_CONTROL_BASE_IDX 2 7384#define regDPG0_DPG_DIMENSIONS 0x1856 7385#define regDPG0_DPG_DIMENSIONS_BASE_IDX 2 7386#define regDPG0_DPG_COLOUR_R_CR 0x1857 7387#define regDPG0_DPG_COLOUR_R_CR_BASE_IDX 2 7388#define regDPG0_DPG_COLOUR_G_Y 0x1858 7389#define regDPG0_DPG_COLOUR_G_Y_BASE_IDX 2 7390#define regDPG0_DPG_COLOUR_B_CB 0x1859 7391#define regDPG0_DPG_COLOUR_B_CB_BASE_IDX 2 7392#define regDPG0_DPG_OFFSET_SEGMENT 0x185a 7393#define regDPG0_DPG_OFFSET_SEGMENT_BASE_IDX 2 7394#define regDPG0_DPG_STATUS 0x185b 7395#define regDPG0_DPG_STATUS_BASE_IDX 2 7396 7397 7398// addressBlock: dce_dc_opp_oppbuf0_dispdec 7399// base address: 0x0 7400#define regOPPBUF0_OPPBUF_CONTROL 0x1884 7401#define regOPPBUF0_OPPBUF_CONTROL_BASE_IDX 2 7402#define regOPPBUF0_OPPBUF_3D_PARAMETERS_0 0x1885 7403#define regOPPBUF0_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 7404#define regOPPBUF0_OPPBUF_3D_PARAMETERS_1 0x1886 7405#define regOPPBUF0_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 7406#define regOPPBUF0_OPPBUF_CONTROL1 0x1889 7407#define regOPPBUF0_OPPBUF_CONTROL1_BASE_IDX 2 7408 7409 7410// addressBlock: dce_dc_opp_opp_pipe0_dispdec 7411// base address: 0x0 7412#define regOPP_PIPE0_OPP_PIPE_CONTROL 0x188c 7413#define regOPP_PIPE0_OPP_PIPE_CONTROL_BASE_IDX 2 7414 7415 7416// addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec 7417// base address: 0x0 7418#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL 0x1891 7419#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 7420#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK 0x1892 7421#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK_BASE_IDX 2 7422#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0 0x1893 7423#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 7424#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1 0x1894 7425#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 7426#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2 0x1895 7427#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 7428 7429 7430// addressBlock: dce_dc_opp_fmt1_dispdec 7431// base address: 0x168 7432#define regFMT1_FMT_CLAMP_COMPONENT_R 0x1896 7433#define regFMT1_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 7434#define regFMT1_FMT_CLAMP_COMPONENT_G 0x1897 7435#define regFMT1_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 7436#define regFMT1_FMT_CLAMP_COMPONENT_B 0x1898 7437#define regFMT1_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 7438#define regFMT1_FMT_DYNAMIC_EXP_CNTL 0x1899 7439#define regFMT1_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 7440#define regFMT1_FMT_CONTROL 0x189a 7441#define regFMT1_FMT_CONTROL_BASE_IDX 2 7442#define regFMT1_FMT_BIT_DEPTH_CONTROL 0x189b 7443#define regFMT1_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 7444#define regFMT1_FMT_DITHER_RAND_R_SEED 0x189c 7445#define regFMT1_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 7446#define regFMT1_FMT_DITHER_RAND_G_SEED 0x189d 7447#define regFMT1_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 7448#define regFMT1_FMT_DITHER_RAND_B_SEED 0x189e 7449#define regFMT1_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 7450#define regFMT1_FMT_CLAMP_CNTL 0x189f 7451#define regFMT1_FMT_CLAMP_CNTL_BASE_IDX 2 7452#define regFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x18a0 7453#define regFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 7454#define regFMT1_FMT_MAP420_MEMORY_CONTROL 0x18a1 7455#define regFMT1_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 7456#define regFMT1_FMT_422_CONTROL 0x18a3 7457#define regFMT1_FMT_422_CONTROL_BASE_IDX 2 7458 7459 7460// addressBlock: dce_dc_opp_dpg1_dispdec 7461// base address: 0x168 7462#define regDPG1_DPG_CONTROL 0x18ae 7463#define regDPG1_DPG_CONTROL_BASE_IDX 2 7464#define regDPG1_DPG_RAMP_CONTROL 0x18af 7465#define regDPG1_DPG_RAMP_CONTROL_BASE_IDX 2 7466#define regDPG1_DPG_DIMENSIONS 0x18b0 7467#define regDPG1_DPG_DIMENSIONS_BASE_IDX 2 7468#define regDPG1_DPG_COLOUR_R_CR 0x18b1 7469#define regDPG1_DPG_COLOUR_R_CR_BASE_IDX 2 7470#define regDPG1_DPG_COLOUR_G_Y 0x18b2 7471#define regDPG1_DPG_COLOUR_G_Y_BASE_IDX 2 7472#define regDPG1_DPG_COLOUR_B_CB 0x18b3 7473#define regDPG1_DPG_COLOUR_B_CB_BASE_IDX 2 7474#define regDPG1_DPG_OFFSET_SEGMENT 0x18b4 7475#define regDPG1_DPG_OFFSET_SEGMENT_BASE_IDX 2 7476#define regDPG1_DPG_STATUS 0x18b5 7477#define regDPG1_DPG_STATUS_BASE_IDX 2 7478 7479 7480// addressBlock: dce_dc_opp_oppbuf1_dispdec 7481// base address: 0x168 7482#define regOPPBUF1_OPPBUF_CONTROL 0x18de 7483#define regOPPBUF1_OPPBUF_CONTROL_BASE_IDX 2 7484#define regOPPBUF1_OPPBUF_3D_PARAMETERS_0 0x18df 7485#define regOPPBUF1_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 7486#define regOPPBUF1_OPPBUF_3D_PARAMETERS_1 0x18e0 7487#define regOPPBUF1_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 7488#define regOPPBUF1_OPPBUF_CONTROL1 0x18e3 7489#define regOPPBUF1_OPPBUF_CONTROL1_BASE_IDX 2 7490 7491 7492// addressBlock: dce_dc_opp_opp_pipe1_dispdec 7493// base address: 0x168 7494#define regOPP_PIPE1_OPP_PIPE_CONTROL 0x18e6 7495#define regOPP_PIPE1_OPP_PIPE_CONTROL_BASE_IDX 2 7496 7497 7498// addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec 7499// base address: 0x168 7500#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL 0x18eb 7501#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 7502#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK 0x18ec 7503#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK_BASE_IDX 2 7504#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0 0x18ed 7505#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 7506#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1 0x18ee 7507#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 7508#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2 0x18ef 7509#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 7510 7511 7512// addressBlock: dce_dc_opp_fmt2_dispdec 7513// base address: 0x2d0 7514#define regFMT2_FMT_CLAMP_COMPONENT_R 0x18f0 7515#define regFMT2_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 7516#define regFMT2_FMT_CLAMP_COMPONENT_G 0x18f1 7517#define regFMT2_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 7518#define regFMT2_FMT_CLAMP_COMPONENT_B 0x18f2 7519#define regFMT2_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 7520#define regFMT2_FMT_DYNAMIC_EXP_CNTL 0x18f3 7521#define regFMT2_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 7522#define regFMT2_FMT_CONTROL 0x18f4 7523#define regFMT2_FMT_CONTROL_BASE_IDX 2 7524#define regFMT2_FMT_BIT_DEPTH_CONTROL 0x18f5 7525#define regFMT2_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 7526#define regFMT2_FMT_DITHER_RAND_R_SEED 0x18f6 7527#define regFMT2_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 7528#define regFMT2_FMT_DITHER_RAND_G_SEED 0x18f7 7529#define regFMT2_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 7530#define regFMT2_FMT_DITHER_RAND_B_SEED 0x18f8 7531#define regFMT2_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 7532#define regFMT2_FMT_CLAMP_CNTL 0x18f9 7533#define regFMT2_FMT_CLAMP_CNTL_BASE_IDX 2 7534#define regFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x18fa 7535#define regFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 7536#define regFMT2_FMT_MAP420_MEMORY_CONTROL 0x18fb 7537#define regFMT2_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 7538#define regFMT2_FMT_422_CONTROL 0x18fd 7539#define regFMT2_FMT_422_CONTROL_BASE_IDX 2 7540 7541 7542// addressBlock: dce_dc_opp_dpg2_dispdec 7543// base address: 0x2d0 7544#define regDPG2_DPG_CONTROL 0x1908 7545#define regDPG2_DPG_CONTROL_BASE_IDX 2 7546#define regDPG2_DPG_RAMP_CONTROL 0x1909 7547#define regDPG2_DPG_RAMP_CONTROL_BASE_IDX 2 7548#define regDPG2_DPG_DIMENSIONS 0x190a 7549#define regDPG2_DPG_DIMENSIONS_BASE_IDX 2 7550#define regDPG2_DPG_COLOUR_R_CR 0x190b 7551#define regDPG2_DPG_COLOUR_R_CR_BASE_IDX 2 7552#define regDPG2_DPG_COLOUR_G_Y 0x190c 7553#define regDPG2_DPG_COLOUR_G_Y_BASE_IDX 2 7554#define regDPG2_DPG_COLOUR_B_CB 0x190d 7555#define regDPG2_DPG_COLOUR_B_CB_BASE_IDX 2 7556#define regDPG2_DPG_OFFSET_SEGMENT 0x190e 7557#define regDPG2_DPG_OFFSET_SEGMENT_BASE_IDX 2 7558#define regDPG2_DPG_STATUS 0x190f 7559#define regDPG2_DPG_STATUS_BASE_IDX 2 7560 7561 7562// addressBlock: dce_dc_opp_oppbuf2_dispdec 7563// base address: 0x2d0 7564#define regOPPBUF2_OPPBUF_CONTROL 0x1938 7565#define regOPPBUF2_OPPBUF_CONTROL_BASE_IDX 2 7566#define regOPPBUF2_OPPBUF_3D_PARAMETERS_0 0x1939 7567#define regOPPBUF2_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 7568#define regOPPBUF2_OPPBUF_3D_PARAMETERS_1 0x193a 7569#define regOPPBUF2_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 7570#define regOPPBUF2_OPPBUF_CONTROL1 0x193d 7571#define regOPPBUF2_OPPBUF_CONTROL1_BASE_IDX 2 7572 7573 7574// addressBlock: dce_dc_opp_opp_pipe2_dispdec 7575// base address: 0x2d0 7576#define regOPP_PIPE2_OPP_PIPE_CONTROL 0x1940 7577#define regOPP_PIPE2_OPP_PIPE_CONTROL_BASE_IDX 2 7578 7579 7580// addressBlock: dce_dc_opp_opp_pipe_crc2_dispdec 7581// base address: 0x2d0 7582#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL 0x1945 7583#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 7584#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK 0x1946 7585#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK_BASE_IDX 2 7586#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0 0x1947 7587#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 7588#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1 0x1948 7589#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 7590#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2 0x1949 7591#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 7592 7593 7594// addressBlock: dce_dc_opp_fmt3_dispdec 7595// base address: 0x438 7596#define regFMT3_FMT_CLAMP_COMPONENT_R 0x194a 7597#define regFMT3_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 7598#define regFMT3_FMT_CLAMP_COMPONENT_G 0x194b 7599#define regFMT3_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 7600#define regFMT3_FMT_CLAMP_COMPONENT_B 0x194c 7601#define regFMT3_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 7602#define regFMT3_FMT_DYNAMIC_EXP_CNTL 0x194d 7603#define regFMT3_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 7604#define regFMT3_FMT_CONTROL 0x194e 7605#define regFMT3_FMT_CONTROL_BASE_IDX 2 7606#define regFMT3_FMT_BIT_DEPTH_CONTROL 0x194f 7607#define regFMT3_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 7608#define regFMT3_FMT_DITHER_RAND_R_SEED 0x1950 7609#define regFMT3_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 7610#define regFMT3_FMT_DITHER_RAND_G_SEED 0x1951 7611#define regFMT3_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 7612#define regFMT3_FMT_DITHER_RAND_B_SEED 0x1952 7613#define regFMT3_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 7614#define regFMT3_FMT_CLAMP_CNTL 0x1953 7615#define regFMT3_FMT_CLAMP_CNTL_BASE_IDX 2 7616#define regFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1954 7617#define regFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 7618#define regFMT3_FMT_MAP420_MEMORY_CONTROL 0x1955 7619#define regFMT3_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 7620#define regFMT3_FMT_422_CONTROL 0x1957 7621#define regFMT3_FMT_422_CONTROL_BASE_IDX 2 7622 7623 7624// addressBlock: dce_dc_opp_dpg3_dispdec 7625// base address: 0x438 7626#define regDPG3_DPG_CONTROL 0x1962 7627#define regDPG3_DPG_CONTROL_BASE_IDX 2 7628#define regDPG3_DPG_RAMP_CONTROL 0x1963 7629#define regDPG3_DPG_RAMP_CONTROL_BASE_IDX 2 7630#define regDPG3_DPG_DIMENSIONS 0x1964 7631#define regDPG3_DPG_DIMENSIONS_BASE_IDX 2 7632#define regDPG3_DPG_COLOUR_R_CR 0x1965 7633#define regDPG3_DPG_COLOUR_R_CR_BASE_IDX 2 7634#define regDPG3_DPG_COLOUR_G_Y 0x1966 7635#define regDPG3_DPG_COLOUR_G_Y_BASE_IDX 2 7636#define regDPG3_DPG_COLOUR_B_CB 0x1967 7637#define regDPG3_DPG_COLOUR_B_CB_BASE_IDX 2 7638#define regDPG3_DPG_OFFSET_SEGMENT 0x1968 7639#define regDPG3_DPG_OFFSET_SEGMENT_BASE_IDX 2 7640#define regDPG3_DPG_STATUS 0x1969 7641#define regDPG3_DPG_STATUS_BASE_IDX 2 7642 7643 7644// addressBlock: dce_dc_opp_oppbuf3_dispdec 7645// base address: 0x438 7646#define regOPPBUF3_OPPBUF_CONTROL 0x1992 7647#define regOPPBUF3_OPPBUF_CONTROL_BASE_IDX 2 7648#define regOPPBUF3_OPPBUF_3D_PARAMETERS_0 0x1993 7649#define regOPPBUF3_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 7650#define regOPPBUF3_OPPBUF_3D_PARAMETERS_1 0x1994 7651#define regOPPBUF3_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 7652#define regOPPBUF3_OPPBUF_CONTROL1 0x1997 7653#define regOPPBUF3_OPPBUF_CONTROL1_BASE_IDX 2 7654 7655 7656// addressBlock: dce_dc_opp_opp_pipe3_dispdec 7657// base address: 0x438 7658#define regOPP_PIPE3_OPP_PIPE_CONTROL 0x199a 7659#define regOPP_PIPE3_OPP_PIPE_CONTROL_BASE_IDX 2 7660 7661 7662// addressBlock: dce_dc_opp_opp_pipe_crc3_dispdec 7663// base address: 0x438 7664#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL 0x199f 7665#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 7666#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK 0x19a0 7667#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK_BASE_IDX 2 7668#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0 0x19a1 7669#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 7670#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1 0x19a2 7671#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 7672#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2 0x19a3 7673#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 7674 7675 7676// addressBlock: dce_dc_opp_opp_top_dispdec 7677// base address: 0x0 7678#define regOPP_TOP_CLK_CONTROL 0x1a5e 7679#define regOPP_TOP_CLK_CONTROL_BASE_IDX 2 7680#define regOPP_ABM_CONTROL 0x1a60 7681#define regOPP_ABM_CONTROL_BASE_IDX 2 7682 7683 7684// addressBlock: dce_dc_opp_dscrm0_dispdec 7685// base address: 0x0 7686#define regDSCRM0_DSCRM_DSC_FORWARD_CONFIG 0x1a64 7687#define regDSCRM0_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 7688 7689 7690// addressBlock: dce_dc_opp_dscrm1_dispdec 7691// base address: 0x4 7692#define regDSCRM1_DSCRM_DSC_FORWARD_CONFIG 0x1a65 7693#define regDSCRM1_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 7694 7695 7696// addressBlock: dce_dc_opp_dscrm2_dispdec 7697// base address: 0x8 7698#define regDSCRM2_DSCRM_DSC_FORWARD_CONFIG 0x1a66 7699#define regDSCRM2_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 7700 7701 7702// addressBlock: dce_dc_opp_dscrm3_dispdec 7703// base address: 0xc 7704#define regDSCRM3_DSCRM_DSC_FORWARD_CONFIG 0x1a67 7705#define regDSCRM3_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 7706 7707 7708// addressBlock: dce_dc_opp_opp_dcperfmon_dc_perfmon_dispdec 7709// base address: 0x6af8 7710#define regDC_PERFMON14_PERFCOUNTER_CNTL 0x1abe 7711#define regDC_PERFMON14_PERFCOUNTER_CNTL_BASE_IDX 2 7712#define regDC_PERFMON14_PERFCOUNTER_CNTL2 0x1abf 7713#define regDC_PERFMON14_PERFCOUNTER_CNTL2_BASE_IDX 2 7714#define regDC_PERFMON14_PERFCOUNTER_STATE 0x1ac0 7715#define regDC_PERFMON14_PERFCOUNTER_STATE_BASE_IDX 2 7716#define regDC_PERFMON14_PERFMON_CNTL 0x1ac1 7717#define regDC_PERFMON14_PERFMON_CNTL_BASE_IDX 2 7718#define regDC_PERFMON14_PERFMON_CNTL2 0x1ac2 7719#define regDC_PERFMON14_PERFMON_CNTL2_BASE_IDX 2 7720#define regDC_PERFMON14_PERFMON_CVALUE_INT_MISC 0x1ac3 7721#define regDC_PERFMON14_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 7722#define regDC_PERFMON14_PERFMON_CVALUE_LOW 0x1ac4 7723#define regDC_PERFMON14_PERFMON_CVALUE_LOW_BASE_IDX 2 7724#define regDC_PERFMON14_PERFMON_HI 0x1ac5 7725#define regDC_PERFMON14_PERFMON_HI_BASE_IDX 2 7726#define regDC_PERFMON14_PERFMON_LOW 0x1ac6 7727#define regDC_PERFMON14_PERFMON_LOW_BASE_IDX 2 7728 7729 7730// addressBlock: dce_dc_optc_odm0_dispdec 7731// base address: 0x0 7732#define regODM0_OPTC_INPUT_GLOBAL_CONTROL 0x1aca 7733#define regODM0_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 7734#define regODM0_OPTC_DATA_SOURCE_SELECT 0x1acb 7735#define regODM0_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 7736#define regODM0_OPTC_DATA_FORMAT_CONTROL 0x1acc 7737#define regODM0_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 7738#define regODM0_OPTC_BYTES_PER_PIXEL 0x1acd 7739#define regODM0_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 7740#define regODM0_OPTC_WIDTH_CONTROL 0x1ace 7741#define regODM0_OPTC_WIDTH_CONTROL_BASE_IDX 2 7742#define regODM0_OPTC_INPUT_CLOCK_CONTROL 0x1acf 7743#define regODM0_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 7744#define regODM0_OPTC_MEMORY_CONFIG 0x1ad0 7745#define regODM0_OPTC_MEMORY_CONFIG_BASE_IDX 2 7746#define regODM0_OPTC_INPUT_SPARE_REGISTER 0x1ad1 7747#define regODM0_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 7748 7749 7750// addressBlock: dce_dc_optc_odm1_dispdec 7751// base address: 0x40 7752#define regODM1_OPTC_INPUT_GLOBAL_CONTROL 0x1ada 7753#define regODM1_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 7754#define regODM1_OPTC_DATA_SOURCE_SELECT 0x1adb 7755#define regODM1_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 7756#define regODM1_OPTC_DATA_FORMAT_CONTROL 0x1adc 7757#define regODM1_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 7758#define regODM1_OPTC_BYTES_PER_PIXEL 0x1add 7759#define regODM1_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 7760#define regODM1_OPTC_WIDTH_CONTROL 0x1ade 7761#define regODM1_OPTC_WIDTH_CONTROL_BASE_IDX 2 7762#define regODM1_OPTC_INPUT_CLOCK_CONTROL 0x1adf 7763#define regODM1_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 7764#define regODM1_OPTC_MEMORY_CONFIG 0x1ae0 7765#define regODM1_OPTC_MEMORY_CONFIG_BASE_IDX 2 7766#define regODM1_OPTC_INPUT_SPARE_REGISTER 0x1ae1 7767#define regODM1_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 7768 7769 7770// addressBlock: dce_dc_optc_odm2_dispdec 7771// base address: 0x80 7772#define regODM2_OPTC_INPUT_GLOBAL_CONTROL 0x1aea 7773#define regODM2_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 7774#define regODM2_OPTC_DATA_SOURCE_SELECT 0x1aeb 7775#define regODM2_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 7776#define regODM2_OPTC_DATA_FORMAT_CONTROL 0x1aec 7777#define regODM2_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 7778#define regODM2_OPTC_BYTES_PER_PIXEL 0x1aed 7779#define regODM2_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 7780#define regODM2_OPTC_WIDTH_CONTROL 0x1aee 7781#define regODM2_OPTC_WIDTH_CONTROL_BASE_IDX 2 7782#define regODM2_OPTC_INPUT_CLOCK_CONTROL 0x1aef 7783#define regODM2_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 7784#define regODM2_OPTC_MEMORY_CONFIG 0x1af0 7785#define regODM2_OPTC_MEMORY_CONFIG_BASE_IDX 2 7786#define regODM2_OPTC_INPUT_SPARE_REGISTER 0x1af1 7787#define regODM2_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 7788 7789 7790// addressBlock: dce_dc_optc_odm3_dispdec 7791// base address: 0xc0 7792#define regODM3_OPTC_INPUT_GLOBAL_CONTROL 0x1afa 7793#define regODM3_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 7794#define regODM3_OPTC_DATA_SOURCE_SELECT 0x1afb 7795#define regODM3_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 7796#define regODM3_OPTC_DATA_FORMAT_CONTROL 0x1afc 7797#define regODM3_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 7798#define regODM3_OPTC_BYTES_PER_PIXEL 0x1afd 7799#define regODM3_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 7800#define regODM3_OPTC_WIDTH_CONTROL 0x1afe 7801#define regODM3_OPTC_WIDTH_CONTROL_BASE_IDX 2 7802#define regODM3_OPTC_INPUT_CLOCK_CONTROL 0x1aff 7803#define regODM3_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 7804#define regODM3_OPTC_MEMORY_CONFIG 0x1b00 7805#define regODM3_OPTC_MEMORY_CONFIG_BASE_IDX 2 7806#define regODM3_OPTC_INPUT_SPARE_REGISTER 0x1b01 7807#define regODM3_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 7808 7809 7810// addressBlock: dce_dc_optc_otg0_dispdec 7811// base address: 0x0 7812#define regOTG0_OTG_H_TOTAL 0x1b2a 7813#define regOTG0_OTG_H_TOTAL_BASE_IDX 2 7814#define regOTG0_OTG_H_BLANK_START_END 0x1b2b 7815#define regOTG0_OTG_H_BLANK_START_END_BASE_IDX 2 7816#define regOTG0_OTG_H_SYNC_A 0x1b2c 7817#define regOTG0_OTG_H_SYNC_A_BASE_IDX 2 7818#define regOTG0_OTG_H_SYNC_A_CNTL 0x1b2d 7819#define regOTG0_OTG_H_SYNC_A_CNTL_BASE_IDX 2 7820#define regOTG0_OTG_H_TIMING_CNTL 0x1b2e 7821#define regOTG0_OTG_H_TIMING_CNTL_BASE_IDX 2 7822#define regOTG0_OTG_V_TOTAL 0x1b2f 7823#define regOTG0_OTG_V_TOTAL_BASE_IDX 2 7824#define regOTG0_OTG_V_TOTAL_MIN 0x1b30 7825#define regOTG0_OTG_V_TOTAL_MIN_BASE_IDX 2 7826#define regOTG0_OTG_V_TOTAL_MAX 0x1b31 7827#define regOTG0_OTG_V_TOTAL_MAX_BASE_IDX 2 7828#define regOTG0_OTG_V_TOTAL_MID 0x1b32 7829#define regOTG0_OTG_V_TOTAL_MID_BASE_IDX 2 7830#define regOTG0_OTG_V_TOTAL_CONTROL 0x1b33 7831#define regOTG0_OTG_V_TOTAL_CONTROL_BASE_IDX 2 7832#define regOTG0_OTG_V_TOTAL_INT_STATUS 0x1b34 7833#define regOTG0_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 7834#define regOTG0_OTG_VSYNC_NOM_INT_STATUS 0x1b35 7835#define regOTG0_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 7836#define regOTG0_OTG_V_BLANK_START_END 0x1b36 7837#define regOTG0_OTG_V_BLANK_START_END_BASE_IDX 2 7838#define regOTG0_OTG_V_SYNC_A 0x1b37 7839#define regOTG0_OTG_V_SYNC_A_BASE_IDX 2 7840#define regOTG0_OTG_V_SYNC_A_CNTL 0x1b38 7841#define regOTG0_OTG_V_SYNC_A_CNTL_BASE_IDX 2 7842#define regOTG0_OTG_TRIGA_CNTL 0x1b39 7843#define regOTG0_OTG_TRIGA_CNTL_BASE_IDX 2 7844#define regOTG0_OTG_TRIGA_MANUAL_TRIG 0x1b3a 7845#define regOTG0_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 7846#define regOTG0_OTG_TRIGB_CNTL 0x1b3b 7847#define regOTG0_OTG_TRIGB_CNTL_BASE_IDX 2 7848#define regOTG0_OTG_TRIGB_MANUAL_TRIG 0x1b3c 7849#define regOTG0_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 7850#define regOTG0_OTG_FORCE_COUNT_NOW_CNTL 0x1b3d 7851#define regOTG0_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 7852#define regOTG0_OTG_FLOW_CONTROL 0x1b3e 7853#define regOTG0_OTG_FLOW_CONTROL_BASE_IDX 2 7854#define regOTG0_OTG_STEREO_FORCE_NEXT_EYE 0x1b3f 7855#define regOTG0_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 7856#define regOTG0_OTG_CONTROL 0x1b41 7857#define regOTG0_OTG_CONTROL_BASE_IDX 2 7858#define regOTG0_OTG_INTERLACE_CONTROL 0x1b44 7859#define regOTG0_OTG_INTERLACE_CONTROL_BASE_IDX 2 7860#define regOTG0_OTG_INTERLACE_STATUS 0x1b45 7861#define regOTG0_OTG_INTERLACE_STATUS_BASE_IDX 2 7862#define regOTG0_OTG_PIXEL_DATA_READBACK0 0x1b47 7863#define regOTG0_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 7864#define regOTG0_OTG_PIXEL_DATA_READBACK1 0x1b48 7865#define regOTG0_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 7866#define regOTG0_OTG_STATUS 0x1b49 7867#define regOTG0_OTG_STATUS_BASE_IDX 2 7868#define regOTG0_OTG_STATUS_POSITION 0x1b4a 7869#define regOTG0_OTG_STATUS_POSITION_BASE_IDX 2 7870#define regOTG0_OTG_NOM_VERT_POSITION 0x1b4b 7871#define regOTG0_OTG_NOM_VERT_POSITION_BASE_IDX 2 7872#define regOTG0_OTG_STATUS_FRAME_COUNT 0x1b4c 7873#define regOTG0_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 7874#define regOTG0_OTG_STATUS_VF_COUNT 0x1b4d 7875#define regOTG0_OTG_STATUS_VF_COUNT_BASE_IDX 2 7876#define regOTG0_OTG_STATUS_HV_COUNT 0x1b4e 7877#define regOTG0_OTG_STATUS_HV_COUNT_BASE_IDX 2 7878#define regOTG0_OTG_COUNT_CONTROL 0x1b4f 7879#define regOTG0_OTG_COUNT_CONTROL_BASE_IDX 2 7880#define regOTG0_OTG_COUNT_RESET 0x1b50 7881#define regOTG0_OTG_COUNT_RESET_BASE_IDX 2 7882#define regOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1b51 7883#define regOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 7884#define regOTG0_OTG_VERT_SYNC_CONTROL 0x1b52 7885#define regOTG0_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 7886#define regOTG0_OTG_STEREO_STATUS 0x1b53 7887#define regOTG0_OTG_STEREO_STATUS_BASE_IDX 2 7888#define regOTG0_OTG_STEREO_CONTROL 0x1b54 7889#define regOTG0_OTG_STEREO_CONTROL_BASE_IDX 2 7890#define regOTG0_OTG_SNAPSHOT_STATUS 0x1b55 7891#define regOTG0_OTG_SNAPSHOT_STATUS_BASE_IDX 2 7892#define regOTG0_OTG_SNAPSHOT_CONTROL 0x1b56 7893#define regOTG0_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 7894#define regOTG0_OTG_SNAPSHOT_POSITION 0x1b57 7895#define regOTG0_OTG_SNAPSHOT_POSITION_BASE_IDX 2 7896#define regOTG0_OTG_SNAPSHOT_FRAME 0x1b58 7897#define regOTG0_OTG_SNAPSHOT_FRAME_BASE_IDX 2 7898#define regOTG0_OTG_INTERRUPT_CONTROL 0x1b59 7899#define regOTG0_OTG_INTERRUPT_CONTROL_BASE_IDX 2 7900#define regOTG0_OTG_UPDATE_LOCK 0x1b5a 7901#define regOTG0_OTG_UPDATE_LOCK_BASE_IDX 2 7902#define regOTG0_OTG_DOUBLE_BUFFER_CONTROL 0x1b5b 7903#define regOTG0_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 7904#define regOTG0_OTG_MASTER_EN 0x1b5c 7905#define regOTG0_OTG_MASTER_EN_BASE_IDX 2 7906#define regOTG0_OTG_VERTICAL_INTERRUPT0_POSITION 0x1b62 7907#define regOTG0_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 7908#define regOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1b63 7909#define regOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 7910#define regOTG0_OTG_VERTICAL_INTERRUPT1_POSITION 0x1b64 7911#define regOTG0_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 7912#define regOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1b65 7913#define regOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 7914#define regOTG0_OTG_VERTICAL_INTERRUPT2_POSITION 0x1b66 7915#define regOTG0_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 7916#define regOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1b67 7917#define regOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 7918#define regOTG0_OTG_CRC_CNTL 0x1b68 7919#define regOTG0_OTG_CRC_CNTL_BASE_IDX 2 7920#define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL 0x1b69 7921#define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 7922#define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL 0x1b6a 7923#define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 7924#define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL 0x1b6b 7925#define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 7926#define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL 0x1b6c 7927#define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 7928#define regOTG0_OTG_CRC0_DATA_RG 0x1b6d 7929#define regOTG0_OTG_CRC0_DATA_RG_BASE_IDX 2 7930#define regOTG0_OTG_CRC0_DATA_B 0x1b6e 7931#define regOTG0_OTG_CRC0_DATA_B_BASE_IDX 2 7932#define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL 0x1b6f 7933#define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 7934#define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL 0x1b70 7935#define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 7936#define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL 0x1b71 7937#define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 7938#define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL 0x1b72 7939#define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 7940#define regOTG0_OTG_CRC1_DATA_RG 0x1b73 7941#define regOTG0_OTG_CRC1_DATA_RG_BASE_IDX 2 7942#define regOTG0_OTG_CRC1_DATA_B 0x1b74 7943#define regOTG0_OTG_CRC1_DATA_B_BASE_IDX 2 7944#define regOTG0_OTG_CRC2_DATA_RG 0x1b75 7945#define regOTG0_OTG_CRC2_DATA_RG_BASE_IDX 2 7946#define regOTG0_OTG_CRC2_DATA_B 0x1b76 7947#define regOTG0_OTG_CRC2_DATA_B_BASE_IDX 2 7948#define regOTG0_OTG_CRC3_DATA_RG 0x1b77 7949#define regOTG0_OTG_CRC3_DATA_RG_BASE_IDX 2 7950#define regOTG0_OTG_CRC3_DATA_B 0x1b78 7951#define regOTG0_OTG_CRC3_DATA_B_BASE_IDX 2 7952#define regOTG0_OTG_CRC_SIG_RED_GREEN_MASK 0x1b79 7953#define regOTG0_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 7954#define regOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1b7a 7955#define regOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 7956#define regOTG0_OTG_STATIC_SCREEN_CONTROL 0x1b81 7957#define regOTG0_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 7958#define regOTG0_OTG_3D_STRUCTURE_CONTROL 0x1b82 7959#define regOTG0_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 7960#define regOTG0_OTG_GSL_VSYNC_GAP 0x1b83 7961#define regOTG0_OTG_GSL_VSYNC_GAP_BASE_IDX 2 7962#define regOTG0_OTG_MASTER_UPDATE_MODE 0x1b84 7963#define regOTG0_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 7964#define regOTG0_OTG_CLOCK_CONTROL 0x1b85 7965#define regOTG0_OTG_CLOCK_CONTROL_BASE_IDX 2 7966#define regOTG0_OTG_VSTARTUP_PARAM 0x1b86 7967#define regOTG0_OTG_VSTARTUP_PARAM_BASE_IDX 2 7968#define regOTG0_OTG_VUPDATE_PARAM 0x1b87 7969#define regOTG0_OTG_VUPDATE_PARAM_BASE_IDX 2 7970#define regOTG0_OTG_VREADY_PARAM 0x1b88 7971#define regOTG0_OTG_VREADY_PARAM_BASE_IDX 2 7972#define regOTG0_OTG_GLOBAL_SYNC_STATUS 0x1b89 7973#define regOTG0_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 7974#define regOTG0_OTG_MASTER_UPDATE_LOCK 0x1b8a 7975#define regOTG0_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 7976#define regOTG0_OTG_GSL_CONTROL 0x1b8b 7977#define regOTG0_OTG_GSL_CONTROL_BASE_IDX 2 7978#define regOTG0_OTG_GSL_WINDOW_X 0x1b8c 7979#define regOTG0_OTG_GSL_WINDOW_X_BASE_IDX 2 7980#define regOTG0_OTG_GSL_WINDOW_Y 0x1b8d 7981#define regOTG0_OTG_GSL_WINDOW_Y_BASE_IDX 2 7982#define regOTG0_OTG_VUPDATE_KEEPOUT 0x1b8e 7983#define regOTG0_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 7984#define regOTG0_OTG_GLOBAL_CONTROL0 0x1b8f 7985#define regOTG0_OTG_GLOBAL_CONTROL0_BASE_IDX 2 7986#define regOTG0_OTG_GLOBAL_CONTROL1 0x1b90 7987#define regOTG0_OTG_GLOBAL_CONTROL1_BASE_IDX 2 7988#define regOTG0_OTG_GLOBAL_CONTROL2 0x1b91 7989#define regOTG0_OTG_GLOBAL_CONTROL2_BASE_IDX 2 7990#define regOTG0_OTG_GLOBAL_CONTROL3 0x1b92 7991#define regOTG0_OTG_GLOBAL_CONTROL3_BASE_IDX 2 7992#define regOTG0_OTG_GLOBAL_CONTROL4 0x1b93 7993#define regOTG0_OTG_GLOBAL_CONTROL4_BASE_IDX 2 7994#define regOTG0_OTG_TRIG_MANUAL_CONTROL 0x1b94 7995#define regOTG0_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 7996#define regOTG0_OTG_MANUAL_FLOW_CONTROL 0x1b95 7997#define regOTG0_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 7998#define regOTG0_OTG_DRR_TIMING_INT_STATUS 0x1b96 7999#define regOTG0_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 8000#define regOTG0_OTG_DRR_V_TOTAL_REACH_RANGE 0x1b97 8001#define regOTG0_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 8002#define regOTG0_OTG_DRR_V_TOTAL_CHANGE 0x1b98 8003#define regOTG0_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 8004#define regOTG0_OTG_DRR_TRIGGER_WINDOW 0x1b99 8005#define regOTG0_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 8006#define regOTG0_OTG_DRR_CONTROL 0x1b9a 8007#define regOTG0_OTG_DRR_CONTROL_BASE_IDX 2 8008#define regOTG0_OTG_M_CONST_DTO0 0x1b9b 8009#define regOTG0_OTG_M_CONST_DTO0_BASE_IDX 2 8010#define regOTG0_OTG_M_CONST_DTO1 0x1b9c 8011#define regOTG0_OTG_M_CONST_DTO1_BASE_IDX 2 8012#define regOTG0_OTG_REQUEST_CONTROL 0x1b9d 8013#define regOTG0_OTG_REQUEST_CONTROL_BASE_IDX 2 8014#define regOTG0_OTG_DSC_START_POSITION 0x1b9e 8015#define regOTG0_OTG_DSC_START_POSITION_BASE_IDX 2 8016#define regOTG0_OTG_PIPE_UPDATE_STATUS 0x1b9f 8017#define regOTG0_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 8018#define regOTG0_OTG_SPARE_REGISTER 0x1ba1 8019#define regOTG0_OTG_SPARE_REGISTER_BASE_IDX 2 8020 8021 8022// addressBlock: dce_dc_optc_otg1_dispdec 8023// base address: 0x200 8024#define regOTG1_OTG_H_TOTAL 0x1baa 8025#define regOTG1_OTG_H_TOTAL_BASE_IDX 2 8026#define regOTG1_OTG_H_BLANK_START_END 0x1bab 8027#define regOTG1_OTG_H_BLANK_START_END_BASE_IDX 2 8028#define regOTG1_OTG_H_SYNC_A 0x1bac 8029#define regOTG1_OTG_H_SYNC_A_BASE_IDX 2 8030#define regOTG1_OTG_H_SYNC_A_CNTL 0x1bad 8031#define regOTG1_OTG_H_SYNC_A_CNTL_BASE_IDX 2 8032#define regOTG1_OTG_H_TIMING_CNTL 0x1bae 8033#define regOTG1_OTG_H_TIMING_CNTL_BASE_IDX 2 8034#define regOTG1_OTG_V_TOTAL 0x1baf 8035#define regOTG1_OTG_V_TOTAL_BASE_IDX 2 8036#define regOTG1_OTG_V_TOTAL_MIN 0x1bb0 8037#define regOTG1_OTG_V_TOTAL_MIN_BASE_IDX 2 8038#define regOTG1_OTG_V_TOTAL_MAX 0x1bb1 8039#define regOTG1_OTG_V_TOTAL_MAX_BASE_IDX 2 8040#define regOTG1_OTG_V_TOTAL_MID 0x1bb2 8041#define regOTG1_OTG_V_TOTAL_MID_BASE_IDX 2 8042#define regOTG1_OTG_V_TOTAL_CONTROL 0x1bb3 8043#define regOTG1_OTG_V_TOTAL_CONTROL_BASE_IDX 2 8044#define regOTG1_OTG_V_TOTAL_INT_STATUS 0x1bb4 8045#define regOTG1_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 8046#define regOTG1_OTG_VSYNC_NOM_INT_STATUS 0x1bb5 8047#define regOTG1_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 8048#define regOTG1_OTG_V_BLANK_START_END 0x1bb6 8049#define regOTG1_OTG_V_BLANK_START_END_BASE_IDX 2 8050#define regOTG1_OTG_V_SYNC_A 0x1bb7 8051#define regOTG1_OTG_V_SYNC_A_BASE_IDX 2 8052#define regOTG1_OTG_V_SYNC_A_CNTL 0x1bb8 8053#define regOTG1_OTG_V_SYNC_A_CNTL_BASE_IDX 2 8054#define regOTG1_OTG_TRIGA_CNTL 0x1bb9 8055#define regOTG1_OTG_TRIGA_CNTL_BASE_IDX 2 8056#define regOTG1_OTG_TRIGA_MANUAL_TRIG 0x1bba 8057#define regOTG1_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 8058#define regOTG1_OTG_TRIGB_CNTL 0x1bbb 8059#define regOTG1_OTG_TRIGB_CNTL_BASE_IDX 2 8060#define regOTG1_OTG_TRIGB_MANUAL_TRIG 0x1bbc 8061#define regOTG1_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 8062#define regOTG1_OTG_FORCE_COUNT_NOW_CNTL 0x1bbd 8063#define regOTG1_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 8064#define regOTG1_OTG_FLOW_CONTROL 0x1bbe 8065#define regOTG1_OTG_FLOW_CONTROL_BASE_IDX 2 8066#define regOTG1_OTG_STEREO_FORCE_NEXT_EYE 0x1bbf 8067#define regOTG1_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 8068#define regOTG1_OTG_CONTROL 0x1bc1 8069#define regOTG1_OTG_CONTROL_BASE_IDX 2 8070#define regOTG1_OTG_INTERLACE_CONTROL 0x1bc4 8071#define regOTG1_OTG_INTERLACE_CONTROL_BASE_IDX 2 8072#define regOTG1_OTG_INTERLACE_STATUS 0x1bc5 8073#define regOTG1_OTG_INTERLACE_STATUS_BASE_IDX 2 8074#define regOTG1_OTG_PIXEL_DATA_READBACK0 0x1bc7 8075#define regOTG1_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 8076#define regOTG1_OTG_PIXEL_DATA_READBACK1 0x1bc8 8077#define regOTG1_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 8078#define regOTG1_OTG_STATUS 0x1bc9 8079#define regOTG1_OTG_STATUS_BASE_IDX 2 8080#define regOTG1_OTG_STATUS_POSITION 0x1bca 8081#define regOTG1_OTG_STATUS_POSITION_BASE_IDX 2 8082#define regOTG1_OTG_NOM_VERT_POSITION 0x1bcb 8083#define regOTG1_OTG_NOM_VERT_POSITION_BASE_IDX 2 8084#define regOTG1_OTG_STATUS_FRAME_COUNT 0x1bcc 8085#define regOTG1_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 8086#define regOTG1_OTG_STATUS_VF_COUNT 0x1bcd 8087#define regOTG1_OTG_STATUS_VF_COUNT_BASE_IDX 2 8088#define regOTG1_OTG_STATUS_HV_COUNT 0x1bce 8089#define regOTG1_OTG_STATUS_HV_COUNT_BASE_IDX 2 8090#define regOTG1_OTG_COUNT_CONTROL 0x1bcf 8091#define regOTG1_OTG_COUNT_CONTROL_BASE_IDX 2 8092#define regOTG1_OTG_COUNT_RESET 0x1bd0 8093#define regOTG1_OTG_COUNT_RESET_BASE_IDX 2 8094#define regOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bd1 8095#define regOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 8096#define regOTG1_OTG_VERT_SYNC_CONTROL 0x1bd2 8097#define regOTG1_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 8098#define regOTG1_OTG_STEREO_STATUS 0x1bd3 8099#define regOTG1_OTG_STEREO_STATUS_BASE_IDX 2 8100#define regOTG1_OTG_STEREO_CONTROL 0x1bd4 8101#define regOTG1_OTG_STEREO_CONTROL_BASE_IDX 2 8102#define regOTG1_OTG_SNAPSHOT_STATUS 0x1bd5 8103#define regOTG1_OTG_SNAPSHOT_STATUS_BASE_IDX 2 8104#define regOTG1_OTG_SNAPSHOT_CONTROL 0x1bd6 8105#define regOTG1_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 8106#define regOTG1_OTG_SNAPSHOT_POSITION 0x1bd7 8107#define regOTG1_OTG_SNAPSHOT_POSITION_BASE_IDX 2 8108#define regOTG1_OTG_SNAPSHOT_FRAME 0x1bd8 8109#define regOTG1_OTG_SNAPSHOT_FRAME_BASE_IDX 2 8110#define regOTG1_OTG_INTERRUPT_CONTROL 0x1bd9 8111#define regOTG1_OTG_INTERRUPT_CONTROL_BASE_IDX 2 8112#define regOTG1_OTG_UPDATE_LOCK 0x1bda 8113#define regOTG1_OTG_UPDATE_LOCK_BASE_IDX 2 8114#define regOTG1_OTG_DOUBLE_BUFFER_CONTROL 0x1bdb 8115#define regOTG1_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 8116#define regOTG1_OTG_MASTER_EN 0x1bdc 8117#define regOTG1_OTG_MASTER_EN_BASE_IDX 2 8118#define regOTG1_OTG_VERTICAL_INTERRUPT0_POSITION 0x1be2 8119#define regOTG1_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 8120#define regOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1be3 8121#define regOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 8122#define regOTG1_OTG_VERTICAL_INTERRUPT1_POSITION 0x1be4 8123#define regOTG1_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 8124#define regOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1be5 8125#define regOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 8126#define regOTG1_OTG_VERTICAL_INTERRUPT2_POSITION 0x1be6 8127#define regOTG1_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 8128#define regOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1be7 8129#define regOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 8130#define regOTG1_OTG_CRC_CNTL 0x1be8 8131#define regOTG1_OTG_CRC_CNTL_BASE_IDX 2 8132#define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL 0x1be9 8133#define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 8134#define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL 0x1bea 8135#define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 8136#define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL 0x1beb 8137#define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 8138#define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL 0x1bec 8139#define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 8140#define regOTG1_OTG_CRC0_DATA_RG 0x1bed 8141#define regOTG1_OTG_CRC0_DATA_RG_BASE_IDX 2 8142#define regOTG1_OTG_CRC0_DATA_B 0x1bee 8143#define regOTG1_OTG_CRC0_DATA_B_BASE_IDX 2 8144#define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL 0x1bef 8145#define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 8146#define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL 0x1bf0 8147#define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 8148#define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL 0x1bf1 8149#define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 8150#define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL 0x1bf2 8151#define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 8152#define regOTG1_OTG_CRC1_DATA_RG 0x1bf3 8153#define regOTG1_OTG_CRC1_DATA_RG_BASE_IDX 2 8154#define regOTG1_OTG_CRC1_DATA_B 0x1bf4 8155#define regOTG1_OTG_CRC1_DATA_B_BASE_IDX 2 8156#define regOTG1_OTG_CRC2_DATA_RG 0x1bf5 8157#define regOTG1_OTG_CRC2_DATA_RG_BASE_IDX 2 8158#define regOTG1_OTG_CRC2_DATA_B 0x1bf6 8159#define regOTG1_OTG_CRC2_DATA_B_BASE_IDX 2 8160#define regOTG1_OTG_CRC3_DATA_RG 0x1bf7 8161#define regOTG1_OTG_CRC3_DATA_RG_BASE_IDX 2 8162#define regOTG1_OTG_CRC3_DATA_B 0x1bf8 8163#define regOTG1_OTG_CRC3_DATA_B_BASE_IDX 2 8164#define regOTG1_OTG_CRC_SIG_RED_GREEN_MASK 0x1bf9 8165#define regOTG1_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 8166#define regOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1bfa 8167#define regOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 8168#define regOTG1_OTG_STATIC_SCREEN_CONTROL 0x1c01 8169#define regOTG1_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 8170#define regOTG1_OTG_3D_STRUCTURE_CONTROL 0x1c02 8171#define regOTG1_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 8172#define regOTG1_OTG_GSL_VSYNC_GAP 0x1c03 8173#define regOTG1_OTG_GSL_VSYNC_GAP_BASE_IDX 2 8174#define regOTG1_OTG_MASTER_UPDATE_MODE 0x1c04 8175#define regOTG1_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 8176#define regOTG1_OTG_CLOCK_CONTROL 0x1c05 8177#define regOTG1_OTG_CLOCK_CONTROL_BASE_IDX 2 8178#define regOTG1_OTG_VSTARTUP_PARAM 0x1c06 8179#define regOTG1_OTG_VSTARTUP_PARAM_BASE_IDX 2 8180#define regOTG1_OTG_VUPDATE_PARAM 0x1c07 8181#define regOTG1_OTG_VUPDATE_PARAM_BASE_IDX 2 8182#define regOTG1_OTG_VREADY_PARAM 0x1c08 8183#define regOTG1_OTG_VREADY_PARAM_BASE_IDX 2 8184#define regOTG1_OTG_GLOBAL_SYNC_STATUS 0x1c09 8185#define regOTG1_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 8186#define regOTG1_OTG_MASTER_UPDATE_LOCK 0x1c0a 8187#define regOTG1_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 8188#define regOTG1_OTG_GSL_CONTROL 0x1c0b 8189#define regOTG1_OTG_GSL_CONTROL_BASE_IDX 2 8190#define regOTG1_OTG_GSL_WINDOW_X 0x1c0c 8191#define regOTG1_OTG_GSL_WINDOW_X_BASE_IDX 2 8192#define regOTG1_OTG_GSL_WINDOW_Y 0x1c0d 8193#define regOTG1_OTG_GSL_WINDOW_Y_BASE_IDX 2 8194#define regOTG1_OTG_VUPDATE_KEEPOUT 0x1c0e 8195#define regOTG1_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 8196#define regOTG1_OTG_GLOBAL_CONTROL0 0x1c0f 8197#define regOTG1_OTG_GLOBAL_CONTROL0_BASE_IDX 2 8198#define regOTG1_OTG_GLOBAL_CONTROL1 0x1c10 8199#define regOTG1_OTG_GLOBAL_CONTROL1_BASE_IDX 2 8200#define regOTG1_OTG_GLOBAL_CONTROL2 0x1c11 8201#define regOTG1_OTG_GLOBAL_CONTROL2_BASE_IDX 2 8202#define regOTG1_OTG_GLOBAL_CONTROL3 0x1c12 8203#define regOTG1_OTG_GLOBAL_CONTROL3_BASE_IDX 2 8204#define regOTG1_OTG_GLOBAL_CONTROL4 0x1c13 8205#define regOTG1_OTG_GLOBAL_CONTROL4_BASE_IDX 2 8206#define regOTG1_OTG_TRIG_MANUAL_CONTROL 0x1c14 8207#define regOTG1_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 8208#define regOTG1_OTG_MANUAL_FLOW_CONTROL 0x1c15 8209#define regOTG1_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 8210#define regOTG1_OTG_DRR_TIMING_INT_STATUS 0x1c16 8211#define regOTG1_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 8212#define regOTG1_OTG_DRR_V_TOTAL_REACH_RANGE 0x1c17 8213#define regOTG1_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 8214#define regOTG1_OTG_DRR_V_TOTAL_CHANGE 0x1c18 8215#define regOTG1_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 8216#define regOTG1_OTG_DRR_TRIGGER_WINDOW 0x1c19 8217#define regOTG1_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 8218#define regOTG1_OTG_DRR_CONTROL 0x1c1a 8219#define regOTG1_OTG_DRR_CONTROL_BASE_IDX 2 8220#define regOTG1_OTG_M_CONST_DTO0 0x1c1b 8221#define regOTG1_OTG_M_CONST_DTO0_BASE_IDX 2 8222#define regOTG1_OTG_M_CONST_DTO1 0x1c1c 8223#define regOTG1_OTG_M_CONST_DTO1_BASE_IDX 2 8224#define regOTG1_OTG_REQUEST_CONTROL 0x1c1d 8225#define regOTG1_OTG_REQUEST_CONTROL_BASE_IDX 2 8226#define regOTG1_OTG_DSC_START_POSITION 0x1c1e 8227#define regOTG1_OTG_DSC_START_POSITION_BASE_IDX 2 8228#define regOTG1_OTG_PIPE_UPDATE_STATUS 0x1c1f 8229#define regOTG1_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 8230#define regOTG1_OTG_SPARE_REGISTER 0x1c21 8231#define regOTG1_OTG_SPARE_REGISTER_BASE_IDX 2 8232 8233 8234// addressBlock: dce_dc_optc_otg2_dispdec 8235// base address: 0x400 8236#define regOTG2_OTG_H_TOTAL 0x1c2a 8237#define regOTG2_OTG_H_TOTAL_BASE_IDX 2 8238#define regOTG2_OTG_H_BLANK_START_END 0x1c2b 8239#define regOTG2_OTG_H_BLANK_START_END_BASE_IDX 2 8240#define regOTG2_OTG_H_SYNC_A 0x1c2c 8241#define regOTG2_OTG_H_SYNC_A_BASE_IDX 2 8242#define regOTG2_OTG_H_SYNC_A_CNTL 0x1c2d 8243#define regOTG2_OTG_H_SYNC_A_CNTL_BASE_IDX 2 8244#define regOTG2_OTG_H_TIMING_CNTL 0x1c2e 8245#define regOTG2_OTG_H_TIMING_CNTL_BASE_IDX 2 8246#define regOTG2_OTG_V_TOTAL 0x1c2f 8247#define regOTG2_OTG_V_TOTAL_BASE_IDX 2 8248#define regOTG2_OTG_V_TOTAL_MIN 0x1c30 8249#define regOTG2_OTG_V_TOTAL_MIN_BASE_IDX 2 8250#define regOTG2_OTG_V_TOTAL_MAX 0x1c31 8251#define regOTG2_OTG_V_TOTAL_MAX_BASE_IDX 2 8252#define regOTG2_OTG_V_TOTAL_MID 0x1c32 8253#define regOTG2_OTG_V_TOTAL_MID_BASE_IDX 2 8254#define regOTG2_OTG_V_TOTAL_CONTROL 0x1c33 8255#define regOTG2_OTG_V_TOTAL_CONTROL_BASE_IDX 2 8256#define regOTG2_OTG_V_TOTAL_INT_STATUS 0x1c34 8257#define regOTG2_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 8258#define regOTG2_OTG_VSYNC_NOM_INT_STATUS 0x1c35 8259#define regOTG2_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 8260#define regOTG2_OTG_V_BLANK_START_END 0x1c36 8261#define regOTG2_OTG_V_BLANK_START_END_BASE_IDX 2 8262#define regOTG2_OTG_V_SYNC_A 0x1c37 8263#define regOTG2_OTG_V_SYNC_A_BASE_IDX 2 8264#define regOTG2_OTG_V_SYNC_A_CNTL 0x1c38 8265#define regOTG2_OTG_V_SYNC_A_CNTL_BASE_IDX 2 8266#define regOTG2_OTG_TRIGA_CNTL 0x1c39 8267#define regOTG2_OTG_TRIGA_CNTL_BASE_IDX 2 8268#define regOTG2_OTG_TRIGA_MANUAL_TRIG 0x1c3a 8269#define regOTG2_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 8270#define regOTG2_OTG_TRIGB_CNTL 0x1c3b 8271#define regOTG2_OTG_TRIGB_CNTL_BASE_IDX 2 8272#define regOTG2_OTG_TRIGB_MANUAL_TRIG 0x1c3c 8273#define regOTG2_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 8274#define regOTG2_OTG_FORCE_COUNT_NOW_CNTL 0x1c3d 8275#define regOTG2_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 8276#define regOTG2_OTG_FLOW_CONTROL 0x1c3e 8277#define regOTG2_OTG_FLOW_CONTROL_BASE_IDX 2 8278#define regOTG2_OTG_STEREO_FORCE_NEXT_EYE 0x1c3f 8279#define regOTG2_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 8280#define regOTG2_OTG_CONTROL 0x1c41 8281#define regOTG2_OTG_CONTROL_BASE_IDX 2 8282#define regOTG2_OTG_INTERLACE_CONTROL 0x1c44 8283#define regOTG2_OTG_INTERLACE_CONTROL_BASE_IDX 2 8284#define regOTG2_OTG_INTERLACE_STATUS 0x1c45 8285#define regOTG2_OTG_INTERLACE_STATUS_BASE_IDX 2 8286#define regOTG2_OTG_PIXEL_DATA_READBACK0 0x1c47 8287#define regOTG2_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 8288#define regOTG2_OTG_PIXEL_DATA_READBACK1 0x1c48 8289#define regOTG2_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 8290#define regOTG2_OTG_STATUS 0x1c49 8291#define regOTG2_OTG_STATUS_BASE_IDX 2 8292#define regOTG2_OTG_STATUS_POSITION 0x1c4a 8293#define regOTG2_OTG_STATUS_POSITION_BASE_IDX 2 8294#define regOTG2_OTG_NOM_VERT_POSITION 0x1c4b 8295#define regOTG2_OTG_NOM_VERT_POSITION_BASE_IDX 2 8296#define regOTG2_OTG_STATUS_FRAME_COUNT 0x1c4c 8297#define regOTG2_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 8298#define regOTG2_OTG_STATUS_VF_COUNT 0x1c4d 8299#define regOTG2_OTG_STATUS_VF_COUNT_BASE_IDX 2 8300#define regOTG2_OTG_STATUS_HV_COUNT 0x1c4e 8301#define regOTG2_OTG_STATUS_HV_COUNT_BASE_IDX 2 8302#define regOTG2_OTG_COUNT_CONTROL 0x1c4f 8303#define regOTG2_OTG_COUNT_CONTROL_BASE_IDX 2 8304#define regOTG2_OTG_COUNT_RESET 0x1c50 8305#define regOTG2_OTG_COUNT_RESET_BASE_IDX 2 8306#define regOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1c51 8307#define regOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 8308#define regOTG2_OTG_VERT_SYNC_CONTROL 0x1c52 8309#define regOTG2_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 8310#define regOTG2_OTG_STEREO_STATUS 0x1c53 8311#define regOTG2_OTG_STEREO_STATUS_BASE_IDX 2 8312#define regOTG2_OTG_STEREO_CONTROL 0x1c54 8313#define regOTG2_OTG_STEREO_CONTROL_BASE_IDX 2 8314#define regOTG2_OTG_SNAPSHOT_STATUS 0x1c55 8315#define regOTG2_OTG_SNAPSHOT_STATUS_BASE_IDX 2 8316#define regOTG2_OTG_SNAPSHOT_CONTROL 0x1c56 8317#define regOTG2_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 8318#define regOTG2_OTG_SNAPSHOT_POSITION 0x1c57 8319#define regOTG2_OTG_SNAPSHOT_POSITION_BASE_IDX 2 8320#define regOTG2_OTG_SNAPSHOT_FRAME 0x1c58 8321#define regOTG2_OTG_SNAPSHOT_FRAME_BASE_IDX 2 8322#define regOTG2_OTG_INTERRUPT_CONTROL 0x1c59 8323#define regOTG2_OTG_INTERRUPT_CONTROL_BASE_IDX 2 8324#define regOTG2_OTG_UPDATE_LOCK 0x1c5a 8325#define regOTG2_OTG_UPDATE_LOCK_BASE_IDX 2 8326#define regOTG2_OTG_DOUBLE_BUFFER_CONTROL 0x1c5b 8327#define regOTG2_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 8328#define regOTG2_OTG_MASTER_EN 0x1c5c 8329#define regOTG2_OTG_MASTER_EN_BASE_IDX 2 8330#define regOTG2_OTG_VERTICAL_INTERRUPT0_POSITION 0x1c62 8331#define regOTG2_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 8332#define regOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1c63 8333#define regOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 8334#define regOTG2_OTG_VERTICAL_INTERRUPT1_POSITION 0x1c64 8335#define regOTG2_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 8336#define regOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1c65 8337#define regOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 8338#define regOTG2_OTG_VERTICAL_INTERRUPT2_POSITION 0x1c66 8339#define regOTG2_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 8340#define regOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1c67 8341#define regOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 8342#define regOTG2_OTG_CRC_CNTL 0x1c68 8343#define regOTG2_OTG_CRC_CNTL_BASE_IDX 2 8344#define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL 0x1c69 8345#define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 8346#define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL 0x1c6a 8347#define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 8348#define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL 0x1c6b 8349#define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 8350#define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL 0x1c6c 8351#define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 8352#define regOTG2_OTG_CRC0_DATA_RG 0x1c6d 8353#define regOTG2_OTG_CRC0_DATA_RG_BASE_IDX 2 8354#define regOTG2_OTG_CRC0_DATA_B 0x1c6e 8355#define regOTG2_OTG_CRC0_DATA_B_BASE_IDX 2 8356#define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL 0x1c6f 8357#define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 8358#define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL 0x1c70 8359#define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 8360#define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL 0x1c71 8361#define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 8362#define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL 0x1c72 8363#define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 8364#define regOTG2_OTG_CRC1_DATA_RG 0x1c73 8365#define regOTG2_OTG_CRC1_DATA_RG_BASE_IDX 2 8366#define regOTG2_OTG_CRC1_DATA_B 0x1c74 8367#define regOTG2_OTG_CRC1_DATA_B_BASE_IDX 2 8368#define regOTG2_OTG_CRC2_DATA_RG 0x1c75 8369#define regOTG2_OTG_CRC2_DATA_RG_BASE_IDX 2 8370#define regOTG2_OTG_CRC2_DATA_B 0x1c76 8371#define regOTG2_OTG_CRC2_DATA_B_BASE_IDX 2 8372#define regOTG2_OTG_CRC3_DATA_RG 0x1c77 8373#define regOTG2_OTG_CRC3_DATA_RG_BASE_IDX 2 8374#define regOTG2_OTG_CRC3_DATA_B 0x1c78 8375#define regOTG2_OTG_CRC3_DATA_B_BASE_IDX 2 8376#define regOTG2_OTG_CRC_SIG_RED_GREEN_MASK 0x1c79 8377#define regOTG2_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 8378#define regOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1c7a 8379#define regOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 8380#define regOTG2_OTG_STATIC_SCREEN_CONTROL 0x1c81 8381#define regOTG2_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 8382#define regOTG2_OTG_3D_STRUCTURE_CONTROL 0x1c82 8383#define regOTG2_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 8384#define regOTG2_OTG_GSL_VSYNC_GAP 0x1c83 8385#define regOTG2_OTG_GSL_VSYNC_GAP_BASE_IDX 2 8386#define regOTG2_OTG_MASTER_UPDATE_MODE 0x1c84 8387#define regOTG2_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 8388#define regOTG2_OTG_CLOCK_CONTROL 0x1c85 8389#define regOTG2_OTG_CLOCK_CONTROL_BASE_IDX 2 8390#define regOTG2_OTG_VSTARTUP_PARAM 0x1c86 8391#define regOTG2_OTG_VSTARTUP_PARAM_BASE_IDX 2 8392#define regOTG2_OTG_VUPDATE_PARAM 0x1c87 8393#define regOTG2_OTG_VUPDATE_PARAM_BASE_IDX 2 8394#define regOTG2_OTG_VREADY_PARAM 0x1c88 8395#define regOTG2_OTG_VREADY_PARAM_BASE_IDX 2 8396#define regOTG2_OTG_GLOBAL_SYNC_STATUS 0x1c89 8397#define regOTG2_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 8398#define regOTG2_OTG_MASTER_UPDATE_LOCK 0x1c8a 8399#define regOTG2_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 8400#define regOTG2_OTG_GSL_CONTROL 0x1c8b 8401#define regOTG2_OTG_GSL_CONTROL_BASE_IDX 2 8402#define regOTG2_OTG_GSL_WINDOW_X 0x1c8c 8403#define regOTG2_OTG_GSL_WINDOW_X_BASE_IDX 2 8404#define regOTG2_OTG_GSL_WINDOW_Y 0x1c8d 8405#define regOTG2_OTG_GSL_WINDOW_Y_BASE_IDX 2 8406#define regOTG2_OTG_VUPDATE_KEEPOUT 0x1c8e 8407#define regOTG2_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 8408#define regOTG2_OTG_GLOBAL_CONTROL0 0x1c8f 8409#define regOTG2_OTG_GLOBAL_CONTROL0_BASE_IDX 2 8410#define regOTG2_OTG_GLOBAL_CONTROL1 0x1c90 8411#define regOTG2_OTG_GLOBAL_CONTROL1_BASE_IDX 2 8412#define regOTG2_OTG_GLOBAL_CONTROL2 0x1c91 8413#define regOTG2_OTG_GLOBAL_CONTROL2_BASE_IDX 2 8414#define regOTG2_OTG_GLOBAL_CONTROL3 0x1c92 8415#define regOTG2_OTG_GLOBAL_CONTROL3_BASE_IDX 2 8416#define regOTG2_OTG_GLOBAL_CONTROL4 0x1c93 8417#define regOTG2_OTG_GLOBAL_CONTROL4_BASE_IDX 2 8418#define regOTG2_OTG_TRIG_MANUAL_CONTROL 0x1c94 8419#define regOTG2_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 8420#define regOTG2_OTG_MANUAL_FLOW_CONTROL 0x1c95 8421#define regOTG2_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 8422#define regOTG2_OTG_DRR_TIMING_INT_STATUS 0x1c96 8423#define regOTG2_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 8424#define regOTG2_OTG_DRR_V_TOTAL_REACH_RANGE 0x1c97 8425#define regOTG2_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 8426#define regOTG2_OTG_DRR_V_TOTAL_CHANGE 0x1c98 8427#define regOTG2_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 8428#define regOTG2_OTG_DRR_TRIGGER_WINDOW 0x1c99 8429#define regOTG2_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 8430#define regOTG2_OTG_DRR_CONTROL 0x1c9a 8431#define regOTG2_OTG_DRR_CONTROL_BASE_IDX 2 8432#define regOTG2_OTG_M_CONST_DTO0 0x1c9b 8433#define regOTG2_OTG_M_CONST_DTO0_BASE_IDX 2 8434#define regOTG2_OTG_M_CONST_DTO1 0x1c9c 8435#define regOTG2_OTG_M_CONST_DTO1_BASE_IDX 2 8436#define regOTG2_OTG_REQUEST_CONTROL 0x1c9d 8437#define regOTG2_OTG_REQUEST_CONTROL_BASE_IDX 2 8438#define regOTG2_OTG_DSC_START_POSITION 0x1c9e 8439#define regOTG2_OTG_DSC_START_POSITION_BASE_IDX 2 8440#define regOTG2_OTG_PIPE_UPDATE_STATUS 0x1c9f 8441#define regOTG2_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 8442#define regOTG2_OTG_SPARE_REGISTER 0x1ca1 8443#define regOTG2_OTG_SPARE_REGISTER_BASE_IDX 2 8444 8445 8446// addressBlock: dce_dc_optc_otg3_dispdec 8447// base address: 0x600 8448#define regOTG3_OTG_H_TOTAL 0x1caa 8449#define regOTG3_OTG_H_TOTAL_BASE_IDX 2 8450#define regOTG3_OTG_H_BLANK_START_END 0x1cab 8451#define regOTG3_OTG_H_BLANK_START_END_BASE_IDX 2 8452#define regOTG3_OTG_H_SYNC_A 0x1cac 8453#define regOTG3_OTG_H_SYNC_A_BASE_IDX 2 8454#define regOTG3_OTG_H_SYNC_A_CNTL 0x1cad 8455#define regOTG3_OTG_H_SYNC_A_CNTL_BASE_IDX 2 8456#define regOTG3_OTG_H_TIMING_CNTL 0x1cae 8457#define regOTG3_OTG_H_TIMING_CNTL_BASE_IDX 2 8458#define regOTG3_OTG_V_TOTAL 0x1caf 8459#define regOTG3_OTG_V_TOTAL_BASE_IDX 2 8460#define regOTG3_OTG_V_TOTAL_MIN 0x1cb0 8461#define regOTG3_OTG_V_TOTAL_MIN_BASE_IDX 2 8462#define regOTG3_OTG_V_TOTAL_MAX 0x1cb1 8463#define regOTG3_OTG_V_TOTAL_MAX_BASE_IDX 2 8464#define regOTG3_OTG_V_TOTAL_MID 0x1cb2 8465#define regOTG3_OTG_V_TOTAL_MID_BASE_IDX 2 8466#define regOTG3_OTG_V_TOTAL_CONTROL 0x1cb3 8467#define regOTG3_OTG_V_TOTAL_CONTROL_BASE_IDX 2 8468#define regOTG3_OTG_V_TOTAL_INT_STATUS 0x1cb4 8469#define regOTG3_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 8470#define regOTG3_OTG_VSYNC_NOM_INT_STATUS 0x1cb5 8471#define regOTG3_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 8472#define regOTG3_OTG_V_BLANK_START_END 0x1cb6 8473#define regOTG3_OTG_V_BLANK_START_END_BASE_IDX 2 8474#define regOTG3_OTG_V_SYNC_A 0x1cb7 8475#define regOTG3_OTG_V_SYNC_A_BASE_IDX 2 8476#define regOTG3_OTG_V_SYNC_A_CNTL 0x1cb8 8477#define regOTG3_OTG_V_SYNC_A_CNTL_BASE_IDX 2 8478#define regOTG3_OTG_TRIGA_CNTL 0x1cb9 8479#define regOTG3_OTG_TRIGA_CNTL_BASE_IDX 2 8480#define regOTG3_OTG_TRIGA_MANUAL_TRIG 0x1cba 8481#define regOTG3_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 8482#define regOTG3_OTG_TRIGB_CNTL 0x1cbb 8483#define regOTG3_OTG_TRIGB_CNTL_BASE_IDX 2 8484#define regOTG3_OTG_TRIGB_MANUAL_TRIG 0x1cbc 8485#define regOTG3_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 8486#define regOTG3_OTG_FORCE_COUNT_NOW_CNTL 0x1cbd 8487#define regOTG3_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 8488#define regOTG3_OTG_FLOW_CONTROL 0x1cbe 8489#define regOTG3_OTG_FLOW_CONTROL_BASE_IDX 2 8490#define regOTG3_OTG_STEREO_FORCE_NEXT_EYE 0x1cbf 8491#define regOTG3_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 8492#define regOTG3_OTG_CONTROL 0x1cc1 8493#define regOTG3_OTG_CONTROL_BASE_IDX 2 8494#define regOTG3_OTG_INTERLACE_CONTROL 0x1cc4 8495#define regOTG3_OTG_INTERLACE_CONTROL_BASE_IDX 2 8496#define regOTG3_OTG_INTERLACE_STATUS 0x1cc5 8497#define regOTG3_OTG_INTERLACE_STATUS_BASE_IDX 2 8498#define regOTG3_OTG_PIXEL_DATA_READBACK0 0x1cc7 8499#define regOTG3_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 8500#define regOTG3_OTG_PIXEL_DATA_READBACK1 0x1cc8 8501#define regOTG3_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 8502#define regOTG3_OTG_STATUS 0x1cc9 8503#define regOTG3_OTG_STATUS_BASE_IDX 2 8504#define regOTG3_OTG_STATUS_POSITION 0x1cca 8505#define regOTG3_OTG_STATUS_POSITION_BASE_IDX 2 8506#define regOTG3_OTG_NOM_VERT_POSITION 0x1ccb 8507#define regOTG3_OTG_NOM_VERT_POSITION_BASE_IDX 2 8508#define regOTG3_OTG_STATUS_FRAME_COUNT 0x1ccc 8509#define regOTG3_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 8510#define regOTG3_OTG_STATUS_VF_COUNT 0x1ccd 8511#define regOTG3_OTG_STATUS_VF_COUNT_BASE_IDX 2 8512#define regOTG3_OTG_STATUS_HV_COUNT 0x1cce 8513#define regOTG3_OTG_STATUS_HV_COUNT_BASE_IDX 2 8514#define regOTG3_OTG_COUNT_CONTROL 0x1ccf 8515#define regOTG3_OTG_COUNT_CONTROL_BASE_IDX 2 8516#define regOTG3_OTG_COUNT_RESET 0x1cd0 8517#define regOTG3_OTG_COUNT_RESET_BASE_IDX 2 8518#define regOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1cd1 8519#define regOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 8520#define regOTG3_OTG_VERT_SYNC_CONTROL 0x1cd2 8521#define regOTG3_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 8522#define regOTG3_OTG_STEREO_STATUS 0x1cd3 8523#define regOTG3_OTG_STEREO_STATUS_BASE_IDX 2 8524#define regOTG3_OTG_STEREO_CONTROL 0x1cd4 8525#define regOTG3_OTG_STEREO_CONTROL_BASE_IDX 2 8526#define regOTG3_OTG_SNAPSHOT_STATUS 0x1cd5 8527#define regOTG3_OTG_SNAPSHOT_STATUS_BASE_IDX 2 8528#define regOTG3_OTG_SNAPSHOT_CONTROL 0x1cd6 8529#define regOTG3_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 8530#define regOTG3_OTG_SNAPSHOT_POSITION 0x1cd7 8531#define regOTG3_OTG_SNAPSHOT_POSITION_BASE_IDX 2 8532#define regOTG3_OTG_SNAPSHOT_FRAME 0x1cd8 8533#define regOTG3_OTG_SNAPSHOT_FRAME_BASE_IDX 2 8534#define regOTG3_OTG_INTERRUPT_CONTROL 0x1cd9 8535#define regOTG3_OTG_INTERRUPT_CONTROL_BASE_IDX 2 8536#define regOTG3_OTG_UPDATE_LOCK 0x1cda 8537#define regOTG3_OTG_UPDATE_LOCK_BASE_IDX 2 8538#define regOTG3_OTG_DOUBLE_BUFFER_CONTROL 0x1cdb 8539#define regOTG3_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 8540#define regOTG3_OTG_MASTER_EN 0x1cdc 8541#define regOTG3_OTG_MASTER_EN_BASE_IDX 2 8542#define regOTG3_OTG_VERTICAL_INTERRUPT0_POSITION 0x1ce2 8543#define regOTG3_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 8544#define regOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1ce3 8545#define regOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 8546#define regOTG3_OTG_VERTICAL_INTERRUPT1_POSITION 0x1ce4 8547#define regOTG3_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 8548#define regOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1ce5 8549#define regOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 8550#define regOTG3_OTG_VERTICAL_INTERRUPT2_POSITION 0x1ce6 8551#define regOTG3_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 8552#define regOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1ce7 8553#define regOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 8554#define regOTG3_OTG_CRC_CNTL 0x1ce8 8555#define regOTG3_OTG_CRC_CNTL_BASE_IDX 2 8556#define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL 0x1ce9 8557#define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 8558#define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL 0x1cea 8559#define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 8560#define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL 0x1ceb 8561#define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 8562#define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL 0x1cec 8563#define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 8564#define regOTG3_OTG_CRC0_DATA_RG 0x1ced 8565#define regOTG3_OTG_CRC0_DATA_RG_BASE_IDX 2 8566#define regOTG3_OTG_CRC0_DATA_B 0x1cee 8567#define regOTG3_OTG_CRC0_DATA_B_BASE_IDX 2 8568#define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL 0x1cef 8569#define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 8570#define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL 0x1cf0 8571#define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 8572#define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL 0x1cf1 8573#define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 8574#define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL 0x1cf2 8575#define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 8576#define regOTG3_OTG_CRC1_DATA_RG 0x1cf3 8577#define regOTG3_OTG_CRC1_DATA_RG_BASE_IDX 2 8578#define regOTG3_OTG_CRC1_DATA_B 0x1cf4 8579#define regOTG3_OTG_CRC1_DATA_B_BASE_IDX 2 8580#define regOTG3_OTG_CRC2_DATA_RG 0x1cf5 8581#define regOTG3_OTG_CRC2_DATA_RG_BASE_IDX 2 8582#define regOTG3_OTG_CRC2_DATA_B 0x1cf6 8583#define regOTG3_OTG_CRC2_DATA_B_BASE_IDX 2 8584#define regOTG3_OTG_CRC3_DATA_RG 0x1cf7 8585#define regOTG3_OTG_CRC3_DATA_RG_BASE_IDX 2 8586#define regOTG3_OTG_CRC3_DATA_B 0x1cf8 8587#define regOTG3_OTG_CRC3_DATA_B_BASE_IDX 2 8588#define regOTG3_OTG_CRC_SIG_RED_GREEN_MASK 0x1cf9 8589#define regOTG3_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 8590#define regOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1cfa 8591#define regOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 8592#define regOTG3_OTG_STATIC_SCREEN_CONTROL 0x1d01 8593#define regOTG3_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 8594#define regOTG3_OTG_3D_STRUCTURE_CONTROL 0x1d02 8595#define regOTG3_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 8596#define regOTG3_OTG_GSL_VSYNC_GAP 0x1d03 8597#define regOTG3_OTG_GSL_VSYNC_GAP_BASE_IDX 2 8598#define regOTG3_OTG_MASTER_UPDATE_MODE 0x1d04 8599#define regOTG3_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 8600#define regOTG3_OTG_CLOCK_CONTROL 0x1d05 8601#define regOTG3_OTG_CLOCK_CONTROL_BASE_IDX 2 8602#define regOTG3_OTG_VSTARTUP_PARAM 0x1d06 8603#define regOTG3_OTG_VSTARTUP_PARAM_BASE_IDX 2 8604#define regOTG3_OTG_VUPDATE_PARAM 0x1d07 8605#define regOTG3_OTG_VUPDATE_PARAM_BASE_IDX 2 8606#define regOTG3_OTG_VREADY_PARAM 0x1d08 8607#define regOTG3_OTG_VREADY_PARAM_BASE_IDX 2 8608#define regOTG3_OTG_GLOBAL_SYNC_STATUS 0x1d09 8609#define regOTG3_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 8610#define regOTG3_OTG_MASTER_UPDATE_LOCK 0x1d0a 8611#define regOTG3_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 8612#define regOTG3_OTG_GSL_CONTROL 0x1d0b 8613#define regOTG3_OTG_GSL_CONTROL_BASE_IDX 2 8614#define regOTG3_OTG_GSL_WINDOW_X 0x1d0c 8615#define regOTG3_OTG_GSL_WINDOW_X_BASE_IDX 2 8616#define regOTG3_OTG_GSL_WINDOW_Y 0x1d0d 8617#define regOTG3_OTG_GSL_WINDOW_Y_BASE_IDX 2 8618#define regOTG3_OTG_VUPDATE_KEEPOUT 0x1d0e 8619#define regOTG3_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 8620#define regOTG3_OTG_GLOBAL_CONTROL0 0x1d0f 8621#define regOTG3_OTG_GLOBAL_CONTROL0_BASE_IDX 2 8622#define regOTG3_OTG_GLOBAL_CONTROL1 0x1d10 8623#define regOTG3_OTG_GLOBAL_CONTROL1_BASE_IDX 2 8624#define regOTG3_OTG_GLOBAL_CONTROL2 0x1d11 8625#define regOTG3_OTG_GLOBAL_CONTROL2_BASE_IDX 2 8626#define regOTG3_OTG_GLOBAL_CONTROL3 0x1d12 8627#define regOTG3_OTG_GLOBAL_CONTROL3_BASE_IDX 2 8628#define regOTG3_OTG_GLOBAL_CONTROL4 0x1d13 8629#define regOTG3_OTG_GLOBAL_CONTROL4_BASE_IDX 2 8630#define regOTG3_OTG_TRIG_MANUAL_CONTROL 0x1d14 8631#define regOTG3_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 8632#define regOTG3_OTG_MANUAL_FLOW_CONTROL 0x1d15 8633#define regOTG3_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 8634#define regOTG3_OTG_DRR_TIMING_INT_STATUS 0x1d16 8635#define regOTG3_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 8636#define regOTG3_OTG_DRR_V_TOTAL_REACH_RANGE 0x1d17 8637#define regOTG3_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 8638#define regOTG3_OTG_DRR_V_TOTAL_CHANGE 0x1d18 8639#define regOTG3_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 8640#define regOTG3_OTG_DRR_TRIGGER_WINDOW 0x1d19 8641#define regOTG3_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 8642#define regOTG3_OTG_DRR_CONTROL 0x1d1a 8643#define regOTG3_OTG_DRR_CONTROL_BASE_IDX 2 8644#define regOTG3_OTG_M_CONST_DTO0 0x1d1b 8645#define regOTG3_OTG_M_CONST_DTO0_BASE_IDX 2 8646#define regOTG3_OTG_M_CONST_DTO1 0x1d1c 8647#define regOTG3_OTG_M_CONST_DTO1_BASE_IDX 2 8648#define regOTG3_OTG_REQUEST_CONTROL 0x1d1d 8649#define regOTG3_OTG_REQUEST_CONTROL_BASE_IDX 2 8650#define regOTG3_OTG_DSC_START_POSITION 0x1d1e 8651#define regOTG3_OTG_DSC_START_POSITION_BASE_IDX 2 8652#define regOTG3_OTG_PIPE_UPDATE_STATUS 0x1d1f 8653#define regOTG3_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 8654#define regOTG3_OTG_SPARE_REGISTER 0x1d21 8655#define regOTG3_OTG_SPARE_REGISTER_BASE_IDX 2 8656 8657 8658// addressBlock: dce_dc_optc_optc_misc_dispdec 8659// base address: 0x0 8660#define regGSL_SOURCE_SELECT 0x1e2b 8661#define regGSL_SOURCE_SELECT_BASE_IDX 2 8662#define regOPTC_CLOCK_CONTROL 0x1e2c 8663#define regOPTC_CLOCK_CONTROL_BASE_IDX 2 8664#define regODM_MEM_PWR_CTRL 0x1e2d 8665#define regODM_MEM_PWR_CTRL_BASE_IDX 2 8666#define regODM_MEM_PWR_CTRL3 0x1e2f 8667#define regODM_MEM_PWR_CTRL3_BASE_IDX 2 8668#define regODM_MEM_PWR_STATUS 0x1e30 8669#define regODM_MEM_PWR_STATUS_BASE_IDX 2 8670#define regOPTC_MISC_SPARE_REGISTER 0x1e31 8671#define regOPTC_MISC_SPARE_REGISTER_BASE_IDX 2 8672 8673 8674// addressBlock: dce_dc_optc_optc_dcperfmon_dc_perfmon_dispdec 8675// base address: 0x79a8 8676#define regDC_PERFMON15_PERFCOUNTER_CNTL 0x1e6a 8677#define regDC_PERFMON15_PERFCOUNTER_CNTL_BASE_IDX 2 8678#define regDC_PERFMON15_PERFCOUNTER_CNTL2 0x1e6b 8679#define regDC_PERFMON15_PERFCOUNTER_CNTL2_BASE_IDX 2 8680#define regDC_PERFMON15_PERFCOUNTER_STATE 0x1e6c 8681#define regDC_PERFMON15_PERFCOUNTER_STATE_BASE_IDX 2 8682#define regDC_PERFMON15_PERFMON_CNTL 0x1e6d 8683#define regDC_PERFMON15_PERFMON_CNTL_BASE_IDX 2 8684#define regDC_PERFMON15_PERFMON_CNTL2 0x1e6e 8685#define regDC_PERFMON15_PERFMON_CNTL2_BASE_IDX 2 8686#define regDC_PERFMON15_PERFMON_CVALUE_INT_MISC 0x1e6f 8687#define regDC_PERFMON15_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 8688#define regDC_PERFMON15_PERFMON_CVALUE_LOW 0x1e70 8689#define regDC_PERFMON15_PERFMON_CVALUE_LOW_BASE_IDX 2 8690#define regDC_PERFMON15_PERFMON_HI 0x1e71 8691#define regDC_PERFMON15_PERFMON_HI_BASE_IDX 2 8692#define regDC_PERFMON15_PERFMON_LOW 0x1e72 8693#define regDC_PERFMON15_PERFMON_LOW_BASE_IDX 2 8694 8695 8696// addressBlock: dce_dc_dio_dout_i2c_dispdec 8697// base address: 0x0 8698#define regDC_I2C_CONTROL 0x1e98 8699#define regDC_I2C_CONTROL_BASE_IDX 2 8700#define regDC_I2C_ARBITRATION 0x1e99 8701#define regDC_I2C_ARBITRATION_BASE_IDX 2 8702#define regDC_I2C_INTERRUPT_CONTROL 0x1e9a 8703#define regDC_I2C_INTERRUPT_CONTROL_BASE_IDX 2 8704#define regDC_I2C_SW_STATUS 0x1e9b 8705#define regDC_I2C_SW_STATUS_BASE_IDX 2 8706#define regDC_I2C_DDC1_HW_STATUS 0x1e9c 8707#define regDC_I2C_DDC1_HW_STATUS_BASE_IDX 2 8708#define regDC_I2C_DDC2_HW_STATUS 0x1e9d 8709#define regDC_I2C_DDC2_HW_STATUS_BASE_IDX 2 8710#define regDC_I2C_DDC3_HW_STATUS 0x1e9e 8711#define regDC_I2C_DDC3_HW_STATUS_BASE_IDX 2 8712#define regDC_I2C_DDC4_HW_STATUS 0x1e9f 8713#define regDC_I2C_DDC4_HW_STATUS_BASE_IDX 2 8714#define regDC_I2C_DDC5_HW_STATUS 0x1ea0 8715#define regDC_I2C_DDC5_HW_STATUS_BASE_IDX 2 8716#define regDC_I2C_DDC1_SPEED 0x1ea2 8717#define regDC_I2C_DDC1_SPEED_BASE_IDX 2 8718#define regDC_I2C_DDC1_SETUP 0x1ea3 8719#define regDC_I2C_DDC1_SETUP_BASE_IDX 2 8720#define regDC_I2C_DDC2_SPEED 0x1ea4 8721#define regDC_I2C_DDC2_SPEED_BASE_IDX 2 8722#define regDC_I2C_DDC2_SETUP 0x1ea5 8723#define regDC_I2C_DDC2_SETUP_BASE_IDX 2 8724#define regDC_I2C_DDC3_SPEED 0x1ea6 8725#define regDC_I2C_DDC3_SPEED_BASE_IDX 2 8726#define regDC_I2C_DDC3_SETUP 0x1ea7 8727#define regDC_I2C_DDC3_SETUP_BASE_IDX 2 8728#define regDC_I2C_DDC4_SPEED 0x1ea8 8729#define regDC_I2C_DDC4_SPEED_BASE_IDX 2 8730#define regDC_I2C_DDC4_SETUP 0x1ea9 8731#define regDC_I2C_DDC4_SETUP_BASE_IDX 2 8732#define regDC_I2C_DDC5_SPEED 0x1eaa 8733#define regDC_I2C_DDC5_SPEED_BASE_IDX 2 8734#define regDC_I2C_DDC5_SETUP 0x1eab 8735#define regDC_I2C_DDC5_SETUP_BASE_IDX 2 8736#define regDC_I2C_TRANSACTION0 0x1eae 8737#define regDC_I2C_TRANSACTION0_BASE_IDX 2 8738#define regDC_I2C_TRANSACTION1 0x1eaf 8739#define regDC_I2C_TRANSACTION1_BASE_IDX 2 8740#define regDC_I2C_TRANSACTION2 0x1eb0 8741#define regDC_I2C_TRANSACTION2_BASE_IDX 2 8742#define regDC_I2C_TRANSACTION3 0x1eb1 8743#define regDC_I2C_TRANSACTION3_BASE_IDX 2 8744#define regDC_I2C_DATA 0x1eb2 8745#define regDC_I2C_DATA_BASE_IDX 2 8746#define regDC_I2C_EDID_DETECT_CTRL 0x1eb6 8747#define regDC_I2C_EDID_DETECT_CTRL_BASE_IDX 2 8748#define regDC_I2C_READ_REQUEST_INTERRUPT 0x1eb7 8749#define regDC_I2C_READ_REQUEST_INTERRUPT_BASE_IDX 2 8750 8751 8752// addressBlock: dce_dc_dio_dio_misc_dispdec 8753// base address: 0x0 8754#define regDIO_SCRATCH0 0x1eca 8755#define regDIO_SCRATCH0_BASE_IDX 2 8756#define regDIO_SCRATCH1 0x1ecb 8757#define regDIO_SCRATCH1_BASE_IDX 2 8758#define regDIO_SCRATCH2 0x1ecc 8759#define regDIO_SCRATCH2_BASE_IDX 2 8760#define regDIO_SCRATCH3 0x1ecd 8761#define regDIO_SCRATCH3_BASE_IDX 2 8762#define regDIO_SCRATCH4 0x1ece 8763#define regDIO_SCRATCH4_BASE_IDX 2 8764#define regDIO_SCRATCH5 0x1ecf 8765#define regDIO_SCRATCH5_BASE_IDX 2 8766#define regDIO_SCRATCH6 0x1ed0 8767#define regDIO_SCRATCH6_BASE_IDX 2 8768#define regDIO_SCRATCH7 0x1ed1 8769#define regDIO_SCRATCH7_BASE_IDX 2 8770#define regDIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS 0x1ed3 8771#define regDIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS_BASE_IDX 2 8772#define regDIO_MEM_PWR_STATUS 0x1edd 8773#define regDIO_MEM_PWR_STATUS_BASE_IDX 2 8774#define regDIO_MEM_PWR_CTRL 0x1ede 8775#define regDIO_MEM_PWR_CTRL_BASE_IDX 2 8776#define regDIO_MEM_PWR_CTRL2 0x1edf 8777#define regDIO_MEM_PWR_CTRL2_BASE_IDX 2 8778#define regDIO_CLK_CNTL 0x1ee0 8779#define regDIO_CLK_CNTL_BASE_IDX 2 8780#define regDIO_POWER_MANAGEMENT_CNTL 0x1ee4 8781#define regDIO_POWER_MANAGEMENT_CNTL_BASE_IDX 2 8782#define regDIG_SOFT_RESET 0x1eee 8783#define regDIG_SOFT_RESET_BASE_IDX 2 8784#define regDIO_CLK_CNTL2 0x1ef2 8785#define regDIO_CLK_CNTL2_BASE_IDX 2 8786#define regDIO_CLK_CNTL3 0x1ef3 8787#define regDIO_CLK_CNTL3_BASE_IDX 2 8788#define regDIO_HDMI_RXSTATUS_TIMER_CONTROL 0x1eff 8789#define regDIO_HDMI_RXSTATUS_TIMER_CONTROL_BASE_IDX 2 8790#define regDIO_GENERIC_INTERRUPT_MESSAGE 0x1f02 8791#define regDIO_GENERIC_INTERRUPT_MESSAGE_BASE_IDX 2 8792#define regDIO_GENERIC_INTERRUPT_CLEAR 0x1f03 8793#define regDIO_GENERIC_INTERRUPT_CLEAR_BASE_IDX 2 8794#define regDIO_LINKA_CNTL 0x1f04 8795#define regDIO_LINKA_CNTL_BASE_IDX 2 8796#define regDIO_LINKB_CNTL 0x1f05 8797#define regDIO_LINKB_CNTL_BASE_IDX 2 8798#define regDIO_LINKC_CNTL 0x1f06 8799#define regDIO_LINKC_CNTL_BASE_IDX 2 8800#define regDIO_LINKD_CNTL 0x1f07 8801#define regDIO_LINKD_CNTL_BASE_IDX 2 8802#define regDIO_LINKE_CNTL 0x1f08 8803#define regDIO_LINKE_CNTL_BASE_IDX 2 8804#define regDIO_LINKF_CNTL 0x1f09 8805#define regDIO_LINKF_CNTL_BASE_IDX 2 8806 8807 8808// addressBlock: dce_dc_dio_hpd0_dispdec 8809// base address: 0x0 8810#define regHPD0_DC_HPD_INT_STATUS 0x1f14 8811#define regHPD0_DC_HPD_INT_STATUS_BASE_IDX 2 8812#define regHPD0_DC_HPD_INT_CONTROL 0x1f15 8813#define regHPD0_DC_HPD_INT_CONTROL_BASE_IDX 2 8814#define regHPD0_DC_HPD_CONTROL 0x1f16 8815#define regHPD0_DC_HPD_CONTROL_BASE_IDX 2 8816#define regHPD0_DC_HPD_FAST_TRAIN_CNTL 0x1f17 8817#define regHPD0_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 8818#define regHPD0_DC_HPD_TOGGLE_FILT_CNTL 0x1f18 8819#define regHPD0_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 8820 8821 8822// addressBlock: dce_dc_dio_hpd1_dispdec 8823// base address: 0x20 8824#define regHPD1_DC_HPD_INT_STATUS 0x1f1c 8825#define regHPD1_DC_HPD_INT_STATUS_BASE_IDX 2 8826#define regHPD1_DC_HPD_INT_CONTROL 0x1f1d 8827#define regHPD1_DC_HPD_INT_CONTROL_BASE_IDX 2 8828#define regHPD1_DC_HPD_CONTROL 0x1f1e 8829#define regHPD1_DC_HPD_CONTROL_BASE_IDX 2 8830#define regHPD1_DC_HPD_FAST_TRAIN_CNTL 0x1f1f 8831#define regHPD1_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 8832#define regHPD1_DC_HPD_TOGGLE_FILT_CNTL 0x1f20 8833#define regHPD1_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 8834 8835 8836// addressBlock: dce_dc_dio_hpd2_dispdec 8837// base address: 0x40 8838#define regHPD2_DC_HPD_INT_STATUS 0x1f24 8839#define regHPD2_DC_HPD_INT_STATUS_BASE_IDX 2 8840#define regHPD2_DC_HPD_INT_CONTROL 0x1f25 8841#define regHPD2_DC_HPD_INT_CONTROL_BASE_IDX 2 8842#define regHPD2_DC_HPD_CONTROL 0x1f26 8843#define regHPD2_DC_HPD_CONTROL_BASE_IDX 2 8844#define regHPD2_DC_HPD_FAST_TRAIN_CNTL 0x1f27 8845#define regHPD2_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 8846#define regHPD2_DC_HPD_TOGGLE_FILT_CNTL 0x1f28 8847#define regHPD2_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 8848 8849 8850// addressBlock: dce_dc_dio_hpd3_dispdec 8851// base address: 0x60 8852#define regHPD3_DC_HPD_INT_STATUS 0x1f2c 8853#define regHPD3_DC_HPD_INT_STATUS_BASE_IDX 2 8854#define regHPD3_DC_HPD_INT_CONTROL 0x1f2d 8855#define regHPD3_DC_HPD_INT_CONTROL_BASE_IDX 2 8856#define regHPD3_DC_HPD_CONTROL 0x1f2e 8857#define regHPD3_DC_HPD_CONTROL_BASE_IDX 2 8858#define regHPD3_DC_HPD_FAST_TRAIN_CNTL 0x1f2f 8859#define regHPD3_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 8860#define regHPD3_DC_HPD_TOGGLE_FILT_CNTL 0x1f30 8861#define regHPD3_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 8862 8863 8864// addressBlock: dce_dc_dio_hpd4_dispdec 8865// base address: 0x80 8866#define regHPD4_DC_HPD_INT_STATUS 0x1f34 8867#define regHPD4_DC_HPD_INT_STATUS_BASE_IDX 2 8868#define regHPD4_DC_HPD_INT_CONTROL 0x1f35 8869#define regHPD4_DC_HPD_INT_CONTROL_BASE_IDX 2 8870#define regHPD4_DC_HPD_CONTROL 0x1f36 8871#define regHPD4_DC_HPD_CONTROL_BASE_IDX 2 8872#define regHPD4_DC_HPD_FAST_TRAIN_CNTL 0x1f37 8873#define regHPD4_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 8874#define regHPD4_DC_HPD_TOGGLE_FILT_CNTL 0x1f38 8875#define regHPD4_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 8876 8877 8878// addressBlock: dce_dc_dio_dio_dcperfmon_dc_perfmon_dispdec 8879// base address: 0x7d10 8880#define regDC_PERFMON16_PERFCOUNTER_CNTL 0x1f44 8881#define regDC_PERFMON16_PERFCOUNTER_CNTL_BASE_IDX 2 8882#define regDC_PERFMON16_PERFCOUNTER_CNTL2 0x1f45 8883#define regDC_PERFMON16_PERFCOUNTER_CNTL2_BASE_IDX 2 8884#define regDC_PERFMON16_PERFCOUNTER_STATE 0x1f46 8885#define regDC_PERFMON16_PERFCOUNTER_STATE_BASE_IDX 2 8886#define regDC_PERFMON16_PERFMON_CNTL 0x1f47 8887#define regDC_PERFMON16_PERFMON_CNTL_BASE_IDX 2 8888#define regDC_PERFMON16_PERFMON_CNTL2 0x1f48 8889#define regDC_PERFMON16_PERFMON_CNTL2_BASE_IDX 2 8890#define regDC_PERFMON16_PERFMON_CVALUE_INT_MISC 0x1f49 8891#define regDC_PERFMON16_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 8892#define regDC_PERFMON16_PERFMON_CVALUE_LOW 0x1f4a 8893#define regDC_PERFMON16_PERFMON_CVALUE_LOW_BASE_IDX 2 8894#define regDC_PERFMON16_PERFMON_HI 0x1f4b 8895#define regDC_PERFMON16_PERFMON_HI_BASE_IDX 2 8896#define regDC_PERFMON16_PERFMON_LOW 0x1f4c 8897#define regDC_PERFMON16_PERFMON_LOW_BASE_IDX 2 8898 8899 8900// addressBlock: dce_dc_dio_dp_aux0_dispdec 8901// base address: 0x0 8902#define regDP_AUX0_AUX_CONTROL 0x1f50 8903#define regDP_AUX0_AUX_CONTROL_BASE_IDX 2 8904#define regDP_AUX0_AUX_SW_CONTROL 0x1f51 8905#define regDP_AUX0_AUX_SW_CONTROL_BASE_IDX 2 8906#define regDP_AUX0_AUX_ARB_CONTROL 0x1f52 8907#define regDP_AUX0_AUX_ARB_CONTROL_BASE_IDX 2 8908#define regDP_AUX0_AUX_INTERRUPT_CONTROL 0x1f53 8909#define regDP_AUX0_AUX_INTERRUPT_CONTROL_BASE_IDX 2 8910#define regDP_AUX0_AUX_SW_STATUS 0x1f54 8911#define regDP_AUX0_AUX_SW_STATUS_BASE_IDX 2 8912#define regDP_AUX0_AUX_LS_STATUS 0x1f55 8913#define regDP_AUX0_AUX_LS_STATUS_BASE_IDX 2 8914#define regDP_AUX0_AUX_SW_DATA 0x1f56 8915#define regDP_AUX0_AUX_SW_DATA_BASE_IDX 2 8916#define regDP_AUX0_AUX_LS_DATA 0x1f57 8917#define regDP_AUX0_AUX_LS_DATA_BASE_IDX 2 8918#define regDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x1f58 8919#define regDP_AUX0_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 8920#define regDP_AUX0_AUX_DPHY_TX_CONTROL 0x1f59 8921#define regDP_AUX0_AUX_DPHY_TX_CONTROL_BASE_IDX 2 8922#define regDP_AUX0_AUX_DPHY_RX_CONTROL0 0x1f5a 8923#define regDP_AUX0_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 8924#define regDP_AUX0_AUX_DPHY_RX_CONTROL1 0x1f5b 8925#define regDP_AUX0_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 8926#define regDP_AUX0_AUX_DPHY_TX_STATUS 0x1f5c 8927#define regDP_AUX0_AUX_DPHY_TX_STATUS_BASE_IDX 2 8928#define regDP_AUX0_AUX_DPHY_RX_STATUS 0x1f5d 8929#define regDP_AUX0_AUX_DPHY_RX_STATUS_BASE_IDX 2 8930#define regDP_AUX0_AUX_GTC_SYNC_CONTROL 0x1f5e 8931#define regDP_AUX0_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 8932#define regDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL 0x1f5f 8933#define regDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 8934#define regDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f60 8935#define regDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 8936#define regDP_AUX0_AUX_GTC_SYNC_STATUS 0x1f61 8937#define regDP_AUX0_AUX_GTC_SYNC_STATUS_BASE_IDX 2 8938#define regDP_AUX0_AUX_PHY_WAKE_CNTL 0x1f66 8939#define regDP_AUX0_AUX_PHY_WAKE_CNTL_BASE_IDX 2 8940 8941 8942// addressBlock: dce_dc_dio_dp_aux1_dispdec 8943// base address: 0x70 8944#define regDP_AUX1_AUX_CONTROL 0x1f6c 8945#define regDP_AUX1_AUX_CONTROL_BASE_IDX 2 8946#define regDP_AUX1_AUX_SW_CONTROL 0x1f6d 8947#define regDP_AUX1_AUX_SW_CONTROL_BASE_IDX 2 8948#define regDP_AUX1_AUX_ARB_CONTROL 0x1f6e 8949#define regDP_AUX1_AUX_ARB_CONTROL_BASE_IDX 2 8950#define regDP_AUX1_AUX_INTERRUPT_CONTROL 0x1f6f 8951#define regDP_AUX1_AUX_INTERRUPT_CONTROL_BASE_IDX 2 8952#define regDP_AUX1_AUX_SW_STATUS 0x1f70 8953#define regDP_AUX1_AUX_SW_STATUS_BASE_IDX 2 8954#define regDP_AUX1_AUX_LS_STATUS 0x1f71 8955#define regDP_AUX1_AUX_LS_STATUS_BASE_IDX 2 8956#define regDP_AUX1_AUX_SW_DATA 0x1f72 8957#define regDP_AUX1_AUX_SW_DATA_BASE_IDX 2 8958#define regDP_AUX1_AUX_LS_DATA 0x1f73 8959#define regDP_AUX1_AUX_LS_DATA_BASE_IDX 2 8960#define regDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x1f74 8961#define regDP_AUX1_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 8962#define regDP_AUX1_AUX_DPHY_TX_CONTROL 0x1f75 8963#define regDP_AUX1_AUX_DPHY_TX_CONTROL_BASE_IDX 2 8964#define regDP_AUX1_AUX_DPHY_RX_CONTROL0 0x1f76 8965#define regDP_AUX1_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 8966#define regDP_AUX1_AUX_DPHY_RX_CONTROL1 0x1f77 8967#define regDP_AUX1_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 8968#define regDP_AUX1_AUX_DPHY_TX_STATUS 0x1f78 8969#define regDP_AUX1_AUX_DPHY_TX_STATUS_BASE_IDX 2 8970#define regDP_AUX1_AUX_DPHY_RX_STATUS 0x1f79 8971#define regDP_AUX1_AUX_DPHY_RX_STATUS_BASE_IDX 2 8972#define regDP_AUX1_AUX_GTC_SYNC_CONTROL 0x1f7a 8973#define regDP_AUX1_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 8974#define regDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL 0x1f7b 8975#define regDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 8976#define regDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f7c 8977#define regDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 8978#define regDP_AUX1_AUX_GTC_SYNC_STATUS 0x1f7d 8979#define regDP_AUX1_AUX_GTC_SYNC_STATUS_BASE_IDX 2 8980#define regDP_AUX1_AUX_PHY_WAKE_CNTL 0x1f82 8981#define regDP_AUX1_AUX_PHY_WAKE_CNTL_BASE_IDX 2 8982 8983 8984// addressBlock: dce_dc_dio_dp_aux2_dispdec 8985// base address: 0xe0 8986#define regDP_AUX2_AUX_CONTROL 0x1f88 8987#define regDP_AUX2_AUX_CONTROL_BASE_IDX 2 8988#define regDP_AUX2_AUX_SW_CONTROL 0x1f89 8989#define regDP_AUX2_AUX_SW_CONTROL_BASE_IDX 2 8990#define regDP_AUX2_AUX_ARB_CONTROL 0x1f8a 8991#define regDP_AUX2_AUX_ARB_CONTROL_BASE_IDX 2 8992#define regDP_AUX2_AUX_INTERRUPT_CONTROL 0x1f8b 8993#define regDP_AUX2_AUX_INTERRUPT_CONTROL_BASE_IDX 2 8994#define regDP_AUX2_AUX_SW_STATUS 0x1f8c 8995#define regDP_AUX2_AUX_SW_STATUS_BASE_IDX 2 8996#define regDP_AUX2_AUX_LS_STATUS 0x1f8d 8997#define regDP_AUX2_AUX_LS_STATUS_BASE_IDX 2 8998#define regDP_AUX2_AUX_SW_DATA 0x1f8e 8999#define regDP_AUX2_AUX_SW_DATA_BASE_IDX 2 9000#define regDP_AUX2_AUX_LS_DATA 0x1f8f 9001#define regDP_AUX2_AUX_LS_DATA_BASE_IDX 2 9002#define regDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0x1f90 9003#define regDP_AUX2_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 9004#define regDP_AUX2_AUX_DPHY_TX_CONTROL 0x1f91 9005#define regDP_AUX2_AUX_DPHY_TX_CONTROL_BASE_IDX 2 9006#define regDP_AUX2_AUX_DPHY_RX_CONTROL0 0x1f92 9007#define regDP_AUX2_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 9008#define regDP_AUX2_AUX_DPHY_RX_CONTROL1 0x1f93 9009#define regDP_AUX2_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 9010#define regDP_AUX2_AUX_DPHY_TX_STATUS 0x1f94 9011#define regDP_AUX2_AUX_DPHY_TX_STATUS_BASE_IDX 2 9012#define regDP_AUX2_AUX_DPHY_RX_STATUS 0x1f95 9013#define regDP_AUX2_AUX_DPHY_RX_STATUS_BASE_IDX 2 9014#define regDP_AUX2_AUX_GTC_SYNC_CONTROL 0x1f96 9015#define regDP_AUX2_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 9016#define regDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL 0x1f97 9017#define regDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 9018#define regDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f98 9019#define regDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 9020#define regDP_AUX2_AUX_GTC_SYNC_STATUS 0x1f99 9021#define regDP_AUX2_AUX_GTC_SYNC_STATUS_BASE_IDX 2 9022#define regDP_AUX2_AUX_PHY_WAKE_CNTL 0x1f9e 9023#define regDP_AUX2_AUX_PHY_WAKE_CNTL_BASE_IDX 2 9024 9025 9026// addressBlock: dce_dc_dio_dp_aux3_dispdec 9027// base address: 0x150 9028#define regDP_AUX3_AUX_CONTROL 0x1fa4 9029#define regDP_AUX3_AUX_CONTROL_BASE_IDX 2 9030#define regDP_AUX3_AUX_SW_CONTROL 0x1fa5 9031#define regDP_AUX3_AUX_SW_CONTROL_BASE_IDX 2 9032#define regDP_AUX3_AUX_ARB_CONTROL 0x1fa6 9033#define regDP_AUX3_AUX_ARB_CONTROL_BASE_IDX 2 9034#define regDP_AUX3_AUX_INTERRUPT_CONTROL 0x1fa7 9035#define regDP_AUX3_AUX_INTERRUPT_CONTROL_BASE_IDX 2 9036#define regDP_AUX3_AUX_SW_STATUS 0x1fa8 9037#define regDP_AUX3_AUX_SW_STATUS_BASE_IDX 2 9038#define regDP_AUX3_AUX_LS_STATUS 0x1fa9 9039#define regDP_AUX3_AUX_LS_STATUS_BASE_IDX 2 9040#define regDP_AUX3_AUX_SW_DATA 0x1faa 9041#define regDP_AUX3_AUX_SW_DATA_BASE_IDX 2 9042#define regDP_AUX3_AUX_LS_DATA 0x1fab 9043#define regDP_AUX3_AUX_LS_DATA_BASE_IDX 2 9044#define regDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0x1fac 9045#define regDP_AUX3_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 9046#define regDP_AUX3_AUX_DPHY_TX_CONTROL 0x1fad 9047#define regDP_AUX3_AUX_DPHY_TX_CONTROL_BASE_IDX 2 9048#define regDP_AUX3_AUX_DPHY_RX_CONTROL0 0x1fae 9049#define regDP_AUX3_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 9050#define regDP_AUX3_AUX_DPHY_RX_CONTROL1 0x1faf 9051#define regDP_AUX3_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 9052#define regDP_AUX3_AUX_DPHY_TX_STATUS 0x1fb0 9053#define regDP_AUX3_AUX_DPHY_TX_STATUS_BASE_IDX 2 9054#define regDP_AUX3_AUX_DPHY_RX_STATUS 0x1fb1 9055#define regDP_AUX3_AUX_DPHY_RX_STATUS_BASE_IDX 2 9056#define regDP_AUX3_AUX_GTC_SYNC_CONTROL 0x1fb2 9057#define regDP_AUX3_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 9058#define regDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL 0x1fb3 9059#define regDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 9060#define regDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1fb4 9061#define regDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 9062#define regDP_AUX3_AUX_GTC_SYNC_STATUS 0x1fb5 9063#define regDP_AUX3_AUX_GTC_SYNC_STATUS_BASE_IDX 2 9064#define regDP_AUX3_AUX_PHY_WAKE_CNTL 0x1fba 9065#define regDP_AUX3_AUX_PHY_WAKE_CNTL_BASE_IDX 2 9066 9067 9068// addressBlock: dce_dc_dio_dp_aux4_dispdec 9069// base address: 0x1c0 9070#define regDP_AUX4_AUX_CONTROL 0x1fc0 9071#define regDP_AUX4_AUX_CONTROL_BASE_IDX 2 9072#define regDP_AUX4_AUX_SW_CONTROL 0x1fc1 9073#define regDP_AUX4_AUX_SW_CONTROL_BASE_IDX 2 9074#define regDP_AUX4_AUX_ARB_CONTROL 0x1fc2 9075#define regDP_AUX4_AUX_ARB_CONTROL_BASE_IDX 2 9076#define regDP_AUX4_AUX_INTERRUPT_CONTROL 0x1fc3 9077#define regDP_AUX4_AUX_INTERRUPT_CONTROL_BASE_IDX 2 9078#define regDP_AUX4_AUX_SW_STATUS 0x1fc4 9079#define regDP_AUX4_AUX_SW_STATUS_BASE_IDX 2 9080#define regDP_AUX4_AUX_LS_STATUS 0x1fc5 9081#define regDP_AUX4_AUX_LS_STATUS_BASE_IDX 2 9082#define regDP_AUX4_AUX_SW_DATA 0x1fc6 9083#define regDP_AUX4_AUX_SW_DATA_BASE_IDX 2 9084#define regDP_AUX4_AUX_LS_DATA 0x1fc7 9085#define regDP_AUX4_AUX_LS_DATA_BASE_IDX 2 9086#define regDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0x1fc8 9087#define regDP_AUX4_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 9088#define regDP_AUX4_AUX_DPHY_TX_CONTROL 0x1fc9 9089#define regDP_AUX4_AUX_DPHY_TX_CONTROL_BASE_IDX 2 9090#define regDP_AUX4_AUX_DPHY_RX_CONTROL0 0x1fca 9091#define regDP_AUX4_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 9092#define regDP_AUX4_AUX_DPHY_RX_CONTROL1 0x1fcb 9093#define regDP_AUX4_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 9094#define regDP_AUX4_AUX_DPHY_TX_STATUS 0x1fcc 9095#define regDP_AUX4_AUX_DPHY_TX_STATUS_BASE_IDX 2 9096#define regDP_AUX4_AUX_DPHY_RX_STATUS 0x1fcd 9097#define regDP_AUX4_AUX_DPHY_RX_STATUS_BASE_IDX 2 9098#define regDP_AUX4_AUX_GTC_SYNC_CONTROL 0x1fce 9099#define regDP_AUX4_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 9100#define regDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL 0x1fcf 9101#define regDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 9102#define regDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1fd0 9103#define regDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 9104#define regDP_AUX4_AUX_GTC_SYNC_STATUS 0x1fd1 9105#define regDP_AUX4_AUX_GTC_SYNC_STATUS_BASE_IDX 2 9106#define regDP_AUX4_AUX_PHY_WAKE_CNTL 0x1fd6 9107#define regDP_AUX4_AUX_PHY_WAKE_CNTL_BASE_IDX 2 9108 9109 9110// addressBlock: dce_dc_dio_dig0_vpg_vpg_dispdec 9111// base address: 0x154a0 9112#define regVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2068 9113#define regVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 9114#define regVPG0_VPG_GENERIC_PACKET_DATA 0x2069 9115#define regVPG0_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 9116#define regVPG0_VPG_GSP_FRAME_UPDATE_CTRL 0x206a 9117#define regVPG0_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 9118#define regVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x206b 9119#define regVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 9120#define regVPG0_VPG_GENERIC_STATUS 0x206c 9121#define regVPG0_VPG_GENERIC_STATUS_BASE_IDX 2 9122#define regVPG0_VPG_MEM_PWR 0x206d 9123#define regVPG0_VPG_MEM_PWR_BASE_IDX 2 9124#define regVPG0_VPG_ISRC1_2_ACCESS_CTRL 0x206e 9125#define regVPG0_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 9126#define regVPG0_VPG_ISRC1_2_DATA 0x206f 9127#define regVPG0_VPG_ISRC1_2_DATA_BASE_IDX 2 9128#define regVPG0_VPG_MPEG_INFO0 0x2070 9129#define regVPG0_VPG_MPEG_INFO0_BASE_IDX 2 9130#define regVPG0_VPG_MPEG_INFO1 0x2071 9131#define regVPG0_VPG_MPEG_INFO1_BASE_IDX 2 9132 9133 9134// addressBlock: dce_dc_dio_dig0_afmt_afmt_dispdec 9135// base address: 0x154cc 9136#define regAFMT0_AFMT_VBI_PACKET_CONTROL 0x2074 9137#define regAFMT0_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 9138#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL2 0x2075 9139#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 9140#define regAFMT0_AFMT_AUDIO_INFO0 0x2076 9141#define regAFMT0_AFMT_AUDIO_INFO0_BASE_IDX 2 9142#define regAFMT0_AFMT_AUDIO_INFO1 0x2077 9143#define regAFMT0_AFMT_AUDIO_INFO1_BASE_IDX 2 9144#define regAFMT0_AFMT_60958_0 0x2078 9145#define regAFMT0_AFMT_60958_0_BASE_IDX 2 9146#define regAFMT0_AFMT_60958_1 0x2079 9147#define regAFMT0_AFMT_60958_1_BASE_IDX 2 9148#define regAFMT0_AFMT_AUDIO_CRC_CONTROL 0x207a 9149#define regAFMT0_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 9150#define regAFMT0_AFMT_RAMP_CONTROL0 0x207b 9151#define regAFMT0_AFMT_RAMP_CONTROL0_BASE_IDX 2 9152#define regAFMT0_AFMT_RAMP_CONTROL1 0x207c 9153#define regAFMT0_AFMT_RAMP_CONTROL1_BASE_IDX 2 9154#define regAFMT0_AFMT_RAMP_CONTROL2 0x207d 9155#define regAFMT0_AFMT_RAMP_CONTROL2_BASE_IDX 2 9156#define regAFMT0_AFMT_RAMP_CONTROL3 0x207e 9157#define regAFMT0_AFMT_RAMP_CONTROL3_BASE_IDX 2 9158#define regAFMT0_AFMT_60958_2 0x207f 9159#define regAFMT0_AFMT_60958_2_BASE_IDX 2 9160#define regAFMT0_AFMT_AUDIO_CRC_RESULT 0x2080 9161#define regAFMT0_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 9162#define regAFMT0_AFMT_STATUS 0x2081 9163#define regAFMT0_AFMT_STATUS_BASE_IDX 2 9164#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL 0x2082 9165#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 9166#define regAFMT0_AFMT_INFOFRAME_CONTROL0 0x2083 9167#define regAFMT0_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 9168#define regAFMT0_AFMT_INTERRUPT_STATUS 0x2084 9169#define regAFMT0_AFMT_INTERRUPT_STATUS_BASE_IDX 2 9170#define regAFMT0_AFMT_AUDIO_SRC_CONTROL 0x2085 9171#define regAFMT0_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 9172#define regAFMT0_AFMT_MEM_PWR 0x2087 9173#define regAFMT0_AFMT_MEM_PWR_BASE_IDX 2 9174 9175 9176// addressBlock: dce_dc_dio_dig0_dme_dme_dispdec 9177// base address: 0x15524 9178#define regDME0_DME_CONTROL 0x2089 9179#define regDME0_DME_CONTROL_BASE_IDX 2 9180#define regDME0_DME_MEMORY_CONTROL 0x208a 9181#define regDME0_DME_MEMORY_CONTROL_BASE_IDX 2 9182 9183 9184// addressBlock: dce_dc_dio_dig0_dispdec 9185// base address: 0x0 9186#define regDIG0_DIG_FE_CNTL 0x208b 9187#define regDIG0_DIG_FE_CNTL_BASE_IDX 2 9188#define regDIG0_DIG_OUTPUT_CRC_CNTL 0x208c 9189#define regDIG0_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 9190#define regDIG0_DIG_OUTPUT_CRC_RESULT 0x208d 9191#define regDIG0_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 9192#define regDIG0_DIG_CLOCK_PATTERN 0x208e 9193#define regDIG0_DIG_CLOCK_PATTERN_BASE_IDX 2 9194#define regDIG0_DIG_TEST_PATTERN 0x208f 9195#define regDIG0_DIG_TEST_PATTERN_BASE_IDX 2 9196#define regDIG0_DIG_RANDOM_PATTERN_SEED 0x2090 9197#define regDIG0_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 9198#define regDIG0_DIG_FIFO_CTRL0 0x2091 9199#define regDIG0_DIG_FIFO_CTRL0_BASE_IDX 2 9200#define regDIG0_DIG_FIFO_CTRL1 0x2092 9201#define regDIG0_DIG_FIFO_CTRL1_BASE_IDX 2 9202#define regDIG0_HDMI_METADATA_PACKET_CONTROL 0x2093 9203#define regDIG0_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 9204#define regDIG0_HDMI_CONTROL 0x2094 9205#define regDIG0_HDMI_CONTROL_BASE_IDX 2 9206#define regDIG0_HDMI_STATUS 0x2095 9207#define regDIG0_HDMI_STATUS_BASE_IDX 2 9208#define regDIG0_HDMI_AUDIO_PACKET_CONTROL 0x2096 9209#define regDIG0_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 9210#define regDIG0_HDMI_ACR_PACKET_CONTROL 0x2097 9211#define regDIG0_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 9212#define regDIG0_HDMI_VBI_PACKET_CONTROL 0x2098 9213#define regDIG0_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 9214#define regDIG0_HDMI_INFOFRAME_CONTROL0 0x2099 9215#define regDIG0_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 9216#define regDIG0_HDMI_INFOFRAME_CONTROL1 0x209a 9217#define regDIG0_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 9218#define regDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x209b 9219#define regDIG0_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 9220#define regDIG0_HDMI_GENERIC_PACKET_CONTROL6 0x209c 9221#define regDIG0_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 9222#define regDIG0_HDMI_GENERIC_PACKET_CONTROL5 0x209d 9223#define regDIG0_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 9224#define regDIG0_HDMI_GC 0x209e 9225#define regDIG0_HDMI_GC_BASE_IDX 2 9226#define regDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x209f 9227#define regDIG0_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 9228#define regDIG0_HDMI_GENERIC_PACKET_CONTROL2 0x20a0 9229#define regDIG0_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 9230#define regDIG0_HDMI_GENERIC_PACKET_CONTROL3 0x20a1 9231#define regDIG0_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 9232#define regDIG0_HDMI_GENERIC_PACKET_CONTROL4 0x20a2 9233#define regDIG0_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 9234#define regDIG0_HDMI_GENERIC_PACKET_CONTROL7 0x20a3 9235#define regDIG0_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 9236#define regDIG0_HDMI_GENERIC_PACKET_CONTROL8 0x20a4 9237#define regDIG0_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 9238#define regDIG0_HDMI_GENERIC_PACKET_CONTROL9 0x20a5 9239#define regDIG0_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 9240#define regDIG0_HDMI_GENERIC_PACKET_CONTROL10 0x20a6 9241#define regDIG0_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 9242#define regDIG0_HDMI_DB_CONTROL 0x20a7 9243#define regDIG0_HDMI_DB_CONTROL_BASE_IDX 2 9244#define regDIG0_HDMI_ACR_32_0 0x20a8 9245#define regDIG0_HDMI_ACR_32_0_BASE_IDX 2 9246#define regDIG0_HDMI_ACR_32_1 0x20a9 9247#define regDIG0_HDMI_ACR_32_1_BASE_IDX 2 9248#define regDIG0_HDMI_ACR_44_0 0x20aa 9249#define regDIG0_HDMI_ACR_44_0_BASE_IDX 2 9250#define regDIG0_HDMI_ACR_44_1 0x20ab 9251#define regDIG0_HDMI_ACR_44_1_BASE_IDX 2 9252#define regDIG0_HDMI_ACR_48_0 0x20ac 9253#define regDIG0_HDMI_ACR_48_0_BASE_IDX 2 9254#define regDIG0_HDMI_ACR_48_1 0x20ad 9255#define regDIG0_HDMI_ACR_48_1_BASE_IDX 2 9256#define regDIG0_HDMI_ACR_STATUS_0 0x20ae 9257#define regDIG0_HDMI_ACR_STATUS_0_BASE_IDX 2 9258#define regDIG0_HDMI_ACR_STATUS_1 0x20af 9259#define regDIG0_HDMI_ACR_STATUS_1_BASE_IDX 2 9260#define regDIG0_AFMT_CNTL 0x20b0 9261#define regDIG0_AFMT_CNTL_BASE_IDX 2 9262#define regDIG0_DIG_BE_CNTL 0x20b1 9263#define regDIG0_DIG_BE_CNTL_BASE_IDX 2 9264#define regDIG0_DIG_BE_EN_CNTL 0x20b2 9265#define regDIG0_DIG_BE_EN_CNTL_BASE_IDX 2 9266#define regDIG0_TMDS_CNTL 0x20d8 9267#define regDIG0_TMDS_CNTL_BASE_IDX 2 9268#define regDIG0_TMDS_CONTROL_CHAR 0x20d9 9269#define regDIG0_TMDS_CONTROL_CHAR_BASE_IDX 2 9270#define regDIG0_TMDS_CONTROL0_FEEDBACK 0x20da 9271#define regDIG0_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 9272#define regDIG0_TMDS_STEREOSYNC_CTL_SEL 0x20db 9273#define regDIG0_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 9274#define regDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x20dc 9275#define regDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 9276#define regDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x20dd 9277#define regDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 9278#define regDIG0_TMDS_CTL_BITS 0x20df 9279#define regDIG0_TMDS_CTL_BITS_BASE_IDX 2 9280#define regDIG0_TMDS_DCBALANCER_CONTROL 0x20e0 9281#define regDIG0_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 9282#define regDIG0_TMDS_SYNC_DCBALANCE_CHAR 0x20e1 9283#define regDIG0_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 9284#define regDIG0_TMDS_CTL0_1_GEN_CNTL 0x20e2 9285#define regDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 9286#define regDIG0_TMDS_CTL2_3_GEN_CNTL 0x20e3 9287#define regDIG0_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 9288#define regDIG0_DIG_VERSION 0x20e5 9289#define regDIG0_DIG_VERSION_BASE_IDX 2 9290#define regDIG0_FORCE_DIG_DISABLE 0x20e6 9291#define regDIG0_FORCE_DIG_DISABLE_BASE_IDX 2 9292 9293 9294// addressBlock: dce_dc_dio_dp0_dispdec 9295// base address: 0x0 9296#define regDP0_DP_LINK_CNTL 0x2108 9297#define regDP0_DP_LINK_CNTL_BASE_IDX 2 9298#define regDP0_DP_PIXEL_FORMAT 0x2109 9299#define regDP0_DP_PIXEL_FORMAT_BASE_IDX 2 9300#define regDP0_DP_MSA_COLORIMETRY 0x210a 9301#define regDP0_DP_MSA_COLORIMETRY_BASE_IDX 2 9302#define regDP0_DP_CONFIG 0x210b 9303#define regDP0_DP_CONFIG_BASE_IDX 2 9304#define regDP0_DP_VID_STREAM_CNTL 0x210c 9305#define regDP0_DP_VID_STREAM_CNTL_BASE_IDX 2 9306#define regDP0_DP_STEER_FIFO 0x210d 9307#define regDP0_DP_STEER_FIFO_BASE_IDX 2 9308#define regDP0_DP_MSA_MISC 0x210e 9309#define regDP0_DP_MSA_MISC_BASE_IDX 2 9310#define regDP0_DP_DPHY_INTERNAL_CTRL 0x210f 9311#define regDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 9312#define regDP0_DP_VID_TIMING 0x2110 9313#define regDP0_DP_VID_TIMING_BASE_IDX 2 9314#define regDP0_DP_VID_N 0x2111 9315#define regDP0_DP_VID_N_BASE_IDX 2 9316#define regDP0_DP_VID_M 0x2112 9317#define regDP0_DP_VID_M_BASE_IDX 2 9318#define regDP0_DP_LINK_FRAMING_CNTL 0x2113 9319#define regDP0_DP_LINK_FRAMING_CNTL_BASE_IDX 2 9320#define regDP0_DP_HBR2_EYE_PATTERN 0x2114 9321#define regDP0_DP_HBR2_EYE_PATTERN_BASE_IDX 2 9322#define regDP0_DP_VID_MSA_VBID 0x2115 9323#define regDP0_DP_VID_MSA_VBID_BASE_IDX 2 9324#define regDP0_DP_VID_INTERRUPT_CNTL 0x2116 9325#define regDP0_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 9326#define regDP0_DP_DPHY_CNTL 0x2117 9327#define regDP0_DP_DPHY_CNTL_BASE_IDX 2 9328#define regDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x2118 9329#define regDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 9330#define regDP0_DP_DPHY_SYM0 0x2119 9331#define regDP0_DP_DPHY_SYM0_BASE_IDX 2 9332#define regDP0_DP_DPHY_SYM1 0x211a 9333#define regDP0_DP_DPHY_SYM1_BASE_IDX 2 9334#define regDP0_DP_DPHY_SYM2 0x211b 9335#define regDP0_DP_DPHY_SYM2_BASE_IDX 2 9336#define regDP0_DP_DPHY_8B10B_CNTL 0x211c 9337#define regDP0_DP_DPHY_8B10B_CNTL_BASE_IDX 2 9338#define regDP0_DP_DPHY_PRBS_CNTL 0x211d 9339#define regDP0_DP_DPHY_PRBS_CNTL_BASE_IDX 2 9340#define regDP0_DP_DPHY_SCRAM_CNTL 0x211e 9341#define regDP0_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 9342#define regDP0_DP_DPHY_CRC_EN 0x211f 9343#define regDP0_DP_DPHY_CRC_EN_BASE_IDX 2 9344#define regDP0_DP_DPHY_CRC_CNTL 0x2120 9345#define regDP0_DP_DPHY_CRC_CNTL_BASE_IDX 2 9346#define regDP0_DP_DPHY_CRC_RESULT 0x2121 9347#define regDP0_DP_DPHY_CRC_RESULT_BASE_IDX 2 9348#define regDP0_DP_DPHY_CRC_MST_CNTL 0x2122 9349#define regDP0_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 9350#define regDP0_DP_DPHY_CRC_MST_STATUS 0x2123 9351#define regDP0_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 9352#define regDP0_DP_DPHY_FAST_TRAINING 0x2124 9353#define regDP0_DP_DPHY_FAST_TRAINING_BASE_IDX 2 9354#define regDP0_DP_DPHY_FAST_TRAINING_STATUS 0x2125 9355#define regDP0_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 9356#define regDP0_DP_SEC_CNTL 0x212b 9357#define regDP0_DP_SEC_CNTL_BASE_IDX 2 9358#define regDP0_DP_SEC_CNTL1 0x212c 9359#define regDP0_DP_SEC_CNTL1_BASE_IDX 2 9360#define regDP0_DP_SEC_FRAMING1 0x212d 9361#define regDP0_DP_SEC_FRAMING1_BASE_IDX 2 9362#define regDP0_DP_SEC_FRAMING2 0x212e 9363#define regDP0_DP_SEC_FRAMING2_BASE_IDX 2 9364#define regDP0_DP_SEC_FRAMING3 0x212f 9365#define regDP0_DP_SEC_FRAMING3_BASE_IDX 2 9366#define regDP0_DP_SEC_FRAMING4 0x2130 9367#define regDP0_DP_SEC_FRAMING4_BASE_IDX 2 9368#define regDP0_DP_SEC_AUD_N 0x2131 9369#define regDP0_DP_SEC_AUD_N_BASE_IDX 2 9370#define regDP0_DP_SEC_AUD_N_READBACK 0x2132 9371#define regDP0_DP_SEC_AUD_N_READBACK_BASE_IDX 2 9372#define regDP0_DP_SEC_AUD_M 0x2133 9373#define regDP0_DP_SEC_AUD_M_BASE_IDX 2 9374#define regDP0_DP_SEC_AUD_M_READBACK 0x2134 9375#define regDP0_DP_SEC_AUD_M_READBACK_BASE_IDX 2 9376#define regDP0_DP_SEC_TIMESTAMP 0x2135 9377#define regDP0_DP_SEC_TIMESTAMP_BASE_IDX 2 9378#define regDP0_DP_SEC_PACKET_CNTL 0x2136 9379#define regDP0_DP_SEC_PACKET_CNTL_BASE_IDX 2 9380#define regDP0_DP_MSE_RATE_CNTL 0x2137 9381#define regDP0_DP_MSE_RATE_CNTL_BASE_IDX 2 9382#define regDP0_DP_MSE_RATE_UPDATE 0x2139 9383#define regDP0_DP_MSE_RATE_UPDATE_BASE_IDX 2 9384#define regDP0_DP_MSE_SAT0 0x213a 9385#define regDP0_DP_MSE_SAT0_BASE_IDX 2 9386#define regDP0_DP_MSE_SAT1 0x213b 9387#define regDP0_DP_MSE_SAT1_BASE_IDX 2 9388#define regDP0_DP_MSE_SAT2 0x213c 9389#define regDP0_DP_MSE_SAT2_BASE_IDX 2 9390#define regDP0_DP_MSE_SAT_UPDATE 0x213d 9391#define regDP0_DP_MSE_SAT_UPDATE_BASE_IDX 2 9392#define regDP0_DP_MSE_LINK_TIMING 0x213e 9393#define regDP0_DP_MSE_LINK_TIMING_BASE_IDX 2 9394#define regDP0_DP_MSE_MISC_CNTL 0x213f 9395#define regDP0_DP_MSE_MISC_CNTL_BASE_IDX 2 9396#define regDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x2144 9397#define regDP0_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 9398#define regDP0_DP_DPHY_HBR2_PATTERN_CONTROL 0x2145 9399#define regDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 9400#define regDP0_DP_MSE_SAT0_STATUS 0x2147 9401#define regDP0_DP_MSE_SAT0_STATUS_BASE_IDX 2 9402#define regDP0_DP_MSE_SAT1_STATUS 0x2148 9403#define regDP0_DP_MSE_SAT1_STATUS_BASE_IDX 2 9404#define regDP0_DP_MSE_SAT2_STATUS 0x2149 9405#define regDP0_DP_MSE_SAT2_STATUS_BASE_IDX 2 9406#define regDP0_DP_DPIA_SPARE 0x214a 9407#define regDP0_DP_DPIA_SPARE_BASE_IDX 2 9408#define regDP0_DP_MSA_TIMING_PARAM1 0x214c 9409#define regDP0_DP_MSA_TIMING_PARAM1_BASE_IDX 2 9410#define regDP0_DP_MSA_TIMING_PARAM2 0x214d 9411#define regDP0_DP_MSA_TIMING_PARAM2_BASE_IDX 2 9412#define regDP0_DP_MSA_TIMING_PARAM3 0x214e 9413#define regDP0_DP_MSA_TIMING_PARAM3_BASE_IDX 2 9414#define regDP0_DP_MSA_TIMING_PARAM4 0x214f 9415#define regDP0_DP_MSA_TIMING_PARAM4_BASE_IDX 2 9416#define regDP0_DP_MSO_CNTL 0x2150 9417#define regDP0_DP_MSO_CNTL_BASE_IDX 2 9418#define regDP0_DP_MSO_CNTL1 0x2151 9419#define regDP0_DP_MSO_CNTL1_BASE_IDX 2 9420#define regDP0_DP_DSC_CNTL 0x2152 9421#define regDP0_DP_DSC_CNTL_BASE_IDX 2 9422#define regDP0_DP_SEC_CNTL2 0x2153 9423#define regDP0_DP_SEC_CNTL2_BASE_IDX 2 9424#define regDP0_DP_SEC_CNTL3 0x2154 9425#define regDP0_DP_SEC_CNTL3_BASE_IDX 2 9426#define regDP0_DP_SEC_CNTL4 0x2155 9427#define regDP0_DP_SEC_CNTL4_BASE_IDX 2 9428#define regDP0_DP_SEC_CNTL5 0x2156 9429#define regDP0_DP_SEC_CNTL5_BASE_IDX 2 9430#define regDP0_DP_SEC_CNTL6 0x2157 9431#define regDP0_DP_SEC_CNTL6_BASE_IDX 2 9432#define regDP0_DP_SEC_CNTL7 0x2158 9433#define regDP0_DP_SEC_CNTL7_BASE_IDX 2 9434#define regDP0_DP_DB_CNTL 0x2159 9435#define regDP0_DP_DB_CNTL_BASE_IDX 2 9436#define regDP0_DP_MSA_VBID_MISC 0x215a 9437#define regDP0_DP_MSA_VBID_MISC_BASE_IDX 2 9438#define regDP0_DP_SEC_METADATA_TRANSMISSION 0x215b 9439#define regDP0_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 9440#define regDP0_DP_ALPM_CNTL 0x215d 9441#define regDP0_DP_ALPM_CNTL_BASE_IDX 2 9442#define regDP0_DP_GSP8_CNTL 0x215e 9443#define regDP0_DP_GSP8_CNTL_BASE_IDX 2 9444#define regDP0_DP_GSP9_CNTL 0x215f 9445#define regDP0_DP_GSP9_CNTL_BASE_IDX 2 9446#define regDP0_DP_GSP10_CNTL 0x2160 9447#define regDP0_DP_GSP10_CNTL_BASE_IDX 2 9448#define regDP0_DP_GSP11_CNTL 0x2161 9449#define regDP0_DP_GSP11_CNTL_BASE_IDX 2 9450#define regDP0_DP_GSP_EN_DB_STATUS 0x2162 9451#define regDP0_DP_GSP_EN_DB_STATUS_BASE_IDX 2 9452#define regDP0_DP_AUXLESS_ALPM_CNTL1 0x2163 9453#define regDP0_DP_AUXLESS_ALPM_CNTL1_BASE_IDX 2 9454#define regDP0_DP_AUXLESS_ALPM_CNTL2 0x2164 9455#define regDP0_DP_AUXLESS_ALPM_CNTL2_BASE_IDX 2 9456#define regDP0_DP_AUXLESS_ALPM_CNTL3 0x2165 9457#define regDP0_DP_AUXLESS_ALPM_CNTL3_BASE_IDX 2 9458#define regDP0_DP_AUXLESS_ALPM_CNTL4 0x2166 9459#define regDP0_DP_AUXLESS_ALPM_CNTL4_BASE_IDX 2 9460#define regDP0_DP_AUXLESS_ALPM_CNTL5 0x2167 9461#define regDP0_DP_AUXLESS_ALPM_CNTL5_BASE_IDX 2 9462 9463 9464// addressBlock: dce_dc_dio_dig1_vpg_vpg_dispdec 9465// base address: 0x158a0 9466#define regVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2168 9467#define regVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 9468#define regVPG1_VPG_GENERIC_PACKET_DATA 0x2169 9469#define regVPG1_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 9470#define regVPG1_VPG_GSP_FRAME_UPDATE_CTRL 0x216a 9471#define regVPG1_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 9472#define regVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x216b 9473#define regVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 9474#define regVPG1_VPG_GENERIC_STATUS 0x216c 9475#define regVPG1_VPG_GENERIC_STATUS_BASE_IDX 2 9476#define regVPG1_VPG_MEM_PWR 0x216d 9477#define regVPG1_VPG_MEM_PWR_BASE_IDX 2 9478#define regVPG1_VPG_ISRC1_2_ACCESS_CTRL 0x216e 9479#define regVPG1_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 9480#define regVPG1_VPG_ISRC1_2_DATA 0x216f 9481#define regVPG1_VPG_ISRC1_2_DATA_BASE_IDX 2 9482#define regVPG1_VPG_MPEG_INFO0 0x2170 9483#define regVPG1_VPG_MPEG_INFO0_BASE_IDX 2 9484#define regVPG1_VPG_MPEG_INFO1 0x2171 9485#define regVPG1_VPG_MPEG_INFO1_BASE_IDX 2 9486 9487 9488// addressBlock: dce_dc_dio_dig1_afmt_afmt_dispdec 9489// base address: 0x158cc 9490#define regAFMT1_AFMT_VBI_PACKET_CONTROL 0x2174 9491#define regAFMT1_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 9492#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL2 0x2175 9493#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 9494#define regAFMT1_AFMT_AUDIO_INFO0 0x2176 9495#define regAFMT1_AFMT_AUDIO_INFO0_BASE_IDX 2 9496#define regAFMT1_AFMT_AUDIO_INFO1 0x2177 9497#define regAFMT1_AFMT_AUDIO_INFO1_BASE_IDX 2 9498#define regAFMT1_AFMT_60958_0 0x2178 9499#define regAFMT1_AFMT_60958_0_BASE_IDX 2 9500#define regAFMT1_AFMT_60958_1 0x2179 9501#define regAFMT1_AFMT_60958_1_BASE_IDX 2 9502#define regAFMT1_AFMT_AUDIO_CRC_CONTROL 0x217a 9503#define regAFMT1_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 9504#define regAFMT1_AFMT_RAMP_CONTROL0 0x217b 9505#define regAFMT1_AFMT_RAMP_CONTROL0_BASE_IDX 2 9506#define regAFMT1_AFMT_RAMP_CONTROL1 0x217c 9507#define regAFMT1_AFMT_RAMP_CONTROL1_BASE_IDX 2 9508#define regAFMT1_AFMT_RAMP_CONTROL2 0x217d 9509#define regAFMT1_AFMT_RAMP_CONTROL2_BASE_IDX 2 9510#define regAFMT1_AFMT_RAMP_CONTROL3 0x217e 9511#define regAFMT1_AFMT_RAMP_CONTROL3_BASE_IDX 2 9512#define regAFMT1_AFMT_60958_2 0x217f 9513#define regAFMT1_AFMT_60958_2_BASE_IDX 2 9514#define regAFMT1_AFMT_AUDIO_CRC_RESULT 0x2180 9515#define regAFMT1_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 9516#define regAFMT1_AFMT_STATUS 0x2181 9517#define regAFMT1_AFMT_STATUS_BASE_IDX 2 9518#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL 0x2182 9519#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 9520#define regAFMT1_AFMT_INFOFRAME_CONTROL0 0x2183 9521#define regAFMT1_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 9522#define regAFMT1_AFMT_INTERRUPT_STATUS 0x2184 9523#define regAFMT1_AFMT_INTERRUPT_STATUS_BASE_IDX 2 9524#define regAFMT1_AFMT_AUDIO_SRC_CONTROL 0x2185 9525#define regAFMT1_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 9526#define regAFMT1_AFMT_MEM_PWR 0x2187 9527#define regAFMT1_AFMT_MEM_PWR_BASE_IDX 2 9528 9529 9530// addressBlock: dce_dc_dio_dig1_dme_dme_dispdec 9531// base address: 0x15924 9532#define regDME1_DME_CONTROL 0x2189 9533#define regDME1_DME_CONTROL_BASE_IDX 2 9534#define regDME1_DME_MEMORY_CONTROL 0x218a 9535#define regDME1_DME_MEMORY_CONTROL_BASE_IDX 2 9536 9537 9538// addressBlock: dce_dc_dio_dig1_dispdec 9539// base address: 0x400 9540#define regDIG1_DIG_FE_CNTL 0x218b 9541#define regDIG1_DIG_FE_CNTL_BASE_IDX 2 9542#define regDIG1_DIG_OUTPUT_CRC_CNTL 0x218c 9543#define regDIG1_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 9544#define regDIG1_DIG_OUTPUT_CRC_RESULT 0x218d 9545#define regDIG1_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 9546#define regDIG1_DIG_CLOCK_PATTERN 0x218e 9547#define regDIG1_DIG_CLOCK_PATTERN_BASE_IDX 2 9548#define regDIG1_DIG_TEST_PATTERN 0x218f 9549#define regDIG1_DIG_TEST_PATTERN_BASE_IDX 2 9550#define regDIG1_DIG_RANDOM_PATTERN_SEED 0x2190 9551#define regDIG1_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 9552#define regDIG1_DIG_FIFO_CTRL0 0x2191 9553#define regDIG1_DIG_FIFO_CTRL0_BASE_IDX 2 9554#define regDIG1_DIG_FIFO_CTRL1 0x2192 9555#define regDIG1_DIG_FIFO_CTRL1_BASE_IDX 2 9556#define regDIG1_HDMI_METADATA_PACKET_CONTROL 0x2193 9557#define regDIG1_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 9558#define regDIG1_HDMI_CONTROL 0x2194 9559#define regDIG1_HDMI_CONTROL_BASE_IDX 2 9560#define regDIG1_HDMI_STATUS 0x2195 9561#define regDIG1_HDMI_STATUS_BASE_IDX 2 9562#define regDIG1_HDMI_AUDIO_PACKET_CONTROL 0x2196 9563#define regDIG1_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 9564#define regDIG1_HDMI_ACR_PACKET_CONTROL 0x2197 9565#define regDIG1_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 9566#define regDIG1_HDMI_VBI_PACKET_CONTROL 0x2198 9567#define regDIG1_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 9568#define regDIG1_HDMI_INFOFRAME_CONTROL0 0x2199 9569#define regDIG1_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 9570#define regDIG1_HDMI_INFOFRAME_CONTROL1 0x219a 9571#define regDIG1_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 9572#define regDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x219b 9573#define regDIG1_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 9574#define regDIG1_HDMI_GENERIC_PACKET_CONTROL6 0x219c 9575#define regDIG1_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 9576#define regDIG1_HDMI_GENERIC_PACKET_CONTROL5 0x219d 9577#define regDIG1_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 9578#define regDIG1_HDMI_GC 0x219e 9579#define regDIG1_HDMI_GC_BASE_IDX 2 9580#define regDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x219f 9581#define regDIG1_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 9582#define regDIG1_HDMI_GENERIC_PACKET_CONTROL2 0x21a0 9583#define regDIG1_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 9584#define regDIG1_HDMI_GENERIC_PACKET_CONTROL3 0x21a1 9585#define regDIG1_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 9586#define regDIG1_HDMI_GENERIC_PACKET_CONTROL4 0x21a2 9587#define regDIG1_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 9588#define regDIG1_HDMI_GENERIC_PACKET_CONTROL7 0x21a3 9589#define regDIG1_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 9590#define regDIG1_HDMI_GENERIC_PACKET_CONTROL8 0x21a4 9591#define regDIG1_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 9592#define regDIG1_HDMI_GENERIC_PACKET_CONTROL9 0x21a5 9593#define regDIG1_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 9594#define regDIG1_HDMI_GENERIC_PACKET_CONTROL10 0x21a6 9595#define regDIG1_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 9596#define regDIG1_HDMI_DB_CONTROL 0x21a7 9597#define regDIG1_HDMI_DB_CONTROL_BASE_IDX 2 9598#define regDIG1_HDMI_ACR_32_0 0x21a8 9599#define regDIG1_HDMI_ACR_32_0_BASE_IDX 2 9600#define regDIG1_HDMI_ACR_32_1 0x21a9 9601#define regDIG1_HDMI_ACR_32_1_BASE_IDX 2 9602#define regDIG1_HDMI_ACR_44_0 0x21aa 9603#define regDIG1_HDMI_ACR_44_0_BASE_IDX 2 9604#define regDIG1_HDMI_ACR_44_1 0x21ab 9605#define regDIG1_HDMI_ACR_44_1_BASE_IDX 2 9606#define regDIG1_HDMI_ACR_48_0 0x21ac 9607#define regDIG1_HDMI_ACR_48_0_BASE_IDX 2 9608#define regDIG1_HDMI_ACR_48_1 0x21ad 9609#define regDIG1_HDMI_ACR_48_1_BASE_IDX 2 9610#define regDIG1_HDMI_ACR_STATUS_0 0x21ae 9611#define regDIG1_HDMI_ACR_STATUS_0_BASE_IDX 2 9612#define regDIG1_HDMI_ACR_STATUS_1 0x21af 9613#define regDIG1_HDMI_ACR_STATUS_1_BASE_IDX 2 9614#define regDIG1_AFMT_CNTL 0x21b0 9615#define regDIG1_AFMT_CNTL_BASE_IDX 2 9616#define regDIG1_DIG_BE_CNTL 0x21b1 9617#define regDIG1_DIG_BE_CNTL_BASE_IDX 2 9618#define regDIG1_DIG_BE_EN_CNTL 0x21b2 9619#define regDIG1_DIG_BE_EN_CNTL_BASE_IDX 2 9620#define regDIG1_TMDS_CNTL 0x21d8 9621#define regDIG1_TMDS_CNTL_BASE_IDX 2 9622#define regDIG1_TMDS_CONTROL_CHAR 0x21d9 9623#define regDIG1_TMDS_CONTROL_CHAR_BASE_IDX 2 9624#define regDIG1_TMDS_CONTROL0_FEEDBACK 0x21da 9625#define regDIG1_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 9626#define regDIG1_TMDS_STEREOSYNC_CTL_SEL 0x21db 9627#define regDIG1_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 9628#define regDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x21dc 9629#define regDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 9630#define regDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x21dd 9631#define regDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 9632#define regDIG1_TMDS_CTL_BITS 0x21df 9633#define regDIG1_TMDS_CTL_BITS_BASE_IDX 2 9634#define regDIG1_TMDS_DCBALANCER_CONTROL 0x21e0 9635#define regDIG1_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 9636#define regDIG1_TMDS_SYNC_DCBALANCE_CHAR 0x21e1 9637#define regDIG1_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 9638#define regDIG1_TMDS_CTL0_1_GEN_CNTL 0x21e2 9639#define regDIG1_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 9640#define regDIG1_TMDS_CTL2_3_GEN_CNTL 0x21e3 9641#define regDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 9642#define regDIG1_DIG_VERSION 0x21e5 9643#define regDIG1_DIG_VERSION_BASE_IDX 2 9644#define regDIG1_FORCE_DIG_DISABLE 0x21e6 9645#define regDIG1_FORCE_DIG_DISABLE_BASE_IDX 2 9646 9647 9648// addressBlock: dce_dc_dio_dp1_dispdec 9649// base address: 0x400 9650#define regDP1_DP_LINK_CNTL 0x2208 9651#define regDP1_DP_LINK_CNTL_BASE_IDX 2 9652#define regDP1_DP_PIXEL_FORMAT 0x2209 9653#define regDP1_DP_PIXEL_FORMAT_BASE_IDX 2 9654#define regDP1_DP_MSA_COLORIMETRY 0x220a 9655#define regDP1_DP_MSA_COLORIMETRY_BASE_IDX 2 9656#define regDP1_DP_CONFIG 0x220b 9657#define regDP1_DP_CONFIG_BASE_IDX 2 9658#define regDP1_DP_VID_STREAM_CNTL 0x220c 9659#define regDP1_DP_VID_STREAM_CNTL_BASE_IDX 2 9660#define regDP1_DP_STEER_FIFO 0x220d 9661#define regDP1_DP_STEER_FIFO_BASE_IDX 2 9662#define regDP1_DP_MSA_MISC 0x220e 9663#define regDP1_DP_MSA_MISC_BASE_IDX 2 9664#define regDP1_DP_DPHY_INTERNAL_CTRL 0x220f 9665#define regDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 9666#define regDP1_DP_VID_TIMING 0x2210 9667#define regDP1_DP_VID_TIMING_BASE_IDX 2 9668#define regDP1_DP_VID_N 0x2211 9669#define regDP1_DP_VID_N_BASE_IDX 2 9670#define regDP1_DP_VID_M 0x2212 9671#define regDP1_DP_VID_M_BASE_IDX 2 9672#define regDP1_DP_LINK_FRAMING_CNTL 0x2213 9673#define regDP1_DP_LINK_FRAMING_CNTL_BASE_IDX 2 9674#define regDP1_DP_HBR2_EYE_PATTERN 0x2214 9675#define regDP1_DP_HBR2_EYE_PATTERN_BASE_IDX 2 9676#define regDP1_DP_VID_MSA_VBID 0x2215 9677#define regDP1_DP_VID_MSA_VBID_BASE_IDX 2 9678#define regDP1_DP_VID_INTERRUPT_CNTL 0x2216 9679#define regDP1_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 9680#define regDP1_DP_DPHY_CNTL 0x2217 9681#define regDP1_DP_DPHY_CNTL_BASE_IDX 2 9682#define regDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x2218 9683#define regDP1_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 9684#define regDP1_DP_DPHY_SYM0 0x2219 9685#define regDP1_DP_DPHY_SYM0_BASE_IDX 2 9686#define regDP1_DP_DPHY_SYM1 0x221a 9687#define regDP1_DP_DPHY_SYM1_BASE_IDX 2 9688#define regDP1_DP_DPHY_SYM2 0x221b 9689#define regDP1_DP_DPHY_SYM2_BASE_IDX 2 9690#define regDP1_DP_DPHY_8B10B_CNTL 0x221c 9691#define regDP1_DP_DPHY_8B10B_CNTL_BASE_IDX 2 9692#define regDP1_DP_DPHY_PRBS_CNTL 0x221d 9693#define regDP1_DP_DPHY_PRBS_CNTL_BASE_IDX 2 9694#define regDP1_DP_DPHY_SCRAM_CNTL 0x221e 9695#define regDP1_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 9696#define regDP1_DP_DPHY_CRC_EN 0x221f 9697#define regDP1_DP_DPHY_CRC_EN_BASE_IDX 2 9698#define regDP1_DP_DPHY_CRC_CNTL 0x2220 9699#define regDP1_DP_DPHY_CRC_CNTL_BASE_IDX 2 9700#define regDP1_DP_DPHY_CRC_RESULT 0x2221 9701#define regDP1_DP_DPHY_CRC_RESULT_BASE_IDX 2 9702#define regDP1_DP_DPHY_CRC_MST_CNTL 0x2222 9703#define regDP1_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 9704#define regDP1_DP_DPHY_CRC_MST_STATUS 0x2223 9705#define regDP1_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 9706#define regDP1_DP_DPHY_FAST_TRAINING 0x2224 9707#define regDP1_DP_DPHY_FAST_TRAINING_BASE_IDX 2 9708#define regDP1_DP_DPHY_FAST_TRAINING_STATUS 0x2225 9709#define regDP1_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 9710#define regDP1_DP_SEC_CNTL 0x222b 9711#define regDP1_DP_SEC_CNTL_BASE_IDX 2 9712#define regDP1_DP_SEC_CNTL1 0x222c 9713#define regDP1_DP_SEC_CNTL1_BASE_IDX 2 9714#define regDP1_DP_SEC_FRAMING1 0x222d 9715#define regDP1_DP_SEC_FRAMING1_BASE_IDX 2 9716#define regDP1_DP_SEC_FRAMING2 0x222e 9717#define regDP1_DP_SEC_FRAMING2_BASE_IDX 2 9718#define regDP1_DP_SEC_FRAMING3 0x222f 9719#define regDP1_DP_SEC_FRAMING3_BASE_IDX 2 9720#define regDP1_DP_SEC_FRAMING4 0x2230 9721#define regDP1_DP_SEC_FRAMING4_BASE_IDX 2 9722#define regDP1_DP_SEC_AUD_N 0x2231 9723#define regDP1_DP_SEC_AUD_N_BASE_IDX 2 9724#define regDP1_DP_SEC_AUD_N_READBACK 0x2232 9725#define regDP1_DP_SEC_AUD_N_READBACK_BASE_IDX 2 9726#define regDP1_DP_SEC_AUD_M 0x2233 9727#define regDP1_DP_SEC_AUD_M_BASE_IDX 2 9728#define regDP1_DP_SEC_AUD_M_READBACK 0x2234 9729#define regDP1_DP_SEC_AUD_M_READBACK_BASE_IDX 2 9730#define regDP1_DP_SEC_TIMESTAMP 0x2235 9731#define regDP1_DP_SEC_TIMESTAMP_BASE_IDX 2 9732#define regDP1_DP_SEC_PACKET_CNTL 0x2236 9733#define regDP1_DP_SEC_PACKET_CNTL_BASE_IDX 2 9734#define regDP1_DP_MSE_RATE_CNTL 0x2237 9735#define regDP1_DP_MSE_RATE_CNTL_BASE_IDX 2 9736#define regDP1_DP_MSE_RATE_UPDATE 0x2239 9737#define regDP1_DP_MSE_RATE_UPDATE_BASE_IDX 2 9738#define regDP1_DP_MSE_SAT0 0x223a 9739#define regDP1_DP_MSE_SAT0_BASE_IDX 2 9740#define regDP1_DP_MSE_SAT1 0x223b 9741#define regDP1_DP_MSE_SAT1_BASE_IDX 2 9742#define regDP1_DP_MSE_SAT2 0x223c 9743#define regDP1_DP_MSE_SAT2_BASE_IDX 2 9744#define regDP1_DP_MSE_SAT_UPDATE 0x223d 9745#define regDP1_DP_MSE_SAT_UPDATE_BASE_IDX 2 9746#define regDP1_DP_MSE_LINK_TIMING 0x223e 9747#define regDP1_DP_MSE_LINK_TIMING_BASE_IDX 2 9748#define regDP1_DP_MSE_MISC_CNTL 0x223f 9749#define regDP1_DP_MSE_MISC_CNTL_BASE_IDX 2 9750#define regDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x2244 9751#define regDP1_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 9752#define regDP1_DP_DPHY_HBR2_PATTERN_CONTROL 0x2245 9753#define regDP1_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 9754#define regDP1_DP_MSE_SAT0_STATUS 0x2247 9755#define regDP1_DP_MSE_SAT0_STATUS_BASE_IDX 2 9756#define regDP1_DP_MSE_SAT1_STATUS 0x2248 9757#define regDP1_DP_MSE_SAT1_STATUS_BASE_IDX 2 9758#define regDP1_DP_MSE_SAT2_STATUS 0x2249 9759#define regDP1_DP_MSE_SAT2_STATUS_BASE_IDX 2 9760#define regDP1_DP_DPIA_SPARE 0x224a 9761#define regDP1_DP_DPIA_SPARE_BASE_IDX 2 9762#define regDP1_DP_MSA_TIMING_PARAM1 0x224c 9763#define regDP1_DP_MSA_TIMING_PARAM1_BASE_IDX 2 9764#define regDP1_DP_MSA_TIMING_PARAM2 0x224d 9765#define regDP1_DP_MSA_TIMING_PARAM2_BASE_IDX 2 9766#define regDP1_DP_MSA_TIMING_PARAM3 0x224e 9767#define regDP1_DP_MSA_TIMING_PARAM3_BASE_IDX 2 9768#define regDP1_DP_MSA_TIMING_PARAM4 0x224f 9769#define regDP1_DP_MSA_TIMING_PARAM4_BASE_IDX 2 9770#define regDP1_DP_MSO_CNTL 0x2250 9771#define regDP1_DP_MSO_CNTL_BASE_IDX 2 9772#define regDP1_DP_MSO_CNTL1 0x2251 9773#define regDP1_DP_MSO_CNTL1_BASE_IDX 2 9774#define regDP1_DP_DSC_CNTL 0x2252 9775#define regDP1_DP_DSC_CNTL_BASE_IDX 2 9776#define regDP1_DP_SEC_CNTL2 0x2253 9777#define regDP1_DP_SEC_CNTL2_BASE_IDX 2 9778#define regDP1_DP_SEC_CNTL3 0x2254 9779#define regDP1_DP_SEC_CNTL3_BASE_IDX 2 9780#define regDP1_DP_SEC_CNTL4 0x2255 9781#define regDP1_DP_SEC_CNTL4_BASE_IDX 2 9782#define regDP1_DP_SEC_CNTL5 0x2256 9783#define regDP1_DP_SEC_CNTL5_BASE_IDX 2 9784#define regDP1_DP_SEC_CNTL6 0x2257 9785#define regDP1_DP_SEC_CNTL6_BASE_IDX 2 9786#define regDP1_DP_SEC_CNTL7 0x2258 9787#define regDP1_DP_SEC_CNTL7_BASE_IDX 2 9788#define regDP1_DP_DB_CNTL 0x2259 9789#define regDP1_DP_DB_CNTL_BASE_IDX 2 9790#define regDP1_DP_MSA_VBID_MISC 0x225a 9791#define regDP1_DP_MSA_VBID_MISC_BASE_IDX 2 9792#define regDP1_DP_SEC_METADATA_TRANSMISSION 0x225b 9793#define regDP1_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 9794#define regDP1_DP_ALPM_CNTL 0x225d 9795#define regDP1_DP_ALPM_CNTL_BASE_IDX 2 9796#define regDP1_DP_GSP8_CNTL 0x225e 9797#define regDP1_DP_GSP8_CNTL_BASE_IDX 2 9798#define regDP1_DP_GSP9_CNTL 0x225f 9799#define regDP1_DP_GSP9_CNTL_BASE_IDX 2 9800#define regDP1_DP_GSP10_CNTL 0x2260 9801#define regDP1_DP_GSP10_CNTL_BASE_IDX 2 9802#define regDP1_DP_GSP11_CNTL 0x2261 9803#define regDP1_DP_GSP11_CNTL_BASE_IDX 2 9804#define regDP1_DP_GSP_EN_DB_STATUS 0x2262 9805#define regDP1_DP_GSP_EN_DB_STATUS_BASE_IDX 2 9806#define regDP1_DP_AUXLESS_ALPM_CNTL1 0x2263 9807#define regDP1_DP_AUXLESS_ALPM_CNTL1_BASE_IDX 2 9808#define regDP1_DP_AUXLESS_ALPM_CNTL2 0x2264 9809#define regDP1_DP_AUXLESS_ALPM_CNTL2_BASE_IDX 2 9810#define regDP1_DP_AUXLESS_ALPM_CNTL3 0x2265 9811#define regDP1_DP_AUXLESS_ALPM_CNTL3_BASE_IDX 2 9812#define regDP1_DP_AUXLESS_ALPM_CNTL4 0x2266 9813#define regDP1_DP_AUXLESS_ALPM_CNTL4_BASE_IDX 2 9814#define regDP1_DP_AUXLESS_ALPM_CNTL5 0x2267 9815#define regDP1_DP_AUXLESS_ALPM_CNTL5_BASE_IDX 2 9816 9817 9818// addressBlock: dce_dc_dio_dig2_vpg_vpg_dispdec 9819// base address: 0x15ca0 9820#define regVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2268 9821#define regVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 9822#define regVPG2_VPG_GENERIC_PACKET_DATA 0x2269 9823#define regVPG2_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 9824#define regVPG2_VPG_GSP_FRAME_UPDATE_CTRL 0x226a 9825#define regVPG2_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 9826#define regVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x226b 9827#define regVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 9828#define regVPG2_VPG_GENERIC_STATUS 0x226c 9829#define regVPG2_VPG_GENERIC_STATUS_BASE_IDX 2 9830#define regVPG2_VPG_MEM_PWR 0x226d 9831#define regVPG2_VPG_MEM_PWR_BASE_IDX 2 9832#define regVPG2_VPG_ISRC1_2_ACCESS_CTRL 0x226e 9833#define regVPG2_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 9834#define regVPG2_VPG_ISRC1_2_DATA 0x226f 9835#define regVPG2_VPG_ISRC1_2_DATA_BASE_IDX 2 9836#define regVPG2_VPG_MPEG_INFO0 0x2270 9837#define regVPG2_VPG_MPEG_INFO0_BASE_IDX 2 9838#define regVPG2_VPG_MPEG_INFO1 0x2271 9839#define regVPG2_VPG_MPEG_INFO1_BASE_IDX 2 9840 9841 9842// addressBlock: dce_dc_dio_dig2_afmt_afmt_dispdec 9843// base address: 0x15ccc 9844#define regAFMT2_AFMT_VBI_PACKET_CONTROL 0x2274 9845#define regAFMT2_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 9846#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL2 0x2275 9847#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 9848#define regAFMT2_AFMT_AUDIO_INFO0 0x2276 9849#define regAFMT2_AFMT_AUDIO_INFO0_BASE_IDX 2 9850#define regAFMT2_AFMT_AUDIO_INFO1 0x2277 9851#define regAFMT2_AFMT_AUDIO_INFO1_BASE_IDX 2 9852#define regAFMT2_AFMT_60958_0 0x2278 9853#define regAFMT2_AFMT_60958_0_BASE_IDX 2 9854#define regAFMT2_AFMT_60958_1 0x2279 9855#define regAFMT2_AFMT_60958_1_BASE_IDX 2 9856#define regAFMT2_AFMT_AUDIO_CRC_CONTROL 0x227a 9857#define regAFMT2_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 9858#define regAFMT2_AFMT_RAMP_CONTROL0 0x227b 9859#define regAFMT2_AFMT_RAMP_CONTROL0_BASE_IDX 2 9860#define regAFMT2_AFMT_RAMP_CONTROL1 0x227c 9861#define regAFMT2_AFMT_RAMP_CONTROL1_BASE_IDX 2 9862#define regAFMT2_AFMT_RAMP_CONTROL2 0x227d 9863#define regAFMT2_AFMT_RAMP_CONTROL2_BASE_IDX 2 9864#define regAFMT2_AFMT_RAMP_CONTROL3 0x227e 9865#define regAFMT2_AFMT_RAMP_CONTROL3_BASE_IDX 2 9866#define regAFMT2_AFMT_60958_2 0x227f 9867#define regAFMT2_AFMT_60958_2_BASE_IDX 2 9868#define regAFMT2_AFMT_AUDIO_CRC_RESULT 0x2280 9869#define regAFMT2_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 9870#define regAFMT2_AFMT_STATUS 0x2281 9871#define regAFMT2_AFMT_STATUS_BASE_IDX 2 9872#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL 0x2282 9873#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 9874#define regAFMT2_AFMT_INFOFRAME_CONTROL0 0x2283 9875#define regAFMT2_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 9876#define regAFMT2_AFMT_INTERRUPT_STATUS 0x2284 9877#define regAFMT2_AFMT_INTERRUPT_STATUS_BASE_IDX 2 9878#define regAFMT2_AFMT_AUDIO_SRC_CONTROL 0x2285 9879#define regAFMT2_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 9880#define regAFMT2_AFMT_MEM_PWR 0x2287 9881#define regAFMT2_AFMT_MEM_PWR_BASE_IDX 2 9882 9883 9884// addressBlock: dce_dc_dio_dig2_dme_dme_dispdec 9885// base address: 0x15d24 9886#define regDME2_DME_CONTROL 0x2289 9887#define regDME2_DME_CONTROL_BASE_IDX 2 9888#define regDME2_DME_MEMORY_CONTROL 0x228a 9889#define regDME2_DME_MEMORY_CONTROL_BASE_IDX 2 9890 9891 9892// addressBlock: dce_dc_dio_dig2_dispdec 9893// base address: 0x800 9894#define regDIG2_DIG_FE_CNTL 0x228b 9895#define regDIG2_DIG_FE_CNTL_BASE_IDX 2 9896#define regDIG2_DIG_OUTPUT_CRC_CNTL 0x228c 9897#define regDIG2_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 9898#define regDIG2_DIG_OUTPUT_CRC_RESULT 0x228d 9899#define regDIG2_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 9900#define regDIG2_DIG_CLOCK_PATTERN 0x228e 9901#define regDIG2_DIG_CLOCK_PATTERN_BASE_IDX 2 9902#define regDIG2_DIG_TEST_PATTERN 0x228f 9903#define regDIG2_DIG_TEST_PATTERN_BASE_IDX 2 9904#define regDIG2_DIG_RANDOM_PATTERN_SEED 0x2290 9905#define regDIG2_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 9906#define regDIG2_DIG_FIFO_CTRL0 0x2291 9907#define regDIG2_DIG_FIFO_CTRL0_BASE_IDX 2 9908#define regDIG2_DIG_FIFO_CTRL1 0x2292 9909#define regDIG2_DIG_FIFO_CTRL1_BASE_IDX 2 9910#define regDIG2_HDMI_METADATA_PACKET_CONTROL 0x2293 9911#define regDIG2_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 9912#define regDIG2_HDMI_CONTROL 0x2294 9913#define regDIG2_HDMI_CONTROL_BASE_IDX 2 9914#define regDIG2_HDMI_STATUS 0x2295 9915#define regDIG2_HDMI_STATUS_BASE_IDX 2 9916#define regDIG2_HDMI_AUDIO_PACKET_CONTROL 0x2296 9917#define regDIG2_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 9918#define regDIG2_HDMI_ACR_PACKET_CONTROL 0x2297 9919#define regDIG2_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 9920#define regDIG2_HDMI_VBI_PACKET_CONTROL 0x2298 9921#define regDIG2_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 9922#define regDIG2_HDMI_INFOFRAME_CONTROL0 0x2299 9923#define regDIG2_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 9924#define regDIG2_HDMI_INFOFRAME_CONTROL1 0x229a 9925#define regDIG2_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 9926#define regDIG2_HDMI_GENERIC_PACKET_CONTROL0 0x229b 9927#define regDIG2_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 9928#define regDIG2_HDMI_GENERIC_PACKET_CONTROL6 0x229c 9929#define regDIG2_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 9930#define regDIG2_HDMI_GENERIC_PACKET_CONTROL5 0x229d 9931#define regDIG2_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 9932#define regDIG2_HDMI_GC 0x229e 9933#define regDIG2_HDMI_GC_BASE_IDX 2 9934#define regDIG2_HDMI_GENERIC_PACKET_CONTROL1 0x229f 9935#define regDIG2_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 9936#define regDIG2_HDMI_GENERIC_PACKET_CONTROL2 0x22a0 9937#define regDIG2_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 9938#define regDIG2_HDMI_GENERIC_PACKET_CONTROL3 0x22a1 9939#define regDIG2_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 9940#define regDIG2_HDMI_GENERIC_PACKET_CONTROL4 0x22a2 9941#define regDIG2_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 9942#define regDIG2_HDMI_GENERIC_PACKET_CONTROL7 0x22a3 9943#define regDIG2_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 9944#define regDIG2_HDMI_GENERIC_PACKET_CONTROL8 0x22a4 9945#define regDIG2_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 9946#define regDIG2_HDMI_GENERIC_PACKET_CONTROL9 0x22a5 9947#define regDIG2_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 9948#define regDIG2_HDMI_GENERIC_PACKET_CONTROL10 0x22a6 9949#define regDIG2_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 9950#define regDIG2_HDMI_DB_CONTROL 0x22a7 9951#define regDIG2_HDMI_DB_CONTROL_BASE_IDX 2 9952#define regDIG2_HDMI_ACR_32_0 0x22a8 9953#define regDIG2_HDMI_ACR_32_0_BASE_IDX 2 9954#define regDIG2_HDMI_ACR_32_1 0x22a9 9955#define regDIG2_HDMI_ACR_32_1_BASE_IDX 2 9956#define regDIG2_HDMI_ACR_44_0 0x22aa 9957#define regDIG2_HDMI_ACR_44_0_BASE_IDX 2 9958#define regDIG2_HDMI_ACR_44_1 0x22ab 9959#define regDIG2_HDMI_ACR_44_1_BASE_IDX 2 9960#define regDIG2_HDMI_ACR_48_0 0x22ac 9961#define regDIG2_HDMI_ACR_48_0_BASE_IDX 2 9962#define regDIG2_HDMI_ACR_48_1 0x22ad 9963#define regDIG2_HDMI_ACR_48_1_BASE_IDX 2 9964#define regDIG2_HDMI_ACR_STATUS_0 0x22ae 9965#define regDIG2_HDMI_ACR_STATUS_0_BASE_IDX 2 9966#define regDIG2_HDMI_ACR_STATUS_1 0x22af 9967#define regDIG2_HDMI_ACR_STATUS_1_BASE_IDX 2 9968#define regDIG2_AFMT_CNTL 0x22b0 9969#define regDIG2_AFMT_CNTL_BASE_IDX 2 9970#define regDIG2_DIG_BE_CNTL 0x22b1 9971#define regDIG2_DIG_BE_CNTL_BASE_IDX 2 9972#define regDIG2_DIG_BE_EN_CNTL 0x22b2 9973#define regDIG2_DIG_BE_EN_CNTL_BASE_IDX 2 9974#define regDIG2_TMDS_CNTL 0x22d8 9975#define regDIG2_TMDS_CNTL_BASE_IDX 2 9976#define regDIG2_TMDS_CONTROL_CHAR 0x22d9 9977#define regDIG2_TMDS_CONTROL_CHAR_BASE_IDX 2 9978#define regDIG2_TMDS_CONTROL0_FEEDBACK 0x22da 9979#define regDIG2_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 9980#define regDIG2_TMDS_STEREOSYNC_CTL_SEL 0x22db 9981#define regDIG2_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 9982#define regDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0x22dc 9983#define regDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 9984#define regDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0x22dd 9985#define regDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 9986#define regDIG2_TMDS_CTL_BITS 0x22df 9987#define regDIG2_TMDS_CTL_BITS_BASE_IDX 2 9988#define regDIG2_TMDS_DCBALANCER_CONTROL 0x22e0 9989#define regDIG2_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 9990#define regDIG2_TMDS_SYNC_DCBALANCE_CHAR 0x22e1 9991#define regDIG2_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 9992#define regDIG2_TMDS_CTL0_1_GEN_CNTL 0x22e2 9993#define regDIG2_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 9994#define regDIG2_TMDS_CTL2_3_GEN_CNTL 0x22e3 9995#define regDIG2_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 9996#define regDIG2_DIG_VERSION 0x22e5 9997#define regDIG2_DIG_VERSION_BASE_IDX 2 9998#define regDIG2_FORCE_DIG_DISABLE 0x22e6 9999#define regDIG2_FORCE_DIG_DISABLE_BASE_IDX 2 10000 10001 10002// addressBlock: dce_dc_dio_dp2_dispdec 10003// base address: 0x800 10004#define regDP2_DP_LINK_CNTL 0x2308 10005#define regDP2_DP_LINK_CNTL_BASE_IDX 2 10006#define regDP2_DP_PIXEL_FORMAT 0x2309 10007#define regDP2_DP_PIXEL_FORMAT_BASE_IDX 2 10008#define regDP2_DP_MSA_COLORIMETRY 0x230a 10009#define regDP2_DP_MSA_COLORIMETRY_BASE_IDX 2 10010#define regDP2_DP_CONFIG 0x230b 10011#define regDP2_DP_CONFIG_BASE_IDX 2 10012#define regDP2_DP_VID_STREAM_CNTL 0x230c 10013#define regDP2_DP_VID_STREAM_CNTL_BASE_IDX 2 10014#define regDP2_DP_STEER_FIFO 0x230d 10015#define regDP2_DP_STEER_FIFO_BASE_IDX 2 10016#define regDP2_DP_MSA_MISC 0x230e 10017#define regDP2_DP_MSA_MISC_BASE_IDX 2 10018#define regDP2_DP_DPHY_INTERNAL_CTRL 0x230f 10019#define regDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 10020#define regDP2_DP_VID_TIMING 0x2310 10021#define regDP2_DP_VID_TIMING_BASE_IDX 2 10022#define regDP2_DP_VID_N 0x2311 10023#define regDP2_DP_VID_N_BASE_IDX 2 10024#define regDP2_DP_VID_M 0x2312 10025#define regDP2_DP_VID_M_BASE_IDX 2 10026#define regDP2_DP_LINK_FRAMING_CNTL 0x2313 10027#define regDP2_DP_LINK_FRAMING_CNTL_BASE_IDX 2 10028#define regDP2_DP_HBR2_EYE_PATTERN 0x2314 10029#define regDP2_DP_HBR2_EYE_PATTERN_BASE_IDX 2 10030#define regDP2_DP_VID_MSA_VBID 0x2315 10031#define regDP2_DP_VID_MSA_VBID_BASE_IDX 2 10032#define regDP2_DP_VID_INTERRUPT_CNTL 0x2316 10033#define regDP2_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 10034#define regDP2_DP_DPHY_CNTL 0x2317 10035#define regDP2_DP_DPHY_CNTL_BASE_IDX 2 10036#define regDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x2318 10037#define regDP2_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 10038#define regDP2_DP_DPHY_SYM0 0x2319 10039#define regDP2_DP_DPHY_SYM0_BASE_IDX 2 10040#define regDP2_DP_DPHY_SYM1 0x231a 10041#define regDP2_DP_DPHY_SYM1_BASE_IDX 2 10042#define regDP2_DP_DPHY_SYM2 0x231b 10043#define regDP2_DP_DPHY_SYM2_BASE_IDX 2 10044#define regDP2_DP_DPHY_8B10B_CNTL 0x231c 10045#define regDP2_DP_DPHY_8B10B_CNTL_BASE_IDX 2 10046#define regDP2_DP_DPHY_PRBS_CNTL 0x231d 10047#define regDP2_DP_DPHY_PRBS_CNTL_BASE_IDX 2 10048#define regDP2_DP_DPHY_SCRAM_CNTL 0x231e 10049#define regDP2_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 10050#define regDP2_DP_DPHY_CRC_EN 0x231f 10051#define regDP2_DP_DPHY_CRC_EN_BASE_IDX 2 10052#define regDP2_DP_DPHY_CRC_CNTL 0x2320 10053#define regDP2_DP_DPHY_CRC_CNTL_BASE_IDX 2 10054#define regDP2_DP_DPHY_CRC_RESULT 0x2321 10055#define regDP2_DP_DPHY_CRC_RESULT_BASE_IDX 2 10056#define regDP2_DP_DPHY_CRC_MST_CNTL 0x2322 10057#define regDP2_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 10058#define regDP2_DP_DPHY_CRC_MST_STATUS 0x2323 10059#define regDP2_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 10060#define regDP2_DP_DPHY_FAST_TRAINING 0x2324 10061#define regDP2_DP_DPHY_FAST_TRAINING_BASE_IDX 2 10062#define regDP2_DP_DPHY_FAST_TRAINING_STATUS 0x2325 10063#define regDP2_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 10064#define regDP2_DP_SEC_CNTL 0x232b 10065#define regDP2_DP_SEC_CNTL_BASE_IDX 2 10066#define regDP2_DP_SEC_CNTL1 0x232c 10067#define regDP2_DP_SEC_CNTL1_BASE_IDX 2 10068#define regDP2_DP_SEC_FRAMING1 0x232d 10069#define regDP2_DP_SEC_FRAMING1_BASE_IDX 2 10070#define regDP2_DP_SEC_FRAMING2 0x232e 10071#define regDP2_DP_SEC_FRAMING2_BASE_IDX 2 10072#define regDP2_DP_SEC_FRAMING3 0x232f 10073#define regDP2_DP_SEC_FRAMING3_BASE_IDX 2 10074#define regDP2_DP_SEC_FRAMING4 0x2330 10075#define regDP2_DP_SEC_FRAMING4_BASE_IDX 2 10076#define regDP2_DP_SEC_AUD_N 0x2331 10077#define regDP2_DP_SEC_AUD_N_BASE_IDX 2 10078#define regDP2_DP_SEC_AUD_N_READBACK 0x2332 10079#define regDP2_DP_SEC_AUD_N_READBACK_BASE_IDX 2 10080#define regDP2_DP_SEC_AUD_M 0x2333 10081#define regDP2_DP_SEC_AUD_M_BASE_IDX 2 10082#define regDP2_DP_SEC_AUD_M_READBACK 0x2334 10083#define regDP2_DP_SEC_AUD_M_READBACK_BASE_IDX 2 10084#define regDP2_DP_SEC_TIMESTAMP 0x2335 10085#define regDP2_DP_SEC_TIMESTAMP_BASE_IDX 2 10086#define regDP2_DP_SEC_PACKET_CNTL 0x2336 10087#define regDP2_DP_SEC_PACKET_CNTL_BASE_IDX 2 10088#define regDP2_DP_MSE_RATE_CNTL 0x2337 10089#define regDP2_DP_MSE_RATE_CNTL_BASE_IDX 2 10090#define regDP2_DP_MSE_RATE_UPDATE 0x2339 10091#define regDP2_DP_MSE_RATE_UPDATE_BASE_IDX 2 10092#define regDP2_DP_MSE_SAT0 0x233a 10093#define regDP2_DP_MSE_SAT0_BASE_IDX 2 10094#define regDP2_DP_MSE_SAT1 0x233b 10095#define regDP2_DP_MSE_SAT1_BASE_IDX 2 10096#define regDP2_DP_MSE_SAT2 0x233c 10097#define regDP2_DP_MSE_SAT2_BASE_IDX 2 10098#define regDP2_DP_MSE_SAT_UPDATE 0x233d 10099#define regDP2_DP_MSE_SAT_UPDATE_BASE_IDX 2 10100#define regDP2_DP_MSE_LINK_TIMING 0x233e 10101#define regDP2_DP_MSE_LINK_TIMING_BASE_IDX 2 10102#define regDP2_DP_MSE_MISC_CNTL 0x233f 10103#define regDP2_DP_MSE_MISC_CNTL_BASE_IDX 2 10104#define regDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x2344 10105#define regDP2_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 10106#define regDP2_DP_DPHY_HBR2_PATTERN_CONTROL 0x2345 10107#define regDP2_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 10108#define regDP2_DP_MSE_SAT0_STATUS 0x2347 10109#define regDP2_DP_MSE_SAT0_STATUS_BASE_IDX 2 10110#define regDP2_DP_MSE_SAT1_STATUS 0x2348 10111#define regDP2_DP_MSE_SAT1_STATUS_BASE_IDX 2 10112#define regDP2_DP_MSE_SAT2_STATUS 0x2349 10113#define regDP2_DP_MSE_SAT2_STATUS_BASE_IDX 2 10114#define regDP2_DP_DPIA_SPARE 0x234a 10115#define regDP2_DP_DPIA_SPARE_BASE_IDX 2 10116#define regDP2_DP_MSA_TIMING_PARAM1 0x234c 10117#define regDP2_DP_MSA_TIMING_PARAM1_BASE_IDX 2 10118#define regDP2_DP_MSA_TIMING_PARAM2 0x234d 10119#define regDP2_DP_MSA_TIMING_PARAM2_BASE_IDX 2 10120#define regDP2_DP_MSA_TIMING_PARAM3 0x234e 10121#define regDP2_DP_MSA_TIMING_PARAM3_BASE_IDX 2 10122#define regDP2_DP_MSA_TIMING_PARAM4 0x234f 10123#define regDP2_DP_MSA_TIMING_PARAM4_BASE_IDX 2 10124#define regDP2_DP_MSO_CNTL 0x2350 10125#define regDP2_DP_MSO_CNTL_BASE_IDX 2 10126#define regDP2_DP_MSO_CNTL1 0x2351 10127#define regDP2_DP_MSO_CNTL1_BASE_IDX 2 10128#define regDP2_DP_DSC_CNTL 0x2352 10129#define regDP2_DP_DSC_CNTL_BASE_IDX 2 10130#define regDP2_DP_SEC_CNTL2 0x2353 10131#define regDP2_DP_SEC_CNTL2_BASE_IDX 2 10132#define regDP2_DP_SEC_CNTL3 0x2354 10133#define regDP2_DP_SEC_CNTL3_BASE_IDX 2 10134#define regDP2_DP_SEC_CNTL4 0x2355 10135#define regDP2_DP_SEC_CNTL4_BASE_IDX 2 10136#define regDP2_DP_SEC_CNTL5 0x2356 10137#define regDP2_DP_SEC_CNTL5_BASE_IDX 2 10138#define regDP2_DP_SEC_CNTL6 0x2357 10139#define regDP2_DP_SEC_CNTL6_BASE_IDX 2 10140#define regDP2_DP_SEC_CNTL7 0x2358 10141#define regDP2_DP_SEC_CNTL7_BASE_IDX 2 10142#define regDP2_DP_DB_CNTL 0x2359 10143#define regDP2_DP_DB_CNTL_BASE_IDX 2 10144#define regDP2_DP_MSA_VBID_MISC 0x235a 10145#define regDP2_DP_MSA_VBID_MISC_BASE_IDX 2 10146#define regDP2_DP_SEC_METADATA_TRANSMISSION 0x235b 10147#define regDP2_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 10148#define regDP2_DP_ALPM_CNTL 0x235d 10149#define regDP2_DP_ALPM_CNTL_BASE_IDX 2 10150#define regDP2_DP_GSP8_CNTL 0x235e 10151#define regDP2_DP_GSP8_CNTL_BASE_IDX 2 10152#define regDP2_DP_GSP9_CNTL 0x235f 10153#define regDP2_DP_GSP9_CNTL_BASE_IDX 2 10154#define regDP2_DP_GSP10_CNTL 0x2360 10155#define regDP2_DP_GSP10_CNTL_BASE_IDX 2 10156#define regDP2_DP_GSP11_CNTL 0x2361 10157#define regDP2_DP_GSP11_CNTL_BASE_IDX 2 10158#define regDP2_DP_GSP_EN_DB_STATUS 0x2362 10159#define regDP2_DP_GSP_EN_DB_STATUS_BASE_IDX 2 10160#define regDP2_DP_AUXLESS_ALPM_CNTL1 0x2363 10161#define regDP2_DP_AUXLESS_ALPM_CNTL1_BASE_IDX 2 10162#define regDP2_DP_AUXLESS_ALPM_CNTL2 0x2364 10163#define regDP2_DP_AUXLESS_ALPM_CNTL2_BASE_IDX 2 10164#define regDP2_DP_AUXLESS_ALPM_CNTL3 0x2365 10165#define regDP2_DP_AUXLESS_ALPM_CNTL3_BASE_IDX 2 10166#define regDP2_DP_AUXLESS_ALPM_CNTL4 0x2366 10167#define regDP2_DP_AUXLESS_ALPM_CNTL4_BASE_IDX 2 10168#define regDP2_DP_AUXLESS_ALPM_CNTL5 0x2367 10169#define regDP2_DP_AUXLESS_ALPM_CNTL5_BASE_IDX 2 10170 10171 10172// addressBlock: dce_dc_dio_dig3_vpg_vpg_dispdec 10173// base address: 0x160a0 10174#define regVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2368 10175#define regVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 10176#define regVPG3_VPG_GENERIC_PACKET_DATA 0x2369 10177#define regVPG3_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 10178#define regVPG3_VPG_GSP_FRAME_UPDATE_CTRL 0x236a 10179#define regVPG3_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 10180#define regVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x236b 10181#define regVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 10182#define regVPG3_VPG_GENERIC_STATUS 0x236c 10183#define regVPG3_VPG_GENERIC_STATUS_BASE_IDX 2 10184#define regVPG3_VPG_MEM_PWR 0x236d 10185#define regVPG3_VPG_MEM_PWR_BASE_IDX 2 10186#define regVPG3_VPG_ISRC1_2_ACCESS_CTRL 0x236e 10187#define regVPG3_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 10188#define regVPG3_VPG_ISRC1_2_DATA 0x236f 10189#define regVPG3_VPG_ISRC1_2_DATA_BASE_IDX 2 10190#define regVPG3_VPG_MPEG_INFO0 0x2370 10191#define regVPG3_VPG_MPEG_INFO0_BASE_IDX 2 10192#define regVPG3_VPG_MPEG_INFO1 0x2371 10193#define regVPG3_VPG_MPEG_INFO1_BASE_IDX 2 10194 10195 10196// addressBlock: dce_dc_dio_dig3_afmt_afmt_dispdec 10197// base address: 0x160cc 10198#define regAFMT3_AFMT_VBI_PACKET_CONTROL 0x2374 10199#define regAFMT3_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 10200#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL2 0x2375 10201#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 10202#define regAFMT3_AFMT_AUDIO_INFO0 0x2376 10203#define regAFMT3_AFMT_AUDIO_INFO0_BASE_IDX 2 10204#define regAFMT3_AFMT_AUDIO_INFO1 0x2377 10205#define regAFMT3_AFMT_AUDIO_INFO1_BASE_IDX 2 10206#define regAFMT3_AFMT_60958_0 0x2378 10207#define regAFMT3_AFMT_60958_0_BASE_IDX 2 10208#define regAFMT3_AFMT_60958_1 0x2379 10209#define regAFMT3_AFMT_60958_1_BASE_IDX 2 10210#define regAFMT3_AFMT_AUDIO_CRC_CONTROL 0x237a 10211#define regAFMT3_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 10212#define regAFMT3_AFMT_RAMP_CONTROL0 0x237b 10213#define regAFMT3_AFMT_RAMP_CONTROL0_BASE_IDX 2 10214#define regAFMT3_AFMT_RAMP_CONTROL1 0x237c 10215#define regAFMT3_AFMT_RAMP_CONTROL1_BASE_IDX 2 10216#define regAFMT3_AFMT_RAMP_CONTROL2 0x237d 10217#define regAFMT3_AFMT_RAMP_CONTROL2_BASE_IDX 2 10218#define regAFMT3_AFMT_RAMP_CONTROL3 0x237e 10219#define regAFMT3_AFMT_RAMP_CONTROL3_BASE_IDX 2 10220#define regAFMT3_AFMT_60958_2 0x237f 10221#define regAFMT3_AFMT_60958_2_BASE_IDX 2 10222#define regAFMT3_AFMT_AUDIO_CRC_RESULT 0x2380 10223#define regAFMT3_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 10224#define regAFMT3_AFMT_STATUS 0x2381 10225#define regAFMT3_AFMT_STATUS_BASE_IDX 2 10226#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL 0x2382 10227#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 10228#define regAFMT3_AFMT_INFOFRAME_CONTROL0 0x2383 10229#define regAFMT3_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 10230#define regAFMT3_AFMT_INTERRUPT_STATUS 0x2384 10231#define regAFMT3_AFMT_INTERRUPT_STATUS_BASE_IDX 2 10232#define regAFMT3_AFMT_AUDIO_SRC_CONTROL 0x2385 10233#define regAFMT3_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 10234#define regAFMT3_AFMT_MEM_PWR 0x2387 10235#define regAFMT3_AFMT_MEM_PWR_BASE_IDX 2 10236 10237 10238// addressBlock: dce_dc_dio_dig3_dme_dme_dispdec 10239// base address: 0x16124 10240#define regDME3_DME_CONTROL 0x2389 10241#define regDME3_DME_CONTROL_BASE_IDX 2 10242#define regDME3_DME_MEMORY_CONTROL 0x238a 10243#define regDME3_DME_MEMORY_CONTROL_BASE_IDX 2 10244 10245 10246// addressBlock: dce_dc_dio_dig3_dispdec 10247// base address: 0xc00 10248#define regDIG3_DIG_FE_CNTL 0x238b 10249#define regDIG3_DIG_FE_CNTL_BASE_IDX 2 10250#define regDIG3_DIG_OUTPUT_CRC_CNTL 0x238c 10251#define regDIG3_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 10252#define regDIG3_DIG_OUTPUT_CRC_RESULT 0x238d 10253#define regDIG3_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 10254#define regDIG3_DIG_CLOCK_PATTERN 0x238e 10255#define regDIG3_DIG_CLOCK_PATTERN_BASE_IDX 2 10256#define regDIG3_DIG_TEST_PATTERN 0x238f 10257#define regDIG3_DIG_TEST_PATTERN_BASE_IDX 2 10258#define regDIG3_DIG_RANDOM_PATTERN_SEED 0x2390 10259#define regDIG3_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 10260#define regDIG3_DIG_FIFO_CTRL0 0x2391 10261#define regDIG3_DIG_FIFO_CTRL0_BASE_IDX 2 10262#define regDIG3_DIG_FIFO_CTRL1 0x2392 10263#define regDIG3_DIG_FIFO_CTRL1_BASE_IDX 2 10264#define regDIG3_HDMI_METADATA_PACKET_CONTROL 0x2393 10265#define regDIG3_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 10266#define regDIG3_HDMI_CONTROL 0x2394 10267#define regDIG3_HDMI_CONTROL_BASE_IDX 2 10268#define regDIG3_HDMI_STATUS 0x2395 10269#define regDIG3_HDMI_STATUS_BASE_IDX 2 10270#define regDIG3_HDMI_AUDIO_PACKET_CONTROL 0x2396 10271#define regDIG3_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 10272#define regDIG3_HDMI_ACR_PACKET_CONTROL 0x2397 10273#define regDIG3_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 10274#define regDIG3_HDMI_VBI_PACKET_CONTROL 0x2398 10275#define regDIG3_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 10276#define regDIG3_HDMI_INFOFRAME_CONTROL0 0x2399 10277#define regDIG3_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 10278#define regDIG3_HDMI_INFOFRAME_CONTROL1 0x239a 10279#define regDIG3_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 10280#define regDIG3_HDMI_GENERIC_PACKET_CONTROL0 0x239b 10281#define regDIG3_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 10282#define regDIG3_HDMI_GENERIC_PACKET_CONTROL6 0x239c 10283#define regDIG3_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 10284#define regDIG3_HDMI_GENERIC_PACKET_CONTROL5 0x239d 10285#define regDIG3_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 10286#define regDIG3_HDMI_GC 0x239e 10287#define regDIG3_HDMI_GC_BASE_IDX 2 10288#define regDIG3_HDMI_GENERIC_PACKET_CONTROL1 0x239f 10289#define regDIG3_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 10290#define regDIG3_HDMI_GENERIC_PACKET_CONTROL2 0x23a0 10291#define regDIG3_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 10292#define regDIG3_HDMI_GENERIC_PACKET_CONTROL3 0x23a1 10293#define regDIG3_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 10294#define regDIG3_HDMI_GENERIC_PACKET_CONTROL4 0x23a2 10295#define regDIG3_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 10296#define regDIG3_HDMI_GENERIC_PACKET_CONTROL7 0x23a3 10297#define regDIG3_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 10298#define regDIG3_HDMI_GENERIC_PACKET_CONTROL8 0x23a4 10299#define regDIG3_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 10300#define regDIG3_HDMI_GENERIC_PACKET_CONTROL9 0x23a5 10301#define regDIG3_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 10302#define regDIG3_HDMI_GENERIC_PACKET_CONTROL10 0x23a6 10303#define regDIG3_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 10304#define regDIG3_HDMI_DB_CONTROL 0x23a7 10305#define regDIG3_HDMI_DB_CONTROL_BASE_IDX 2 10306#define regDIG3_HDMI_ACR_32_0 0x23a8 10307#define regDIG3_HDMI_ACR_32_0_BASE_IDX 2 10308#define regDIG3_HDMI_ACR_32_1 0x23a9 10309#define regDIG3_HDMI_ACR_32_1_BASE_IDX 2 10310#define regDIG3_HDMI_ACR_44_0 0x23aa 10311#define regDIG3_HDMI_ACR_44_0_BASE_IDX 2 10312#define regDIG3_HDMI_ACR_44_1 0x23ab 10313#define regDIG3_HDMI_ACR_44_1_BASE_IDX 2 10314#define regDIG3_HDMI_ACR_48_0 0x23ac 10315#define regDIG3_HDMI_ACR_48_0_BASE_IDX 2 10316#define regDIG3_HDMI_ACR_48_1 0x23ad 10317#define regDIG3_HDMI_ACR_48_1_BASE_IDX 2 10318#define regDIG3_HDMI_ACR_STATUS_0 0x23ae 10319#define regDIG3_HDMI_ACR_STATUS_0_BASE_IDX 2 10320#define regDIG3_HDMI_ACR_STATUS_1 0x23af 10321#define regDIG3_HDMI_ACR_STATUS_1_BASE_IDX 2 10322#define regDIG3_AFMT_CNTL 0x23b0 10323#define regDIG3_AFMT_CNTL_BASE_IDX 2 10324#define regDIG3_DIG_BE_CNTL 0x23b1 10325#define regDIG3_DIG_BE_CNTL_BASE_IDX 2 10326#define regDIG3_DIG_BE_EN_CNTL 0x23b2 10327#define regDIG3_DIG_BE_EN_CNTL_BASE_IDX 2 10328#define regDIG3_TMDS_CNTL 0x23d8 10329#define regDIG3_TMDS_CNTL_BASE_IDX 2 10330#define regDIG3_TMDS_CONTROL_CHAR 0x23d9 10331#define regDIG3_TMDS_CONTROL_CHAR_BASE_IDX 2 10332#define regDIG3_TMDS_CONTROL0_FEEDBACK 0x23da 10333#define regDIG3_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 10334#define regDIG3_TMDS_STEREOSYNC_CTL_SEL 0x23db 10335#define regDIG3_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 10336#define regDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0x23dc 10337#define regDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 10338#define regDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0x23dd 10339#define regDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 10340#define regDIG3_TMDS_CTL_BITS 0x23df 10341#define regDIG3_TMDS_CTL_BITS_BASE_IDX 2 10342#define regDIG3_TMDS_DCBALANCER_CONTROL 0x23e0 10343#define regDIG3_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 10344#define regDIG3_TMDS_SYNC_DCBALANCE_CHAR 0x23e1 10345#define regDIG3_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 10346#define regDIG3_TMDS_CTL0_1_GEN_CNTL 0x23e2 10347#define regDIG3_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 10348#define regDIG3_TMDS_CTL2_3_GEN_CNTL 0x23e3 10349#define regDIG3_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 10350#define regDIG3_DIG_VERSION 0x23e5 10351#define regDIG3_DIG_VERSION_BASE_IDX 2 10352#define regDIG3_FORCE_DIG_DISABLE 0x23e6 10353#define regDIG3_FORCE_DIG_DISABLE_BASE_IDX 2 10354 10355 10356// addressBlock: dce_dc_dio_dp3_dispdec 10357// base address: 0xc00 10358#define regDP3_DP_LINK_CNTL 0x2408 10359#define regDP3_DP_LINK_CNTL_BASE_IDX 2 10360#define regDP3_DP_PIXEL_FORMAT 0x2409 10361#define regDP3_DP_PIXEL_FORMAT_BASE_IDX 2 10362#define regDP3_DP_MSA_COLORIMETRY 0x240a 10363#define regDP3_DP_MSA_COLORIMETRY_BASE_IDX 2 10364#define regDP3_DP_CONFIG 0x240b 10365#define regDP3_DP_CONFIG_BASE_IDX 2 10366#define regDP3_DP_VID_STREAM_CNTL 0x240c 10367#define regDP3_DP_VID_STREAM_CNTL_BASE_IDX 2 10368#define regDP3_DP_STEER_FIFO 0x240d 10369#define regDP3_DP_STEER_FIFO_BASE_IDX 2 10370#define regDP3_DP_MSA_MISC 0x240e 10371#define regDP3_DP_MSA_MISC_BASE_IDX 2 10372#define regDP3_DP_DPHY_INTERNAL_CTRL 0x240f 10373#define regDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 10374#define regDP3_DP_VID_TIMING 0x2410 10375#define regDP3_DP_VID_TIMING_BASE_IDX 2 10376#define regDP3_DP_VID_N 0x2411 10377#define regDP3_DP_VID_N_BASE_IDX 2 10378#define regDP3_DP_VID_M 0x2412 10379#define regDP3_DP_VID_M_BASE_IDX 2 10380#define regDP3_DP_LINK_FRAMING_CNTL 0x2413 10381#define regDP3_DP_LINK_FRAMING_CNTL_BASE_IDX 2 10382#define regDP3_DP_HBR2_EYE_PATTERN 0x2414 10383#define regDP3_DP_HBR2_EYE_PATTERN_BASE_IDX 2 10384#define regDP3_DP_VID_MSA_VBID 0x2415 10385#define regDP3_DP_VID_MSA_VBID_BASE_IDX 2 10386#define regDP3_DP_VID_INTERRUPT_CNTL 0x2416 10387#define regDP3_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 10388#define regDP3_DP_DPHY_CNTL 0x2417 10389#define regDP3_DP_DPHY_CNTL_BASE_IDX 2 10390#define regDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x2418 10391#define regDP3_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 10392#define regDP3_DP_DPHY_SYM0 0x2419 10393#define regDP3_DP_DPHY_SYM0_BASE_IDX 2 10394#define regDP3_DP_DPHY_SYM1 0x241a 10395#define regDP3_DP_DPHY_SYM1_BASE_IDX 2 10396#define regDP3_DP_DPHY_SYM2 0x241b 10397#define regDP3_DP_DPHY_SYM2_BASE_IDX 2 10398#define regDP3_DP_DPHY_8B10B_CNTL 0x241c 10399#define regDP3_DP_DPHY_8B10B_CNTL_BASE_IDX 2 10400#define regDP3_DP_DPHY_PRBS_CNTL 0x241d 10401#define regDP3_DP_DPHY_PRBS_CNTL_BASE_IDX 2 10402#define regDP3_DP_DPHY_SCRAM_CNTL 0x241e 10403#define regDP3_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 10404#define regDP3_DP_DPHY_CRC_EN 0x241f 10405#define regDP3_DP_DPHY_CRC_EN_BASE_IDX 2 10406#define regDP3_DP_DPHY_CRC_CNTL 0x2420 10407#define regDP3_DP_DPHY_CRC_CNTL_BASE_IDX 2 10408#define regDP3_DP_DPHY_CRC_RESULT 0x2421 10409#define regDP3_DP_DPHY_CRC_RESULT_BASE_IDX 2 10410#define regDP3_DP_DPHY_CRC_MST_CNTL 0x2422 10411#define regDP3_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 10412#define regDP3_DP_DPHY_CRC_MST_STATUS 0x2423 10413#define regDP3_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 10414#define regDP3_DP_DPHY_FAST_TRAINING 0x2424 10415#define regDP3_DP_DPHY_FAST_TRAINING_BASE_IDX 2 10416#define regDP3_DP_DPHY_FAST_TRAINING_STATUS 0x2425 10417#define regDP3_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 10418#define regDP3_DP_SEC_CNTL 0x242b 10419#define regDP3_DP_SEC_CNTL_BASE_IDX 2 10420#define regDP3_DP_SEC_CNTL1 0x242c 10421#define regDP3_DP_SEC_CNTL1_BASE_IDX 2 10422#define regDP3_DP_SEC_FRAMING1 0x242d 10423#define regDP3_DP_SEC_FRAMING1_BASE_IDX 2 10424#define regDP3_DP_SEC_FRAMING2 0x242e 10425#define regDP3_DP_SEC_FRAMING2_BASE_IDX 2 10426#define regDP3_DP_SEC_FRAMING3 0x242f 10427#define regDP3_DP_SEC_FRAMING3_BASE_IDX 2 10428#define regDP3_DP_SEC_FRAMING4 0x2430 10429#define regDP3_DP_SEC_FRAMING4_BASE_IDX 2 10430#define regDP3_DP_SEC_AUD_N 0x2431 10431#define regDP3_DP_SEC_AUD_N_BASE_IDX 2 10432#define regDP3_DP_SEC_AUD_N_READBACK 0x2432 10433#define regDP3_DP_SEC_AUD_N_READBACK_BASE_IDX 2 10434#define regDP3_DP_SEC_AUD_M 0x2433 10435#define regDP3_DP_SEC_AUD_M_BASE_IDX 2 10436#define regDP3_DP_SEC_AUD_M_READBACK 0x2434 10437#define regDP3_DP_SEC_AUD_M_READBACK_BASE_IDX 2 10438#define regDP3_DP_SEC_TIMESTAMP 0x2435 10439#define regDP3_DP_SEC_TIMESTAMP_BASE_IDX 2 10440#define regDP3_DP_SEC_PACKET_CNTL 0x2436 10441#define regDP3_DP_SEC_PACKET_CNTL_BASE_IDX 2 10442#define regDP3_DP_MSE_RATE_CNTL 0x2437 10443#define regDP3_DP_MSE_RATE_CNTL_BASE_IDX 2 10444#define regDP3_DP_MSE_RATE_UPDATE 0x2439 10445#define regDP3_DP_MSE_RATE_UPDATE_BASE_IDX 2 10446#define regDP3_DP_MSE_SAT0 0x243a 10447#define regDP3_DP_MSE_SAT0_BASE_IDX 2 10448#define regDP3_DP_MSE_SAT1 0x243b 10449#define regDP3_DP_MSE_SAT1_BASE_IDX 2 10450#define regDP3_DP_MSE_SAT2 0x243c 10451#define regDP3_DP_MSE_SAT2_BASE_IDX 2 10452#define regDP3_DP_MSE_SAT_UPDATE 0x243d 10453#define regDP3_DP_MSE_SAT_UPDATE_BASE_IDX 2 10454#define regDP3_DP_MSE_LINK_TIMING 0x243e 10455#define regDP3_DP_MSE_LINK_TIMING_BASE_IDX 2 10456#define regDP3_DP_MSE_MISC_CNTL 0x243f 10457#define regDP3_DP_MSE_MISC_CNTL_BASE_IDX 2 10458#define regDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x2444 10459#define regDP3_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 10460#define regDP3_DP_DPHY_HBR2_PATTERN_CONTROL 0x2445 10461#define regDP3_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 10462#define regDP3_DP_MSE_SAT0_STATUS 0x2447 10463#define regDP3_DP_MSE_SAT0_STATUS_BASE_IDX 2 10464#define regDP3_DP_MSE_SAT1_STATUS 0x2448 10465#define regDP3_DP_MSE_SAT1_STATUS_BASE_IDX 2 10466#define regDP3_DP_MSE_SAT2_STATUS 0x2449 10467#define regDP3_DP_MSE_SAT2_STATUS_BASE_IDX 2 10468#define regDP3_DP_DPIA_SPARE 0x244a 10469#define regDP3_DP_DPIA_SPARE_BASE_IDX 2 10470#define regDP3_DP_MSA_TIMING_PARAM1 0x244c 10471#define regDP3_DP_MSA_TIMING_PARAM1_BASE_IDX 2 10472#define regDP3_DP_MSA_TIMING_PARAM2 0x244d 10473#define regDP3_DP_MSA_TIMING_PARAM2_BASE_IDX 2 10474#define regDP3_DP_MSA_TIMING_PARAM3 0x244e 10475#define regDP3_DP_MSA_TIMING_PARAM3_BASE_IDX 2 10476#define regDP3_DP_MSA_TIMING_PARAM4 0x244f 10477#define regDP3_DP_MSA_TIMING_PARAM4_BASE_IDX 2 10478#define regDP3_DP_MSO_CNTL 0x2450 10479#define regDP3_DP_MSO_CNTL_BASE_IDX 2 10480#define regDP3_DP_MSO_CNTL1 0x2451 10481#define regDP3_DP_MSO_CNTL1_BASE_IDX 2 10482#define regDP3_DP_DSC_CNTL 0x2452 10483#define regDP3_DP_DSC_CNTL_BASE_IDX 2 10484#define regDP3_DP_SEC_CNTL2 0x2453 10485#define regDP3_DP_SEC_CNTL2_BASE_IDX 2 10486#define regDP3_DP_SEC_CNTL3 0x2454 10487#define regDP3_DP_SEC_CNTL3_BASE_IDX 2 10488#define regDP3_DP_SEC_CNTL4 0x2455 10489#define regDP3_DP_SEC_CNTL4_BASE_IDX 2 10490#define regDP3_DP_SEC_CNTL5 0x2456 10491#define regDP3_DP_SEC_CNTL5_BASE_IDX 2 10492#define regDP3_DP_SEC_CNTL6 0x2457 10493#define regDP3_DP_SEC_CNTL6_BASE_IDX 2 10494#define regDP3_DP_SEC_CNTL7 0x2458 10495#define regDP3_DP_SEC_CNTL7_BASE_IDX 2 10496#define regDP3_DP_DB_CNTL 0x2459 10497#define regDP3_DP_DB_CNTL_BASE_IDX 2 10498#define regDP3_DP_MSA_VBID_MISC 0x245a 10499#define regDP3_DP_MSA_VBID_MISC_BASE_IDX 2 10500#define regDP3_DP_SEC_METADATA_TRANSMISSION 0x245b 10501#define regDP3_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 10502#define regDP3_DP_ALPM_CNTL 0x245d 10503#define regDP3_DP_ALPM_CNTL_BASE_IDX 2 10504#define regDP3_DP_GSP8_CNTL 0x245e 10505#define regDP3_DP_GSP8_CNTL_BASE_IDX 2 10506#define regDP3_DP_GSP9_CNTL 0x245f 10507#define regDP3_DP_GSP9_CNTL_BASE_IDX 2 10508#define regDP3_DP_GSP10_CNTL 0x2460 10509#define regDP3_DP_GSP10_CNTL_BASE_IDX 2 10510#define regDP3_DP_GSP11_CNTL 0x2461 10511#define regDP3_DP_GSP11_CNTL_BASE_IDX 2 10512#define regDP3_DP_GSP_EN_DB_STATUS 0x2462 10513#define regDP3_DP_GSP_EN_DB_STATUS_BASE_IDX 2 10514#define regDP3_DP_AUXLESS_ALPM_CNTL1 0x2463 10515#define regDP3_DP_AUXLESS_ALPM_CNTL1_BASE_IDX 2 10516#define regDP3_DP_AUXLESS_ALPM_CNTL2 0x2464 10517#define regDP3_DP_AUXLESS_ALPM_CNTL2_BASE_IDX 2 10518#define regDP3_DP_AUXLESS_ALPM_CNTL3 0x2465 10519#define regDP3_DP_AUXLESS_ALPM_CNTL3_BASE_IDX 2 10520#define regDP3_DP_AUXLESS_ALPM_CNTL4 0x2466 10521#define regDP3_DP_AUXLESS_ALPM_CNTL4_BASE_IDX 2 10522#define regDP3_DP_AUXLESS_ALPM_CNTL5 0x2467 10523#define regDP3_DP_AUXLESS_ALPM_CNTL5_BASE_IDX 2 10524 10525 10526// addressBlock: dce_dc_dio_dig4_vpg_vpg_dispdec 10527// base address: 0x164a0 10528#define regVPG4_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2468 10529#define regVPG4_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 10530#define regVPG4_VPG_GENERIC_PACKET_DATA 0x2469 10531#define regVPG4_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 10532#define regVPG4_VPG_GSP_FRAME_UPDATE_CTRL 0x246a 10533#define regVPG4_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 10534#define regVPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x246b 10535#define regVPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 10536#define regVPG4_VPG_GENERIC_STATUS 0x246c 10537#define regVPG4_VPG_GENERIC_STATUS_BASE_IDX 2 10538#define regVPG4_VPG_MEM_PWR 0x246d 10539#define regVPG4_VPG_MEM_PWR_BASE_IDX 2 10540#define regVPG4_VPG_ISRC1_2_ACCESS_CTRL 0x246e 10541#define regVPG4_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 10542#define regVPG4_VPG_ISRC1_2_DATA 0x246f 10543#define regVPG4_VPG_ISRC1_2_DATA_BASE_IDX 2 10544#define regVPG4_VPG_MPEG_INFO0 0x2470 10545#define regVPG4_VPG_MPEG_INFO0_BASE_IDX 2 10546#define regVPG4_VPG_MPEG_INFO1 0x2471 10547#define regVPG4_VPG_MPEG_INFO1_BASE_IDX 2 10548 10549 10550// addressBlock: dce_dc_dio_dig4_afmt_afmt_dispdec 10551// base address: 0x164cc 10552#define regAFMT4_AFMT_VBI_PACKET_CONTROL 0x2474 10553#define regAFMT4_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 10554#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL2 0x2475 10555#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 10556#define regAFMT4_AFMT_AUDIO_INFO0 0x2476 10557#define regAFMT4_AFMT_AUDIO_INFO0_BASE_IDX 2 10558#define regAFMT4_AFMT_AUDIO_INFO1 0x2477 10559#define regAFMT4_AFMT_AUDIO_INFO1_BASE_IDX 2 10560#define regAFMT4_AFMT_60958_0 0x2478 10561#define regAFMT4_AFMT_60958_0_BASE_IDX 2 10562#define regAFMT4_AFMT_60958_1 0x2479 10563#define regAFMT4_AFMT_60958_1_BASE_IDX 2 10564#define regAFMT4_AFMT_AUDIO_CRC_CONTROL 0x247a 10565#define regAFMT4_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 10566#define regAFMT4_AFMT_RAMP_CONTROL0 0x247b 10567#define regAFMT4_AFMT_RAMP_CONTROL0_BASE_IDX 2 10568#define regAFMT4_AFMT_RAMP_CONTROL1 0x247c 10569#define regAFMT4_AFMT_RAMP_CONTROL1_BASE_IDX 2 10570#define regAFMT4_AFMT_RAMP_CONTROL2 0x247d 10571#define regAFMT4_AFMT_RAMP_CONTROL2_BASE_IDX 2 10572#define regAFMT4_AFMT_RAMP_CONTROL3 0x247e 10573#define regAFMT4_AFMT_RAMP_CONTROL3_BASE_IDX 2 10574#define regAFMT4_AFMT_60958_2 0x247f 10575#define regAFMT4_AFMT_60958_2_BASE_IDX 2 10576#define regAFMT4_AFMT_AUDIO_CRC_RESULT 0x2480 10577#define regAFMT4_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 10578#define regAFMT4_AFMT_STATUS 0x2481 10579#define regAFMT4_AFMT_STATUS_BASE_IDX 2 10580#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL 0x2482 10581#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 10582#define regAFMT4_AFMT_INFOFRAME_CONTROL0 0x2483 10583#define regAFMT4_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 10584#define regAFMT4_AFMT_INTERRUPT_STATUS 0x2484 10585#define regAFMT4_AFMT_INTERRUPT_STATUS_BASE_IDX 2 10586#define regAFMT4_AFMT_AUDIO_SRC_CONTROL 0x2485 10587#define regAFMT4_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 10588#define regAFMT4_AFMT_MEM_PWR 0x2487 10589#define regAFMT4_AFMT_MEM_PWR_BASE_IDX 2 10590 10591 10592// addressBlock: dce_dc_dio_dig4_dme_dme_dispdec 10593// base address: 0x16524 10594#define regDME4_DME_CONTROL 0x2489 10595#define regDME4_DME_CONTROL_BASE_IDX 2 10596#define regDME4_DME_MEMORY_CONTROL 0x248a 10597#define regDME4_DME_MEMORY_CONTROL_BASE_IDX 2 10598 10599 10600// addressBlock: dce_dc_dio_dig4_dispdec 10601// base address: 0x1000 10602#define regDIG4_DIG_FE_CNTL 0x248b 10603#define regDIG4_DIG_FE_CNTL_BASE_IDX 2 10604#define regDIG4_DIG_OUTPUT_CRC_CNTL 0x248c 10605#define regDIG4_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 10606#define regDIG4_DIG_OUTPUT_CRC_RESULT 0x248d 10607#define regDIG4_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 10608#define regDIG4_DIG_CLOCK_PATTERN 0x248e 10609#define regDIG4_DIG_CLOCK_PATTERN_BASE_IDX 2 10610#define regDIG4_DIG_TEST_PATTERN 0x248f 10611#define regDIG4_DIG_TEST_PATTERN_BASE_IDX 2 10612#define regDIG4_DIG_RANDOM_PATTERN_SEED 0x2490 10613#define regDIG4_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 10614#define regDIG4_DIG_FIFO_CTRL0 0x2491 10615#define regDIG4_DIG_FIFO_CTRL0_BASE_IDX 2 10616#define regDIG4_DIG_FIFO_CTRL1 0x2492 10617#define regDIG4_DIG_FIFO_CTRL1_BASE_IDX 2 10618#define regDIG4_HDMI_METADATA_PACKET_CONTROL 0x2493 10619#define regDIG4_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 10620#define regDIG4_HDMI_CONTROL 0x2494 10621#define regDIG4_HDMI_CONTROL_BASE_IDX 2 10622#define regDIG4_HDMI_STATUS 0x2495 10623#define regDIG4_HDMI_STATUS_BASE_IDX 2 10624#define regDIG4_HDMI_AUDIO_PACKET_CONTROL 0x2496 10625#define regDIG4_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 10626#define regDIG4_HDMI_ACR_PACKET_CONTROL 0x2497 10627#define regDIG4_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 10628#define regDIG4_HDMI_VBI_PACKET_CONTROL 0x2498 10629#define regDIG4_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 10630#define regDIG4_HDMI_INFOFRAME_CONTROL0 0x2499 10631#define regDIG4_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 10632#define regDIG4_HDMI_INFOFRAME_CONTROL1 0x249a 10633#define regDIG4_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 10634#define regDIG4_HDMI_GENERIC_PACKET_CONTROL0 0x249b 10635#define regDIG4_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 10636#define regDIG4_HDMI_GENERIC_PACKET_CONTROL6 0x249c 10637#define regDIG4_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 10638#define regDIG4_HDMI_GENERIC_PACKET_CONTROL5 0x249d 10639#define regDIG4_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 10640#define regDIG4_HDMI_GC 0x249e 10641#define regDIG4_HDMI_GC_BASE_IDX 2 10642#define regDIG4_HDMI_GENERIC_PACKET_CONTROL1 0x249f 10643#define regDIG4_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 10644#define regDIG4_HDMI_GENERIC_PACKET_CONTROL2 0x24a0 10645#define regDIG4_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 10646#define regDIG4_HDMI_GENERIC_PACKET_CONTROL3 0x24a1 10647#define regDIG4_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 10648#define regDIG4_HDMI_GENERIC_PACKET_CONTROL4 0x24a2 10649#define regDIG4_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 10650#define regDIG4_HDMI_GENERIC_PACKET_CONTROL7 0x24a3 10651#define regDIG4_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 10652#define regDIG4_HDMI_GENERIC_PACKET_CONTROL8 0x24a4 10653#define regDIG4_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 10654#define regDIG4_HDMI_GENERIC_PACKET_CONTROL9 0x24a5 10655#define regDIG4_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 10656#define regDIG4_HDMI_GENERIC_PACKET_CONTROL10 0x24a6 10657#define regDIG4_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 10658#define regDIG4_HDMI_DB_CONTROL 0x24a7 10659#define regDIG4_HDMI_DB_CONTROL_BASE_IDX 2 10660#define regDIG4_HDMI_ACR_32_0 0x24a8 10661#define regDIG4_HDMI_ACR_32_0_BASE_IDX 2 10662#define regDIG4_HDMI_ACR_32_1 0x24a9 10663#define regDIG4_HDMI_ACR_32_1_BASE_IDX 2 10664#define regDIG4_HDMI_ACR_44_0 0x24aa 10665#define regDIG4_HDMI_ACR_44_0_BASE_IDX 2 10666#define regDIG4_HDMI_ACR_44_1 0x24ab 10667#define regDIG4_HDMI_ACR_44_1_BASE_IDX 2 10668#define regDIG4_HDMI_ACR_48_0 0x24ac 10669#define regDIG4_HDMI_ACR_48_0_BASE_IDX 2 10670#define regDIG4_HDMI_ACR_48_1 0x24ad 10671#define regDIG4_HDMI_ACR_48_1_BASE_IDX 2 10672#define regDIG4_HDMI_ACR_STATUS_0 0x24ae 10673#define regDIG4_HDMI_ACR_STATUS_0_BASE_IDX 2 10674#define regDIG4_HDMI_ACR_STATUS_1 0x24af 10675#define regDIG4_HDMI_ACR_STATUS_1_BASE_IDX 2 10676#define regDIG4_AFMT_CNTL 0x24b0 10677#define regDIG4_AFMT_CNTL_BASE_IDX 2 10678#define regDIG4_DIG_BE_CNTL 0x24b1 10679#define regDIG4_DIG_BE_CNTL_BASE_IDX 2 10680#define regDIG4_DIG_BE_EN_CNTL 0x24b2 10681#define regDIG4_DIG_BE_EN_CNTL_BASE_IDX 2 10682#define regDIG4_TMDS_CNTL 0x24d8 10683#define regDIG4_TMDS_CNTL_BASE_IDX 2 10684#define regDIG4_TMDS_CONTROL_CHAR 0x24d9 10685#define regDIG4_TMDS_CONTROL_CHAR_BASE_IDX 2 10686#define regDIG4_TMDS_CONTROL0_FEEDBACK 0x24da 10687#define regDIG4_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 10688#define regDIG4_TMDS_STEREOSYNC_CTL_SEL 0x24db 10689#define regDIG4_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 10690#define regDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0x24dc 10691#define regDIG4_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 10692#define regDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0x24dd 10693#define regDIG4_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 10694#define regDIG4_TMDS_CTL_BITS 0x24df 10695#define regDIG4_TMDS_CTL_BITS_BASE_IDX 2 10696#define regDIG4_TMDS_DCBALANCER_CONTROL 0x24e0 10697#define regDIG4_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 10698#define regDIG4_TMDS_SYNC_DCBALANCE_CHAR 0x24e1 10699#define regDIG4_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 10700#define regDIG4_TMDS_CTL0_1_GEN_CNTL 0x24e2 10701#define regDIG4_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 10702#define regDIG4_TMDS_CTL2_3_GEN_CNTL 0x24e3 10703#define regDIG4_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 10704#define regDIG4_DIG_VERSION 0x24e5 10705#define regDIG4_DIG_VERSION_BASE_IDX 2 10706#define regDIG4_FORCE_DIG_DISABLE 0x24e6 10707#define regDIG4_FORCE_DIG_DISABLE_BASE_IDX 2 10708 10709 10710// addressBlock: dce_dc_dio_dp4_dispdec 10711// base address: 0x1000 10712#define regDP4_DP_LINK_CNTL 0x2508 10713#define regDP4_DP_LINK_CNTL_BASE_IDX 2 10714#define regDP4_DP_PIXEL_FORMAT 0x2509 10715#define regDP4_DP_PIXEL_FORMAT_BASE_IDX 2 10716#define regDP4_DP_MSA_COLORIMETRY 0x250a 10717#define regDP4_DP_MSA_COLORIMETRY_BASE_IDX 2 10718#define regDP4_DP_CONFIG 0x250b 10719#define regDP4_DP_CONFIG_BASE_IDX 2 10720#define regDP4_DP_VID_STREAM_CNTL 0x250c 10721#define regDP4_DP_VID_STREAM_CNTL_BASE_IDX 2 10722#define regDP4_DP_STEER_FIFO 0x250d 10723#define regDP4_DP_STEER_FIFO_BASE_IDX 2 10724#define regDP4_DP_MSA_MISC 0x250e 10725#define regDP4_DP_MSA_MISC_BASE_IDX 2 10726#define regDP4_DP_DPHY_INTERNAL_CTRL 0x250f 10727#define regDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 10728#define regDP4_DP_VID_TIMING 0x2510 10729#define regDP4_DP_VID_TIMING_BASE_IDX 2 10730#define regDP4_DP_VID_N 0x2511 10731#define regDP4_DP_VID_N_BASE_IDX 2 10732#define regDP4_DP_VID_M 0x2512 10733#define regDP4_DP_VID_M_BASE_IDX 2 10734#define regDP4_DP_LINK_FRAMING_CNTL 0x2513 10735#define regDP4_DP_LINK_FRAMING_CNTL_BASE_IDX 2 10736#define regDP4_DP_HBR2_EYE_PATTERN 0x2514 10737#define regDP4_DP_HBR2_EYE_PATTERN_BASE_IDX 2 10738#define regDP4_DP_VID_MSA_VBID 0x2515 10739#define regDP4_DP_VID_MSA_VBID_BASE_IDX 2 10740#define regDP4_DP_VID_INTERRUPT_CNTL 0x2516 10741#define regDP4_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 10742#define regDP4_DP_DPHY_CNTL 0x2517 10743#define regDP4_DP_DPHY_CNTL_BASE_IDX 2 10744#define regDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x2518 10745#define regDP4_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 10746#define regDP4_DP_DPHY_SYM0 0x2519 10747#define regDP4_DP_DPHY_SYM0_BASE_IDX 2 10748#define regDP4_DP_DPHY_SYM1 0x251a 10749#define regDP4_DP_DPHY_SYM1_BASE_IDX 2 10750#define regDP4_DP_DPHY_SYM2 0x251b 10751#define regDP4_DP_DPHY_SYM2_BASE_IDX 2 10752#define regDP4_DP_DPHY_8B10B_CNTL 0x251c 10753#define regDP4_DP_DPHY_8B10B_CNTL_BASE_IDX 2 10754#define regDP4_DP_DPHY_PRBS_CNTL 0x251d 10755#define regDP4_DP_DPHY_PRBS_CNTL_BASE_IDX 2 10756#define regDP4_DP_DPHY_SCRAM_CNTL 0x251e 10757#define regDP4_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 10758#define regDP4_DP_DPHY_CRC_EN 0x251f 10759#define regDP4_DP_DPHY_CRC_EN_BASE_IDX 2 10760#define regDP4_DP_DPHY_CRC_CNTL 0x2520 10761#define regDP4_DP_DPHY_CRC_CNTL_BASE_IDX 2 10762#define regDP4_DP_DPHY_CRC_RESULT 0x2521 10763#define regDP4_DP_DPHY_CRC_RESULT_BASE_IDX 2 10764#define regDP4_DP_DPHY_CRC_MST_CNTL 0x2522 10765#define regDP4_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 10766#define regDP4_DP_DPHY_CRC_MST_STATUS 0x2523 10767#define regDP4_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 10768#define regDP4_DP_DPHY_FAST_TRAINING 0x2524 10769#define regDP4_DP_DPHY_FAST_TRAINING_BASE_IDX 2 10770#define regDP4_DP_DPHY_FAST_TRAINING_STATUS 0x2525 10771#define regDP4_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 10772#define regDP4_DP_SEC_CNTL 0x252b 10773#define regDP4_DP_SEC_CNTL_BASE_IDX 2 10774#define regDP4_DP_SEC_CNTL1 0x252c 10775#define regDP4_DP_SEC_CNTL1_BASE_IDX 2 10776#define regDP4_DP_SEC_FRAMING1 0x252d 10777#define regDP4_DP_SEC_FRAMING1_BASE_IDX 2 10778#define regDP4_DP_SEC_FRAMING2 0x252e 10779#define regDP4_DP_SEC_FRAMING2_BASE_IDX 2 10780#define regDP4_DP_SEC_FRAMING3 0x252f 10781#define regDP4_DP_SEC_FRAMING3_BASE_IDX 2 10782#define regDP4_DP_SEC_FRAMING4 0x2530 10783#define regDP4_DP_SEC_FRAMING4_BASE_IDX 2 10784#define regDP4_DP_SEC_AUD_N 0x2531 10785#define regDP4_DP_SEC_AUD_N_BASE_IDX 2 10786#define regDP4_DP_SEC_AUD_N_READBACK 0x2532 10787#define regDP4_DP_SEC_AUD_N_READBACK_BASE_IDX 2 10788#define regDP4_DP_SEC_AUD_M 0x2533 10789#define regDP4_DP_SEC_AUD_M_BASE_IDX 2 10790#define regDP4_DP_SEC_AUD_M_READBACK 0x2534 10791#define regDP4_DP_SEC_AUD_M_READBACK_BASE_IDX 2 10792#define regDP4_DP_SEC_TIMESTAMP 0x2535 10793#define regDP4_DP_SEC_TIMESTAMP_BASE_IDX 2 10794#define regDP4_DP_SEC_PACKET_CNTL 0x2536 10795#define regDP4_DP_SEC_PACKET_CNTL_BASE_IDX 2 10796#define regDP4_DP_MSE_RATE_CNTL 0x2537 10797#define regDP4_DP_MSE_RATE_CNTL_BASE_IDX 2 10798#define regDP4_DP_MSE_RATE_UPDATE 0x2539 10799#define regDP4_DP_MSE_RATE_UPDATE_BASE_IDX 2 10800#define regDP4_DP_MSE_SAT0 0x253a 10801#define regDP4_DP_MSE_SAT0_BASE_IDX 2 10802#define regDP4_DP_MSE_SAT1 0x253b 10803#define regDP4_DP_MSE_SAT1_BASE_IDX 2 10804#define regDP4_DP_MSE_SAT2 0x253c 10805#define regDP4_DP_MSE_SAT2_BASE_IDX 2 10806#define regDP4_DP_MSE_SAT_UPDATE 0x253d 10807#define regDP4_DP_MSE_SAT_UPDATE_BASE_IDX 2 10808#define regDP4_DP_MSE_LINK_TIMING 0x253e 10809#define regDP4_DP_MSE_LINK_TIMING_BASE_IDX 2 10810#define regDP4_DP_MSE_MISC_CNTL 0x253f 10811#define regDP4_DP_MSE_MISC_CNTL_BASE_IDX 2 10812#define regDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x2544 10813#define regDP4_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 10814#define regDP4_DP_DPHY_HBR2_PATTERN_CONTROL 0x2545 10815#define regDP4_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 10816#define regDP4_DP_MSE_SAT0_STATUS 0x2547 10817#define regDP4_DP_MSE_SAT0_STATUS_BASE_IDX 2 10818#define regDP4_DP_MSE_SAT1_STATUS 0x2548 10819#define regDP4_DP_MSE_SAT1_STATUS_BASE_IDX 2 10820#define regDP4_DP_MSE_SAT2_STATUS 0x2549 10821#define regDP4_DP_MSE_SAT2_STATUS_BASE_IDX 2 10822#define regDP4_DP_DPIA_SPARE 0x254a 10823#define regDP4_DP_DPIA_SPARE_BASE_IDX 2 10824#define regDP4_DP_MSA_TIMING_PARAM1 0x254c 10825#define regDP4_DP_MSA_TIMING_PARAM1_BASE_IDX 2 10826#define regDP4_DP_MSA_TIMING_PARAM2 0x254d 10827#define regDP4_DP_MSA_TIMING_PARAM2_BASE_IDX 2 10828#define regDP4_DP_MSA_TIMING_PARAM3 0x254e 10829#define regDP4_DP_MSA_TIMING_PARAM3_BASE_IDX 2 10830#define regDP4_DP_MSA_TIMING_PARAM4 0x254f 10831#define regDP4_DP_MSA_TIMING_PARAM4_BASE_IDX 2 10832#define regDP4_DP_MSO_CNTL 0x2550 10833#define regDP4_DP_MSO_CNTL_BASE_IDX 2 10834#define regDP4_DP_MSO_CNTL1 0x2551 10835#define regDP4_DP_MSO_CNTL1_BASE_IDX 2 10836#define regDP4_DP_DSC_CNTL 0x2552 10837#define regDP4_DP_DSC_CNTL_BASE_IDX 2 10838#define regDP4_DP_SEC_CNTL2 0x2553 10839#define regDP4_DP_SEC_CNTL2_BASE_IDX 2 10840#define regDP4_DP_SEC_CNTL3 0x2554 10841#define regDP4_DP_SEC_CNTL3_BASE_IDX 2 10842#define regDP4_DP_SEC_CNTL4 0x2555 10843#define regDP4_DP_SEC_CNTL4_BASE_IDX 2 10844#define regDP4_DP_SEC_CNTL5 0x2556 10845#define regDP4_DP_SEC_CNTL5_BASE_IDX 2 10846#define regDP4_DP_SEC_CNTL6 0x2557 10847#define regDP4_DP_SEC_CNTL6_BASE_IDX 2 10848#define regDP4_DP_SEC_CNTL7 0x2558 10849#define regDP4_DP_SEC_CNTL7_BASE_IDX 2 10850#define regDP4_DP_DB_CNTL 0x2559 10851#define regDP4_DP_DB_CNTL_BASE_IDX 2 10852#define regDP4_DP_MSA_VBID_MISC 0x255a 10853#define regDP4_DP_MSA_VBID_MISC_BASE_IDX 2 10854#define regDP4_DP_SEC_METADATA_TRANSMISSION 0x255b 10855#define regDP4_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 10856#define regDP4_DP_ALPM_CNTL 0x255d 10857#define regDP4_DP_ALPM_CNTL_BASE_IDX 2 10858#define regDP4_DP_GSP8_CNTL 0x255e 10859#define regDP4_DP_GSP8_CNTL_BASE_IDX 2 10860#define regDP4_DP_GSP9_CNTL 0x255f 10861#define regDP4_DP_GSP9_CNTL_BASE_IDX 2 10862#define regDP4_DP_GSP10_CNTL 0x2560 10863#define regDP4_DP_GSP10_CNTL_BASE_IDX 2 10864#define regDP4_DP_GSP11_CNTL 0x2561 10865#define regDP4_DP_GSP11_CNTL_BASE_IDX 2 10866#define regDP4_DP_GSP_EN_DB_STATUS 0x2562 10867#define regDP4_DP_GSP_EN_DB_STATUS_BASE_IDX 2 10868#define regDP4_DP_AUXLESS_ALPM_CNTL1 0x2563 10869#define regDP4_DP_AUXLESS_ALPM_CNTL1_BASE_IDX 2 10870#define regDP4_DP_AUXLESS_ALPM_CNTL2 0x2564 10871#define regDP4_DP_AUXLESS_ALPM_CNTL2_BASE_IDX 2 10872#define regDP4_DP_AUXLESS_ALPM_CNTL3 0x2565 10873#define regDP4_DP_AUXLESS_ALPM_CNTL3_BASE_IDX 2 10874#define regDP4_DP_AUXLESS_ALPM_CNTL4 0x2566 10875#define regDP4_DP_AUXLESS_ALPM_CNTL4_BASE_IDX 2 10876#define regDP4_DP_AUXLESS_ALPM_CNTL5 0x2567 10877#define regDP4_DP_AUXLESS_ALPM_CNTL5_BASE_IDX 2 10878 10879 10880// addressBlock: dce_dc_dcio_dcio_dispdec 10881// base address: 0x0 10882#define regDC_GENERICA 0x2868 10883#define regDC_GENERICA_BASE_IDX 2 10884#define regDC_GENERICB 0x2869 10885#define regDC_GENERICB_BASE_IDX 2 10886#define regDCIO_CLOCK_CNTL 0x286a 10887#define regDCIO_CLOCK_CNTL_BASE_IDX 2 10888#define regDC_REF_CLK_CNTL 0x286b 10889#define regDC_REF_CLK_CNTL_BASE_IDX 2 10890#define regUNIPHYA_LINK_CNTL 0x286d 10891#define regUNIPHYA_LINK_CNTL_BASE_IDX 2 10892#define regUNIPHYA_CHANNEL_XBAR_CNTL 0x286e 10893#define regUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX 2 10894#define regUNIPHYB_LINK_CNTL 0x286f 10895#define regUNIPHYB_LINK_CNTL_BASE_IDX 2 10896#define regUNIPHYB_CHANNEL_XBAR_CNTL 0x2870 10897#define regUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX 2 10898#define regUNIPHYC_LINK_CNTL 0x2871 10899#define regUNIPHYC_LINK_CNTL_BASE_IDX 2 10900#define regUNIPHYC_CHANNEL_XBAR_CNTL 0x2872 10901#define regUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX 2 10902#define regUNIPHYD_CHANNEL_XBAR_CNTL 0x2874 10903#define regUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX 2 10904#define regUNIPHYE_CHANNEL_XBAR_CNTL 0x2876 10905#define regUNIPHYE_CHANNEL_XBAR_CNTL_BASE_IDX 2 10906#define regDCIO_WRCMD_DELAY 0x287e 10907#define regDCIO_WRCMD_DELAY_BASE_IDX 2 10908#define regDC_PINSTRAPS 0x2880 10909#define regDC_PINSTRAPS_BASE_IDX 2 10910#define regDCIO_SPARE 0x2882 10911#define regDCIO_SPARE_BASE_IDX 2 10912#define regINTERCEPT_STATE 0x2884 10913#define regINTERCEPT_STATE_BASE_IDX 2 10914#define regDCIO_PATTERN_GEN_PAT 0x2886 10915#define regDCIO_PATTERN_GEN_PAT_BASE_IDX 2 10916#define regDCIO_PATTERN_GEN_EN 0x2887 10917#define regDCIO_PATTERN_GEN_EN_BASE_IDX 2 10918#define regDCIO_BL_PWM_FRAME_START_DISP_SEL 0x288b 10919#define regDCIO_BL_PWM_FRAME_START_DISP_SEL_BASE_IDX 2 10920#define regDCIO_GSL_GENLK_PAD_CNTL 0x288c 10921#define regDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX 2 10922#define regDCIO_GSL_SWAPLOCK_PAD_CNTL 0x288d 10923#define regDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX 2 10924#define regDCIO_SOFT_RESET 0x289e 10925#define regDCIO_SOFT_RESET_BASE_IDX 2 10926 10927 10928// addressBlock: dce_dc_dcio_dcio_chip_dispdec 10929// base address: 0x0 10930#define regDC_GPIO_GENERIC_MASK 0x28c8 10931#define regDC_GPIO_GENERIC_MASK_BASE_IDX 2 10932#define regDC_GPIO_GENERIC_A 0x28c9 10933#define regDC_GPIO_GENERIC_A_BASE_IDX 2 10934#define regDC_GPIO_GENERIC_EN 0x28ca 10935#define regDC_GPIO_GENERIC_EN_BASE_IDX 2 10936#define regDC_GPIO_GENERIC_Y 0x28cb 10937#define regDC_GPIO_GENERIC_Y_BASE_IDX 2 10938#define regDC_GPIO_DDC1_MASK 0x28d0 10939#define regDC_GPIO_DDC1_MASK_BASE_IDX 2 10940#define regDC_GPIO_DDC1_A 0x28d1 10941#define regDC_GPIO_DDC1_A_BASE_IDX 2 10942#define regDC_GPIO_DDC1_EN 0x28d2 10943#define regDC_GPIO_DDC1_EN_BASE_IDX 2 10944#define regDC_GPIO_DDC1_Y 0x28d3 10945#define regDC_GPIO_DDC1_Y_BASE_IDX 2 10946#define regDC_GPIO_DDC2_MASK 0x28d4 10947#define regDC_GPIO_DDC2_MASK_BASE_IDX 2 10948#define regDC_GPIO_DDC2_A 0x28d5 10949#define regDC_GPIO_DDC2_A_BASE_IDX 2 10950#define regDC_GPIO_DDC2_EN 0x28d6 10951#define regDC_GPIO_DDC2_EN_BASE_IDX 2 10952#define regDC_GPIO_DDC2_Y 0x28d7 10953#define regDC_GPIO_DDC2_Y_BASE_IDX 2 10954#define regDC_GPIO_DDC3_MASK 0x28d8 10955#define regDC_GPIO_DDC3_MASK_BASE_IDX 2 10956#define regDC_GPIO_DDC3_A 0x28d9 10957#define regDC_GPIO_DDC3_A_BASE_IDX 2 10958#define regDC_GPIO_DDC3_EN 0x28da 10959#define regDC_GPIO_DDC3_EN_BASE_IDX 2 10960#define regDC_GPIO_DDC3_Y 0x28db 10961#define regDC_GPIO_DDC3_Y_BASE_IDX 2 10962#define regDC_GPIO_DDC4_MASK 0x28dc 10963#define regDC_GPIO_DDC4_MASK_BASE_IDX 2 10964#define regDC_GPIO_DDC4_A 0x28dd 10965#define regDC_GPIO_DDC4_A_BASE_IDX 2 10966#define regDC_GPIO_DDC4_EN 0x28de 10967#define regDC_GPIO_DDC4_EN_BASE_IDX 2 10968#define regDC_GPIO_DDC4_Y 0x28df 10969#define regDC_GPIO_DDC4_Y_BASE_IDX 2 10970#define regDC_GPIO_DDC5_MASK 0x28e0 10971#define regDC_GPIO_DDC5_MASK_BASE_IDX 2 10972#define regDC_GPIO_DDC5_A 0x28e1 10973#define regDC_GPIO_DDC5_A_BASE_IDX 2 10974#define regDC_GPIO_DDC5_EN 0x28e2 10975#define regDC_GPIO_DDC5_EN_BASE_IDX 2 10976#define regDC_GPIO_DDC5_Y 0x28e3 10977#define regDC_GPIO_DDC5_Y_BASE_IDX 2 10978#define regDC_GPIO_DDCVGA_MASK 0x28e8 10979#define regDC_GPIO_DDCVGA_MASK_BASE_IDX 2 10980#define regDC_GPIO_DDCVGA_A 0x28e9 10981#define regDC_GPIO_DDCVGA_A_BASE_IDX 2 10982#define regDC_GPIO_DDCVGA_EN 0x28ea 10983#define regDC_GPIO_DDCVGA_EN_BASE_IDX 2 10984#define regDC_GPIO_DDCVGA_Y 0x28eb 10985#define regDC_GPIO_DDCVGA_Y_BASE_IDX 2 10986#define regDC_GPIO_GENLK_MASK 0x28f0 10987#define regDC_GPIO_GENLK_MASK_BASE_IDX 2 10988#define regDC_GPIO_GENLK_A 0x28f1 10989#define regDC_GPIO_GENLK_A_BASE_IDX 2 10990#define regDC_GPIO_GENLK_EN 0x28f2 10991#define regDC_GPIO_GENLK_EN_BASE_IDX 2 10992#define regDC_GPIO_GENLK_Y 0x28f3 10993#define regDC_GPIO_GENLK_Y_BASE_IDX 2 10994#define regDC_GPIO_HPD_MASK 0x28f4 10995#define regDC_GPIO_HPD_MASK_BASE_IDX 2 10996#define regDC_GPIO_HPD_A 0x28f5 10997#define regDC_GPIO_HPD_A_BASE_IDX 2 10998#define regDC_GPIO_HPD_EN 0x28f6 10999#define regDC_GPIO_HPD_EN_BASE_IDX 2 11000#define regDC_GPIO_HPD_Y 0x28f7 11001#define regDC_GPIO_HPD_Y_BASE_IDX 2 11002#define regDC_GPIO_PWRSEQ0_EN 0x28fa 11003#define regDC_GPIO_PWRSEQ0_EN_BASE_IDX 2 11004#define regDC_GPIO_PAD_STRENGTH_1 0x28fc 11005#define regDC_GPIO_PAD_STRENGTH_1_BASE_IDX 2 11006#define regDC_GPIO_PAD_STRENGTH_2 0x28fd 11007#define regDC_GPIO_PAD_STRENGTH_2_BASE_IDX 2 11008#define regPHY_AUX_CNTL 0x28ff 11009#define regPHY_AUX_CNTL_BASE_IDX 2 11010#define regDC_GPIO_PWRSEQ1_EN 0x2902 11011#define regDC_GPIO_PWRSEQ1_EN_BASE_IDX 2 11012#define regDC_GPIO_TX12_EN 0x2915 11013#define regDC_GPIO_TX12_EN_BASE_IDX 2 11014#define regDC_GPIO_AUX_CTRL_0 0x2916 11015#define regDC_GPIO_AUX_CTRL_0_BASE_IDX 2 11016#define regDC_GPIO_AUX_CTRL_1 0x2917 11017#define regDC_GPIO_AUX_CTRL_1_BASE_IDX 2 11018#define regDC_GPIO_AUX_CTRL_2 0x2918 11019#define regDC_GPIO_AUX_CTRL_2_BASE_IDX 2 11020#define regDC_GPIO_RXEN 0x2919 11021#define regDC_GPIO_RXEN_BASE_IDX 2 11022#define regDC_GPIO_PULLUPEN 0x291a 11023#define regDC_GPIO_PULLUPEN_BASE_IDX 2 11024#define regDC_GPIO_AUX_CTRL_3 0x291b 11025#define regDC_GPIO_AUX_CTRL_3_BASE_IDX 2 11026#define regDC_GPIO_AUX_CTRL_4 0x291c 11027#define regDC_GPIO_AUX_CTRL_4_BASE_IDX 2 11028#define regDC_GPIO_AUX_CTRL_5 0x291d 11029#define regDC_GPIO_AUX_CTRL_5_BASE_IDX 2 11030#define regAUXI2C_PAD_ALL_PWR_OK 0x291e 11031#define regAUXI2C_PAD_ALL_PWR_OK_BASE_IDX 2 11032 11033 11034// addressBlock: dce_dc_dcio_dcio_uniphy1_dispdec 11035// base address: 0x360 11036#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0 0x2a00 11037#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 11038#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1 0x2a01 11039#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 11040#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2 0x2a02 11041#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 11042#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3 0x2a03 11043#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 11044#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4 0x2a04 11045#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 11046#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5 0x2a05 11047#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 11048#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6 0x2a06 11049#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 11050#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7 0x2a07 11051#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 11052#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8 0x2a08 11053#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 11054#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9 0x2a09 11055#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 11056#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10 0x2a0a 11057#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 11058#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11 0x2a0b 11059#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 11060#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12 0x2a0c 11061#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 11062#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13 0x2a0d 11063#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 11064#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14 0x2a0e 11065#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 11066#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15 0x2a0f 11067#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 11068#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16 0x2a10 11069#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 11070#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17 0x2a11 11071#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 11072#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18 0x2a12 11073#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 11074#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19 0x2a13 11075#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 11076#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20 0x2a14 11077#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 11078#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21 0x2a15 11079#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 11080#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22 0x2a16 11081#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 11082#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23 0x2a17 11083#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 11084#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24 0x2a18 11085#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 11086#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25 0x2a19 11087#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 11088#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26 0x2a1a 11089#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 11090#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27 0x2a1b 11091#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 11092#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28 0x2a1c 11093#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 11094#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29 0x2a1d 11095#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 11096#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30 0x2a1e 11097#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 11098#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31 0x2a1f 11099#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 11100#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32 0x2a20 11101#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 11102#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33 0x2a21 11103#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 11104#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34 0x2a22 11105#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 11106#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35 0x2a23 11107#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 11108#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36 0x2a24 11109#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 11110#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37 0x2a25 11111#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 11112#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38 0x2a26 11113#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 11114#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39 0x2a27 11115#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 11116#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40 0x2a28 11117#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 11118#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41 0x2a29 11119#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 11120#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42 0x2a2a 11121#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 11122#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43 0x2a2b 11123#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 11124#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44 0x2a2c 11125#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 11126#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45 0x2a2d 11127#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 11128#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46 0x2a2e 11129#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 11130#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47 0x2a2f 11131#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 11132#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48 0x2a30 11133#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 11134#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49 0x2a31 11135#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 11136#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50 0x2a32 11137#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 11138#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51 0x2a33 11139#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 11140#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52 0x2a34 11141#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 11142#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53 0x2a35 11143#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 11144#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54 0x2a36 11145#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 11146#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55 0x2a37 11147#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 11148#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56 0x2a38 11149#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 11150#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57 0x2a39 11151#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 11152 11153 11154// addressBlock: dce_dc_dcio_dcio_uniphy2_dispdec 11155// base address: 0x6c0 11156#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0 0x2ad8 11157#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 11158#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1 0x2ad9 11159#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 11160#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2 0x2ada 11161#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 11162#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3 0x2adb 11163#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 11164#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4 0x2adc 11165#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 11166#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5 0x2add 11167#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 11168#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6 0x2ade 11169#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 11170#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7 0x2adf 11171#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 11172#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8 0x2ae0 11173#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 11174#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9 0x2ae1 11175#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 11176#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10 0x2ae2 11177#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 11178#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11 0x2ae3 11179#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 11180#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12 0x2ae4 11181#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 11182#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13 0x2ae5 11183#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 11184#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14 0x2ae6 11185#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 11186#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15 0x2ae7 11187#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 11188#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16 0x2ae8 11189#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 11190#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17 0x2ae9 11191#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 11192#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18 0x2aea 11193#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 11194#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19 0x2aeb 11195#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 11196#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20 0x2aec 11197#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 11198#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21 0x2aed 11199#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 11200#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22 0x2aee 11201#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 11202#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23 0x2aef 11203#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 11204#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24 0x2af0 11205#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 11206#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25 0x2af1 11207#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 11208#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26 0x2af2 11209#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 11210#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27 0x2af3 11211#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 11212#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28 0x2af4 11213#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 11214#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29 0x2af5 11215#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 11216#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30 0x2af6 11217#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 11218#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31 0x2af7 11219#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 11220#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32 0x2af8 11221#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 11222#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33 0x2af9 11223#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 11224#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34 0x2afa 11225#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 11226#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35 0x2afb 11227#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 11228#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36 0x2afc 11229#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 11230#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37 0x2afd 11231#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 11232#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38 0x2afe 11233#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 11234#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39 0x2aff 11235#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 11236#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40 0x2b00 11237#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 11238#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41 0x2b01 11239#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 11240#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42 0x2b02 11241#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 11242#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43 0x2b03 11243#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 11244#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44 0x2b04 11245#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 11246#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45 0x2b05 11247#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 11248#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46 0x2b06 11249#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 11250#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47 0x2b07 11251#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 11252#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48 0x2b08 11253#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 11254#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49 0x2b09 11255#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 11256#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50 0x2b0a 11257#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 11258#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51 0x2b0b 11259#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 11260#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52 0x2b0c 11261#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 11262#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53 0x2b0d 11263#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 11264#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54 0x2b0e 11265#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 11266#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55 0x2b0f 11267#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 11268#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56 0x2b10 11269#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 11270#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57 0x2b11 11271#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 11272 11273 11274// addressBlock: dce_dc_dcio_dcio_uniphy3_dispdec 11275// base address: 0xa20 11276#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0 0x2bb0 11277#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 11278#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1 0x2bb1 11279#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 11280#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2 0x2bb2 11281#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 11282#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3 0x2bb3 11283#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 11284#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4 0x2bb4 11285#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 11286#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5 0x2bb5 11287#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 11288#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6 0x2bb6 11289#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 11290#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7 0x2bb7 11291#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 11292#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8 0x2bb8 11293#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 11294#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9 0x2bb9 11295#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 11296#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10 0x2bba 11297#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 11298#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11 0x2bbb 11299#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 11300#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12 0x2bbc 11301#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 11302#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13 0x2bbd 11303#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 11304#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14 0x2bbe 11305#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 11306#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15 0x2bbf 11307#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 11308#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16 0x2bc0 11309#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 11310#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17 0x2bc1 11311#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 11312#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18 0x2bc2 11313#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 11314#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19 0x2bc3 11315#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 11316#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20 0x2bc4 11317#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 11318#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21 0x2bc5 11319#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 11320#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22 0x2bc6 11321#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 11322#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23 0x2bc7 11323#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 11324#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24 0x2bc8 11325#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 11326#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25 0x2bc9 11327#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 11328#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26 0x2bca 11329#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 11330#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27 0x2bcb 11331#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 11332#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28 0x2bcc 11333#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 11334#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29 0x2bcd 11335#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 11336#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30 0x2bce 11337#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 11338#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31 0x2bcf 11339#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 11340#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32 0x2bd0 11341#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 11342#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33 0x2bd1 11343#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 11344#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34 0x2bd2 11345#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 11346#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35 0x2bd3 11347#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 11348#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36 0x2bd4 11349#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 11350#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37 0x2bd5 11351#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 11352#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38 0x2bd6 11353#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 11354#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39 0x2bd7 11355#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 11356#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40 0x2bd8 11357#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 11358#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41 0x2bd9 11359#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 11360#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42 0x2bda 11361#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 11362#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43 0x2bdb 11363#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 11364#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44 0x2bdc 11365#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 11366#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45 0x2bdd 11367#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 11368#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46 0x2bde 11369#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 11370#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47 0x2bdf 11371#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 11372#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48 0x2be0 11373#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 11374#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49 0x2be1 11375#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 11376#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50 0x2be2 11377#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 11378#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51 0x2be3 11379#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 11380#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52 0x2be4 11381#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 11382#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53 0x2be5 11383#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 11384#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54 0x2be6 11385#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 11386#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55 0x2be7 11387#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 11388#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56 0x2be8 11389#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 11390#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57 0x2be9 11391#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 11392 11393 11394// addressBlock: dce_dc_dcio_dcio_uniphy4_dispdec 11395// base address: 0xd80 11396#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0 0x2c88 11397#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 11398#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1 0x2c89 11399#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 11400#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2 0x2c8a 11401#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 11402#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3 0x2c8b 11403#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 11404#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4 0x2c8c 11405#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 11406#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5 0x2c8d 11407#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 11408#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6 0x2c8e 11409#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 11410#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7 0x2c8f 11411#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 11412#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8 0x2c90 11413#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 11414#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9 0x2c91 11415#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 11416#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10 0x2c92 11417#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 11418#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11 0x2c93 11419#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 11420#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12 0x2c94 11421#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 11422#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13 0x2c95 11423#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 11424#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14 0x2c96 11425#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 11426#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15 0x2c97 11427#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 11428#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16 0x2c98 11429#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 11430#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17 0x2c99 11431#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 11432#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18 0x2c9a 11433#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 11434#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19 0x2c9b 11435#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 11436#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20 0x2c9c 11437#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 11438#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21 0x2c9d 11439#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 11440#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22 0x2c9e 11441#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 11442#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23 0x2c9f 11443#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 11444#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24 0x2ca0 11445#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 11446#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25 0x2ca1 11447#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 11448#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26 0x2ca2 11449#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 11450#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27 0x2ca3 11451#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 11452#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28 0x2ca4 11453#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 11454#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29 0x2ca5 11455#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 11456#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30 0x2ca6 11457#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 11458#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31 0x2ca7 11459#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 11460#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32 0x2ca8 11461#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 11462#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33 0x2ca9 11463#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 11464#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34 0x2caa 11465#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 11466#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35 0x2cab 11467#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 11468#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36 0x2cac 11469#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 11470#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37 0x2cad 11471#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 11472#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38 0x2cae 11473#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 11474#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39 0x2caf 11475#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 11476#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40 0x2cb0 11477#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 11478#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41 0x2cb1 11479#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 11480#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42 0x2cb2 11481#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 11482#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43 0x2cb3 11483#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 11484#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44 0x2cb4 11485#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 11486#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45 0x2cb5 11487#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 11488#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46 0x2cb6 11489#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 11490#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47 0x2cb7 11491#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 11492#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48 0x2cb8 11493#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 11494#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49 0x2cb9 11495#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 11496#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50 0x2cba 11497#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 11498#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51 0x2cbb 11499#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 11500#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52 0x2cbc 11501#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 11502#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53 0x2cbd 11503#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 11504#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54 0x2cbe 11505#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 11506#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55 0x2cbf 11507#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 11508#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56 0x2cc0 11509#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 11510#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57 0x2cc1 11511#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 11512 11513 11514// addressBlock: dce_dc_pwrseq0_dispdec_pwrseq_dispdec 11515// base address: 0x0 11516#define regPWRSEQ0_DC_GPIO_PWRSEQ_EN 0x2f10 11517#define regPWRSEQ0_DC_GPIO_PWRSEQ_EN_BASE_IDX 2 11518#define regPWRSEQ0_DC_GPIO_PWRSEQ_CTRL 0x2f11 11519#define regPWRSEQ0_DC_GPIO_PWRSEQ_CTRL_BASE_IDX 2 11520#define regPWRSEQ0_DC_GPIO_PWRSEQ_MASK 0x2f12 11521#define regPWRSEQ0_DC_GPIO_PWRSEQ_MASK_BASE_IDX 2 11522#define regPWRSEQ0_DC_GPIO_PWRSEQ_A_Y 0x2f13 11523#define regPWRSEQ0_DC_GPIO_PWRSEQ_A_Y_BASE_IDX 2 11524#define regPWRSEQ0_PANEL_PWRSEQ_CNTL 0x2f14 11525#define regPWRSEQ0_PANEL_PWRSEQ_CNTL_BASE_IDX 2 11526#define regPWRSEQ0_PANEL_PWRSEQ_STATE 0x2f15 11527#define regPWRSEQ0_PANEL_PWRSEQ_STATE_BASE_IDX 2 11528#define regPWRSEQ0_PANEL_PWRSEQ_DELAY1 0x2f16 11529#define regPWRSEQ0_PANEL_PWRSEQ_DELAY1_BASE_IDX 2 11530#define regPWRSEQ0_PANEL_PWRSEQ_DELAY2 0x2f17 11531#define regPWRSEQ0_PANEL_PWRSEQ_DELAY2_BASE_IDX 2 11532#define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV1 0x2f18 11533#define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV1_BASE_IDX 2 11534#define regPWRSEQ0_BL_PWM_CNTL 0x2f19 11535#define regPWRSEQ0_BL_PWM_CNTL_BASE_IDX 2 11536#define regPWRSEQ0_BL_PWM_CNTL2 0x2f1a 11537#define regPWRSEQ0_BL_PWM_CNTL2_BASE_IDX 2 11538#define regPWRSEQ0_BL_PWM_PERIOD_CNTL 0x2f1b 11539#define regPWRSEQ0_BL_PWM_PERIOD_CNTL_BASE_IDX 2 11540#define regPWRSEQ0_BL_PWM_GRP1_REG_LOCK 0x2f1c 11541#define regPWRSEQ0_BL_PWM_GRP1_REG_LOCK_BASE_IDX 2 11542#define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV2 0x2f1d 11543#define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV2_BASE_IDX 2 11544#define regPWRSEQ0_PWRSEQ_SPARE 0x2f21 11545#define regPWRSEQ0_PWRSEQ_SPARE_BASE_IDX 2 11546 11547 11548// addressBlock: dce_dc_pwrseq1_dispdec_pwrseq_dispdec 11549// base address: 0x1b0 11550#define regPWRSEQ1_DC_GPIO_PWRSEQ_EN 0x2f7c 11551#define regPWRSEQ1_DC_GPIO_PWRSEQ_EN_BASE_IDX 2 11552#define regPWRSEQ1_DC_GPIO_PWRSEQ_CTRL 0x2f7d 11553#define regPWRSEQ1_DC_GPIO_PWRSEQ_CTRL_BASE_IDX 2 11554#define regPWRSEQ1_DC_GPIO_PWRSEQ_MASK 0x2f7e 11555#define regPWRSEQ1_DC_GPIO_PWRSEQ_MASK_BASE_IDX 2 11556#define regPWRSEQ1_DC_GPIO_PWRSEQ_A_Y 0x2f7f 11557#define regPWRSEQ1_DC_GPIO_PWRSEQ_A_Y_BASE_IDX 2 11558#define regPWRSEQ1_PANEL_PWRSEQ_CNTL 0x2f80 11559#define regPWRSEQ1_PANEL_PWRSEQ_CNTL_BASE_IDX 2 11560#define regPWRSEQ1_PANEL_PWRSEQ_STATE 0x2f81 11561#define regPWRSEQ1_PANEL_PWRSEQ_STATE_BASE_IDX 2 11562#define regPWRSEQ1_PANEL_PWRSEQ_DELAY1 0x2f82 11563#define regPWRSEQ1_PANEL_PWRSEQ_DELAY1_BASE_IDX 2 11564#define regPWRSEQ1_PANEL_PWRSEQ_DELAY2 0x2f83 11565#define regPWRSEQ1_PANEL_PWRSEQ_DELAY2_BASE_IDX 2 11566#define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV1 0x2f84 11567#define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV1_BASE_IDX 2 11568#define regPWRSEQ1_BL_PWM_CNTL 0x2f85 11569#define regPWRSEQ1_BL_PWM_CNTL_BASE_IDX 2 11570#define regPWRSEQ1_BL_PWM_CNTL2 0x2f86 11571#define regPWRSEQ1_BL_PWM_CNTL2_BASE_IDX 2 11572#define regPWRSEQ1_BL_PWM_PERIOD_CNTL 0x2f87 11573#define regPWRSEQ1_BL_PWM_PERIOD_CNTL_BASE_IDX 2 11574#define regPWRSEQ1_BL_PWM_GRP1_REG_LOCK 0x2f88 11575#define regPWRSEQ1_BL_PWM_GRP1_REG_LOCK_BASE_IDX 2 11576#define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV2 0x2f89 11577#define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV2_BASE_IDX 2 11578#define regPWRSEQ1_PWRSEQ_SPARE 0x2f8d 11579#define regPWRSEQ1_PWRSEQ_SPARE_BASE_IDX 2 11580 11581 11582// addressBlock: dce_dc_dsc0_dispdec_dsc_top_dispdec 11583// base address: 0x0 11584#define regDSC_TOP0_DSC_TOP_CONTROL 0x3000 11585#define regDSC_TOP0_DSC_TOP_CONTROL_BASE_IDX 2 11586#define regDSC_TOP0_DSC_DEBUG_CONTROL 0x3001 11587#define regDSC_TOP0_DSC_DEBUG_CONTROL_BASE_IDX 2 11588 11589 11590// addressBlock: dce_dc_dsc0_dispdec_dsccif_dispdec 11591// base address: 0x0 11592#define regDSCCIF0_DSCCIF_CONFIG0 0x3005 11593#define regDSCCIF0_DSCCIF_CONFIG0_BASE_IDX 2 11594#define regDSCCIF0_DSCCIF_CONFIG1 0x3006 11595#define regDSCCIF0_DSCCIF_CONFIG1_BASE_IDX 2 11596 11597 11598// addressBlock: dce_dc_dsc0_dispdec_dscc_dispdec 11599// base address: 0x0 11600#define regDSCC0_DSCC_CONFIG0 0x300a 11601#define regDSCC0_DSCC_CONFIG0_BASE_IDX 2 11602#define regDSCC0_DSCC_CONFIG1 0x300b 11603#define regDSCC0_DSCC_CONFIG1_BASE_IDX 2 11604#define regDSCC0_DSCC_STATUS 0x300c 11605#define regDSCC0_DSCC_STATUS_BASE_IDX 2 11606#define regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS 0x300d 11607#define regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 11608#define regDSCC0_DSCC_PPS_CONFIG0 0x300e 11609#define regDSCC0_DSCC_PPS_CONFIG0_BASE_IDX 2 11610#define regDSCC0_DSCC_PPS_CONFIG1 0x300f 11611#define regDSCC0_DSCC_PPS_CONFIG1_BASE_IDX 2 11612#define regDSCC0_DSCC_PPS_CONFIG2 0x3010 11613#define regDSCC0_DSCC_PPS_CONFIG2_BASE_IDX 2 11614#define regDSCC0_DSCC_PPS_CONFIG3 0x3011 11615#define regDSCC0_DSCC_PPS_CONFIG3_BASE_IDX 2 11616#define regDSCC0_DSCC_PPS_CONFIG4 0x3012 11617#define regDSCC0_DSCC_PPS_CONFIG4_BASE_IDX 2 11618#define regDSCC0_DSCC_PPS_CONFIG5 0x3013 11619#define regDSCC0_DSCC_PPS_CONFIG5_BASE_IDX 2 11620#define regDSCC0_DSCC_PPS_CONFIG6 0x3014 11621#define regDSCC0_DSCC_PPS_CONFIG6_BASE_IDX 2 11622#define regDSCC0_DSCC_PPS_CONFIG7 0x3015 11623#define regDSCC0_DSCC_PPS_CONFIG7_BASE_IDX 2 11624#define regDSCC0_DSCC_PPS_CONFIG8 0x3016 11625#define regDSCC0_DSCC_PPS_CONFIG8_BASE_IDX 2 11626#define regDSCC0_DSCC_PPS_CONFIG9 0x3017 11627#define regDSCC0_DSCC_PPS_CONFIG9_BASE_IDX 2 11628#define regDSCC0_DSCC_PPS_CONFIG10 0x3018 11629#define regDSCC0_DSCC_PPS_CONFIG10_BASE_IDX 2 11630#define regDSCC0_DSCC_PPS_CONFIG11 0x3019 11631#define regDSCC0_DSCC_PPS_CONFIG11_BASE_IDX 2 11632#define regDSCC0_DSCC_PPS_CONFIG12 0x301a 11633#define regDSCC0_DSCC_PPS_CONFIG12_BASE_IDX 2 11634#define regDSCC0_DSCC_PPS_CONFIG13 0x301b 11635#define regDSCC0_DSCC_PPS_CONFIG13_BASE_IDX 2 11636#define regDSCC0_DSCC_PPS_CONFIG14 0x301c 11637#define regDSCC0_DSCC_PPS_CONFIG14_BASE_IDX 2 11638#define regDSCC0_DSCC_PPS_CONFIG15 0x301d 11639#define regDSCC0_DSCC_PPS_CONFIG15_BASE_IDX 2 11640#define regDSCC0_DSCC_PPS_CONFIG16 0x301e 11641#define regDSCC0_DSCC_PPS_CONFIG16_BASE_IDX 2 11642#define regDSCC0_DSCC_PPS_CONFIG17 0x301f 11643#define regDSCC0_DSCC_PPS_CONFIG17_BASE_IDX 2 11644#define regDSCC0_DSCC_PPS_CONFIG18 0x3020 11645#define regDSCC0_DSCC_PPS_CONFIG18_BASE_IDX 2 11646#define regDSCC0_DSCC_PPS_CONFIG19 0x3021 11647#define regDSCC0_DSCC_PPS_CONFIG19_BASE_IDX 2 11648#define regDSCC0_DSCC_PPS_CONFIG20 0x3022 11649#define regDSCC0_DSCC_PPS_CONFIG20_BASE_IDX 2 11650#define regDSCC0_DSCC_PPS_CONFIG21 0x3023 11651#define regDSCC0_DSCC_PPS_CONFIG21_BASE_IDX 2 11652#define regDSCC0_DSCC_PPS_CONFIG22 0x3024 11653#define regDSCC0_DSCC_PPS_CONFIG22_BASE_IDX 2 11654#define regDSCC0_DSCC_MEM_POWER_CONTROL 0x3025 11655#define regDSCC0_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 11656#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER 0x3026 11657#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 11658#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER 0x3027 11659#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 11660#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER 0x3028 11661#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 11662#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER 0x3029 11663#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 11664#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER 0x302a 11665#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 11666#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER 0x302b 11667#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 11668#define regDSCC0_DSCC_MAX_ABS_ERROR0 0x302c 11669#define regDSCC0_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 11670#define regDSCC0_DSCC_MAX_ABS_ERROR1 0x302d 11671#define regDSCC0_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 11672#define regDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x302e 11673#define regDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 11674#define regDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x302f 11675#define regDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 11676#define regDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x3030 11677#define regDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 11678#define regDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x3031 11679#define regDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 11680#define regDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x3032 11681#define regDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 11682#define regDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x3033 11683#define regDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 11684#define regDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3034 11685#define regDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 11686#define regDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3035 11687#define regDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 11688#define regDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE 0x303a 11689#define regDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 11690 11691 11692// addressBlock: dce_dc_dsc0_dispdec_dsc_dcperfmon_dc_perfmon_dispdec 11693// base address: 0xc140 11694#define regDC_PERFMON17_PERFCOUNTER_CNTL 0x3050 11695#define regDC_PERFMON17_PERFCOUNTER_CNTL_BASE_IDX 2 11696#define regDC_PERFMON17_PERFCOUNTER_CNTL2 0x3051 11697#define regDC_PERFMON17_PERFCOUNTER_CNTL2_BASE_IDX 2 11698#define regDC_PERFMON17_PERFCOUNTER_STATE 0x3052 11699#define regDC_PERFMON17_PERFCOUNTER_STATE_BASE_IDX 2 11700#define regDC_PERFMON17_PERFMON_CNTL 0x3053 11701#define regDC_PERFMON17_PERFMON_CNTL_BASE_IDX 2 11702#define regDC_PERFMON17_PERFMON_CNTL2 0x3054 11703#define regDC_PERFMON17_PERFMON_CNTL2_BASE_IDX 2 11704#define regDC_PERFMON17_PERFMON_CVALUE_INT_MISC 0x3055 11705#define regDC_PERFMON17_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 11706#define regDC_PERFMON17_PERFMON_CVALUE_LOW 0x3056 11707#define regDC_PERFMON17_PERFMON_CVALUE_LOW_BASE_IDX 2 11708#define regDC_PERFMON17_PERFMON_HI 0x3057 11709#define regDC_PERFMON17_PERFMON_HI_BASE_IDX 2 11710#define regDC_PERFMON17_PERFMON_LOW 0x3058 11711#define regDC_PERFMON17_PERFMON_LOW_BASE_IDX 2 11712 11713 11714// addressBlock: dce_dc_dsc1_dispdec_dsc_top_dispdec 11715// base address: 0x170 11716#define regDSC_TOP1_DSC_TOP_CONTROL 0x305c 11717#define regDSC_TOP1_DSC_TOP_CONTROL_BASE_IDX 2 11718#define regDSC_TOP1_DSC_DEBUG_CONTROL 0x305d 11719#define regDSC_TOP1_DSC_DEBUG_CONTROL_BASE_IDX 2 11720 11721 11722// addressBlock: dce_dc_dsc1_dispdec_dsccif_dispdec 11723// base address: 0x170 11724#define regDSCCIF1_DSCCIF_CONFIG0 0x3061 11725#define regDSCCIF1_DSCCIF_CONFIG0_BASE_IDX 2 11726#define regDSCCIF1_DSCCIF_CONFIG1 0x3062 11727#define regDSCCIF1_DSCCIF_CONFIG1_BASE_IDX 2 11728 11729 11730// addressBlock: dce_dc_dsc1_dispdec_dscc_dispdec 11731// base address: 0x170 11732#define regDSCC1_DSCC_CONFIG0 0x3066 11733#define regDSCC1_DSCC_CONFIG0_BASE_IDX 2 11734#define regDSCC1_DSCC_CONFIG1 0x3067 11735#define regDSCC1_DSCC_CONFIG1_BASE_IDX 2 11736#define regDSCC1_DSCC_STATUS 0x3068 11737#define regDSCC1_DSCC_STATUS_BASE_IDX 2 11738#define regDSCC1_DSCC_INTERRUPT_CONTROL_STATUS 0x3069 11739#define regDSCC1_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 11740#define regDSCC1_DSCC_PPS_CONFIG0 0x306a 11741#define regDSCC1_DSCC_PPS_CONFIG0_BASE_IDX 2 11742#define regDSCC1_DSCC_PPS_CONFIG1 0x306b 11743#define regDSCC1_DSCC_PPS_CONFIG1_BASE_IDX 2 11744#define regDSCC1_DSCC_PPS_CONFIG2 0x306c 11745#define regDSCC1_DSCC_PPS_CONFIG2_BASE_IDX 2 11746#define regDSCC1_DSCC_PPS_CONFIG3 0x306d 11747#define regDSCC1_DSCC_PPS_CONFIG3_BASE_IDX 2 11748#define regDSCC1_DSCC_PPS_CONFIG4 0x306e 11749#define regDSCC1_DSCC_PPS_CONFIG4_BASE_IDX 2 11750#define regDSCC1_DSCC_PPS_CONFIG5 0x306f 11751#define regDSCC1_DSCC_PPS_CONFIG5_BASE_IDX 2 11752#define regDSCC1_DSCC_PPS_CONFIG6 0x3070 11753#define regDSCC1_DSCC_PPS_CONFIG6_BASE_IDX 2 11754#define regDSCC1_DSCC_PPS_CONFIG7 0x3071 11755#define regDSCC1_DSCC_PPS_CONFIG7_BASE_IDX 2 11756#define regDSCC1_DSCC_PPS_CONFIG8 0x3072 11757#define regDSCC1_DSCC_PPS_CONFIG8_BASE_IDX 2 11758#define regDSCC1_DSCC_PPS_CONFIG9 0x3073 11759#define regDSCC1_DSCC_PPS_CONFIG9_BASE_IDX 2 11760#define regDSCC1_DSCC_PPS_CONFIG10 0x3074 11761#define regDSCC1_DSCC_PPS_CONFIG10_BASE_IDX 2 11762#define regDSCC1_DSCC_PPS_CONFIG11 0x3075 11763#define regDSCC1_DSCC_PPS_CONFIG11_BASE_IDX 2 11764#define regDSCC1_DSCC_PPS_CONFIG12 0x3076 11765#define regDSCC1_DSCC_PPS_CONFIG12_BASE_IDX 2 11766#define regDSCC1_DSCC_PPS_CONFIG13 0x3077 11767#define regDSCC1_DSCC_PPS_CONFIG13_BASE_IDX 2 11768#define regDSCC1_DSCC_PPS_CONFIG14 0x3078 11769#define regDSCC1_DSCC_PPS_CONFIG14_BASE_IDX 2 11770#define regDSCC1_DSCC_PPS_CONFIG15 0x3079 11771#define regDSCC1_DSCC_PPS_CONFIG15_BASE_IDX 2 11772#define regDSCC1_DSCC_PPS_CONFIG16 0x307a 11773#define regDSCC1_DSCC_PPS_CONFIG16_BASE_IDX 2 11774#define regDSCC1_DSCC_PPS_CONFIG17 0x307b 11775#define regDSCC1_DSCC_PPS_CONFIG17_BASE_IDX 2 11776#define regDSCC1_DSCC_PPS_CONFIG18 0x307c 11777#define regDSCC1_DSCC_PPS_CONFIG18_BASE_IDX 2 11778#define regDSCC1_DSCC_PPS_CONFIG19 0x307d 11779#define regDSCC1_DSCC_PPS_CONFIG19_BASE_IDX 2 11780#define regDSCC1_DSCC_PPS_CONFIG20 0x307e 11781#define regDSCC1_DSCC_PPS_CONFIG20_BASE_IDX 2 11782#define regDSCC1_DSCC_PPS_CONFIG21 0x307f 11783#define regDSCC1_DSCC_PPS_CONFIG21_BASE_IDX 2 11784#define regDSCC1_DSCC_PPS_CONFIG22 0x3080 11785#define regDSCC1_DSCC_PPS_CONFIG22_BASE_IDX 2 11786#define regDSCC1_DSCC_MEM_POWER_CONTROL 0x3081 11787#define regDSCC1_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 11788#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER 0x3082 11789#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 11790#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER 0x3083 11791#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 11792#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER 0x3084 11793#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 11794#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER 0x3085 11795#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 11796#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER 0x3086 11797#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 11798#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER 0x3087 11799#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 11800#define regDSCC1_DSCC_MAX_ABS_ERROR0 0x3088 11801#define regDSCC1_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 11802#define regDSCC1_DSCC_MAX_ABS_ERROR1 0x3089 11803#define regDSCC1_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 11804#define regDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x308a 11805#define regDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 11806#define regDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x308b 11807#define regDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 11808#define regDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x308c 11809#define regDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 11810#define regDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x308d 11811#define regDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 11812#define regDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x308e 11813#define regDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 11814#define regDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x308f 11815#define regDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 11816#define regDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3090 11817#define regDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 11818#define regDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3091 11819#define regDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 11820#define regDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE 0x3096 11821#define regDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 11822 11823 11824// addressBlock: dce_dc_dsc1_dispdec_dsc_dcperfmon_dc_perfmon_dispdec 11825// base address: 0xc2b0 11826#define regDC_PERFMON18_PERFCOUNTER_CNTL 0x30ac 11827#define regDC_PERFMON18_PERFCOUNTER_CNTL_BASE_IDX 2 11828#define regDC_PERFMON18_PERFCOUNTER_CNTL2 0x30ad 11829#define regDC_PERFMON18_PERFCOUNTER_CNTL2_BASE_IDX 2 11830#define regDC_PERFMON18_PERFCOUNTER_STATE 0x30ae 11831#define regDC_PERFMON18_PERFCOUNTER_STATE_BASE_IDX 2 11832#define regDC_PERFMON18_PERFMON_CNTL 0x30af 11833#define regDC_PERFMON18_PERFMON_CNTL_BASE_IDX 2 11834#define regDC_PERFMON18_PERFMON_CNTL2 0x30b0 11835#define regDC_PERFMON18_PERFMON_CNTL2_BASE_IDX 2 11836#define regDC_PERFMON18_PERFMON_CVALUE_INT_MISC 0x30b1 11837#define regDC_PERFMON18_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 11838#define regDC_PERFMON18_PERFMON_CVALUE_LOW 0x30b2 11839#define regDC_PERFMON18_PERFMON_CVALUE_LOW_BASE_IDX 2 11840#define regDC_PERFMON18_PERFMON_HI 0x30b3 11841#define regDC_PERFMON18_PERFMON_HI_BASE_IDX 2 11842#define regDC_PERFMON18_PERFMON_LOW 0x30b4 11843#define regDC_PERFMON18_PERFMON_LOW_BASE_IDX 2 11844 11845 11846// addressBlock: dce_dc_dsc2_dispdec_dsc_top_dispdec 11847// base address: 0x2e0 11848#define regDSC_TOP2_DSC_TOP_CONTROL 0x30b8 11849#define regDSC_TOP2_DSC_TOP_CONTROL_BASE_IDX 2 11850#define regDSC_TOP2_DSC_DEBUG_CONTROL 0x30b9 11851#define regDSC_TOP2_DSC_DEBUG_CONTROL_BASE_IDX 2 11852 11853 11854// addressBlock: dce_dc_dsc2_dispdec_dsccif_dispdec 11855// base address: 0x2e0 11856#define regDSCCIF2_DSCCIF_CONFIG0 0x30bd 11857#define regDSCCIF2_DSCCIF_CONFIG0_BASE_IDX 2 11858#define regDSCCIF2_DSCCIF_CONFIG1 0x30be 11859#define regDSCCIF2_DSCCIF_CONFIG1_BASE_IDX 2 11860 11861 11862// addressBlock: dce_dc_dsc2_dispdec_dscc_dispdec 11863// base address: 0x2e0 11864#define regDSCC2_DSCC_CONFIG0 0x30c2 11865#define regDSCC2_DSCC_CONFIG0_BASE_IDX 2 11866#define regDSCC2_DSCC_CONFIG1 0x30c3 11867#define regDSCC2_DSCC_CONFIG1_BASE_IDX 2 11868#define regDSCC2_DSCC_STATUS 0x30c4 11869#define regDSCC2_DSCC_STATUS_BASE_IDX 2 11870#define regDSCC2_DSCC_INTERRUPT_CONTROL_STATUS 0x30c5 11871#define regDSCC2_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 11872#define regDSCC2_DSCC_PPS_CONFIG0 0x30c6 11873#define regDSCC2_DSCC_PPS_CONFIG0_BASE_IDX 2 11874#define regDSCC2_DSCC_PPS_CONFIG1 0x30c7 11875#define regDSCC2_DSCC_PPS_CONFIG1_BASE_IDX 2 11876#define regDSCC2_DSCC_PPS_CONFIG2 0x30c8 11877#define regDSCC2_DSCC_PPS_CONFIG2_BASE_IDX 2 11878#define regDSCC2_DSCC_PPS_CONFIG3 0x30c9 11879#define regDSCC2_DSCC_PPS_CONFIG3_BASE_IDX 2 11880#define regDSCC2_DSCC_PPS_CONFIG4 0x30ca 11881#define regDSCC2_DSCC_PPS_CONFIG4_BASE_IDX 2 11882#define regDSCC2_DSCC_PPS_CONFIG5 0x30cb 11883#define regDSCC2_DSCC_PPS_CONFIG5_BASE_IDX 2 11884#define regDSCC2_DSCC_PPS_CONFIG6 0x30cc 11885#define regDSCC2_DSCC_PPS_CONFIG6_BASE_IDX 2 11886#define regDSCC2_DSCC_PPS_CONFIG7 0x30cd 11887#define regDSCC2_DSCC_PPS_CONFIG7_BASE_IDX 2 11888#define regDSCC2_DSCC_PPS_CONFIG8 0x30ce 11889#define regDSCC2_DSCC_PPS_CONFIG8_BASE_IDX 2 11890#define regDSCC2_DSCC_PPS_CONFIG9 0x30cf 11891#define regDSCC2_DSCC_PPS_CONFIG9_BASE_IDX 2 11892#define regDSCC2_DSCC_PPS_CONFIG10 0x30d0 11893#define regDSCC2_DSCC_PPS_CONFIG10_BASE_IDX 2 11894#define regDSCC2_DSCC_PPS_CONFIG11 0x30d1 11895#define regDSCC2_DSCC_PPS_CONFIG11_BASE_IDX 2 11896#define regDSCC2_DSCC_PPS_CONFIG12 0x30d2 11897#define regDSCC2_DSCC_PPS_CONFIG12_BASE_IDX 2 11898#define regDSCC2_DSCC_PPS_CONFIG13 0x30d3 11899#define regDSCC2_DSCC_PPS_CONFIG13_BASE_IDX 2 11900#define regDSCC2_DSCC_PPS_CONFIG14 0x30d4 11901#define regDSCC2_DSCC_PPS_CONFIG14_BASE_IDX 2 11902#define regDSCC2_DSCC_PPS_CONFIG15 0x30d5 11903#define regDSCC2_DSCC_PPS_CONFIG15_BASE_IDX 2 11904#define regDSCC2_DSCC_PPS_CONFIG16 0x30d6 11905#define regDSCC2_DSCC_PPS_CONFIG16_BASE_IDX 2 11906#define regDSCC2_DSCC_PPS_CONFIG17 0x30d7 11907#define regDSCC2_DSCC_PPS_CONFIG17_BASE_IDX 2 11908#define regDSCC2_DSCC_PPS_CONFIG18 0x30d8 11909#define regDSCC2_DSCC_PPS_CONFIG18_BASE_IDX 2 11910#define regDSCC2_DSCC_PPS_CONFIG19 0x30d9 11911#define regDSCC2_DSCC_PPS_CONFIG19_BASE_IDX 2 11912#define regDSCC2_DSCC_PPS_CONFIG20 0x30da 11913#define regDSCC2_DSCC_PPS_CONFIG20_BASE_IDX 2 11914#define regDSCC2_DSCC_PPS_CONFIG21 0x30db 11915#define regDSCC2_DSCC_PPS_CONFIG21_BASE_IDX 2 11916#define regDSCC2_DSCC_PPS_CONFIG22 0x30dc 11917#define regDSCC2_DSCC_PPS_CONFIG22_BASE_IDX 2 11918#define regDSCC2_DSCC_MEM_POWER_CONTROL 0x30dd 11919#define regDSCC2_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 11920#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER 0x30de 11921#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 11922#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER 0x30df 11923#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 11924#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER 0x30e0 11925#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 11926#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER 0x30e1 11927#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 11928#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER 0x30e2 11929#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 11930#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER 0x30e3 11931#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 11932#define regDSCC2_DSCC_MAX_ABS_ERROR0 0x30e4 11933#define regDSCC2_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 11934#define regDSCC2_DSCC_MAX_ABS_ERROR1 0x30e5 11935#define regDSCC2_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 11936#define regDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x30e6 11937#define regDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 11938#define regDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x30e7 11939#define regDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 11940#define regDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x30e8 11941#define regDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 11942#define regDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x30e9 11943#define regDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 11944#define regDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x30ea 11945#define regDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 11946#define regDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x30eb 11947#define regDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 11948#define regDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x30ec 11949#define regDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 11950#define regDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x30ed 11951#define regDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 11952#define regDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE 0x30f2 11953#define regDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 11954 11955 11956// addressBlock: dce_dc_dsc2_dispdec_dsc_dcperfmon_dc_perfmon_dispdec 11957// base address: 0xc420 11958#define regDC_PERFMON19_PERFCOUNTER_CNTL 0x3108 11959#define regDC_PERFMON19_PERFCOUNTER_CNTL_BASE_IDX 2 11960#define regDC_PERFMON19_PERFCOUNTER_CNTL2 0x3109 11961#define regDC_PERFMON19_PERFCOUNTER_CNTL2_BASE_IDX 2 11962#define regDC_PERFMON19_PERFCOUNTER_STATE 0x310a 11963#define regDC_PERFMON19_PERFCOUNTER_STATE_BASE_IDX 2 11964#define regDC_PERFMON19_PERFMON_CNTL 0x310b 11965#define regDC_PERFMON19_PERFMON_CNTL_BASE_IDX 2 11966#define regDC_PERFMON19_PERFMON_CNTL2 0x310c 11967#define regDC_PERFMON19_PERFMON_CNTL2_BASE_IDX 2 11968#define regDC_PERFMON19_PERFMON_CVALUE_INT_MISC 0x310d 11969#define regDC_PERFMON19_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 11970#define regDC_PERFMON19_PERFMON_CVALUE_LOW 0x310e 11971#define regDC_PERFMON19_PERFMON_CVALUE_LOW_BASE_IDX 2 11972#define regDC_PERFMON19_PERFMON_HI 0x310f 11973#define regDC_PERFMON19_PERFMON_HI_BASE_IDX 2 11974#define regDC_PERFMON19_PERFMON_LOW 0x3110 11975#define regDC_PERFMON19_PERFMON_LOW_BASE_IDX 2 11976 11977 11978// addressBlock: dce_dc_dsc3_dispdec_dsc_top_dispdec 11979// base address: 0x450 11980#define regDSC_TOP3_DSC_TOP_CONTROL 0x3114 11981#define regDSC_TOP3_DSC_TOP_CONTROL_BASE_IDX 2 11982#define regDSC_TOP3_DSC_DEBUG_CONTROL 0x3115 11983#define regDSC_TOP3_DSC_DEBUG_CONTROL_BASE_IDX 2 11984 11985 11986// addressBlock: dce_dc_dsc3_dispdec_dsccif_dispdec 11987// base address: 0x450 11988#define regDSCCIF3_DSCCIF_CONFIG0 0x3119 11989#define regDSCCIF3_DSCCIF_CONFIG0_BASE_IDX 2 11990#define regDSCCIF3_DSCCIF_CONFIG1 0x311a 11991#define regDSCCIF3_DSCCIF_CONFIG1_BASE_IDX 2 11992 11993 11994// addressBlock: dce_dc_dsc3_dispdec_dscc_dispdec 11995// base address: 0x450 11996#define regDSCC3_DSCC_CONFIG0 0x311e 11997#define regDSCC3_DSCC_CONFIG0_BASE_IDX 2 11998#define regDSCC3_DSCC_CONFIG1 0x311f 11999#define regDSCC3_DSCC_CONFIG1_BASE_IDX 2 12000#define regDSCC3_DSCC_STATUS 0x3120 12001#define regDSCC3_DSCC_STATUS_BASE_IDX 2 12002#define regDSCC3_DSCC_INTERRUPT_CONTROL_STATUS 0x3121 12003#define regDSCC3_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 12004#define regDSCC3_DSCC_PPS_CONFIG0 0x3122 12005#define regDSCC3_DSCC_PPS_CONFIG0_BASE_IDX 2 12006#define regDSCC3_DSCC_PPS_CONFIG1 0x3123 12007#define regDSCC3_DSCC_PPS_CONFIG1_BASE_IDX 2 12008#define regDSCC3_DSCC_PPS_CONFIG2 0x3124 12009#define regDSCC3_DSCC_PPS_CONFIG2_BASE_IDX 2 12010#define regDSCC3_DSCC_PPS_CONFIG3 0x3125 12011#define regDSCC3_DSCC_PPS_CONFIG3_BASE_IDX 2 12012#define regDSCC3_DSCC_PPS_CONFIG4 0x3126 12013#define regDSCC3_DSCC_PPS_CONFIG4_BASE_IDX 2 12014#define regDSCC3_DSCC_PPS_CONFIG5 0x3127 12015#define regDSCC3_DSCC_PPS_CONFIG5_BASE_IDX 2 12016#define regDSCC3_DSCC_PPS_CONFIG6 0x3128 12017#define regDSCC3_DSCC_PPS_CONFIG6_BASE_IDX 2 12018#define regDSCC3_DSCC_PPS_CONFIG7 0x3129 12019#define regDSCC3_DSCC_PPS_CONFIG7_BASE_IDX 2 12020#define regDSCC3_DSCC_PPS_CONFIG8 0x312a 12021#define regDSCC3_DSCC_PPS_CONFIG8_BASE_IDX 2 12022#define regDSCC3_DSCC_PPS_CONFIG9 0x312b 12023#define regDSCC3_DSCC_PPS_CONFIG9_BASE_IDX 2 12024#define regDSCC3_DSCC_PPS_CONFIG10 0x312c 12025#define regDSCC3_DSCC_PPS_CONFIG10_BASE_IDX 2 12026#define regDSCC3_DSCC_PPS_CONFIG11 0x312d 12027#define regDSCC3_DSCC_PPS_CONFIG11_BASE_IDX 2 12028#define regDSCC3_DSCC_PPS_CONFIG12 0x312e 12029#define regDSCC3_DSCC_PPS_CONFIG12_BASE_IDX 2 12030#define regDSCC3_DSCC_PPS_CONFIG13 0x312f 12031#define regDSCC3_DSCC_PPS_CONFIG13_BASE_IDX 2 12032#define regDSCC3_DSCC_PPS_CONFIG14 0x3130 12033#define regDSCC3_DSCC_PPS_CONFIG14_BASE_IDX 2 12034#define regDSCC3_DSCC_PPS_CONFIG15 0x3131 12035#define regDSCC3_DSCC_PPS_CONFIG15_BASE_IDX 2 12036#define regDSCC3_DSCC_PPS_CONFIG16 0x3132 12037#define regDSCC3_DSCC_PPS_CONFIG16_BASE_IDX 2 12038#define regDSCC3_DSCC_PPS_CONFIG17 0x3133 12039#define regDSCC3_DSCC_PPS_CONFIG17_BASE_IDX 2 12040#define regDSCC3_DSCC_PPS_CONFIG18 0x3134 12041#define regDSCC3_DSCC_PPS_CONFIG18_BASE_IDX 2 12042#define regDSCC3_DSCC_PPS_CONFIG19 0x3135 12043#define regDSCC3_DSCC_PPS_CONFIG19_BASE_IDX 2 12044#define regDSCC3_DSCC_PPS_CONFIG20 0x3136 12045#define regDSCC3_DSCC_PPS_CONFIG20_BASE_IDX 2 12046#define regDSCC3_DSCC_PPS_CONFIG21 0x3137 12047#define regDSCC3_DSCC_PPS_CONFIG21_BASE_IDX 2 12048#define regDSCC3_DSCC_PPS_CONFIG22 0x3138 12049#define regDSCC3_DSCC_PPS_CONFIG22_BASE_IDX 2 12050#define regDSCC3_DSCC_MEM_POWER_CONTROL 0x3139 12051#define regDSCC3_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 12052#define regDSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER 0x313a 12053#define regDSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 12054#define regDSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER 0x313b 12055#define regDSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 12056#define regDSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER 0x313c 12057#define regDSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 12058#define regDSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER 0x313d 12059#define regDSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 12060#define regDSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER 0x313e 12061#define regDSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 12062#define regDSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER 0x313f 12063#define regDSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 12064#define regDSCC3_DSCC_MAX_ABS_ERROR0 0x3140 12065#define regDSCC3_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 12066#define regDSCC3_DSCC_MAX_ABS_ERROR1 0x3141 12067#define regDSCC3_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 12068#define regDSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x3142 12069#define regDSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 12070#define regDSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x3143 12071#define regDSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 12072#define regDSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x3144 12073#define regDSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 12074#define regDSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x3145 12075#define regDSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 12076#define regDSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x3146 12077#define regDSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 12078#define regDSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x3147 12079#define regDSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 12080#define regDSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3148 12081#define regDSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 12082#define regDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3149 12083#define regDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 12084#define regDSCC3_DSCC_TEST_DEBUG_BUS_ROTATE 0x314e 12085#define regDSCC3_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 12086 12087 12088// addressBlock: dce_dc_dsc3_dispdec_dsc_dcperfmon_dc_perfmon_dispdec 12089// base address: 0xc590 12090#define regDC_PERFMON20_PERFCOUNTER_CNTL 0x3164 12091#define regDC_PERFMON20_PERFCOUNTER_CNTL_BASE_IDX 2 12092#define regDC_PERFMON20_PERFCOUNTER_CNTL2 0x3165 12093#define regDC_PERFMON20_PERFCOUNTER_CNTL2_BASE_IDX 2 12094#define regDC_PERFMON20_PERFCOUNTER_STATE 0x3166 12095#define regDC_PERFMON20_PERFCOUNTER_STATE_BASE_IDX 2 12096#define regDC_PERFMON20_PERFMON_CNTL 0x3167 12097#define regDC_PERFMON20_PERFMON_CNTL_BASE_IDX 2 12098#define regDC_PERFMON20_PERFMON_CNTL2 0x3168 12099#define regDC_PERFMON20_PERFMON_CNTL2_BASE_IDX 2 12100#define regDC_PERFMON20_PERFMON_CVALUE_INT_MISC 0x3169 12101#define regDC_PERFMON20_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 12102#define regDC_PERFMON20_PERFMON_CVALUE_LOW 0x316a 12103#define regDC_PERFMON20_PERFMON_CVALUE_LOW_BASE_IDX 2 12104#define regDC_PERFMON20_PERFMON_HI 0x316b 12105#define regDC_PERFMON20_PERFMON_HI_BASE_IDX 2 12106#define regDC_PERFMON20_PERFMON_LOW 0x316c 12107#define regDC_PERFMON20_PERFMON_LOW_BASE_IDX 2 12108 12109 12110// addressBlock: dce_dc_wb0_dispdec_dwb_top_dispdec 12111// base address: 0x0 12112#define regDWB_ENABLE_CLK_CTRL 0x3228 12113#define regDWB_ENABLE_CLK_CTRL_BASE_IDX 2 12114#define regDWB_MEM_PWR_CTRL 0x3229 12115#define regDWB_MEM_PWR_CTRL_BASE_IDX 2 12116#define regFC_MODE_CTRL 0x322a 12117#define regFC_MODE_CTRL_BASE_IDX 2 12118#define regFC_FLOW_CTRL 0x322b 12119#define regFC_FLOW_CTRL_BASE_IDX 2 12120#define regFC_WINDOW_START 0x322c 12121#define regFC_WINDOW_START_BASE_IDX 2 12122#define regFC_WINDOW_SIZE 0x322d 12123#define regFC_WINDOW_SIZE_BASE_IDX 2 12124#define regFC_SOURCE_SIZE 0x322e 12125#define regFC_SOURCE_SIZE_BASE_IDX 2 12126#define regDWB_UPDATE_CTRL 0x322f 12127#define regDWB_UPDATE_CTRL_BASE_IDX 2 12128#define regDWB_CRC_CTRL 0x3230 12129#define regDWB_CRC_CTRL_BASE_IDX 2 12130#define regDWB_CRC_MASK_R_G 0x3231 12131#define regDWB_CRC_MASK_R_G_BASE_IDX 2 12132#define regDWB_CRC_MASK_B_A 0x3232 12133#define regDWB_CRC_MASK_B_A_BASE_IDX 2 12134#define regDWB_CRC_VAL_R_G 0x3233 12135#define regDWB_CRC_VAL_R_G_BASE_IDX 2 12136#define regDWB_CRC_VAL_B_A 0x3234 12137#define regDWB_CRC_VAL_B_A_BASE_IDX 2 12138#define regDWB_OUT_CTRL 0x3235 12139#define regDWB_OUT_CTRL_BASE_IDX 2 12140#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_EN 0x3236 12141#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_EN_BASE_IDX 2 12142#define regDWB_MMHUBBUB_BACKPRESSURE_CNT 0x3237 12143#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_BASE_IDX 2 12144#define regDWB_HOST_READ_CONTROL 0x3238 12145#define regDWB_HOST_READ_CONTROL_BASE_IDX 2 12146#define regDWB_OVERFLOW_STATUS 0x3239 12147#define regDWB_OVERFLOW_STATUS_BASE_IDX 2 12148#define regDWB_OVERFLOW_COUNTER 0x323a 12149#define regDWB_OVERFLOW_COUNTER_BASE_IDX 2 12150#define regDWB_SOFT_RESET 0x323b 12151#define regDWB_SOFT_RESET_BASE_IDX 2 12152#define regDWB_DEBUG_CTRL 0x323c 12153#define regDWB_DEBUG_CTRL_BASE_IDX 2 12154 12155 12156// addressBlock: dce_dc_wb0_dispdec_wb_dcperfmon_dc_perfmon_dispdec 12157// base address: 0xca20 12158#define regDC_PERFMON21_PERFCOUNTER_CNTL 0x3288 12159#define regDC_PERFMON21_PERFCOUNTER_CNTL_BASE_IDX 2 12160#define regDC_PERFMON21_PERFCOUNTER_CNTL2 0x3289 12161#define regDC_PERFMON21_PERFCOUNTER_CNTL2_BASE_IDX 2 12162#define regDC_PERFMON21_PERFCOUNTER_STATE 0x328a 12163#define regDC_PERFMON21_PERFCOUNTER_STATE_BASE_IDX 2 12164#define regDC_PERFMON21_PERFMON_CNTL 0x328b 12165#define regDC_PERFMON21_PERFMON_CNTL_BASE_IDX 2 12166#define regDC_PERFMON21_PERFMON_CNTL2 0x328c 12167#define regDC_PERFMON21_PERFMON_CNTL2_BASE_IDX 2 12168#define regDC_PERFMON21_PERFMON_CVALUE_INT_MISC 0x328d 12169#define regDC_PERFMON21_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 12170#define regDC_PERFMON21_PERFMON_CVALUE_LOW 0x328e 12171#define regDC_PERFMON21_PERFMON_CVALUE_LOW_BASE_IDX 2 12172#define regDC_PERFMON21_PERFMON_HI 0x328f 12173#define regDC_PERFMON21_PERFMON_HI_BASE_IDX 2 12174#define regDC_PERFMON21_PERFMON_LOW 0x3290 12175#define regDC_PERFMON21_PERFMON_LOW_BASE_IDX 2 12176 12177 12178// addressBlock: dce_dc_wb0_dispdec_dwbcp_dispdec 12179// base address: 0x0 12180#define regDWB_HDR_MULT_COEF 0x3294 12181#define regDWB_HDR_MULT_COEF_BASE_IDX 2 12182#define regDWB_GAMUT_REMAP_MODE 0x3295 12183#define regDWB_GAMUT_REMAP_MODE_BASE_IDX 2 12184#define regDWB_GAMUT_REMAP_COEF_FORMAT 0x3296 12185#define regDWB_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 2 12186#define regDWB_GAMUT_REMAPA_C11_C12 0x3297 12187#define regDWB_GAMUT_REMAPA_C11_C12_BASE_IDX 2 12188#define regDWB_GAMUT_REMAPA_C13_C14 0x3298 12189#define regDWB_GAMUT_REMAPA_C13_C14_BASE_IDX 2 12190#define regDWB_GAMUT_REMAPA_C21_C22 0x3299 12191#define regDWB_GAMUT_REMAPA_C21_C22_BASE_IDX 2 12192#define regDWB_GAMUT_REMAPA_C23_C24 0x329a 12193#define regDWB_GAMUT_REMAPA_C23_C24_BASE_IDX 2 12194#define regDWB_GAMUT_REMAPA_C31_C32 0x329b 12195#define regDWB_GAMUT_REMAPA_C31_C32_BASE_IDX 2 12196#define regDWB_GAMUT_REMAPA_C33_C34 0x329c 12197#define regDWB_GAMUT_REMAPA_C33_C34_BASE_IDX 2 12198#define regDWB_GAMUT_REMAPB_C11_C12 0x329d 12199#define regDWB_GAMUT_REMAPB_C11_C12_BASE_IDX 2 12200#define regDWB_GAMUT_REMAPB_C13_C14 0x329e 12201#define regDWB_GAMUT_REMAPB_C13_C14_BASE_IDX 2 12202#define regDWB_GAMUT_REMAPB_C21_C22 0x329f 12203#define regDWB_GAMUT_REMAPB_C21_C22_BASE_IDX 2 12204#define regDWB_GAMUT_REMAPB_C23_C24 0x32a0 12205#define regDWB_GAMUT_REMAPB_C23_C24_BASE_IDX 2 12206#define regDWB_GAMUT_REMAPB_C31_C32 0x32a1 12207#define regDWB_GAMUT_REMAPB_C31_C32_BASE_IDX 2 12208#define regDWB_GAMUT_REMAPB_C33_C34 0x32a2 12209#define regDWB_GAMUT_REMAPB_C33_C34_BASE_IDX 2 12210#define regDWB_OGAM_CONTROL 0x32a3 12211#define regDWB_OGAM_CONTROL_BASE_IDX 2 12212#define regDWB_OGAM_LUT_INDEX 0x32a4 12213#define regDWB_OGAM_LUT_INDEX_BASE_IDX 2 12214#define regDWB_OGAM_LUT_DATA 0x32a5 12215#define regDWB_OGAM_LUT_DATA_BASE_IDX 2 12216#define regDWB_OGAM_LUT_CONTROL 0x32a6 12217#define regDWB_OGAM_LUT_CONTROL_BASE_IDX 2 12218#define regDWB_OGAM_RAMA_START_CNTL_B 0x32a7 12219#define regDWB_OGAM_RAMA_START_CNTL_B_BASE_IDX 2 12220#define regDWB_OGAM_RAMA_START_CNTL_G 0x32a8 12221#define regDWB_OGAM_RAMA_START_CNTL_G_BASE_IDX 2 12222#define regDWB_OGAM_RAMA_START_CNTL_R 0x32a9 12223#define regDWB_OGAM_RAMA_START_CNTL_R_BASE_IDX 2 12224#define regDWB_OGAM_RAMA_START_BASE_CNTL_B 0x32aa 12225#define regDWB_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2 12226#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_B 0x32ab 12227#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 12228#define regDWB_OGAM_RAMA_START_BASE_CNTL_G 0x32ac 12229#define regDWB_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2 12230#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_G 0x32ad 12231#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 12232#define regDWB_OGAM_RAMA_START_BASE_CNTL_R 0x32ae 12233#define regDWB_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2 12234#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_R 0x32af 12235#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 12236#define regDWB_OGAM_RAMA_END_CNTL1_B 0x32b0 12237#define regDWB_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2 12238#define regDWB_OGAM_RAMA_END_CNTL2_B 0x32b1 12239#define regDWB_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2 12240#define regDWB_OGAM_RAMA_END_CNTL1_G 0x32b2 12241#define regDWB_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2 12242#define regDWB_OGAM_RAMA_END_CNTL2_G 0x32b3 12243#define regDWB_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2 12244#define regDWB_OGAM_RAMA_END_CNTL1_R 0x32b4 12245#define regDWB_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2 12246#define regDWB_OGAM_RAMA_END_CNTL2_R 0x32b5 12247#define regDWB_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2 12248#define regDWB_OGAM_RAMA_OFFSET_B 0x32b6 12249#define regDWB_OGAM_RAMA_OFFSET_B_BASE_IDX 2 12250#define regDWB_OGAM_RAMA_OFFSET_G 0x32b7 12251#define regDWB_OGAM_RAMA_OFFSET_G_BASE_IDX 2 12252#define regDWB_OGAM_RAMA_OFFSET_R 0x32b8 12253#define regDWB_OGAM_RAMA_OFFSET_R_BASE_IDX 2 12254#define regDWB_OGAM_RAMA_REGION_0_1 0x32b9 12255#define regDWB_OGAM_RAMA_REGION_0_1_BASE_IDX 2 12256#define regDWB_OGAM_RAMA_REGION_2_3 0x32ba 12257#define regDWB_OGAM_RAMA_REGION_2_3_BASE_IDX 2 12258#define regDWB_OGAM_RAMA_REGION_4_5 0x32bb 12259#define regDWB_OGAM_RAMA_REGION_4_5_BASE_IDX 2 12260#define regDWB_OGAM_RAMA_REGION_6_7 0x32bc 12261#define regDWB_OGAM_RAMA_REGION_6_7_BASE_IDX 2 12262#define regDWB_OGAM_RAMA_REGION_8_9 0x32bd 12263#define regDWB_OGAM_RAMA_REGION_8_9_BASE_IDX 2 12264#define regDWB_OGAM_RAMA_REGION_10_11 0x32be 12265#define regDWB_OGAM_RAMA_REGION_10_11_BASE_IDX 2 12266#define regDWB_OGAM_RAMA_REGION_12_13 0x32bf 12267#define regDWB_OGAM_RAMA_REGION_12_13_BASE_IDX 2 12268#define regDWB_OGAM_RAMA_REGION_14_15 0x32c0 12269#define regDWB_OGAM_RAMA_REGION_14_15_BASE_IDX 2 12270#define regDWB_OGAM_RAMA_REGION_16_17 0x32c1 12271#define regDWB_OGAM_RAMA_REGION_16_17_BASE_IDX 2 12272#define regDWB_OGAM_RAMA_REGION_18_19 0x32c2 12273#define regDWB_OGAM_RAMA_REGION_18_19_BASE_IDX 2 12274#define regDWB_OGAM_RAMA_REGION_20_21 0x32c3 12275#define regDWB_OGAM_RAMA_REGION_20_21_BASE_IDX 2 12276#define regDWB_OGAM_RAMA_REGION_22_23 0x32c4 12277#define regDWB_OGAM_RAMA_REGION_22_23_BASE_IDX 2 12278#define regDWB_OGAM_RAMA_REGION_24_25 0x32c5 12279#define regDWB_OGAM_RAMA_REGION_24_25_BASE_IDX 2 12280#define regDWB_OGAM_RAMA_REGION_26_27 0x32c6 12281#define regDWB_OGAM_RAMA_REGION_26_27_BASE_IDX 2 12282#define regDWB_OGAM_RAMA_REGION_28_29 0x32c7 12283#define regDWB_OGAM_RAMA_REGION_28_29_BASE_IDX 2 12284#define regDWB_OGAM_RAMA_REGION_30_31 0x32c8 12285#define regDWB_OGAM_RAMA_REGION_30_31_BASE_IDX 2 12286#define regDWB_OGAM_RAMA_REGION_32_33 0x32c9 12287#define regDWB_OGAM_RAMA_REGION_32_33_BASE_IDX 2 12288#define regDWB_OGAM_RAMB_START_CNTL_B 0x32ca 12289#define regDWB_OGAM_RAMB_START_CNTL_B_BASE_IDX 2 12290#define regDWB_OGAM_RAMB_START_CNTL_G 0x32cb 12291#define regDWB_OGAM_RAMB_START_CNTL_G_BASE_IDX 2 12292#define regDWB_OGAM_RAMB_START_CNTL_R 0x32cc 12293#define regDWB_OGAM_RAMB_START_CNTL_R_BASE_IDX 2 12294#define regDWB_OGAM_RAMB_START_BASE_CNTL_B 0x32cd 12295#define regDWB_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2 12296#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_B 0x32ce 12297#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 12298#define regDWB_OGAM_RAMB_START_BASE_CNTL_G 0x32cf 12299#define regDWB_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2 12300#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_G 0x32d0 12301#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 12302#define regDWB_OGAM_RAMB_START_BASE_CNTL_R 0x32d1 12303#define regDWB_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2 12304#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_R 0x32d2 12305#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 12306#define regDWB_OGAM_RAMB_END_CNTL1_B 0x32d3 12307#define regDWB_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2 12308#define regDWB_OGAM_RAMB_END_CNTL2_B 0x32d4 12309#define regDWB_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2 12310#define regDWB_OGAM_RAMB_END_CNTL1_G 0x32d5 12311#define regDWB_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2 12312#define regDWB_OGAM_RAMB_END_CNTL2_G 0x32d6 12313#define regDWB_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2 12314#define regDWB_OGAM_RAMB_END_CNTL1_R 0x32d7 12315#define regDWB_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2 12316#define regDWB_OGAM_RAMB_END_CNTL2_R 0x32d8 12317#define regDWB_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2 12318#define regDWB_OGAM_RAMB_OFFSET_B 0x32d9 12319#define regDWB_OGAM_RAMB_OFFSET_B_BASE_IDX 2 12320#define regDWB_OGAM_RAMB_OFFSET_G 0x32da 12321#define regDWB_OGAM_RAMB_OFFSET_G_BASE_IDX 2 12322#define regDWB_OGAM_RAMB_OFFSET_R 0x32db 12323#define regDWB_OGAM_RAMB_OFFSET_R_BASE_IDX 2 12324#define regDWB_OGAM_RAMB_REGION_0_1 0x32dc 12325#define regDWB_OGAM_RAMB_REGION_0_1_BASE_IDX 2 12326#define regDWB_OGAM_RAMB_REGION_2_3 0x32dd 12327#define regDWB_OGAM_RAMB_REGION_2_3_BASE_IDX 2 12328#define regDWB_OGAM_RAMB_REGION_4_5 0x32de 12329#define regDWB_OGAM_RAMB_REGION_4_5_BASE_IDX 2 12330#define regDWB_OGAM_RAMB_REGION_6_7 0x32df 12331#define regDWB_OGAM_RAMB_REGION_6_7_BASE_IDX 2 12332#define regDWB_OGAM_RAMB_REGION_8_9 0x32e0 12333#define regDWB_OGAM_RAMB_REGION_8_9_BASE_IDX 2 12334#define regDWB_OGAM_RAMB_REGION_10_11 0x32e1 12335#define regDWB_OGAM_RAMB_REGION_10_11_BASE_IDX 2 12336#define regDWB_OGAM_RAMB_REGION_12_13 0x32e2 12337#define regDWB_OGAM_RAMB_REGION_12_13_BASE_IDX 2 12338#define regDWB_OGAM_RAMB_REGION_14_15 0x32e3 12339#define regDWB_OGAM_RAMB_REGION_14_15_BASE_IDX 2 12340#define regDWB_OGAM_RAMB_REGION_16_17 0x32e4 12341#define regDWB_OGAM_RAMB_REGION_16_17_BASE_IDX 2 12342#define regDWB_OGAM_RAMB_REGION_18_19 0x32e5 12343#define regDWB_OGAM_RAMB_REGION_18_19_BASE_IDX 2 12344#define regDWB_OGAM_RAMB_REGION_20_21 0x32e6 12345#define regDWB_OGAM_RAMB_REGION_20_21_BASE_IDX 2 12346#define regDWB_OGAM_RAMB_REGION_22_23 0x32e7 12347#define regDWB_OGAM_RAMB_REGION_22_23_BASE_IDX 2 12348#define regDWB_OGAM_RAMB_REGION_24_25 0x32e8 12349#define regDWB_OGAM_RAMB_REGION_24_25_BASE_IDX 2 12350#define regDWB_OGAM_RAMB_REGION_26_27 0x32e9 12351#define regDWB_OGAM_RAMB_REGION_26_27_BASE_IDX 2 12352#define regDWB_OGAM_RAMB_REGION_28_29 0x32ea 12353#define regDWB_OGAM_RAMB_REGION_28_29_BASE_IDX 2 12354#define regDWB_OGAM_RAMB_REGION_30_31 0x32eb 12355#define regDWB_OGAM_RAMB_REGION_30_31_BASE_IDX 2 12356#define regDWB_OGAM_RAMB_REGION_32_33 0x32ec 12357#define regDWB_OGAM_RAMB_REGION_32_33_BASE_IDX 2 12358 12359 12360// addressBlock: dce_dc_dchvm_hvm_dispdec 12361// base address: 0x0 12362#define regDCHVM_CTRL0 0x3603 12363#define regDCHVM_CTRL0_BASE_IDX 2 12364#define regDCHVM_CTRL1 0x3604 12365#define regDCHVM_CTRL1_BASE_IDX 2 12366#define regDCHVM_CLK_CTRL 0x3605 12367#define regDCHVM_CLK_CTRL_BASE_IDX 2 12368#define regDCHVM_MEM_CTRL 0x3606 12369#define regDCHVM_MEM_CTRL_BASE_IDX 2 12370#define regDCHVM_RIOMMU_CTRL0 0x3607 12371#define regDCHVM_RIOMMU_CTRL0_BASE_IDX 2 12372#define regDCHVM_RIOMMU_STAT0 0x3608 12373#define regDCHVM_RIOMMU_STAT0_BASE_IDX 2 12374 12375 12376// addressBlock: dce_dc_hpo_dp_stream_enc0_dispdec 12377// base address: 0x1ab8c 12378#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL 0x3623 12379#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2 12380#define regDP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x3624 12381#define regDP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2 12382#define regDP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL 0x3625 12383#define regDP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2 12384#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x3626 12385#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2 12386#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x3627 12387#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2 12388#define regDP_STREAM_ENC0_DP_STREAM_ENC_SPARE 0x3628 12389#define regDP_STREAM_ENC0_DP_STREAM_ENC_SPARE_BASE_IDX 2 12390 12391 12392// addressBlock: dce_dc_hpo_dp_stream_enc0_apg_apg_dispdec 12393// base address: 0x1abc0 12394#define regAPG0_APG_CONTROL 0x3630 12395#define regAPG0_APG_CONTROL_BASE_IDX 2 12396#define regAPG0_APG_CONTROL2 0x3631 12397#define regAPG0_APG_CONTROL2_BASE_IDX 2 12398#define regAPG0_APG_DBG_GEN_CONTROL 0x3632 12399#define regAPG0_APG_DBG_GEN_CONTROL_BASE_IDX 2 12400#define regAPG0_APG_PACKET_CONTROL 0x3633 12401#define regAPG0_APG_PACKET_CONTROL_BASE_IDX 2 12402#define regAPG0_APG_AUDIO_CRC_CONTROL 0x363a 12403#define regAPG0_APG_AUDIO_CRC_CONTROL_BASE_IDX 2 12404#define regAPG0_APG_AUDIO_CRC_CONTROL2 0x363b 12405#define regAPG0_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2 12406#define regAPG0_APG_AUDIO_CRC_RESULT 0x363c 12407#define regAPG0_APG_AUDIO_CRC_RESULT_BASE_IDX 2 12408#define regAPG0_APG_STATUS 0x3641 12409#define regAPG0_APG_STATUS_BASE_IDX 2 12410#define regAPG0_APG_STATUS2 0x3642 12411#define regAPG0_APG_STATUS2_BASE_IDX 2 12412#define regAPG0_APG_MEM_PWR 0x3644 12413#define regAPG0_APG_MEM_PWR_BASE_IDX 2 12414#define regAPG0_APG_SPARE 0x3646 12415#define regAPG0_APG_SPARE_BASE_IDX 2 12416 12417 12418// addressBlock: dce_dc_hpo_dp_stream_enc0_dme_dme_dispdec 12419// base address: 0x1ac38 12420#define regDME5_DME_CONTROL 0x364e 12421#define regDME5_DME_CONTROL_BASE_IDX 2 12422#define regDME5_DME_MEMORY_CONTROL 0x364f 12423#define regDME5_DME_MEMORY_CONTROL_BASE_IDX 2 12424 12425 12426// addressBlock: dce_dc_hpo_dp_stream_enc0_vpg_vpg_dispdec 12427// base address: 0x1ac44 12428#define regVPG5_VPG_GENERIC_PACKET_ACCESS_CTRL 0x3651 12429#define regVPG5_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 12430#define regVPG5_VPG_GENERIC_PACKET_DATA 0x3652 12431#define regVPG5_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 12432#define regVPG5_VPG_GSP_FRAME_UPDATE_CTRL 0x3653 12433#define regVPG5_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 12434#define regVPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x3654 12435#define regVPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 12436#define regVPG5_VPG_GENERIC_STATUS 0x3655 12437#define regVPG5_VPG_GENERIC_STATUS_BASE_IDX 2 12438#define regVPG5_VPG_MEM_PWR 0x3656 12439#define regVPG5_VPG_MEM_PWR_BASE_IDX 2 12440#define regVPG5_VPG_ISRC1_2_ACCESS_CTRL 0x3657 12441#define regVPG5_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 12442#define regVPG5_VPG_ISRC1_2_DATA 0x3658 12443#define regVPG5_VPG_ISRC1_2_DATA_BASE_IDX 2 12444#define regVPG5_VPG_MPEG_INFO0 0x3659 12445#define regVPG5_VPG_MPEG_INFO0_BASE_IDX 2 12446#define regVPG5_VPG_MPEG_INFO1 0x365a 12447#define regVPG5_VPG_MPEG_INFO1_BASE_IDX 2 12448 12449 12450// addressBlock: dce_dc_hpo_dp_sym32_enc0_dispdec 12451// base address: 0x1ac74 12452#define regDP_SYM32_ENC0_DP_SYM32_ENC_CONTROL 0x365d 12453#define regDP_SYM32_ENC0_DP_SYM32_ENC_CONTROL_BASE_IDX 2 12454#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL 0x365e 12455#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2 12456#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x365f 12457#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 12458#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x3660 12459#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 12460#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x3661 12461#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2 12462#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0 0x3662 12463#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2 12464#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1 0x3663 12465#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2 12466#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2 0x3664 12467#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2 12468#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3 0x3665 12469#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2 12470#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4 0x3666 12471#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2 12472#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5 0x3667 12473#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2 12474#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6 0x3668 12475#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2 12476#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7 0x3669 12477#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2 12478#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8 0x366a 12479#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2 12480#define regDP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL 0x366b 12481#define regDP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2 12482#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x366c 12483#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2 12484#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x366d 12485#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2 12486#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x366e 12487#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2 12488#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x366f 12489#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2 12490#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x3670 12491#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2 12492#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x3671 12493#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2 12494#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x3672 12495#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2 12496#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x3673 12497#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2 12498#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x3674 12499#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2 12500#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x3675 12501#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2 12502#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x3676 12503#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2 12504#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x3677 12505#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2 12506#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x3678 12507#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2 12508#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x3679 12509#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2 12510#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x367a 12511#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2 12512#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL 0x367b 12513#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2 12514#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x367c 12515#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2 12516#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x367d 12517#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2 12518#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x367e 12519#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2 12520#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL 0x3683 12521#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2 12522#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL 0x3684 12523#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2 12524#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL 0x3685 12525#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2 12526#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x3686 12527#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 12528#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL 0x3687 12529#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2 12530#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0 0x3688 12531#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2 12532#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1 0x3689 12533#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2 12534#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS 0x368a 12535#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2 12536#define regDP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL 0x368b 12537#define regDP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2 12538#define regDP_SYM32_ENC0_DP_SYM32_ENC_SPARE 0x368c 12539#define regDP_SYM32_ENC0_DP_SYM32_ENC_SPARE_BASE_IDX 2 12540 12541 12542// addressBlock: dce_dc_hpo_dp_link_enc0_dispdec 12543// base address: 0x1ad5c 12544#define regDP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL 0x3697 12545#define regDP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX 2 12546#define regDP_LINK_ENC0_DP_LINK_ENC_SPARE 0x3698 12547#define regDP_LINK_ENC0_DP_LINK_ENC_SPARE_BASE_IDX 2 12548 12549 12550// addressBlock: dce_dc_hpo_dp_dphy_sym320_dispdec 12551// base address: 0x1ae00 12552#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL 0x36c0 12553#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL_BASE_IDX 2 12554#define regDP_DPHY_SYM320_DP_DPHY_SYM32_STATUS 0x36c1 12555#define regDP_DPHY_SYM320_DP_DPHY_SYM32_STATUS_BASE_IDX 2 12556#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE 0x36c4 12557#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX 2 12558#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0 0x36c5 12559#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX 2 12560#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1 0x36c6 12561#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX 2 12562#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2 0x36c7 12563#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX 2 12564#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3 0x36c8 12565#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX 2 12566#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0 0x36cb 12567#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0_BASE_IDX 2 12568#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1 0x36cc 12569#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1_BASE_IDX 2 12570#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2 0x36cd 12571#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2_BASE_IDX 2 12572#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3 0x36ce 12573#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3_BASE_IDX 2 12574#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0 0x36d1 12575#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX 2 12576#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1 0x36d2 12577#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX 2 12578#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2 0x36d3 12579#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX 2 12580#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3 0x36d4 12581#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX 2 12582#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG 0x36d7 12583#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX 2 12584#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0 0x36d8 12585#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX 2 12586#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1 0x36d9 12587#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX 2 12588#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2 0x36da 12589#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX 2 12590#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3 0x36db 12591#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX 2 12592#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE 0x36dc 12593#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX 2 12594#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0 0x36dd 12595#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX 2 12596#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1 0x36de 12597#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX 2 12598#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2 0x36df 12599#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX 2 12600#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3 0x36e0 12601#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX 2 12602#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4 0x36e1 12603#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX 2 12604#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5 0x36e2 12605#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX 2 12606#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6 0x36e3 12607#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX 2 12608#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7 0x36e4 12609#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX 2 12610#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8 0x36e5 12611#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX 2 12612#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9 0x36e6 12613#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX 2 12614#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10 0x36e7 12615#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX 2 12616#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS 0x36e8 12617#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX 2 12618#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE 0x36ea 12619#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE_BASE_IDX 2 12620#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0 0x36eb 12621#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0_BASE_IDX 2 12622#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1 0x36ec 12623#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1_BASE_IDX 2 12624#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS 0x36ed 12625#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS_BASE_IDX 2 12626#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT 0x36ee 12627#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT_BASE_IDX 2 12628 12629 12630// addressBlock: dce_dc_hpo_dp_stream_enc1_dispdec 12631// base address: 0x1aedc 12632#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL 0x36f7 12633#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2 12634#define regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x36f8 12635#define regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2 12636#define regDP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL 0x36f9 12637#define regDP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2 12638#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x36fa 12639#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2 12640#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x36fb 12641#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2 12642#define regDP_STREAM_ENC1_DP_STREAM_ENC_SPARE 0x36fc 12643#define regDP_STREAM_ENC1_DP_STREAM_ENC_SPARE_BASE_IDX 2 12644 12645 12646// addressBlock: dce_dc_hpo_dp_stream_enc1_apg_apg_dispdec 12647// base address: 0x1af10 12648#define regAPG1_APG_CONTROL 0x3704 12649#define regAPG1_APG_CONTROL_BASE_IDX 2 12650#define regAPG1_APG_CONTROL2 0x3705 12651#define regAPG1_APG_CONTROL2_BASE_IDX 2 12652#define regAPG1_APG_DBG_GEN_CONTROL 0x3706 12653#define regAPG1_APG_DBG_GEN_CONTROL_BASE_IDX 2 12654#define regAPG1_APG_PACKET_CONTROL 0x3707 12655#define regAPG1_APG_PACKET_CONTROL_BASE_IDX 2 12656#define regAPG1_APG_AUDIO_CRC_CONTROL 0x370e 12657#define regAPG1_APG_AUDIO_CRC_CONTROL_BASE_IDX 2 12658#define regAPG1_APG_AUDIO_CRC_CONTROL2 0x370f 12659#define regAPG1_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2 12660#define regAPG1_APG_AUDIO_CRC_RESULT 0x3710 12661#define regAPG1_APG_AUDIO_CRC_RESULT_BASE_IDX 2 12662#define regAPG1_APG_STATUS 0x3715 12663#define regAPG1_APG_STATUS_BASE_IDX 2 12664#define regAPG1_APG_STATUS2 0x3716 12665#define regAPG1_APG_STATUS2_BASE_IDX 2 12666#define regAPG1_APG_MEM_PWR 0x3718 12667#define regAPG1_APG_MEM_PWR_BASE_IDX 2 12668#define regAPG1_APG_SPARE 0x371a 12669#define regAPG1_APG_SPARE_BASE_IDX 2 12670 12671 12672// addressBlock: dce_dc_hpo_dp_stream_enc1_dme_dme_dispdec 12673// base address: 0x1af88 12674#define regDME6_DME_CONTROL 0x3722 12675#define regDME6_DME_CONTROL_BASE_IDX 2 12676#define regDME6_DME_MEMORY_CONTROL 0x3723 12677#define regDME6_DME_MEMORY_CONTROL_BASE_IDX 2 12678 12679 12680// addressBlock: dce_dc_hpo_dp_stream_enc1_vpg_vpg_dispdec 12681// base address: 0x1af94 12682#define regVPG6_VPG_GENERIC_PACKET_ACCESS_CTRL 0x3725 12683#define regVPG6_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 12684#define regVPG6_VPG_GENERIC_PACKET_DATA 0x3726 12685#define regVPG6_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 12686#define regVPG6_VPG_GSP_FRAME_UPDATE_CTRL 0x3727 12687#define regVPG6_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 12688#define regVPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x3728 12689#define regVPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 12690#define regVPG6_VPG_GENERIC_STATUS 0x3729 12691#define regVPG6_VPG_GENERIC_STATUS_BASE_IDX 2 12692#define regVPG6_VPG_MEM_PWR 0x372a 12693#define regVPG6_VPG_MEM_PWR_BASE_IDX 2 12694#define regVPG6_VPG_ISRC1_2_ACCESS_CTRL 0x372b 12695#define regVPG6_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 12696#define regVPG6_VPG_ISRC1_2_DATA 0x372c 12697#define regVPG6_VPG_ISRC1_2_DATA_BASE_IDX 2 12698#define regVPG6_VPG_MPEG_INFO0 0x372d 12699#define regVPG6_VPG_MPEG_INFO0_BASE_IDX 2 12700#define regVPG6_VPG_MPEG_INFO1 0x372e 12701#define regVPG6_VPG_MPEG_INFO1_BASE_IDX 2 12702 12703 12704// addressBlock: dce_dc_hpo_dp_sym32_enc1_dispdec 12705// base address: 0x1afc4 12706#define regDP_SYM32_ENC1_DP_SYM32_ENC_CONTROL 0x3731 12707#define regDP_SYM32_ENC1_DP_SYM32_ENC_CONTROL_BASE_IDX 2 12708#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL 0x3732 12709#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2 12710#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x3733 12711#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 12712#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x3734 12713#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 12714#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x3735 12715#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2 12716#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0 0x3736 12717#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2 12718#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1 0x3737 12719#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2 12720#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2 0x3738 12721#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2 12722#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3 0x3739 12723#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2 12724#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4 0x373a 12725#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2 12726#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5 0x373b 12727#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2 12728#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6 0x373c 12729#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2 12730#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7 0x373d 12731#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2 12732#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8 0x373e 12733#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2 12734#define regDP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL 0x373f 12735#define regDP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2 12736#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x3740 12737#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2 12738#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x3741 12739#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2 12740#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x3742 12741#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2 12742#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x3743 12743#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2 12744#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x3744 12745#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2 12746#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x3745 12747#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2 12748#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x3746 12749#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2 12750#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x3747 12751#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2 12752#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x3748 12753#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2 12754#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x3749 12755#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2 12756#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x374a 12757#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2 12758#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x374b 12759#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2 12760#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x374c 12761#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2 12762#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x374d 12763#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2 12764#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x374e 12765#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2 12766#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL 0x374f 12767#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2 12768#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x3750 12769#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2 12770#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x3751 12771#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2 12772#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x3752 12773#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2 12774#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL 0x3757 12775#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2 12776#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL 0x3758 12777#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2 12778#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL 0x3759 12779#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2 12780#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x375a 12781#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 12782#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL 0x375b 12783#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2 12784#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0 0x375c 12785#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2 12786#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1 0x375d 12787#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2 12788#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS 0x375e 12789#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2 12790#define regDP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL 0x375f 12791#define regDP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2 12792#define regDP_SYM32_ENC1_DP_SYM32_ENC_SPARE 0x3760 12793#define regDP_SYM32_ENC1_DP_SYM32_ENC_SPARE_BASE_IDX 2 12794 12795 12796// addressBlock: dce_dc_hpo_dp_link_enc1_dispdec 12797// base address: 0x1b0ac 12798#define regDP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL 0x376b 12799#define regDP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX 2 12800#define regDP_LINK_ENC1_DP_LINK_ENC_SPARE 0x376c 12801#define regDP_LINK_ENC1_DP_LINK_ENC_SPARE_BASE_IDX 2 12802 12803 12804// addressBlock: dce_dc_hpo_dp_dphy_sym321_dispdec 12805// base address: 0x1b150 12806#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL 0x3794 12807#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL_BASE_IDX 2 12808#define regDP_DPHY_SYM321_DP_DPHY_SYM32_STATUS 0x3795 12809#define regDP_DPHY_SYM321_DP_DPHY_SYM32_STATUS_BASE_IDX 2 12810#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE 0x3798 12811#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX 2 12812#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0 0x3799 12813#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX 2 12814#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1 0x379a 12815#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX 2 12816#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2 0x379b 12817#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX 2 12818#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3 0x379c 12819#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX 2 12820#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0 0x379f 12821#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0_BASE_IDX 2 12822#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1 0x37a0 12823#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1_BASE_IDX 2 12824#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2 0x37a1 12825#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2_BASE_IDX 2 12826#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3 0x37a2 12827#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3_BASE_IDX 2 12828#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0 0x37a5 12829#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX 2 12830#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1 0x37a6 12831#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX 2 12832#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2 0x37a7 12833#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX 2 12834#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3 0x37a8 12835#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX 2 12836#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG 0x37ab 12837#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX 2 12838#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0 0x37ac 12839#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX 2 12840#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1 0x37ad 12841#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX 2 12842#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2 0x37ae 12843#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX 2 12844#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3 0x37af 12845#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX 2 12846#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE 0x37b0 12847#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX 2 12848#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0 0x37b1 12849#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX 2 12850#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1 0x37b2 12851#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX 2 12852#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2 0x37b3 12853#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX 2 12854#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3 0x37b4 12855#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX 2 12856#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4 0x37b5 12857#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX 2 12858#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5 0x37b6 12859#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX 2 12860#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6 0x37b7 12861#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX 2 12862#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7 0x37b8 12863#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX 2 12864#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8 0x37b9 12865#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX 2 12866#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9 0x37ba 12867#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX 2 12868#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10 0x37bb 12869#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX 2 12870#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS 0x37bc 12871#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX 2 12872#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE 0x37be 12873#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE_BASE_IDX 2 12874#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0 0x37bf 12875#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0_BASE_IDX 2 12876#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1 0x37c0 12877#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1_BASE_IDX 2 12878#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS 0x37c1 12879#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS_BASE_IDX 2 12880#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT 0x37c2 12881#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT_BASE_IDX 2 12882 12883 12884// addressBlock: dce_dc_hpo_dp_stream_enc2_dispdec 12885// base address: 0x1b22c 12886#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL 0x37cb 12887#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2 12888#define regDP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x37cc 12889#define regDP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2 12890#define regDP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL 0x37cd 12891#define regDP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2 12892#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x37ce 12893#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2 12894#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x37cf 12895#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2 12896#define regDP_STREAM_ENC2_DP_STREAM_ENC_SPARE 0x37d0 12897#define regDP_STREAM_ENC2_DP_STREAM_ENC_SPARE_BASE_IDX 2 12898 12899 12900// addressBlock: dce_dc_hpo_dp_stream_enc2_apg_apg_dispdec 12901// base address: 0x1b260 12902#define regAPG2_APG_CONTROL 0x37d8 12903#define regAPG2_APG_CONTROL_BASE_IDX 2 12904#define regAPG2_APG_CONTROL2 0x37d9 12905#define regAPG2_APG_CONTROL2_BASE_IDX 2 12906#define regAPG2_APG_DBG_GEN_CONTROL 0x37da 12907#define regAPG2_APG_DBG_GEN_CONTROL_BASE_IDX 2 12908#define regAPG2_APG_PACKET_CONTROL 0x37db 12909#define regAPG2_APG_PACKET_CONTROL_BASE_IDX 2 12910#define regAPG2_APG_AUDIO_CRC_CONTROL 0x37e2 12911#define regAPG2_APG_AUDIO_CRC_CONTROL_BASE_IDX 2 12912#define regAPG2_APG_AUDIO_CRC_CONTROL2 0x37e3 12913#define regAPG2_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2 12914#define regAPG2_APG_AUDIO_CRC_RESULT 0x37e4 12915#define regAPG2_APG_AUDIO_CRC_RESULT_BASE_IDX 2 12916#define regAPG2_APG_STATUS 0x37e9 12917#define regAPG2_APG_STATUS_BASE_IDX 2 12918#define regAPG2_APG_STATUS2 0x37ea 12919#define regAPG2_APG_STATUS2_BASE_IDX 2 12920#define regAPG2_APG_MEM_PWR 0x37ec 12921#define regAPG2_APG_MEM_PWR_BASE_IDX 2 12922#define regAPG2_APG_SPARE 0x37ee 12923#define regAPG2_APG_SPARE_BASE_IDX 2 12924 12925 12926// addressBlock: dce_dc_hpo_dp_stream_enc2_dme_dme_dispdec 12927// base address: 0x1b2d8 12928#define regDME7_DME_CONTROL 0x37f6 12929#define regDME7_DME_CONTROL_BASE_IDX 2 12930#define regDME7_DME_MEMORY_CONTROL 0x37f7 12931#define regDME7_DME_MEMORY_CONTROL_BASE_IDX 2 12932 12933 12934// addressBlock: dce_dc_hpo_dp_stream_enc2_vpg_vpg_dispdec 12935// base address: 0x1b2e4 12936#define regVPG7_VPG_GENERIC_PACKET_ACCESS_CTRL 0x37f9 12937#define regVPG7_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 12938#define regVPG7_VPG_GENERIC_PACKET_DATA 0x37fa 12939#define regVPG7_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 12940#define regVPG7_VPG_GSP_FRAME_UPDATE_CTRL 0x37fb 12941#define regVPG7_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 12942#define regVPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x37fc 12943#define regVPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 12944#define regVPG7_VPG_GENERIC_STATUS 0x37fd 12945#define regVPG7_VPG_GENERIC_STATUS_BASE_IDX 2 12946#define regVPG7_VPG_MEM_PWR 0x37fe 12947#define regVPG7_VPG_MEM_PWR_BASE_IDX 2 12948#define regVPG7_VPG_ISRC1_2_ACCESS_CTRL 0x37ff 12949#define regVPG7_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 12950#define regVPG7_VPG_ISRC1_2_DATA 0x3800 12951#define regVPG7_VPG_ISRC1_2_DATA_BASE_IDX 2 12952#define regVPG7_VPG_MPEG_INFO0 0x3801 12953#define regVPG7_VPG_MPEG_INFO0_BASE_IDX 2 12954#define regVPG7_VPG_MPEG_INFO1 0x3802 12955#define regVPG7_VPG_MPEG_INFO1_BASE_IDX 2 12956 12957 12958// addressBlock: dce_dc_hpo_dp_sym32_enc2_dispdec 12959// base address: 0x1b314 12960#define regDP_SYM32_ENC2_DP_SYM32_ENC_CONTROL 0x3805 12961#define regDP_SYM32_ENC2_DP_SYM32_ENC_CONTROL_BASE_IDX 2 12962#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL 0x3806 12963#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2 12964#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x3807 12965#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 12966#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x3808 12967#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 12968#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x3809 12969#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2 12970#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0 0x380a 12971#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2 12972#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1 0x380b 12973#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2 12974#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2 0x380c 12975#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2 12976#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3 0x380d 12977#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2 12978#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4 0x380e 12979#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2 12980#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5 0x380f 12981#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2 12982#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6 0x3810 12983#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2 12984#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7 0x3811 12985#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2 12986#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8 0x3812 12987#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2 12988#define regDP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL 0x3813 12989#define regDP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2 12990#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x3814 12991#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2 12992#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x3815 12993#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2 12994#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x3816 12995#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2 12996#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x3817 12997#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2 12998#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x3818 12999#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2 13000#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x3819 13001#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2 13002#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x381a 13003#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2 13004#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x381b 13005#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2 13006#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x381c 13007#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2 13008#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x381d 13009#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2 13010#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x381e 13011#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2 13012#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x381f 13013#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2 13014#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x3820 13015#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2 13016#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x3821 13017#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2 13018#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x3822 13019#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2 13020#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL 0x3823 13021#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2 13022#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x3824 13023#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2 13024#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x3825 13025#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2 13026#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x3826 13027#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2 13028#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL 0x382b 13029#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2 13030#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL 0x382c 13031#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2 13032#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL 0x382d 13033#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2 13034#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x382e 13035#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 13036#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL 0x382f 13037#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2 13038#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0 0x3830 13039#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2 13040#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1 0x3831 13041#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2 13042#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS 0x3832 13043#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2 13044#define regDP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL 0x3833 13045#define regDP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2 13046#define regDP_SYM32_ENC2_DP_SYM32_ENC_SPARE 0x3834 13047#define regDP_SYM32_ENC2_DP_SYM32_ENC_SPARE_BASE_IDX 2 13048 13049 13050// addressBlock: dce_dc_hpo_dp_stream_enc3_dispdec 13051// base address: 0x1b57c 13052#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL 0x389f 13053#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2 13054#define regDP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x38a0 13055#define regDP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2 13056#define regDP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL 0x38a1 13057#define regDP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2 13058#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x38a2 13059#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2 13060#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x38a3 13061#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2 13062#define regDP_STREAM_ENC3_DP_STREAM_ENC_SPARE 0x38a4 13063#define regDP_STREAM_ENC3_DP_STREAM_ENC_SPARE_BASE_IDX 2 13064 13065 13066// addressBlock: dce_dc_hpo_dp_stream_enc3_apg_apg_dispdec 13067// base address: 0x1b5b0 13068#define regAPG3_APG_CONTROL 0x38ac 13069#define regAPG3_APG_CONTROL_BASE_IDX 2 13070#define regAPG3_APG_CONTROL2 0x38ad 13071#define regAPG3_APG_CONTROL2_BASE_IDX 2 13072#define regAPG3_APG_DBG_GEN_CONTROL 0x38ae 13073#define regAPG3_APG_DBG_GEN_CONTROL_BASE_IDX 2 13074#define regAPG3_APG_PACKET_CONTROL 0x38af 13075#define regAPG3_APG_PACKET_CONTROL_BASE_IDX 2 13076#define regAPG3_APG_AUDIO_CRC_CONTROL 0x38b6 13077#define regAPG3_APG_AUDIO_CRC_CONTROL_BASE_IDX 2 13078#define regAPG3_APG_AUDIO_CRC_CONTROL2 0x38b7 13079#define regAPG3_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2 13080#define regAPG3_APG_AUDIO_CRC_RESULT 0x38b8 13081#define regAPG3_APG_AUDIO_CRC_RESULT_BASE_IDX 2 13082#define regAPG3_APG_STATUS 0x38bd 13083#define regAPG3_APG_STATUS_BASE_IDX 2 13084#define regAPG3_APG_STATUS2 0x38be 13085#define regAPG3_APG_STATUS2_BASE_IDX 2 13086#define regAPG3_APG_MEM_PWR 0x38c0 13087#define regAPG3_APG_MEM_PWR_BASE_IDX 2 13088#define regAPG3_APG_SPARE 0x38c2 13089#define regAPG3_APG_SPARE_BASE_IDX 2 13090 13091 13092// addressBlock: dce_dc_hpo_dp_stream_enc3_dme_dme_dispdec 13093// base address: 0x1b628 13094#define regDME8_DME_CONTROL 0x38ca 13095#define regDME8_DME_CONTROL_BASE_IDX 2 13096#define regDME8_DME_MEMORY_CONTROL 0x38cb 13097#define regDME8_DME_MEMORY_CONTROL_BASE_IDX 2 13098 13099 13100// addressBlock: dce_dc_hpo_dp_stream_enc3_vpg_vpg_dispdec 13101// base address: 0x1b634 13102#define regVPG8_VPG_GENERIC_PACKET_ACCESS_CTRL 0x38cd 13103#define regVPG8_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 13104#define regVPG8_VPG_GENERIC_PACKET_DATA 0x38ce 13105#define regVPG8_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 13106#define regVPG8_VPG_GSP_FRAME_UPDATE_CTRL 0x38cf 13107#define regVPG8_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 13108#define regVPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x38d0 13109#define regVPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 13110#define regVPG8_VPG_GENERIC_STATUS 0x38d1 13111#define regVPG8_VPG_GENERIC_STATUS_BASE_IDX 2 13112#define regVPG8_VPG_MEM_PWR 0x38d2 13113#define regVPG8_VPG_MEM_PWR_BASE_IDX 2 13114#define regVPG8_VPG_ISRC1_2_ACCESS_CTRL 0x38d3 13115#define regVPG8_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 13116#define regVPG8_VPG_ISRC1_2_DATA 0x38d4 13117#define regVPG8_VPG_ISRC1_2_DATA_BASE_IDX 2 13118#define regVPG8_VPG_MPEG_INFO0 0x38d5 13119#define regVPG8_VPG_MPEG_INFO0_BASE_IDX 2 13120#define regVPG8_VPG_MPEG_INFO1 0x38d6 13121#define regVPG8_VPG_MPEG_INFO1_BASE_IDX 2 13122 13123 13124// addressBlock: dce_dc_hpo_dp_sym32_enc3_dispdec 13125// base address: 0x1b664 13126#define regDP_SYM32_ENC3_DP_SYM32_ENC_CONTROL 0x38d9 13127#define regDP_SYM32_ENC3_DP_SYM32_ENC_CONTROL_BASE_IDX 2 13128#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL 0x38da 13129#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2 13130#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x38db 13131#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 13132#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x38dc 13133#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 13134#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x38dd 13135#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2 13136#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0 0x38de 13137#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2 13138#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1 0x38df 13139#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2 13140#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2 0x38e0 13141#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2 13142#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3 0x38e1 13143#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2 13144#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4 0x38e2 13145#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2 13146#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5 0x38e3 13147#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2 13148#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6 0x38e4 13149#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2 13150#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7 0x38e5 13151#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2 13152#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8 0x38e6 13153#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2 13154#define regDP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL 0x38e7 13155#define regDP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2 13156#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x38e8 13157#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2 13158#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x38e9 13159#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2 13160#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x38ea 13161#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2 13162#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x38eb 13163#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2 13164#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x38ec 13165#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2 13166#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x38ed 13167#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2 13168#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x38ee 13169#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2 13170#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x38ef 13171#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2 13172#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x38f0 13173#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2 13174#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x38f1 13175#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2 13176#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x38f2 13177#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2 13178#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x38f3 13179#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2 13180#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x38f4 13181#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2 13182#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x38f5 13183#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2 13184#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x38f6 13185#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2 13186#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL 0x38f7 13187#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2 13188#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x38f8 13189#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2 13190#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x38f9 13191#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2 13192#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x38fa 13193#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2 13194#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL 0x38ff 13195#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2 13196#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL 0x3900 13197#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2 13198#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL 0x3901 13199#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2 13200#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x3902 13201#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 13202#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL 0x3903 13203#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2 13204#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0 0x3904 13205#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2 13206#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1 0x3905 13207#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2 13208#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS 0x3906 13209#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2 13210#define regDP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL 0x3907 13211#define regDP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2 13212#define regDP_SYM32_ENC3_DP_SYM32_ENC_SPARE 0x3908 13213#define regDP_SYM32_ENC3_DP_SYM32_ENC_SPARE_BASE_IDX 2 13214 13215 13216// addressBlock: dce_dc_mpc_mpcc0_dispdec 13217// base address: 0x0 13218#define regMPCC0_MPCC_TOP_SEL 0x0000 13219#define regMPCC0_MPCC_TOP_SEL_BASE_IDX 3 13220#define regMPCC0_MPCC_BOT_SEL 0x0001 13221#define regMPCC0_MPCC_BOT_SEL_BASE_IDX 3 13222#define regMPCC0_MPCC_OPP_ID 0x0002 13223#define regMPCC0_MPCC_OPP_ID_BASE_IDX 3 13224#define regMPCC0_MPCC_CONTROL 0x0003 13225#define regMPCC0_MPCC_CONTROL_BASE_IDX 3 13226#define regMPCC0_MPCC_SM_CONTROL 0x0004 13227#define regMPCC0_MPCC_SM_CONTROL_BASE_IDX 3 13228#define regMPCC0_MPCC_UPDATE_LOCK_SEL 0x0005 13229#define regMPCC0_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 13230#define regMPCC0_MPCC_TOP_GAIN 0x0006 13231#define regMPCC0_MPCC_TOP_GAIN_BASE_IDX 3 13232#define regMPCC0_MPCC_BOT_GAIN_INSIDE 0x0007 13233#define regMPCC0_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 13234#define regMPCC0_MPCC_BOT_GAIN_OUTSIDE 0x0008 13235#define regMPCC0_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 13236#define regMPCC0_MPCC_BG_R_CR 0x0009 13237#define regMPCC0_MPCC_BG_R_CR_BASE_IDX 3 13238#define regMPCC0_MPCC_BG_G_Y 0x000a 13239#define regMPCC0_MPCC_BG_G_Y_BASE_IDX 3 13240#define regMPCC0_MPCC_BG_B_CB 0x000b 13241#define regMPCC0_MPCC_BG_B_CB_BASE_IDX 3 13242#define regMPCC0_MPCC_MEM_PWR_CTRL 0x000c 13243#define regMPCC0_MPCC_MEM_PWR_CTRL_BASE_IDX 3 13244#define regMPCC0_MPCC_STATUS 0x000d 13245#define regMPCC0_MPCC_STATUS_BASE_IDX 3 13246 13247 13248// addressBlock: dce_dc_mpc_mpcc1_dispdec 13249// base address: 0x80 13250#define regMPCC1_MPCC_TOP_SEL 0x0020 13251#define regMPCC1_MPCC_TOP_SEL_BASE_IDX 3 13252#define regMPCC1_MPCC_BOT_SEL 0x0021 13253#define regMPCC1_MPCC_BOT_SEL_BASE_IDX 3 13254#define regMPCC1_MPCC_OPP_ID 0x0022 13255#define regMPCC1_MPCC_OPP_ID_BASE_IDX 3 13256#define regMPCC1_MPCC_CONTROL 0x0023 13257#define regMPCC1_MPCC_CONTROL_BASE_IDX 3 13258#define regMPCC1_MPCC_SM_CONTROL 0x0024 13259#define regMPCC1_MPCC_SM_CONTROL_BASE_IDX 3 13260#define regMPCC1_MPCC_UPDATE_LOCK_SEL 0x0025 13261#define regMPCC1_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 13262#define regMPCC1_MPCC_TOP_GAIN 0x0026 13263#define regMPCC1_MPCC_TOP_GAIN_BASE_IDX 3 13264#define regMPCC1_MPCC_BOT_GAIN_INSIDE 0x0027 13265#define regMPCC1_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 13266#define regMPCC1_MPCC_BOT_GAIN_OUTSIDE 0x0028 13267#define regMPCC1_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 13268#define regMPCC1_MPCC_BG_R_CR 0x0029 13269#define regMPCC1_MPCC_BG_R_CR_BASE_IDX 3 13270#define regMPCC1_MPCC_BG_G_Y 0x002a 13271#define regMPCC1_MPCC_BG_G_Y_BASE_IDX 3 13272#define regMPCC1_MPCC_BG_B_CB 0x002b 13273#define regMPCC1_MPCC_BG_B_CB_BASE_IDX 3 13274#define regMPCC1_MPCC_MEM_PWR_CTRL 0x002c 13275#define regMPCC1_MPCC_MEM_PWR_CTRL_BASE_IDX 3 13276#define regMPCC1_MPCC_STATUS 0x002d 13277#define regMPCC1_MPCC_STATUS_BASE_IDX 3 13278 13279 13280// addressBlock: dce_dc_mpc_mpcc2_dispdec 13281// base address: 0x100 13282#define regMPCC2_MPCC_TOP_SEL 0x0040 13283#define regMPCC2_MPCC_TOP_SEL_BASE_IDX 3 13284#define regMPCC2_MPCC_BOT_SEL 0x0041 13285#define regMPCC2_MPCC_BOT_SEL_BASE_IDX 3 13286#define regMPCC2_MPCC_OPP_ID 0x0042 13287#define regMPCC2_MPCC_OPP_ID_BASE_IDX 3 13288#define regMPCC2_MPCC_CONTROL 0x0043 13289#define regMPCC2_MPCC_CONTROL_BASE_IDX 3 13290#define regMPCC2_MPCC_SM_CONTROL 0x0044 13291#define regMPCC2_MPCC_SM_CONTROL_BASE_IDX 3 13292#define regMPCC2_MPCC_UPDATE_LOCK_SEL 0x0045 13293#define regMPCC2_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 13294#define regMPCC2_MPCC_TOP_GAIN 0x0046 13295#define regMPCC2_MPCC_TOP_GAIN_BASE_IDX 3 13296#define regMPCC2_MPCC_BOT_GAIN_INSIDE 0x0047 13297#define regMPCC2_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 13298#define regMPCC2_MPCC_BOT_GAIN_OUTSIDE 0x0048 13299#define regMPCC2_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 13300#define regMPCC2_MPCC_BG_R_CR 0x0049 13301#define regMPCC2_MPCC_BG_R_CR_BASE_IDX 3 13302#define regMPCC2_MPCC_BG_G_Y 0x004a 13303#define regMPCC2_MPCC_BG_G_Y_BASE_IDX 3 13304#define regMPCC2_MPCC_BG_B_CB 0x004b 13305#define regMPCC2_MPCC_BG_B_CB_BASE_IDX 3 13306#define regMPCC2_MPCC_MEM_PWR_CTRL 0x004c 13307#define regMPCC2_MPCC_MEM_PWR_CTRL_BASE_IDX 3 13308#define regMPCC2_MPCC_STATUS 0x004d 13309#define regMPCC2_MPCC_STATUS_BASE_IDX 3 13310 13311 13312// addressBlock: dce_dc_mpc_mpcc3_dispdec 13313// base address: 0x180 13314#define regMPCC3_MPCC_TOP_SEL 0x0060 13315#define regMPCC3_MPCC_TOP_SEL_BASE_IDX 3 13316#define regMPCC3_MPCC_BOT_SEL 0x0061 13317#define regMPCC3_MPCC_BOT_SEL_BASE_IDX 3 13318#define regMPCC3_MPCC_OPP_ID 0x0062 13319#define regMPCC3_MPCC_OPP_ID_BASE_IDX 3 13320#define regMPCC3_MPCC_CONTROL 0x0063 13321#define regMPCC3_MPCC_CONTROL_BASE_IDX 3 13322#define regMPCC3_MPCC_SM_CONTROL 0x0064 13323#define regMPCC3_MPCC_SM_CONTROL_BASE_IDX 3 13324#define regMPCC3_MPCC_UPDATE_LOCK_SEL 0x0065 13325#define regMPCC3_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 13326#define regMPCC3_MPCC_TOP_GAIN 0x0066 13327#define regMPCC3_MPCC_TOP_GAIN_BASE_IDX 3 13328#define regMPCC3_MPCC_BOT_GAIN_INSIDE 0x0067 13329#define regMPCC3_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 13330#define regMPCC3_MPCC_BOT_GAIN_OUTSIDE 0x0068 13331#define regMPCC3_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 13332#define regMPCC3_MPCC_BG_R_CR 0x0069 13333#define regMPCC3_MPCC_BG_R_CR_BASE_IDX 3 13334#define regMPCC3_MPCC_BG_G_Y 0x006a 13335#define regMPCC3_MPCC_BG_G_Y_BASE_IDX 3 13336#define regMPCC3_MPCC_BG_B_CB 0x006b 13337#define regMPCC3_MPCC_BG_B_CB_BASE_IDX 3 13338#define regMPCC3_MPCC_MEM_PWR_CTRL 0x006c 13339#define regMPCC3_MPCC_MEM_PWR_CTRL_BASE_IDX 3 13340#define regMPCC3_MPCC_STATUS 0x006d 13341#define regMPCC3_MPCC_STATUS_BASE_IDX 3 13342 13343 13344// addressBlock: dce_dc_mpc_mpcc_ogam0_dispdec 13345// base address: 0x0 13346#define regMPCC_OGAM0_MPCC_OGAM_CONTROL 0x0100 13347#define regMPCC_OGAM0_MPCC_OGAM_CONTROL_BASE_IDX 3 13348#define regMPCC_OGAM0_MPCC_OGAM_LUT_INDEX 0x0101 13349#define regMPCC_OGAM0_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 13350#define regMPCC_OGAM0_MPCC_OGAM_LUT_DATA 0x0102 13351#define regMPCC_OGAM0_MPCC_OGAM_LUT_DATA_BASE_IDX 3 13352#define regMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL 0x0103 13353#define regMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 13354#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B 0x0104 13355#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 13356#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G 0x0105 13357#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 13358#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R 0x0106 13359#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 13360#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x0107 13361#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 13362#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x0108 13363#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 13364#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x0109 13365#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 13366#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x010a 13367#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 13368#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x010b 13369#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 13370#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x010c 13371#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 13372#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B 0x010d 13373#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 13374#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B 0x010e 13375#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 13376#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G 0x010f 13377#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 13378#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G 0x0110 13379#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 13380#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R 0x0111 13381#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 13382#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R 0x0112 13383#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 13384#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B 0x0113 13385#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 13386#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G 0x0114 13387#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 13388#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R 0x0115 13389#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 13390#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1 0x0116 13391#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 13392#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3 0x0117 13393#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 13394#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5 0x0118 13395#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 13396#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7 0x0119 13397#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 13398#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9 0x011a 13399#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 13400#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11 0x011b 13401#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 13402#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13 0x011c 13403#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 13404#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15 0x011d 13405#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 13406#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17 0x011e 13407#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 13408#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19 0x011f 13409#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 13410#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21 0x0120 13411#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 13412#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23 0x0121 13413#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 13414#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25 0x0122 13415#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 13416#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27 0x0123 13417#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 13418#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29 0x0124 13419#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 13420#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31 0x0125 13421#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 13422#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33 0x0126 13423#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 13424#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B 0x0127 13425#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 13426#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G 0x0128 13427#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 13428#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R 0x0129 13429#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 13430#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x012a 13431#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 13432#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x012b 13433#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 13434#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x012c 13435#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 13436#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x012d 13437#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 13438#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x012e 13439#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 13440#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x012f 13441#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 13442#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B 0x0130 13443#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 13444#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B 0x0131 13445#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 13446#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G 0x0132 13447#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 13448#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G 0x0133 13449#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 13450#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R 0x0134 13451#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 13452#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R 0x0135 13453#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 13454#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B 0x0136 13455#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 13456#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G 0x0137 13457#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 13458#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R 0x0138 13459#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 13460#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1 0x0139 13461#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 13462#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3 0x013a 13463#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 13464#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5 0x013b 13465#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 13466#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7 0x013c 13467#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 13468#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9 0x013d 13469#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 13470#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11 0x013e 13471#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 13472#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13 0x013f 13473#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 13474#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15 0x0140 13475#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 13476#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17 0x0141 13477#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 13478#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19 0x0142 13479#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 13480#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21 0x0143 13481#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 13482#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23 0x0144 13483#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 13484#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25 0x0145 13485#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 13486#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27 0x0146 13487#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 13488#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29 0x0147 13489#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 13490#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31 0x0148 13491#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 13492#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33 0x0149 13493#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 13494#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT 0x014a 13495#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 13496#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE 0x014b 13497#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 13498#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A 0x014c 13499#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 13500#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A 0x014d 13501#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 13502#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A 0x014e 13503#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 13504#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A 0x014f 13505#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 13506#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A 0x0150 13507#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 13508#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A 0x0151 13509#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 13510#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B 0x0152 13511#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 13512#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B 0x0153 13513#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 13514#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B 0x0154 13515#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 13516#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B 0x0155 13517#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 13518#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B 0x0156 13519#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 13520#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B 0x0157 13521#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 13522 13523 13524// addressBlock: dce_dc_mpc_mpcc_ogam1_dispdec 13525// base address: 0x200 13526#define regMPCC_OGAM1_MPCC_OGAM_CONTROL 0x0180 13527#define regMPCC_OGAM1_MPCC_OGAM_CONTROL_BASE_IDX 3 13528#define regMPCC_OGAM1_MPCC_OGAM_LUT_INDEX 0x0181 13529#define regMPCC_OGAM1_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 13530#define regMPCC_OGAM1_MPCC_OGAM_LUT_DATA 0x0182 13531#define regMPCC_OGAM1_MPCC_OGAM_LUT_DATA_BASE_IDX 3 13532#define regMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL 0x0183 13533#define regMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 13534#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B 0x0184 13535#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 13536#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G 0x0185 13537#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 13538#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R 0x0186 13539#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 13540#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x0187 13541#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 13542#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x0188 13543#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 13544#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x0189 13545#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 13546#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x018a 13547#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 13548#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x018b 13549#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 13550#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x018c 13551#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 13552#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B 0x018d 13553#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 13554#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B 0x018e 13555#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 13556#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G 0x018f 13557#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 13558#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G 0x0190 13559#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 13560#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R 0x0191 13561#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 13562#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R 0x0192 13563#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 13564#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B 0x0193 13565#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 13566#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G 0x0194 13567#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 13568#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R 0x0195 13569#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 13570#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1 0x0196 13571#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 13572#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3 0x0197 13573#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 13574#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5 0x0198 13575#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 13576#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7 0x0199 13577#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 13578#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9 0x019a 13579#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 13580#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11 0x019b 13581#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 13582#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13 0x019c 13583#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 13584#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15 0x019d 13585#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 13586#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17 0x019e 13587#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 13588#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19 0x019f 13589#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 13590#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21 0x01a0 13591#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 13592#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23 0x01a1 13593#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 13594#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25 0x01a2 13595#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 13596#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27 0x01a3 13597#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 13598#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29 0x01a4 13599#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 13600#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31 0x01a5 13601#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 13602#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33 0x01a6 13603#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 13604#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B 0x01a7 13605#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 13606#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G 0x01a8 13607#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 13608#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R 0x01a9 13609#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 13610#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x01aa 13611#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 13612#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x01ab 13613#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 13614#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x01ac 13615#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 13616#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x01ad 13617#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 13618#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x01ae 13619#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 13620#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x01af 13621#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 13622#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B 0x01b0 13623#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 13624#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B 0x01b1 13625#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 13626#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G 0x01b2 13627#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 13628#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G 0x01b3 13629#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 13630#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R 0x01b4 13631#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 13632#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R 0x01b5 13633#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 13634#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B 0x01b6 13635#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 13636#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G 0x01b7 13637#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 13638#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R 0x01b8 13639#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 13640#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1 0x01b9 13641#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 13642#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3 0x01ba 13643#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 13644#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5 0x01bb 13645#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 13646#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7 0x01bc 13647#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 13648#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9 0x01bd 13649#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 13650#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11 0x01be 13651#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 13652#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13 0x01bf 13653#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 13654#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15 0x01c0 13655#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 13656#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17 0x01c1 13657#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 13658#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19 0x01c2 13659#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 13660#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21 0x01c3 13661#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 13662#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23 0x01c4 13663#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 13664#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25 0x01c5 13665#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 13666#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27 0x01c6 13667#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 13668#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29 0x01c7 13669#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 13670#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31 0x01c8 13671#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 13672#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33 0x01c9 13673#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 13674#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT 0x01ca 13675#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 13676#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE 0x01cb 13677#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 13678#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A 0x01cc 13679#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 13680#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A 0x01cd 13681#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 13682#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A 0x01ce 13683#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 13684#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A 0x01cf 13685#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 13686#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A 0x01d0 13687#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 13688#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A 0x01d1 13689#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 13690#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B 0x01d2 13691#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 13692#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B 0x01d3 13693#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 13694#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B 0x01d4 13695#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 13696#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B 0x01d5 13697#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 13698#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B 0x01d6 13699#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 13700#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B 0x01d7 13701#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 13702 13703 13704// addressBlock: dce_dc_mpc_mpcc_ogam2_dispdec 13705// base address: 0x400 13706#define regMPCC_OGAM2_MPCC_OGAM_CONTROL 0x0200 13707#define regMPCC_OGAM2_MPCC_OGAM_CONTROL_BASE_IDX 3 13708#define regMPCC_OGAM2_MPCC_OGAM_LUT_INDEX 0x0201 13709#define regMPCC_OGAM2_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 13710#define regMPCC_OGAM2_MPCC_OGAM_LUT_DATA 0x0202 13711#define regMPCC_OGAM2_MPCC_OGAM_LUT_DATA_BASE_IDX 3 13712#define regMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL 0x0203 13713#define regMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 13714#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B 0x0204 13715#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 13716#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G 0x0205 13717#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 13718#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R 0x0206 13719#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 13720#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x0207 13721#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 13722#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x0208 13723#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 13724#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x0209 13725#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 13726#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x020a 13727#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 13728#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x020b 13729#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 13730#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x020c 13731#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 13732#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B 0x020d 13733#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 13734#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B 0x020e 13735#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 13736#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G 0x020f 13737#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 13738#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G 0x0210 13739#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 13740#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R 0x0211 13741#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 13742#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R 0x0212 13743#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 13744#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B 0x0213 13745#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 13746#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G 0x0214 13747#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 13748#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R 0x0215 13749#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 13750#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1 0x0216 13751#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 13752#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3 0x0217 13753#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 13754#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5 0x0218 13755#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 13756#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7 0x0219 13757#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 13758#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9 0x021a 13759#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 13760#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11 0x021b 13761#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 13762#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13 0x021c 13763#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 13764#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15 0x021d 13765#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 13766#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17 0x021e 13767#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 13768#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19 0x021f 13769#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 13770#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21 0x0220 13771#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 13772#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23 0x0221 13773#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 13774#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25 0x0222 13775#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 13776#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27 0x0223 13777#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 13778#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29 0x0224 13779#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 13780#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31 0x0225 13781#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 13782#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33 0x0226 13783#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 13784#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B 0x0227 13785#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 13786#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G 0x0228 13787#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 13788#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R 0x0229 13789#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 13790#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x022a 13791#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 13792#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x022b 13793#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 13794#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x022c 13795#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 13796#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x022d 13797#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 13798#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x022e 13799#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 13800#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x022f 13801#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 13802#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B 0x0230 13803#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 13804#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B 0x0231 13805#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 13806#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G 0x0232 13807#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 13808#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G 0x0233 13809#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 13810#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R 0x0234 13811#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 13812#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R 0x0235 13813#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 13814#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B 0x0236 13815#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 13816#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G 0x0237 13817#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 13818#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R 0x0238 13819#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 13820#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1 0x0239 13821#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 13822#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3 0x023a 13823#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 13824#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5 0x023b 13825#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 13826#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7 0x023c 13827#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 13828#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9 0x023d 13829#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 13830#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11 0x023e 13831#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 13832#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13 0x023f 13833#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 13834#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15 0x0240 13835#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 13836#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17 0x0241 13837#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 13838#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19 0x0242 13839#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 13840#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21 0x0243 13841#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 13842#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23 0x0244 13843#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 13844#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25 0x0245 13845#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 13846#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27 0x0246 13847#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 13848#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29 0x0247 13849#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 13850#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31 0x0248 13851#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 13852#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33 0x0249 13853#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 13854#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT 0x024a 13855#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 13856#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE 0x024b 13857#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 13858#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A 0x024c 13859#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 13860#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A 0x024d 13861#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 13862#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A 0x024e 13863#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 13864#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A 0x024f 13865#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 13866#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A 0x0250 13867#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 13868#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A 0x0251 13869#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 13870#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B 0x0252 13871#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 13872#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B 0x0253 13873#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 13874#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B 0x0254 13875#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 13876#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B 0x0255 13877#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 13878#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B 0x0256 13879#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 13880#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B 0x0257 13881#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 13882 13883 13884// addressBlock: dce_dc_mpc_mpcc_ogam3_dispdec 13885// base address: 0x600 13886#define regMPCC_OGAM3_MPCC_OGAM_CONTROL 0x0280 13887#define regMPCC_OGAM3_MPCC_OGAM_CONTROL_BASE_IDX 3 13888#define regMPCC_OGAM3_MPCC_OGAM_LUT_INDEX 0x0281 13889#define regMPCC_OGAM3_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 13890#define regMPCC_OGAM3_MPCC_OGAM_LUT_DATA 0x0282 13891#define regMPCC_OGAM3_MPCC_OGAM_LUT_DATA_BASE_IDX 3 13892#define regMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL 0x0283 13893#define regMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 13894#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B 0x0284 13895#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 13896#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G 0x0285 13897#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 13898#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R 0x0286 13899#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 13900#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x0287 13901#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 13902#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x0288 13903#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 13904#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x0289 13905#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 13906#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x028a 13907#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 13908#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x028b 13909#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 13910#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x028c 13911#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 13912#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B 0x028d 13913#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 13914#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B 0x028e 13915#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 13916#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G 0x028f 13917#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 13918#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G 0x0290 13919#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 13920#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R 0x0291 13921#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 13922#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R 0x0292 13923#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 13924#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B 0x0293 13925#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 13926#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G 0x0294 13927#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 13928#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R 0x0295 13929#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 13930#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1 0x0296 13931#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 13932#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3 0x0297 13933#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 13934#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5 0x0298 13935#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 13936#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7 0x0299 13937#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 13938#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9 0x029a 13939#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 13940#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11 0x029b 13941#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 13942#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13 0x029c 13943#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 13944#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15 0x029d 13945#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 13946#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17 0x029e 13947#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 13948#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19 0x029f 13949#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 13950#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21 0x02a0 13951#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 13952#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23 0x02a1 13953#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 13954#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25 0x02a2 13955#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 13956#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27 0x02a3 13957#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 13958#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29 0x02a4 13959#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 13960#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31 0x02a5 13961#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 13962#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33 0x02a6 13963#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 13964#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B 0x02a7 13965#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 13966#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G 0x02a8 13967#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 13968#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R 0x02a9 13969#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 13970#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x02aa 13971#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 13972#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x02ab 13973#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 13974#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x02ac 13975#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 13976#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x02ad 13977#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 13978#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x02ae 13979#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 13980#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x02af 13981#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 13982#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B 0x02b0 13983#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 13984#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B 0x02b1 13985#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 13986#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G 0x02b2 13987#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 13988#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G 0x02b3 13989#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 13990#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R 0x02b4 13991#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 13992#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R 0x02b5 13993#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 13994#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B 0x02b6 13995#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 13996#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G 0x02b7 13997#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 13998#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R 0x02b8 13999#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 14000#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1 0x02b9 14001#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 14002#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3 0x02ba 14003#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 14004#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5 0x02bb 14005#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 14006#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7 0x02bc 14007#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 14008#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9 0x02bd 14009#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 14010#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11 0x02be 14011#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 14012#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13 0x02bf 14013#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 14014#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15 0x02c0 14015#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 14016#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17 0x02c1 14017#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 14018#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19 0x02c2 14019#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 14020#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21 0x02c3 14021#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 14022#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23 0x02c4 14023#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 14024#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25 0x02c5 14025#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 14026#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27 0x02c6 14027#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 14028#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29 0x02c7 14029#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 14030#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31 0x02c8 14031#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 14032#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33 0x02c9 14033#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 14034#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT 0x02ca 14035#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 14036#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE 0x02cb 14037#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 14038#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A 0x02cc 14039#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 14040#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A 0x02cd 14041#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 14042#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A 0x02ce 14043#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 14044#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A 0x02cf 14045#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 14046#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A 0x02d0 14047#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 14048#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A 0x02d1 14049#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 14050#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B 0x02d2 14051#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 14052#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B 0x02d3 14053#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 14054#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B 0x02d4 14055#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 14056#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B 0x02d5 14057#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 14058#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B 0x02d6 14059#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 14060#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B 0x02d7 14061#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 14062 14063 14064// addressBlock: dce_dc_mpc_mpc_cfg_dispdec 14065// base address: 0x0 14066#define regMPC_CLOCK_CONTROL 0x0500 14067#define regMPC_CLOCK_CONTROL_BASE_IDX 3 14068#define regMPC_SOFT_RESET 0x0501 14069#define regMPC_SOFT_RESET_BASE_IDX 3 14070#define regMPC_CRC_CTRL 0x0502 14071#define regMPC_CRC_CTRL_BASE_IDX 3 14072#define regMPC_CRC_SEL_CONTROL 0x0503 14073#define regMPC_CRC_SEL_CONTROL_BASE_IDX 3 14074#define regMPC_CRC_RESULT_AR 0x0504 14075#define regMPC_CRC_RESULT_AR_BASE_IDX 3 14076#define regMPC_CRC_RESULT_GB 0x0505 14077#define regMPC_CRC_RESULT_GB_BASE_IDX 3 14078#define regMPC_CRC_RESULT_C 0x0506 14079#define regMPC_CRC_RESULT_C_BASE_IDX 3 14080#define regMPC_PERFMON_EVENT_CTRL 0x0509 14081#define regMPC_PERFMON_EVENT_CTRL_BASE_IDX 3 14082#define regMPC_BYPASS_BG_AR 0x050a 14083#define regMPC_BYPASS_BG_AR_BASE_IDX 3 14084#define regMPC_BYPASS_BG_GB 0x050b 14085#define regMPC_BYPASS_BG_GB_BASE_IDX 3 14086#define regMPC_HOST_READ_CONTROL 0x050c 14087#define regMPC_HOST_READ_CONTROL_BASE_IDX 3 14088#define regMPC_DPP_PENDING_STATUS 0x050d 14089#define regMPC_DPP_PENDING_STATUS_BASE_IDX 3 14090#define regMPC_PENDING_STATUS_MISC 0x050e 14091#define regMPC_PENDING_STATUS_MISC_BASE_IDX 3 14092#define regADR_CFG_CUR_VUPDATE_LOCK_SET0 0x050f 14093#define regADR_CFG_CUR_VUPDATE_LOCK_SET0_BASE_IDX 3 14094#define regADR_CFG_VUPDATE_LOCK_SET0 0x0510 14095#define regADR_CFG_VUPDATE_LOCK_SET0_BASE_IDX 3 14096#define regADR_VUPDATE_LOCK_SET0 0x0511 14097#define regADR_VUPDATE_LOCK_SET0_BASE_IDX 3 14098#define regCFG_VUPDATE_LOCK_SET0 0x0512 14099#define regCFG_VUPDATE_LOCK_SET0_BASE_IDX 3 14100#define regCUR_VUPDATE_LOCK_SET0 0x0513 14101#define regCUR_VUPDATE_LOCK_SET0_BASE_IDX 3 14102#define regADR_CFG_CUR_VUPDATE_LOCK_SET1 0x0514 14103#define regADR_CFG_CUR_VUPDATE_LOCK_SET1_BASE_IDX 3 14104#define regADR_CFG_VUPDATE_LOCK_SET1 0x0515 14105#define regADR_CFG_VUPDATE_LOCK_SET1_BASE_IDX 3 14106#define regADR_VUPDATE_LOCK_SET1 0x0516 14107#define regADR_VUPDATE_LOCK_SET1_BASE_IDX 3 14108#define regCFG_VUPDATE_LOCK_SET1 0x0517 14109#define regCFG_VUPDATE_LOCK_SET1_BASE_IDX 3 14110#define regCUR_VUPDATE_LOCK_SET1 0x0518 14111#define regCUR_VUPDATE_LOCK_SET1_BASE_IDX 3 14112#define regADR_CFG_CUR_VUPDATE_LOCK_SET2 0x0519 14113#define regADR_CFG_CUR_VUPDATE_LOCK_SET2_BASE_IDX 3 14114#define regADR_CFG_VUPDATE_LOCK_SET2 0x051a 14115#define regADR_CFG_VUPDATE_LOCK_SET2_BASE_IDX 3 14116#define regADR_VUPDATE_LOCK_SET2 0x051b 14117#define regADR_VUPDATE_LOCK_SET2_BASE_IDX 3 14118#define regCFG_VUPDATE_LOCK_SET2 0x051c 14119#define regCFG_VUPDATE_LOCK_SET2_BASE_IDX 3 14120#define regCUR_VUPDATE_LOCK_SET2 0x051d 14121#define regCUR_VUPDATE_LOCK_SET2_BASE_IDX 3 14122#define regADR_CFG_CUR_VUPDATE_LOCK_SET3 0x051e 14123#define regADR_CFG_CUR_VUPDATE_LOCK_SET3_BASE_IDX 3 14124#define regADR_CFG_VUPDATE_LOCK_SET3 0x051f 14125#define regADR_CFG_VUPDATE_LOCK_SET3_BASE_IDX 3 14126#define regADR_VUPDATE_LOCK_SET3 0x0520 14127#define regADR_VUPDATE_LOCK_SET3_BASE_IDX 3 14128#define regCFG_VUPDATE_LOCK_SET3 0x0521 14129#define regCFG_VUPDATE_LOCK_SET3_BASE_IDX 3 14130#define regCUR_VUPDATE_LOCK_SET3 0x0522 14131#define regCUR_VUPDATE_LOCK_SET3_BASE_IDX 3 14132#define regMPC_DWB0_MUX 0x055c 14133#define regMPC_DWB0_MUX_BASE_IDX 3 14134 14135 14136// addressBlock: dce_dc_mpc_mpc_ocsc_dispdec 14137// base address: 0x0 14138#define regMPC_OUT0_MUX 0x0580 14139#define regMPC_OUT0_MUX_BASE_IDX 3 14140#define regMPC_OUT0_DENORM_CONTROL 0x0581 14141#define regMPC_OUT0_DENORM_CONTROL_BASE_IDX 3 14142#define regMPC_OUT0_DENORM_CLAMP_G_Y 0x0582 14143#define regMPC_OUT0_DENORM_CLAMP_G_Y_BASE_IDX 3 14144#define regMPC_OUT0_DENORM_CLAMP_B_CB 0x0583 14145#define regMPC_OUT0_DENORM_CLAMP_B_CB_BASE_IDX 3 14146#define regMPC_OUT1_MUX 0x0584 14147#define regMPC_OUT1_MUX_BASE_IDX 3 14148#define regMPC_OUT1_DENORM_CONTROL 0x0585 14149#define regMPC_OUT1_DENORM_CONTROL_BASE_IDX 3 14150#define regMPC_OUT1_DENORM_CLAMP_G_Y 0x0586 14151#define regMPC_OUT1_DENORM_CLAMP_G_Y_BASE_IDX 3 14152#define regMPC_OUT1_DENORM_CLAMP_B_CB 0x0587 14153#define regMPC_OUT1_DENORM_CLAMP_B_CB_BASE_IDX 3 14154#define regMPC_OUT2_MUX 0x0588 14155#define regMPC_OUT2_MUX_BASE_IDX 3 14156#define regMPC_OUT2_DENORM_CONTROL 0x0589 14157#define regMPC_OUT2_DENORM_CONTROL_BASE_IDX 3 14158#define regMPC_OUT2_DENORM_CLAMP_G_Y 0x058a 14159#define regMPC_OUT2_DENORM_CLAMP_G_Y_BASE_IDX 3 14160#define regMPC_OUT2_DENORM_CLAMP_B_CB 0x058b 14161#define regMPC_OUT2_DENORM_CLAMP_B_CB_BASE_IDX 3 14162#define regMPC_OUT3_MUX 0x058c 14163#define regMPC_OUT3_MUX_BASE_IDX 3 14164#define regMPC_OUT3_DENORM_CONTROL 0x058d 14165#define regMPC_OUT3_DENORM_CONTROL_BASE_IDX 3 14166#define regMPC_OUT3_DENORM_CLAMP_G_Y 0x058e 14167#define regMPC_OUT3_DENORM_CLAMP_G_Y_BASE_IDX 3 14168#define regMPC_OUT3_DENORM_CLAMP_B_CB 0x058f 14169#define regMPC_OUT3_DENORM_CLAMP_B_CB_BASE_IDX 3 14170#define regMPC_OUT_CSC_COEF_FORMAT 0x05a0 14171#define regMPC_OUT_CSC_COEF_FORMAT_BASE_IDX 3 14172#define regMPC_OUT0_CSC_MODE 0x05a1 14173#define regMPC_OUT0_CSC_MODE_BASE_IDX 3 14174#define regMPC_OUT0_CSC_C11_C12_A 0x05a2 14175#define regMPC_OUT0_CSC_C11_C12_A_BASE_IDX 3 14176#define regMPC_OUT0_CSC_C13_C14_A 0x05a3 14177#define regMPC_OUT0_CSC_C13_C14_A_BASE_IDX 3 14178#define regMPC_OUT0_CSC_C21_C22_A 0x05a4 14179#define regMPC_OUT0_CSC_C21_C22_A_BASE_IDX 3 14180#define regMPC_OUT0_CSC_C23_C24_A 0x05a5 14181#define regMPC_OUT0_CSC_C23_C24_A_BASE_IDX 3 14182#define regMPC_OUT0_CSC_C31_C32_A 0x05a6 14183#define regMPC_OUT0_CSC_C31_C32_A_BASE_IDX 3 14184#define regMPC_OUT0_CSC_C33_C34_A 0x05a7 14185#define regMPC_OUT0_CSC_C33_C34_A_BASE_IDX 3 14186#define regMPC_OUT0_CSC_C11_C12_B 0x05a8 14187#define regMPC_OUT0_CSC_C11_C12_B_BASE_IDX 3 14188#define regMPC_OUT0_CSC_C13_C14_B 0x05a9 14189#define regMPC_OUT0_CSC_C13_C14_B_BASE_IDX 3 14190#define regMPC_OUT0_CSC_C21_C22_B 0x05aa 14191#define regMPC_OUT0_CSC_C21_C22_B_BASE_IDX 3 14192#define regMPC_OUT0_CSC_C23_C24_B 0x05ab 14193#define regMPC_OUT0_CSC_C23_C24_B_BASE_IDX 3 14194#define regMPC_OUT0_CSC_C31_C32_B 0x05ac 14195#define regMPC_OUT0_CSC_C31_C32_B_BASE_IDX 3 14196#define regMPC_OUT0_CSC_C33_C34_B 0x05ad 14197#define regMPC_OUT0_CSC_C33_C34_B_BASE_IDX 3 14198#define regMPC_OUT1_CSC_MODE 0x05ae 14199#define regMPC_OUT1_CSC_MODE_BASE_IDX 3 14200#define regMPC_OUT1_CSC_C11_C12_A 0x05af 14201#define regMPC_OUT1_CSC_C11_C12_A_BASE_IDX 3 14202#define regMPC_OUT1_CSC_C13_C14_A 0x05b0 14203#define regMPC_OUT1_CSC_C13_C14_A_BASE_IDX 3 14204#define regMPC_OUT1_CSC_C21_C22_A 0x05b1 14205#define regMPC_OUT1_CSC_C21_C22_A_BASE_IDX 3 14206#define regMPC_OUT1_CSC_C23_C24_A 0x05b2 14207#define regMPC_OUT1_CSC_C23_C24_A_BASE_IDX 3 14208#define regMPC_OUT1_CSC_C31_C32_A 0x05b3 14209#define regMPC_OUT1_CSC_C31_C32_A_BASE_IDX 3 14210#define regMPC_OUT1_CSC_C33_C34_A 0x05b4 14211#define regMPC_OUT1_CSC_C33_C34_A_BASE_IDX 3 14212#define regMPC_OUT1_CSC_C11_C12_B 0x05b5 14213#define regMPC_OUT1_CSC_C11_C12_B_BASE_IDX 3 14214#define regMPC_OUT1_CSC_C13_C14_B 0x05b6 14215#define regMPC_OUT1_CSC_C13_C14_B_BASE_IDX 3 14216#define regMPC_OUT1_CSC_C21_C22_B 0x05b7 14217#define regMPC_OUT1_CSC_C21_C22_B_BASE_IDX 3 14218#define regMPC_OUT1_CSC_C23_C24_B 0x05b8 14219#define regMPC_OUT1_CSC_C23_C24_B_BASE_IDX 3 14220#define regMPC_OUT1_CSC_C31_C32_B 0x05b9 14221#define regMPC_OUT1_CSC_C31_C32_B_BASE_IDX 3 14222#define regMPC_OUT1_CSC_C33_C34_B 0x05ba 14223#define regMPC_OUT1_CSC_C33_C34_B_BASE_IDX 3 14224#define regMPC_OUT2_CSC_MODE 0x05bb 14225#define regMPC_OUT2_CSC_MODE_BASE_IDX 3 14226#define regMPC_OUT2_CSC_C11_C12_A 0x05bc 14227#define regMPC_OUT2_CSC_C11_C12_A_BASE_IDX 3 14228#define regMPC_OUT2_CSC_C13_C14_A 0x05bd 14229#define regMPC_OUT2_CSC_C13_C14_A_BASE_IDX 3 14230#define regMPC_OUT2_CSC_C21_C22_A 0x05be 14231#define regMPC_OUT2_CSC_C21_C22_A_BASE_IDX 3 14232#define regMPC_OUT2_CSC_C23_C24_A 0x05bf 14233#define regMPC_OUT2_CSC_C23_C24_A_BASE_IDX 3 14234#define regMPC_OUT2_CSC_C31_C32_A 0x05c0 14235#define regMPC_OUT2_CSC_C31_C32_A_BASE_IDX 3 14236#define regMPC_OUT2_CSC_C33_C34_A 0x05c1 14237#define regMPC_OUT2_CSC_C33_C34_A_BASE_IDX 3 14238#define regMPC_OUT2_CSC_C11_C12_B 0x05c2 14239#define regMPC_OUT2_CSC_C11_C12_B_BASE_IDX 3 14240#define regMPC_OUT2_CSC_C13_C14_B 0x05c3 14241#define regMPC_OUT2_CSC_C13_C14_B_BASE_IDX 3 14242#define regMPC_OUT2_CSC_C21_C22_B 0x05c4 14243#define regMPC_OUT2_CSC_C21_C22_B_BASE_IDX 3 14244#define regMPC_OUT2_CSC_C23_C24_B 0x05c5 14245#define regMPC_OUT2_CSC_C23_C24_B_BASE_IDX 3 14246#define regMPC_OUT2_CSC_C31_C32_B 0x05c6 14247#define regMPC_OUT2_CSC_C31_C32_B_BASE_IDX 3 14248#define regMPC_OUT2_CSC_C33_C34_B 0x05c7 14249#define regMPC_OUT2_CSC_C33_C34_B_BASE_IDX 3 14250#define regMPC_OUT3_CSC_MODE 0x05c8 14251#define regMPC_OUT3_CSC_MODE_BASE_IDX 3 14252#define regMPC_OUT3_CSC_C11_C12_A 0x05c9 14253#define regMPC_OUT3_CSC_C11_C12_A_BASE_IDX 3 14254#define regMPC_OUT3_CSC_C13_C14_A 0x05ca 14255#define regMPC_OUT3_CSC_C13_C14_A_BASE_IDX 3 14256#define regMPC_OUT3_CSC_C21_C22_A 0x05cb 14257#define regMPC_OUT3_CSC_C21_C22_A_BASE_IDX 3 14258#define regMPC_OUT3_CSC_C23_C24_A 0x05cc 14259#define regMPC_OUT3_CSC_C23_C24_A_BASE_IDX 3 14260#define regMPC_OUT3_CSC_C31_C32_A 0x05cd 14261#define regMPC_OUT3_CSC_C31_C32_A_BASE_IDX 3 14262#define regMPC_OUT3_CSC_C33_C34_A 0x05ce 14263#define regMPC_OUT3_CSC_C33_C34_A_BASE_IDX 3 14264#define regMPC_OUT3_CSC_C11_C12_B 0x05cf 14265#define regMPC_OUT3_CSC_C11_C12_B_BASE_IDX 3 14266#define regMPC_OUT3_CSC_C13_C14_B 0x05d0 14267#define regMPC_OUT3_CSC_C13_C14_B_BASE_IDX 3 14268#define regMPC_OUT3_CSC_C21_C22_B 0x05d1 14269#define regMPC_OUT3_CSC_C21_C22_B_BASE_IDX 3 14270#define regMPC_OUT3_CSC_C23_C24_B 0x05d2 14271#define regMPC_OUT3_CSC_C23_C24_B_BASE_IDX 3 14272#define regMPC_OUT3_CSC_C31_C32_B 0x05d3 14273#define regMPC_OUT3_CSC_C31_C32_B_BASE_IDX 3 14274#define regMPC_OUT3_CSC_C33_C34_B 0x05d4 14275#define regMPC_OUT3_CSC_C33_C34_B_BASE_IDX 3 14276 14277 14278// addressBlock: dce_dc_mpc_mpc_rmu_dispdec 14279// base address: 0x0 14280#define regMPC_RMU_CONTROL 0x0680 14281#define regMPC_RMU_CONTROL_BASE_IDX 3 14282#define regMPC_RMU_MEM_PWR_CTRL 0x0681 14283#define regMPC_RMU_MEM_PWR_CTRL_BASE_IDX 3 14284#define regMPC_RMU0_SHAPER_CONTROL 0x0682 14285#define regMPC_RMU0_SHAPER_CONTROL_BASE_IDX 3 14286#define regMPC_RMU0_SHAPER_OFFSET_R 0x0683 14287#define regMPC_RMU0_SHAPER_OFFSET_R_BASE_IDX 3 14288#define regMPC_RMU0_SHAPER_OFFSET_G 0x0684 14289#define regMPC_RMU0_SHAPER_OFFSET_G_BASE_IDX 3 14290#define regMPC_RMU0_SHAPER_OFFSET_B 0x0685 14291#define regMPC_RMU0_SHAPER_OFFSET_B_BASE_IDX 3 14292#define regMPC_RMU0_SHAPER_SCALE_R 0x0686 14293#define regMPC_RMU0_SHAPER_SCALE_R_BASE_IDX 3 14294#define regMPC_RMU0_SHAPER_SCALE_G_B 0x0687 14295#define regMPC_RMU0_SHAPER_SCALE_G_B_BASE_IDX 3 14296#define regMPC_RMU0_SHAPER_LUT_INDEX 0x0688 14297#define regMPC_RMU0_SHAPER_LUT_INDEX_BASE_IDX 3 14298#define regMPC_RMU0_SHAPER_LUT_DATA 0x0689 14299#define regMPC_RMU0_SHAPER_LUT_DATA_BASE_IDX 3 14300#define regMPC_RMU0_SHAPER_LUT_WRITE_EN_MASK 0x068a 14301#define regMPC_RMU0_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3 14302#define regMPC_RMU0_SHAPER_RAMA_START_CNTL_B 0x068b 14303#define regMPC_RMU0_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3 14304#define regMPC_RMU0_SHAPER_RAMA_START_CNTL_G 0x068c 14305#define regMPC_RMU0_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3 14306#define regMPC_RMU0_SHAPER_RAMA_START_CNTL_R 0x068d 14307#define regMPC_RMU0_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3 14308#define regMPC_RMU0_SHAPER_RAMA_END_CNTL_B 0x068e 14309#define regMPC_RMU0_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3 14310#define regMPC_RMU0_SHAPER_RAMA_END_CNTL_G 0x068f 14311#define regMPC_RMU0_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3 14312#define regMPC_RMU0_SHAPER_RAMA_END_CNTL_R 0x0690 14313#define regMPC_RMU0_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3 14314#define regMPC_RMU0_SHAPER_RAMA_REGION_0_1 0x0691 14315#define regMPC_RMU0_SHAPER_RAMA_REGION_0_1_BASE_IDX 3 14316#define regMPC_RMU0_SHAPER_RAMA_REGION_2_3 0x0692 14317#define regMPC_RMU0_SHAPER_RAMA_REGION_2_3_BASE_IDX 3 14318#define regMPC_RMU0_SHAPER_RAMA_REGION_4_5 0x0693 14319#define regMPC_RMU0_SHAPER_RAMA_REGION_4_5_BASE_IDX 3 14320#define regMPC_RMU0_SHAPER_RAMA_REGION_6_7 0x0694 14321#define regMPC_RMU0_SHAPER_RAMA_REGION_6_7_BASE_IDX 3 14322#define regMPC_RMU0_SHAPER_RAMA_REGION_8_9 0x0695 14323#define regMPC_RMU0_SHAPER_RAMA_REGION_8_9_BASE_IDX 3 14324#define regMPC_RMU0_SHAPER_RAMA_REGION_10_11 0x0696 14325#define regMPC_RMU0_SHAPER_RAMA_REGION_10_11_BASE_IDX 3 14326#define regMPC_RMU0_SHAPER_RAMA_REGION_12_13 0x0697 14327#define regMPC_RMU0_SHAPER_RAMA_REGION_12_13_BASE_IDX 3 14328#define regMPC_RMU0_SHAPER_RAMA_REGION_14_15 0x0698 14329#define regMPC_RMU0_SHAPER_RAMA_REGION_14_15_BASE_IDX 3 14330#define regMPC_RMU0_SHAPER_RAMA_REGION_16_17 0x0699 14331#define regMPC_RMU0_SHAPER_RAMA_REGION_16_17_BASE_IDX 3 14332#define regMPC_RMU0_SHAPER_RAMA_REGION_18_19 0x069a 14333#define regMPC_RMU0_SHAPER_RAMA_REGION_18_19_BASE_IDX 3 14334#define regMPC_RMU0_SHAPER_RAMA_REGION_20_21 0x069b 14335#define regMPC_RMU0_SHAPER_RAMA_REGION_20_21_BASE_IDX 3 14336#define regMPC_RMU0_SHAPER_RAMA_REGION_22_23 0x069c 14337#define regMPC_RMU0_SHAPER_RAMA_REGION_22_23_BASE_IDX 3 14338#define regMPC_RMU0_SHAPER_RAMA_REGION_24_25 0x069d 14339#define regMPC_RMU0_SHAPER_RAMA_REGION_24_25_BASE_IDX 3 14340#define regMPC_RMU0_SHAPER_RAMA_REGION_26_27 0x069e 14341#define regMPC_RMU0_SHAPER_RAMA_REGION_26_27_BASE_IDX 3 14342#define regMPC_RMU0_SHAPER_RAMA_REGION_28_29 0x069f 14343#define regMPC_RMU0_SHAPER_RAMA_REGION_28_29_BASE_IDX 3 14344#define regMPC_RMU0_SHAPER_RAMA_REGION_30_31 0x06a0 14345#define regMPC_RMU0_SHAPER_RAMA_REGION_30_31_BASE_IDX 3 14346#define regMPC_RMU0_SHAPER_RAMA_REGION_32_33 0x06a1 14347#define regMPC_RMU0_SHAPER_RAMA_REGION_32_33_BASE_IDX 3 14348#define regMPC_RMU0_SHAPER_RAMB_START_CNTL_B 0x06a2 14349#define regMPC_RMU0_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3 14350#define regMPC_RMU0_SHAPER_RAMB_START_CNTL_G 0x06a3 14351#define regMPC_RMU0_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3 14352#define regMPC_RMU0_SHAPER_RAMB_START_CNTL_R 0x06a4 14353#define regMPC_RMU0_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3 14354#define regMPC_RMU0_SHAPER_RAMB_END_CNTL_B 0x06a5 14355#define regMPC_RMU0_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3 14356#define regMPC_RMU0_SHAPER_RAMB_END_CNTL_G 0x06a6 14357#define regMPC_RMU0_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3 14358#define regMPC_RMU0_SHAPER_RAMB_END_CNTL_R 0x06a7 14359#define regMPC_RMU0_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3 14360#define regMPC_RMU0_SHAPER_RAMB_REGION_0_1 0x06a8 14361#define regMPC_RMU0_SHAPER_RAMB_REGION_0_1_BASE_IDX 3 14362#define regMPC_RMU0_SHAPER_RAMB_REGION_2_3 0x06a9 14363#define regMPC_RMU0_SHAPER_RAMB_REGION_2_3_BASE_IDX 3 14364#define regMPC_RMU0_SHAPER_RAMB_REGION_4_5 0x06aa 14365#define regMPC_RMU0_SHAPER_RAMB_REGION_4_5_BASE_IDX 3 14366#define regMPC_RMU0_SHAPER_RAMB_REGION_6_7 0x06ab 14367#define regMPC_RMU0_SHAPER_RAMB_REGION_6_7_BASE_IDX 3 14368#define regMPC_RMU0_SHAPER_RAMB_REGION_8_9 0x06ac 14369#define regMPC_RMU0_SHAPER_RAMB_REGION_8_9_BASE_IDX 3 14370#define regMPC_RMU0_SHAPER_RAMB_REGION_10_11 0x06ad 14371#define regMPC_RMU0_SHAPER_RAMB_REGION_10_11_BASE_IDX 3 14372#define regMPC_RMU0_SHAPER_RAMB_REGION_12_13 0x06ae 14373#define regMPC_RMU0_SHAPER_RAMB_REGION_12_13_BASE_IDX 3 14374#define regMPC_RMU0_SHAPER_RAMB_REGION_14_15 0x06af 14375#define regMPC_RMU0_SHAPER_RAMB_REGION_14_15_BASE_IDX 3 14376#define regMPC_RMU0_SHAPER_RAMB_REGION_16_17 0x06b0 14377#define regMPC_RMU0_SHAPER_RAMB_REGION_16_17_BASE_IDX 3 14378#define regMPC_RMU0_SHAPER_RAMB_REGION_18_19 0x06b1 14379#define regMPC_RMU0_SHAPER_RAMB_REGION_18_19_BASE_IDX 3 14380#define regMPC_RMU0_SHAPER_RAMB_REGION_20_21 0x06b2 14381#define regMPC_RMU0_SHAPER_RAMB_REGION_20_21_BASE_IDX 3 14382#define regMPC_RMU0_SHAPER_RAMB_REGION_22_23 0x06b3 14383#define regMPC_RMU0_SHAPER_RAMB_REGION_22_23_BASE_IDX 3 14384#define regMPC_RMU0_SHAPER_RAMB_REGION_24_25 0x06b4 14385#define regMPC_RMU0_SHAPER_RAMB_REGION_24_25_BASE_IDX 3 14386#define regMPC_RMU0_SHAPER_RAMB_REGION_26_27 0x06b5 14387#define regMPC_RMU0_SHAPER_RAMB_REGION_26_27_BASE_IDX 3 14388#define regMPC_RMU0_SHAPER_RAMB_REGION_28_29 0x06b6 14389#define regMPC_RMU0_SHAPER_RAMB_REGION_28_29_BASE_IDX 3 14390#define regMPC_RMU0_SHAPER_RAMB_REGION_30_31 0x06b7 14391#define regMPC_RMU0_SHAPER_RAMB_REGION_30_31_BASE_IDX 3 14392#define regMPC_RMU0_SHAPER_RAMB_REGION_32_33 0x06b8 14393#define regMPC_RMU0_SHAPER_RAMB_REGION_32_33_BASE_IDX 3 14394#define regMPC_RMU0_3DLUT_MODE 0x06b9 14395#define regMPC_RMU0_3DLUT_MODE_BASE_IDX 3 14396#define regMPC_RMU0_3DLUT_INDEX 0x06ba 14397#define regMPC_RMU0_3DLUT_INDEX_BASE_IDX 3 14398#define regMPC_RMU0_3DLUT_DATA 0x06bb 14399#define regMPC_RMU0_3DLUT_DATA_BASE_IDX 3 14400#define regMPC_RMU0_3DLUT_DATA_30BIT 0x06bc 14401#define regMPC_RMU0_3DLUT_DATA_30BIT_BASE_IDX 3 14402#define regMPC_RMU0_3DLUT_READ_WRITE_CONTROL 0x06bd 14403#define regMPC_RMU0_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3 14404#define regMPC_RMU0_3DLUT_OUT_NORM_FACTOR 0x06be 14405#define regMPC_RMU0_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3 14406#define regMPC_RMU0_3DLUT_OUT_OFFSET_R 0x06bf 14407#define regMPC_RMU0_3DLUT_OUT_OFFSET_R_BASE_IDX 3 14408#define regMPC_RMU0_3DLUT_OUT_OFFSET_G 0x06c0 14409#define regMPC_RMU0_3DLUT_OUT_OFFSET_G_BASE_IDX 3 14410#define regMPC_RMU0_3DLUT_OUT_OFFSET_B 0x06c1 14411#define regMPC_RMU0_3DLUT_OUT_OFFSET_B_BASE_IDX 3 14412#define regMPC_RMU1_SHAPER_CONTROL 0x06c2 14413#define regMPC_RMU1_SHAPER_CONTROL_BASE_IDX 3 14414#define regMPC_RMU1_SHAPER_OFFSET_R 0x06c3 14415#define regMPC_RMU1_SHAPER_OFFSET_R_BASE_IDX 3 14416#define regMPC_RMU1_SHAPER_OFFSET_G 0x06c4 14417#define regMPC_RMU1_SHAPER_OFFSET_G_BASE_IDX 3 14418#define regMPC_RMU1_SHAPER_OFFSET_B 0x06c5 14419#define regMPC_RMU1_SHAPER_OFFSET_B_BASE_IDX 3 14420#define regMPC_RMU1_SHAPER_SCALE_R 0x06c6 14421#define regMPC_RMU1_SHAPER_SCALE_R_BASE_IDX 3 14422#define regMPC_RMU1_SHAPER_SCALE_G_B 0x06c7 14423#define regMPC_RMU1_SHAPER_SCALE_G_B_BASE_IDX 3 14424#define regMPC_RMU1_SHAPER_LUT_INDEX 0x06c8 14425#define regMPC_RMU1_SHAPER_LUT_INDEX_BASE_IDX 3 14426#define regMPC_RMU1_SHAPER_LUT_DATA 0x06c9 14427#define regMPC_RMU1_SHAPER_LUT_DATA_BASE_IDX 3 14428#define regMPC_RMU1_SHAPER_LUT_WRITE_EN_MASK 0x06ca 14429#define regMPC_RMU1_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3 14430#define regMPC_RMU1_SHAPER_RAMA_START_CNTL_B 0x06cb 14431#define regMPC_RMU1_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3 14432#define regMPC_RMU1_SHAPER_RAMA_START_CNTL_G 0x06cc 14433#define regMPC_RMU1_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3 14434#define regMPC_RMU1_SHAPER_RAMA_START_CNTL_R 0x06cd 14435#define regMPC_RMU1_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3 14436#define regMPC_RMU1_SHAPER_RAMA_END_CNTL_B 0x06ce 14437#define regMPC_RMU1_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3 14438#define regMPC_RMU1_SHAPER_RAMA_END_CNTL_G 0x06cf 14439#define regMPC_RMU1_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3 14440#define regMPC_RMU1_SHAPER_RAMA_END_CNTL_R 0x06d0 14441#define regMPC_RMU1_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3 14442#define regMPC_RMU1_SHAPER_RAMA_REGION_0_1 0x06d1 14443#define regMPC_RMU1_SHAPER_RAMA_REGION_0_1_BASE_IDX 3 14444#define regMPC_RMU1_SHAPER_RAMA_REGION_2_3 0x06d2 14445#define regMPC_RMU1_SHAPER_RAMA_REGION_2_3_BASE_IDX 3 14446#define regMPC_RMU1_SHAPER_RAMA_REGION_4_5 0x06d3 14447#define regMPC_RMU1_SHAPER_RAMA_REGION_4_5_BASE_IDX 3 14448#define regMPC_RMU1_SHAPER_RAMA_REGION_6_7 0x06d4 14449#define regMPC_RMU1_SHAPER_RAMA_REGION_6_7_BASE_IDX 3 14450#define regMPC_RMU1_SHAPER_RAMA_REGION_8_9 0x06d5 14451#define regMPC_RMU1_SHAPER_RAMA_REGION_8_9_BASE_IDX 3 14452#define regMPC_RMU1_SHAPER_RAMA_REGION_10_11 0x06d6 14453#define regMPC_RMU1_SHAPER_RAMA_REGION_10_11_BASE_IDX 3 14454#define regMPC_RMU1_SHAPER_RAMA_REGION_12_13 0x06d7 14455#define regMPC_RMU1_SHAPER_RAMA_REGION_12_13_BASE_IDX 3 14456#define regMPC_RMU1_SHAPER_RAMA_REGION_14_15 0x06d8 14457#define regMPC_RMU1_SHAPER_RAMA_REGION_14_15_BASE_IDX 3 14458#define regMPC_RMU1_SHAPER_RAMA_REGION_16_17 0x06d9 14459#define regMPC_RMU1_SHAPER_RAMA_REGION_16_17_BASE_IDX 3 14460#define regMPC_RMU1_SHAPER_RAMA_REGION_18_19 0x06da 14461#define regMPC_RMU1_SHAPER_RAMA_REGION_18_19_BASE_IDX 3 14462#define regMPC_RMU1_SHAPER_RAMA_REGION_20_21 0x06db 14463#define regMPC_RMU1_SHAPER_RAMA_REGION_20_21_BASE_IDX 3 14464#define regMPC_RMU1_SHAPER_RAMA_REGION_22_23 0x06dc 14465#define regMPC_RMU1_SHAPER_RAMA_REGION_22_23_BASE_IDX 3 14466#define regMPC_RMU1_SHAPER_RAMA_REGION_24_25 0x06dd 14467#define regMPC_RMU1_SHAPER_RAMA_REGION_24_25_BASE_IDX 3 14468#define regMPC_RMU1_SHAPER_RAMA_REGION_26_27 0x06de 14469#define regMPC_RMU1_SHAPER_RAMA_REGION_26_27_BASE_IDX 3 14470#define regMPC_RMU1_SHAPER_RAMA_REGION_28_29 0x06df 14471#define regMPC_RMU1_SHAPER_RAMA_REGION_28_29_BASE_IDX 3 14472#define regMPC_RMU1_SHAPER_RAMA_REGION_30_31 0x06e0 14473#define regMPC_RMU1_SHAPER_RAMA_REGION_30_31_BASE_IDX 3 14474#define regMPC_RMU1_SHAPER_RAMA_REGION_32_33 0x06e1 14475#define regMPC_RMU1_SHAPER_RAMA_REGION_32_33_BASE_IDX 3 14476#define regMPC_RMU1_SHAPER_RAMB_START_CNTL_B 0x06e2 14477#define regMPC_RMU1_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3 14478#define regMPC_RMU1_SHAPER_RAMB_START_CNTL_G 0x06e3 14479#define regMPC_RMU1_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3 14480#define regMPC_RMU1_SHAPER_RAMB_START_CNTL_R 0x06e4 14481#define regMPC_RMU1_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3 14482#define regMPC_RMU1_SHAPER_RAMB_END_CNTL_B 0x06e5 14483#define regMPC_RMU1_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3 14484#define regMPC_RMU1_SHAPER_RAMB_END_CNTL_G 0x06e6 14485#define regMPC_RMU1_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3 14486#define regMPC_RMU1_SHAPER_RAMB_END_CNTL_R 0x06e7 14487#define regMPC_RMU1_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3 14488#define regMPC_RMU1_SHAPER_RAMB_REGION_0_1 0x06e8 14489#define regMPC_RMU1_SHAPER_RAMB_REGION_0_1_BASE_IDX 3 14490#define regMPC_RMU1_SHAPER_RAMB_REGION_2_3 0x06e9 14491#define regMPC_RMU1_SHAPER_RAMB_REGION_2_3_BASE_IDX 3 14492#define regMPC_RMU1_SHAPER_RAMB_REGION_4_5 0x06ea 14493#define regMPC_RMU1_SHAPER_RAMB_REGION_4_5_BASE_IDX 3 14494#define regMPC_RMU1_SHAPER_RAMB_REGION_6_7 0x06eb 14495#define regMPC_RMU1_SHAPER_RAMB_REGION_6_7_BASE_IDX 3 14496#define regMPC_RMU1_SHAPER_RAMB_REGION_8_9 0x06ec 14497#define regMPC_RMU1_SHAPER_RAMB_REGION_8_9_BASE_IDX 3 14498#define regMPC_RMU1_SHAPER_RAMB_REGION_10_11 0x06ed 14499#define regMPC_RMU1_SHAPER_RAMB_REGION_10_11_BASE_IDX 3 14500#define regMPC_RMU1_SHAPER_RAMB_REGION_12_13 0x06ee 14501#define regMPC_RMU1_SHAPER_RAMB_REGION_12_13_BASE_IDX 3 14502#define regMPC_RMU1_SHAPER_RAMB_REGION_14_15 0x06ef 14503#define regMPC_RMU1_SHAPER_RAMB_REGION_14_15_BASE_IDX 3 14504#define regMPC_RMU1_SHAPER_RAMB_REGION_16_17 0x06f0 14505#define regMPC_RMU1_SHAPER_RAMB_REGION_16_17_BASE_IDX 3 14506#define regMPC_RMU1_SHAPER_RAMB_REGION_18_19 0x06f1 14507#define regMPC_RMU1_SHAPER_RAMB_REGION_18_19_BASE_IDX 3 14508#define regMPC_RMU1_SHAPER_RAMB_REGION_20_21 0x06f2 14509#define regMPC_RMU1_SHAPER_RAMB_REGION_20_21_BASE_IDX 3 14510#define regMPC_RMU1_SHAPER_RAMB_REGION_22_23 0x06f3 14511#define regMPC_RMU1_SHAPER_RAMB_REGION_22_23_BASE_IDX 3 14512#define regMPC_RMU1_SHAPER_RAMB_REGION_24_25 0x06f4 14513#define regMPC_RMU1_SHAPER_RAMB_REGION_24_25_BASE_IDX 3 14514#define regMPC_RMU1_SHAPER_RAMB_REGION_26_27 0x06f5 14515#define regMPC_RMU1_SHAPER_RAMB_REGION_26_27_BASE_IDX 3 14516#define regMPC_RMU1_SHAPER_RAMB_REGION_28_29 0x06f6 14517#define regMPC_RMU1_SHAPER_RAMB_REGION_28_29_BASE_IDX 3 14518#define regMPC_RMU1_SHAPER_RAMB_REGION_30_31 0x06f7 14519#define regMPC_RMU1_SHAPER_RAMB_REGION_30_31_BASE_IDX 3 14520#define regMPC_RMU1_SHAPER_RAMB_REGION_32_33 0x06f8 14521#define regMPC_RMU1_SHAPER_RAMB_REGION_32_33_BASE_IDX 3 14522#define regMPC_RMU1_3DLUT_MODE 0x06f9 14523#define regMPC_RMU1_3DLUT_MODE_BASE_IDX 3 14524#define regMPC_RMU1_3DLUT_INDEX 0x06fa 14525#define regMPC_RMU1_3DLUT_INDEX_BASE_IDX 3 14526#define regMPC_RMU1_3DLUT_DATA 0x06fb 14527#define regMPC_RMU1_3DLUT_DATA_BASE_IDX 3 14528#define regMPC_RMU1_3DLUT_DATA_30BIT 0x06fc 14529#define regMPC_RMU1_3DLUT_DATA_30BIT_BASE_IDX 3 14530#define regMPC_RMU1_3DLUT_READ_WRITE_CONTROL 0x06fd 14531#define regMPC_RMU1_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3 14532#define regMPC_RMU1_3DLUT_OUT_NORM_FACTOR 0x06fe 14533#define regMPC_RMU1_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3 14534#define regMPC_RMU1_3DLUT_OUT_OFFSET_R 0x06ff 14535#define regMPC_RMU1_3DLUT_OUT_OFFSET_R_BASE_IDX 3 14536#define regMPC_RMU1_3DLUT_OUT_OFFSET_G 0x0700 14537#define regMPC_RMU1_3DLUT_OUT_OFFSET_G_BASE_IDX 3 14538#define regMPC_RMU1_3DLUT_OUT_OFFSET_B 0x0701 14539#define regMPC_RMU1_3DLUT_OUT_OFFSET_B_BASE_IDX 3 14540 14541 14542// addressBlock: dce_dc_mpc_mpc_dcperfmon_dc_perfmon_dispdec 14543// base address: 0x1901c 14544#define regDC_PERFMON22_PERFCOUNTER_CNTL 0x08c7 14545#define regDC_PERFMON22_PERFCOUNTER_CNTL_BASE_IDX 3 14546#define regDC_PERFMON22_PERFCOUNTER_CNTL2 0x08c8 14547#define regDC_PERFMON22_PERFCOUNTER_CNTL2_BASE_IDX 3 14548#define regDC_PERFMON22_PERFCOUNTER_STATE 0x08c9 14549#define regDC_PERFMON22_PERFCOUNTER_STATE_BASE_IDX 3 14550#define regDC_PERFMON22_PERFMON_CNTL 0x08ca 14551#define regDC_PERFMON22_PERFMON_CNTL_BASE_IDX 3 14552#define regDC_PERFMON22_PERFMON_CNTL2 0x08cb 14553#define regDC_PERFMON22_PERFMON_CNTL2_BASE_IDX 3 14554#define regDC_PERFMON22_PERFMON_CVALUE_INT_MISC 0x08cc 14555#define regDC_PERFMON22_PERFMON_CVALUE_INT_MISC_BASE_IDX 3 14556#define regDC_PERFMON22_PERFMON_CVALUE_LOW 0x08cd 14557#define regDC_PERFMON22_PERFMON_CVALUE_LOW_BASE_IDX 3 14558#define regDC_PERFMON22_PERFMON_HI 0x08ce 14559#define regDC_PERFMON22_PERFMON_HI_BASE_IDX 3 14560#define regDC_PERFMON22_PERFMON_LOW 0x08cf 14561#define regDC_PERFMON22_PERFMON_LOW_BASE_IDX 3 14562 14563 14564// addressBlock: dce_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec 14565// base address: 0x2646c 14566#define regAFMT5_AFMT_VBI_PACKET_CONTROL 0x091c 14567#define regAFMT5_AFMT_VBI_PACKET_CONTROL_BASE_IDX 3 14568#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL2 0x091d 14569#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 3 14570#define regAFMT5_AFMT_AUDIO_INFO0 0x091e 14571#define regAFMT5_AFMT_AUDIO_INFO0_BASE_IDX 3 14572#define regAFMT5_AFMT_AUDIO_INFO1 0x091f 14573#define regAFMT5_AFMT_AUDIO_INFO1_BASE_IDX 3 14574#define regAFMT5_AFMT_60958_0 0x0920 14575#define regAFMT5_AFMT_60958_0_BASE_IDX 3 14576#define regAFMT5_AFMT_60958_1 0x0921 14577#define regAFMT5_AFMT_60958_1_BASE_IDX 3 14578#define regAFMT5_AFMT_AUDIO_CRC_CONTROL 0x0922 14579#define regAFMT5_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 3 14580#define regAFMT5_AFMT_RAMP_CONTROL0 0x0923 14581#define regAFMT5_AFMT_RAMP_CONTROL0_BASE_IDX 3 14582#define regAFMT5_AFMT_RAMP_CONTROL1 0x0924 14583#define regAFMT5_AFMT_RAMP_CONTROL1_BASE_IDX 3 14584#define regAFMT5_AFMT_RAMP_CONTROL2 0x0925 14585#define regAFMT5_AFMT_RAMP_CONTROL2_BASE_IDX 3 14586#define regAFMT5_AFMT_RAMP_CONTROL3 0x0926 14587#define regAFMT5_AFMT_RAMP_CONTROL3_BASE_IDX 3 14588#define regAFMT5_AFMT_60958_2 0x0927 14589#define regAFMT5_AFMT_60958_2_BASE_IDX 3 14590#define regAFMT5_AFMT_AUDIO_CRC_RESULT 0x0928 14591#define regAFMT5_AFMT_AUDIO_CRC_RESULT_BASE_IDX 3 14592#define regAFMT5_AFMT_STATUS 0x0929 14593#define regAFMT5_AFMT_STATUS_BASE_IDX 3 14594#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL 0x092a 14595#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 3 14596#define regAFMT5_AFMT_INFOFRAME_CONTROL0 0x092b 14597#define regAFMT5_AFMT_INFOFRAME_CONTROL0_BASE_IDX 3 14598#define regAFMT5_AFMT_INTERRUPT_STATUS 0x092c 14599#define regAFMT5_AFMT_INTERRUPT_STATUS_BASE_IDX 3 14600#define regAFMT5_AFMT_AUDIO_SRC_CONTROL 0x092d 14601#define regAFMT5_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 3 14602#define regAFMT5_AFMT_MEM_PWR 0x092f 14603#define regAFMT5_AFMT_MEM_PWR_BASE_IDX 3 14604 14605 14606// addressBlock: dce_dc_hpo_hdmi_stream_enc0_vpg_vpg_dispdec 14607// base address: 0x264c4 14608#define regVPG9_VPG_GENERIC_PACKET_ACCESS_CTRL 0x0931 14609#define regVPG9_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 3 14610#define regVPG9_VPG_GENERIC_PACKET_DATA 0x0932 14611#define regVPG9_VPG_GENERIC_PACKET_DATA_BASE_IDX 3 14612#define regVPG9_VPG_GSP_FRAME_UPDATE_CTRL 0x0933 14613#define regVPG9_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 3 14614#define regVPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x0934 14615#define regVPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 3 14616#define regVPG9_VPG_GENERIC_STATUS 0x0935 14617#define regVPG9_VPG_GENERIC_STATUS_BASE_IDX 3 14618#define regVPG9_VPG_MEM_PWR 0x0936 14619#define regVPG9_VPG_MEM_PWR_BASE_IDX 3 14620#define regVPG9_VPG_ISRC1_2_ACCESS_CTRL 0x0937 14621#define regVPG9_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 3 14622#define regVPG9_VPG_ISRC1_2_DATA 0x0938 14623#define regVPG9_VPG_ISRC1_2_DATA_BASE_IDX 3 14624#define regVPG9_VPG_MPEG_INFO0 0x0939 14625#define regVPG9_VPG_MPEG_INFO0_BASE_IDX 3 14626#define regVPG9_VPG_MPEG_INFO1 0x093a 14627#define regVPG9_VPG_MPEG_INFO1_BASE_IDX 3 14628 14629 14630// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dme_dme_dispdec 14631// base address: 0x264f0 14632#define regDME9_DME_CONTROL 0x093c 14633#define regDME9_DME_CONTROL_BASE_IDX 3 14634#define regDME9_DME_MEMORY_CONTROL 0x093d 14635#define regDME9_DME_MEMORY_CONTROL_BASE_IDX 3 14636 14637 14638// addressBlock: dce_dc_hpo_hpo_top_dispdec 14639// base address: 0x2790c 14640#define regHPO_TOP_CLOCK_CONTROL 0x0e43 14641#define regHPO_TOP_CLOCK_CONTROL_BASE_IDX 3 14642#define regHPO_TOP_HW_CONTROL 0x0e4a 14643#define regHPO_TOP_HW_CONTROL_BASE_IDX 3 14644 14645 14646// addressBlock: dce_dc_hpo_dp_stream_mapper_dispdec 14647// base address: 0x27958 14648#define regDP_STREAM_MAPPER_CONTROL0 0x0e56 14649#define regDP_STREAM_MAPPER_CONTROL0_BASE_IDX 3 14650#define regDP_STREAM_MAPPER_CONTROL1 0x0e57 14651#define regDP_STREAM_MAPPER_CONTROL1_BASE_IDX 3 14652#define regDP_STREAM_MAPPER_CONTROL2 0x0e58 14653#define regDP_STREAM_MAPPER_CONTROL2_BASE_IDX 3 14654#define regDP_STREAM_MAPPER_CONTROL3 0x0e59 14655#define regDP_STREAM_MAPPER_CONTROL3_BASE_IDX 3 14656 14657 14658// addressBlock: dce_dc_hpo_hpo_dcperfmon_dc_perfmon_dispdec 14659// base address: 0x1a698 14660#define regDC_PERFMON23_PERFCOUNTER_CNTL 0x0e66 14661#define regDC_PERFMON23_PERFCOUNTER_CNTL_BASE_IDX 3 14662#define regDC_PERFMON23_PERFCOUNTER_CNTL2 0x0e67 14663#define regDC_PERFMON23_PERFCOUNTER_CNTL2_BASE_IDX 3 14664#define regDC_PERFMON23_PERFCOUNTER_STATE 0x0e68 14665#define regDC_PERFMON23_PERFCOUNTER_STATE_BASE_IDX 3 14666#define regDC_PERFMON23_PERFMON_CNTL 0x0e69 14667#define regDC_PERFMON23_PERFMON_CNTL_BASE_IDX 3 14668#define regDC_PERFMON23_PERFMON_CNTL2 0x0e6a 14669#define regDC_PERFMON23_PERFMON_CNTL2_BASE_IDX 3 14670#define regDC_PERFMON23_PERFMON_CVALUE_INT_MISC 0x0e6b 14671#define regDC_PERFMON23_PERFMON_CVALUE_INT_MISC_BASE_IDX 3 14672#define regDC_PERFMON23_PERFMON_CVALUE_LOW 0x0e6c 14673#define regDC_PERFMON23_PERFMON_CVALUE_LOW_BASE_IDX 3 14674#define regDC_PERFMON23_PERFMON_HI 0x0e6d 14675#define regDC_PERFMON23_PERFMON_HI_BASE_IDX 3 14676#define regDC_PERFMON23_PERFMON_LOW 0x0e6e 14677#define regDC_PERFMON23_PERFMON_LOW_BASE_IDX 3 14678 14679 14680// addressBlock: dce_dc_opp_abm0_dispdec 14681// base address: 0x0 14682#define regABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0e7a 14683#define regABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 14684#define regABM0_BL1_PWM_USER_LEVEL 0x0e7b 14685#define regABM0_BL1_PWM_USER_LEVEL_BASE_IDX 3 14686#define regABM0_BL1_PWM_TARGET_ABM_LEVEL 0x0e7c 14687#define regABM0_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 14688#define regABM0_BL1_PWM_CURRENT_ABM_LEVEL 0x0e7d 14689#define regABM0_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 14690#define regABM0_BL1_PWM_FINAL_DUTY_CYCLE 0x0e7e 14691#define regABM0_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 14692#define regABM0_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0e7f 14693#define regABM0_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 14694#define regABM0_BL1_PWM_ABM_CNTL 0x0e80 14695#define regABM0_BL1_PWM_ABM_CNTL_BASE_IDX 3 14696#define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0e81 14697#define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 14698#define regABM0_BL1_PWM_GRP2_REG_LOCK 0x0e82 14699#define regABM0_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 14700#define regABM0_DC_ABM1_CNTL 0x0e83 14701#define regABM0_DC_ABM1_CNTL_BASE_IDX 3 14702#define regABM0_DC_ABM1_IPCSC_COEFF_SEL 0x0e84 14703#define regABM0_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 14704#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0e85 14705#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 14706#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0e86 14707#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 14708#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0e87 14709#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 14710#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0e88 14711#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 14712#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0e89 14713#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 14714#define regABM0_DC_ABM1_ACE_THRES_12 0x0e8a 14715#define regABM0_DC_ABM1_ACE_THRES_12_BASE_IDX 3 14716#define regABM0_DC_ABM1_ACE_THRES_34 0x0e8b 14717#define regABM0_DC_ABM1_ACE_THRES_34_BASE_IDX 3 14718#define regABM0_DC_ABM1_ACE_CNTL_MISC 0x0e8c 14719#define regABM0_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 14720#define regABM0_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0e8e 14721#define regABM0_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 14722#define regABM0_DC_ABM1_HG_MISC_CTRL 0x0e8f 14723#define regABM0_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 14724#define regABM0_DC_ABM1_LS_SUM_OF_LUMA 0x0e90 14725#define regABM0_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 14726#define regABM0_DC_ABM1_LS_MIN_MAX_LUMA 0x0e91 14727#define regABM0_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 14728#define regABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0e92 14729#define regABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 14730#define regABM0_DC_ABM1_LS_PIXEL_COUNT 0x0e93 14731#define regABM0_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 14732#define regABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0e94 14733#define regABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 14734#define regABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0e95 14735#define regABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 14736#define regABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0e96 14737#define regABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 14738#define regABM0_DC_ABM1_HG_SAMPLE_RATE 0x0e97 14739#define regABM0_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 14740#define regABM0_DC_ABM1_LS_SAMPLE_RATE 0x0e98 14741#define regABM0_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 14742#define regABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0e99 14743#define regABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 14744#define regABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0e9a 14745#define regABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 14746#define regABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0e9b 14747#define regABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 14748#define regABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0e9c 14749#define regABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 14750#define regABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0e9d 14751#define regABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 14752#define regABM0_DC_ABM1_HG_RESULT_1 0x0e9e 14753#define regABM0_DC_ABM1_HG_RESULT_1_BASE_IDX 3 14754#define regABM0_DC_ABM1_HG_RESULT_2 0x0e9f 14755#define regABM0_DC_ABM1_HG_RESULT_2_BASE_IDX 3 14756#define regABM0_DC_ABM1_HG_RESULT_3 0x0ea0 14757#define regABM0_DC_ABM1_HG_RESULT_3_BASE_IDX 3 14758#define regABM0_DC_ABM1_HG_RESULT_4 0x0ea1 14759#define regABM0_DC_ABM1_HG_RESULT_4_BASE_IDX 3 14760#define regABM0_DC_ABM1_HG_RESULT_5 0x0ea2 14761#define regABM0_DC_ABM1_HG_RESULT_5_BASE_IDX 3 14762#define regABM0_DC_ABM1_HG_RESULT_6 0x0ea3 14763#define regABM0_DC_ABM1_HG_RESULT_6_BASE_IDX 3 14764#define regABM0_DC_ABM1_HG_RESULT_7 0x0ea4 14765#define regABM0_DC_ABM1_HG_RESULT_7_BASE_IDX 3 14766#define regABM0_DC_ABM1_HG_RESULT_8 0x0ea5 14767#define regABM0_DC_ABM1_HG_RESULT_8_BASE_IDX 3 14768#define regABM0_DC_ABM1_HG_RESULT_9 0x0ea6 14769#define regABM0_DC_ABM1_HG_RESULT_9_BASE_IDX 3 14770#define regABM0_DC_ABM1_HG_RESULT_10 0x0ea7 14771#define regABM0_DC_ABM1_HG_RESULT_10_BASE_IDX 3 14772#define regABM0_DC_ABM1_HG_RESULT_11 0x0ea8 14773#define regABM0_DC_ABM1_HG_RESULT_11_BASE_IDX 3 14774#define regABM0_DC_ABM1_HG_RESULT_12 0x0ea9 14775#define regABM0_DC_ABM1_HG_RESULT_12_BASE_IDX 3 14776#define regABM0_DC_ABM1_HG_RESULT_13 0x0eaa 14777#define regABM0_DC_ABM1_HG_RESULT_13_BASE_IDX 3 14778#define regABM0_DC_ABM1_HG_RESULT_14 0x0eab 14779#define regABM0_DC_ABM1_HG_RESULT_14_BASE_IDX 3 14780#define regABM0_DC_ABM1_HG_RESULT_15 0x0eac 14781#define regABM0_DC_ABM1_HG_RESULT_15_BASE_IDX 3 14782#define regABM0_DC_ABM1_HG_RESULT_16 0x0ead 14783#define regABM0_DC_ABM1_HG_RESULT_16_BASE_IDX 3 14784#define regABM0_DC_ABM1_HG_RESULT_17 0x0eae 14785#define regABM0_DC_ABM1_HG_RESULT_17_BASE_IDX 3 14786#define regABM0_DC_ABM1_HG_RESULT_18 0x0eaf 14787#define regABM0_DC_ABM1_HG_RESULT_18_BASE_IDX 3 14788#define regABM0_DC_ABM1_HG_RESULT_19 0x0eb0 14789#define regABM0_DC_ABM1_HG_RESULT_19_BASE_IDX 3 14790#define regABM0_DC_ABM1_HG_RESULT_20 0x0eb1 14791#define regABM0_DC_ABM1_HG_RESULT_20_BASE_IDX 3 14792#define regABM0_DC_ABM1_HG_RESULT_21 0x0eb2 14793#define regABM0_DC_ABM1_HG_RESULT_21_BASE_IDX 3 14794#define regABM0_DC_ABM1_HG_RESULT_22 0x0eb3 14795#define regABM0_DC_ABM1_HG_RESULT_22_BASE_IDX 3 14796#define regABM0_DC_ABM1_HG_RESULT_23 0x0eb4 14797#define regABM0_DC_ABM1_HG_RESULT_23_BASE_IDX 3 14798#define regABM0_DC_ABM1_HG_RESULT_24 0x0eb5 14799#define regABM0_DC_ABM1_HG_RESULT_24_BASE_IDX 3 14800#define regABM0_DC_ABM1_BL_MASTER_LOCK 0x0eb6 14801#define regABM0_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 14802 14803 14804// addressBlock: dce_dc_opp_abm1_dispdec 14805// base address: 0x104 14806#define regABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0ebb 14807#define regABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 14808#define regABM1_BL1_PWM_USER_LEVEL 0x0ebc 14809#define regABM1_BL1_PWM_USER_LEVEL_BASE_IDX 3 14810#define regABM1_BL1_PWM_TARGET_ABM_LEVEL 0x0ebd 14811#define regABM1_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 14812#define regABM1_BL1_PWM_CURRENT_ABM_LEVEL 0x0ebe 14813#define regABM1_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 14814#define regABM1_BL1_PWM_FINAL_DUTY_CYCLE 0x0ebf 14815#define regABM1_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 14816#define regABM1_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0ec0 14817#define regABM1_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 14818#define regABM1_BL1_PWM_ABM_CNTL 0x0ec1 14819#define regABM1_BL1_PWM_ABM_CNTL_BASE_IDX 3 14820#define regABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0ec2 14821#define regABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 14822#define regABM1_BL1_PWM_GRP2_REG_LOCK 0x0ec3 14823#define regABM1_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 14824#define regABM1_DC_ABM1_CNTL 0x0ec4 14825#define regABM1_DC_ABM1_CNTL_BASE_IDX 3 14826#define regABM1_DC_ABM1_IPCSC_COEFF_SEL 0x0ec5 14827#define regABM1_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 14828#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0ec6 14829#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 14830#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0ec7 14831#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 14832#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0ec8 14833#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 14834#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0ec9 14835#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 14836#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0eca 14837#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 14838#define regABM1_DC_ABM1_ACE_THRES_12 0x0ecb 14839#define regABM1_DC_ABM1_ACE_THRES_12_BASE_IDX 3 14840#define regABM1_DC_ABM1_ACE_THRES_34 0x0ecc 14841#define regABM1_DC_ABM1_ACE_THRES_34_BASE_IDX 3 14842#define regABM1_DC_ABM1_ACE_CNTL_MISC 0x0ecd 14843#define regABM1_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 14844#define regABM1_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0ecf 14845#define regABM1_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 14846#define regABM1_DC_ABM1_HG_MISC_CTRL 0x0ed0 14847#define regABM1_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 14848#define regABM1_DC_ABM1_LS_SUM_OF_LUMA 0x0ed1 14849#define regABM1_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 14850#define regABM1_DC_ABM1_LS_MIN_MAX_LUMA 0x0ed2 14851#define regABM1_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 14852#define regABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0ed3 14853#define regABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 14854#define regABM1_DC_ABM1_LS_PIXEL_COUNT 0x0ed4 14855#define regABM1_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 14856#define regABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0ed5 14857#define regABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 14858#define regABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0ed6 14859#define regABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 14860#define regABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0ed7 14861#define regABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 14862#define regABM1_DC_ABM1_HG_SAMPLE_RATE 0x0ed8 14863#define regABM1_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 14864#define regABM1_DC_ABM1_LS_SAMPLE_RATE 0x0ed9 14865#define regABM1_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 14866#define regABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0eda 14867#define regABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 14868#define regABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0edb 14869#define regABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 14870#define regABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0edc 14871#define regABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 14872#define regABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0edd 14873#define regABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 14874#define regABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0ede 14875#define regABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 14876#define regABM1_DC_ABM1_HG_RESULT_1 0x0edf 14877#define regABM1_DC_ABM1_HG_RESULT_1_BASE_IDX 3 14878#define regABM1_DC_ABM1_HG_RESULT_2 0x0ee0 14879#define regABM1_DC_ABM1_HG_RESULT_2_BASE_IDX 3 14880#define regABM1_DC_ABM1_HG_RESULT_3 0x0ee1 14881#define regABM1_DC_ABM1_HG_RESULT_3_BASE_IDX 3 14882#define regABM1_DC_ABM1_HG_RESULT_4 0x0ee2 14883#define regABM1_DC_ABM1_HG_RESULT_4_BASE_IDX 3 14884#define regABM1_DC_ABM1_HG_RESULT_5 0x0ee3 14885#define regABM1_DC_ABM1_HG_RESULT_5_BASE_IDX 3 14886#define regABM1_DC_ABM1_HG_RESULT_6 0x0ee4 14887#define regABM1_DC_ABM1_HG_RESULT_6_BASE_IDX 3 14888#define regABM1_DC_ABM1_HG_RESULT_7 0x0ee5 14889#define regABM1_DC_ABM1_HG_RESULT_7_BASE_IDX 3 14890#define regABM1_DC_ABM1_HG_RESULT_8 0x0ee6 14891#define regABM1_DC_ABM1_HG_RESULT_8_BASE_IDX 3 14892#define regABM1_DC_ABM1_HG_RESULT_9 0x0ee7 14893#define regABM1_DC_ABM1_HG_RESULT_9_BASE_IDX 3 14894#define regABM1_DC_ABM1_HG_RESULT_10 0x0ee8 14895#define regABM1_DC_ABM1_HG_RESULT_10_BASE_IDX 3 14896#define regABM1_DC_ABM1_HG_RESULT_11 0x0ee9 14897#define regABM1_DC_ABM1_HG_RESULT_11_BASE_IDX 3 14898#define regABM1_DC_ABM1_HG_RESULT_12 0x0eea 14899#define regABM1_DC_ABM1_HG_RESULT_12_BASE_IDX 3 14900#define regABM1_DC_ABM1_HG_RESULT_13 0x0eeb 14901#define regABM1_DC_ABM1_HG_RESULT_13_BASE_IDX 3 14902#define regABM1_DC_ABM1_HG_RESULT_14 0x0eec 14903#define regABM1_DC_ABM1_HG_RESULT_14_BASE_IDX 3 14904#define regABM1_DC_ABM1_HG_RESULT_15 0x0eed 14905#define regABM1_DC_ABM1_HG_RESULT_15_BASE_IDX 3 14906#define regABM1_DC_ABM1_HG_RESULT_16 0x0eee 14907#define regABM1_DC_ABM1_HG_RESULT_16_BASE_IDX 3 14908#define regABM1_DC_ABM1_HG_RESULT_17 0x0eef 14909#define regABM1_DC_ABM1_HG_RESULT_17_BASE_IDX 3 14910#define regABM1_DC_ABM1_HG_RESULT_18 0x0ef0 14911#define regABM1_DC_ABM1_HG_RESULT_18_BASE_IDX 3 14912#define regABM1_DC_ABM1_HG_RESULT_19 0x0ef1 14913#define regABM1_DC_ABM1_HG_RESULT_19_BASE_IDX 3 14914#define regABM1_DC_ABM1_HG_RESULT_20 0x0ef2 14915#define regABM1_DC_ABM1_HG_RESULT_20_BASE_IDX 3 14916#define regABM1_DC_ABM1_HG_RESULT_21 0x0ef3 14917#define regABM1_DC_ABM1_HG_RESULT_21_BASE_IDX 3 14918#define regABM1_DC_ABM1_HG_RESULT_22 0x0ef4 14919#define regABM1_DC_ABM1_HG_RESULT_22_BASE_IDX 3 14920#define regABM1_DC_ABM1_HG_RESULT_23 0x0ef5 14921#define regABM1_DC_ABM1_HG_RESULT_23_BASE_IDX 3 14922#define regABM1_DC_ABM1_HG_RESULT_24 0x0ef6 14923#define regABM1_DC_ABM1_HG_RESULT_24_BASE_IDX 3 14924#define regABM1_DC_ABM1_BL_MASTER_LOCK 0x0ef7 14925#define regABM1_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 14926 14927 14928// addressBlock: dce_dc_opp_abm2_dispdec 14929// base address: 0x208 14930#define regABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0efc 14931#define regABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 14932#define regABM2_BL1_PWM_USER_LEVEL 0x0efd 14933#define regABM2_BL1_PWM_USER_LEVEL_BASE_IDX 3 14934#define regABM2_BL1_PWM_TARGET_ABM_LEVEL 0x0efe 14935#define regABM2_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 14936#define regABM2_BL1_PWM_CURRENT_ABM_LEVEL 0x0eff 14937#define regABM2_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 14938#define regABM2_BL1_PWM_FINAL_DUTY_CYCLE 0x0f00 14939#define regABM2_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 14940#define regABM2_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0f01 14941#define regABM2_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 14942#define regABM2_BL1_PWM_ABM_CNTL 0x0f02 14943#define regABM2_BL1_PWM_ABM_CNTL_BASE_IDX 3 14944#define regABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0f03 14945#define regABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 14946#define regABM2_BL1_PWM_GRP2_REG_LOCK 0x0f04 14947#define regABM2_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 14948#define regABM2_DC_ABM1_CNTL 0x0f05 14949#define regABM2_DC_ABM1_CNTL_BASE_IDX 3 14950#define regABM2_DC_ABM1_IPCSC_COEFF_SEL 0x0f06 14951#define regABM2_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 14952#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0f07 14953#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 14954#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0f08 14955#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 14956#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0f09 14957#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 14958#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0f0a 14959#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 14960#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0f0b 14961#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 14962#define regABM2_DC_ABM1_ACE_THRES_12 0x0f0c 14963#define regABM2_DC_ABM1_ACE_THRES_12_BASE_IDX 3 14964#define regABM2_DC_ABM1_ACE_THRES_34 0x0f0d 14965#define regABM2_DC_ABM1_ACE_THRES_34_BASE_IDX 3 14966#define regABM2_DC_ABM1_ACE_CNTL_MISC 0x0f0e 14967#define regABM2_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 14968#define regABM2_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0f10 14969#define regABM2_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 14970#define regABM2_DC_ABM1_HG_MISC_CTRL 0x0f11 14971#define regABM2_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 14972#define regABM2_DC_ABM1_LS_SUM_OF_LUMA 0x0f12 14973#define regABM2_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 14974#define regABM2_DC_ABM1_LS_MIN_MAX_LUMA 0x0f13 14975#define regABM2_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 14976#define regABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0f14 14977#define regABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 14978#define regABM2_DC_ABM1_LS_PIXEL_COUNT 0x0f15 14979#define regABM2_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 14980#define regABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0f16 14981#define regABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 14982#define regABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0f17 14983#define regABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 14984#define regABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0f18 14985#define regABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 14986#define regABM2_DC_ABM1_HG_SAMPLE_RATE 0x0f19 14987#define regABM2_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 14988#define regABM2_DC_ABM1_LS_SAMPLE_RATE 0x0f1a 14989#define regABM2_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 14990#define regABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0f1b 14991#define regABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 14992#define regABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0f1c 14993#define regABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 14994#define regABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0f1d 14995#define regABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 14996#define regABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0f1e 14997#define regABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 14998#define regABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0f1f 14999#define regABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 15000#define regABM2_DC_ABM1_HG_RESULT_1 0x0f20 15001#define regABM2_DC_ABM1_HG_RESULT_1_BASE_IDX 3 15002#define regABM2_DC_ABM1_HG_RESULT_2 0x0f21 15003#define regABM2_DC_ABM1_HG_RESULT_2_BASE_IDX 3 15004#define regABM2_DC_ABM1_HG_RESULT_3 0x0f22 15005#define regABM2_DC_ABM1_HG_RESULT_3_BASE_IDX 3 15006#define regABM2_DC_ABM1_HG_RESULT_4 0x0f23 15007#define regABM2_DC_ABM1_HG_RESULT_4_BASE_IDX 3 15008#define regABM2_DC_ABM1_HG_RESULT_5 0x0f24 15009#define regABM2_DC_ABM1_HG_RESULT_5_BASE_IDX 3 15010#define regABM2_DC_ABM1_HG_RESULT_6 0x0f25 15011#define regABM2_DC_ABM1_HG_RESULT_6_BASE_IDX 3 15012#define regABM2_DC_ABM1_HG_RESULT_7 0x0f26 15013#define regABM2_DC_ABM1_HG_RESULT_7_BASE_IDX 3 15014#define regABM2_DC_ABM1_HG_RESULT_8 0x0f27 15015#define regABM2_DC_ABM1_HG_RESULT_8_BASE_IDX 3 15016#define regABM2_DC_ABM1_HG_RESULT_9 0x0f28 15017#define regABM2_DC_ABM1_HG_RESULT_9_BASE_IDX 3 15018#define regABM2_DC_ABM1_HG_RESULT_10 0x0f29 15019#define regABM2_DC_ABM1_HG_RESULT_10_BASE_IDX 3 15020#define regABM2_DC_ABM1_HG_RESULT_11 0x0f2a 15021#define regABM2_DC_ABM1_HG_RESULT_11_BASE_IDX 3 15022#define regABM2_DC_ABM1_HG_RESULT_12 0x0f2b 15023#define regABM2_DC_ABM1_HG_RESULT_12_BASE_IDX 3 15024#define regABM2_DC_ABM1_HG_RESULT_13 0x0f2c 15025#define regABM2_DC_ABM1_HG_RESULT_13_BASE_IDX 3 15026#define regABM2_DC_ABM1_HG_RESULT_14 0x0f2d 15027#define regABM2_DC_ABM1_HG_RESULT_14_BASE_IDX 3 15028#define regABM2_DC_ABM1_HG_RESULT_15 0x0f2e 15029#define regABM2_DC_ABM1_HG_RESULT_15_BASE_IDX 3 15030#define regABM2_DC_ABM1_HG_RESULT_16 0x0f2f 15031#define regABM2_DC_ABM1_HG_RESULT_16_BASE_IDX 3 15032#define regABM2_DC_ABM1_HG_RESULT_17 0x0f30 15033#define regABM2_DC_ABM1_HG_RESULT_17_BASE_IDX 3 15034#define regABM2_DC_ABM1_HG_RESULT_18 0x0f31 15035#define regABM2_DC_ABM1_HG_RESULT_18_BASE_IDX 3 15036#define regABM2_DC_ABM1_HG_RESULT_19 0x0f32 15037#define regABM2_DC_ABM1_HG_RESULT_19_BASE_IDX 3 15038#define regABM2_DC_ABM1_HG_RESULT_20 0x0f33 15039#define regABM2_DC_ABM1_HG_RESULT_20_BASE_IDX 3 15040#define regABM2_DC_ABM1_HG_RESULT_21 0x0f34 15041#define regABM2_DC_ABM1_HG_RESULT_21_BASE_IDX 3 15042#define regABM2_DC_ABM1_HG_RESULT_22 0x0f35 15043#define regABM2_DC_ABM1_HG_RESULT_22_BASE_IDX 3 15044#define regABM2_DC_ABM1_HG_RESULT_23 0x0f36 15045#define regABM2_DC_ABM1_HG_RESULT_23_BASE_IDX 3 15046#define regABM2_DC_ABM1_HG_RESULT_24 0x0f37 15047#define regABM2_DC_ABM1_HG_RESULT_24_BASE_IDX 3 15048#define regABM2_DC_ABM1_BL_MASTER_LOCK 0x0f38 15049#define regABM2_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 15050 15051 15052// addressBlock: dce_dc_opp_abm3_dispdec 15053// base address: 0x30c 15054#define regABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0f3d 15055#define regABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 15056#define regABM3_BL1_PWM_USER_LEVEL 0x0f3e 15057#define regABM3_BL1_PWM_USER_LEVEL_BASE_IDX 3 15058#define regABM3_BL1_PWM_TARGET_ABM_LEVEL 0x0f3f 15059#define regABM3_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 15060#define regABM3_BL1_PWM_CURRENT_ABM_LEVEL 0x0f40 15061#define regABM3_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 15062#define regABM3_BL1_PWM_FINAL_DUTY_CYCLE 0x0f41 15063#define regABM3_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 15064#define regABM3_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0f42 15065#define regABM3_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 15066#define regABM3_BL1_PWM_ABM_CNTL 0x0f43 15067#define regABM3_BL1_PWM_ABM_CNTL_BASE_IDX 3 15068#define regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0f44 15069#define regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 15070#define regABM3_BL1_PWM_GRP2_REG_LOCK 0x0f45 15071#define regABM3_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 15072#define regABM3_DC_ABM1_CNTL 0x0f46 15073#define regABM3_DC_ABM1_CNTL_BASE_IDX 3 15074#define regABM3_DC_ABM1_IPCSC_COEFF_SEL 0x0f47 15075#define regABM3_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 15076#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0f48 15077#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 15078#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0f49 15079#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 15080#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0f4a 15081#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 15082#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0f4b 15083#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 15084#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0f4c 15085#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 15086#define regABM3_DC_ABM1_ACE_THRES_12 0x0f4d 15087#define regABM3_DC_ABM1_ACE_THRES_12_BASE_IDX 3 15088#define regABM3_DC_ABM1_ACE_THRES_34 0x0f4e 15089#define regABM3_DC_ABM1_ACE_THRES_34_BASE_IDX 3 15090#define regABM3_DC_ABM1_ACE_CNTL_MISC 0x0f4f 15091#define regABM3_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 15092#define regABM3_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0f51 15093#define regABM3_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 15094#define regABM3_DC_ABM1_HG_MISC_CTRL 0x0f52 15095#define regABM3_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 15096#define regABM3_DC_ABM1_LS_SUM_OF_LUMA 0x0f53 15097#define regABM3_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 15098#define regABM3_DC_ABM1_LS_MIN_MAX_LUMA 0x0f54 15099#define regABM3_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 15100#define regABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0f55 15101#define regABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 15102#define regABM3_DC_ABM1_LS_PIXEL_COUNT 0x0f56 15103#define regABM3_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 15104#define regABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0f57 15105#define regABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 15106#define regABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0f58 15107#define regABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 15108#define regABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0f59 15109#define regABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 15110#define regABM3_DC_ABM1_HG_SAMPLE_RATE 0x0f5a 15111#define regABM3_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 15112#define regABM3_DC_ABM1_LS_SAMPLE_RATE 0x0f5b 15113#define regABM3_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 15114#define regABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0f5c 15115#define regABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 15116#define regABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0f5d 15117#define regABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 15118#define regABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0f5e 15119#define regABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 15120#define regABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0f5f 15121#define regABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 15122#define regABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0f60 15123#define regABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 15124#define regABM3_DC_ABM1_HG_RESULT_1 0x0f61 15125#define regABM3_DC_ABM1_HG_RESULT_1_BASE_IDX 3 15126#define regABM3_DC_ABM1_HG_RESULT_2 0x0f62 15127#define regABM3_DC_ABM1_HG_RESULT_2_BASE_IDX 3 15128#define regABM3_DC_ABM1_HG_RESULT_3 0x0f63 15129#define regABM3_DC_ABM1_HG_RESULT_3_BASE_IDX 3 15130#define regABM3_DC_ABM1_HG_RESULT_4 0x0f64 15131#define regABM3_DC_ABM1_HG_RESULT_4_BASE_IDX 3 15132#define regABM3_DC_ABM1_HG_RESULT_5 0x0f65 15133#define regABM3_DC_ABM1_HG_RESULT_5_BASE_IDX 3 15134#define regABM3_DC_ABM1_HG_RESULT_6 0x0f66 15135#define regABM3_DC_ABM1_HG_RESULT_6_BASE_IDX 3 15136#define regABM3_DC_ABM1_HG_RESULT_7 0x0f67 15137#define regABM3_DC_ABM1_HG_RESULT_7_BASE_IDX 3 15138#define regABM3_DC_ABM1_HG_RESULT_8 0x0f68 15139#define regABM3_DC_ABM1_HG_RESULT_8_BASE_IDX 3 15140#define regABM3_DC_ABM1_HG_RESULT_9 0x0f69 15141#define regABM3_DC_ABM1_HG_RESULT_9_BASE_IDX 3 15142#define regABM3_DC_ABM1_HG_RESULT_10 0x0f6a 15143#define regABM3_DC_ABM1_HG_RESULT_10_BASE_IDX 3 15144#define regABM3_DC_ABM1_HG_RESULT_11 0x0f6b 15145#define regABM3_DC_ABM1_HG_RESULT_11_BASE_IDX 3 15146#define regABM3_DC_ABM1_HG_RESULT_12 0x0f6c 15147#define regABM3_DC_ABM1_HG_RESULT_12_BASE_IDX 3 15148#define regABM3_DC_ABM1_HG_RESULT_13 0x0f6d 15149#define regABM3_DC_ABM1_HG_RESULT_13_BASE_IDX 3 15150#define regABM3_DC_ABM1_HG_RESULT_14 0x0f6e 15151#define regABM3_DC_ABM1_HG_RESULT_14_BASE_IDX 3 15152#define regABM3_DC_ABM1_HG_RESULT_15 0x0f6f 15153#define regABM3_DC_ABM1_HG_RESULT_15_BASE_IDX 3 15154#define regABM3_DC_ABM1_HG_RESULT_16 0x0f70 15155#define regABM3_DC_ABM1_HG_RESULT_16_BASE_IDX 3 15156#define regABM3_DC_ABM1_HG_RESULT_17 0x0f71 15157#define regABM3_DC_ABM1_HG_RESULT_17_BASE_IDX 3 15158#define regABM3_DC_ABM1_HG_RESULT_18 0x0f72 15159#define regABM3_DC_ABM1_HG_RESULT_18_BASE_IDX 3 15160#define regABM3_DC_ABM1_HG_RESULT_19 0x0f73 15161#define regABM3_DC_ABM1_HG_RESULT_19_BASE_IDX 3 15162#define regABM3_DC_ABM1_HG_RESULT_20 0x0f74 15163#define regABM3_DC_ABM1_HG_RESULT_20_BASE_IDX 3 15164#define regABM3_DC_ABM1_HG_RESULT_21 0x0f75 15165#define regABM3_DC_ABM1_HG_RESULT_21_BASE_IDX 3 15166#define regABM3_DC_ABM1_HG_RESULT_22 0x0f76 15167#define regABM3_DC_ABM1_HG_RESULT_22_BASE_IDX 3 15168#define regABM3_DC_ABM1_HG_RESULT_23 0x0f77 15169#define regABM3_DC_ABM1_HG_RESULT_23_BASE_IDX 3 15170#define regABM3_DC_ABM1_HG_RESULT_24 0x0f78 15171#define regABM3_DC_ABM1_HG_RESULT_24_BASE_IDX 3 15172#define regABM3_DC_ABM1_BL_MASTER_LOCK 0x0f79 15173#define regABM3_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 15174 15175 15176// addressBlock: dce_dpia_dpia_mu0_dpiadec 15177// base address: 0x72000 15178#define regDPIA_MU_RBBMIF_TIMEOUT_CTRL 0x1381e 15179#define regDPIA_MU_RBBMIF_TIMEOUT_CTRL_BASE_IDX 3 15180#define regDPIA_MU_RBBMIF_TIMEOUT_CTRL2 0x1381f 15181#define regDPIA_MU_RBBMIF_TIMEOUT_CTRL2_BASE_IDX 3 15182#define regDPIA_MU_RBBMIF_STATUS 0x13820 15183#define regDPIA_MU_RBBMIF_STATUS_BASE_IDX 3 15184 15185 15186// addressBlock: dce_dc_hda_azcontroller_azdec 15187// base address: 0x1300000 15188#define regAZCONTROLLER1_CORB_WRITE_POINTER 0x4b7012 15189#define regAZCONTROLLER1_CORB_WRITE_POINTER_BASE_IDX 3 15190#define regAZCONTROLLER1_CORB_READ_POINTER 0x4b7012 15191#define regAZCONTROLLER1_CORB_READ_POINTER_BASE_IDX 3 15192#define regAZCONTROLLER1_CORB_CONTROL 0x4b7013 15193#define regAZCONTROLLER1_CORB_CONTROL_BASE_IDX 3 15194#define regAZCONTROLLER1_CORB_STATUS 0x4b7013 15195#define regAZCONTROLLER1_CORB_STATUS_BASE_IDX 3 15196#define regAZCONTROLLER1_CORB_SIZE 0x4b7013 15197#define regAZCONTROLLER1_CORB_SIZE_BASE_IDX 3 15198#define regAZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS 0x4b7014 15199#define regAZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS_BASE_IDX 3 15200#define regAZCONTROLLER1_RIRB_UPPER_BASE_ADDRESS 0x4b7015 15201#define regAZCONTROLLER1_RIRB_UPPER_BASE_ADDRESS_BASE_IDX 3 15202#define regAZCONTROLLER1_RIRB_WRITE_POINTER 0x4b7016 15203#define regAZCONTROLLER1_RIRB_WRITE_POINTER_BASE_IDX 3 15204#define regAZCONTROLLER1_RESPONSE_INTERRUPT_COUNT 0x4b7016 15205#define regAZCONTROLLER1_RESPONSE_INTERRUPT_COUNT_BASE_IDX 3 15206#define regAZCONTROLLER1_RIRB_CONTROL 0x4b7017 15207#define regAZCONTROLLER1_RIRB_CONTROL_BASE_IDX 3 15208#define regAZCONTROLLER1_RIRB_STATUS 0x4b7017 15209#define regAZCONTROLLER1_RIRB_STATUS_BASE_IDX 3 15210#define regAZCONTROLLER1_RIRB_SIZE 0x4b7017 15211#define regAZCONTROLLER1_RIRB_SIZE_BASE_IDX 3 15212#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x4b7018 15213#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX 3 15214#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x4b7018 15215#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 3 15216#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x4b7018 15217#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 3 15218#define regAZCONTROLLER1_IMMEDIATE_RESPONSE_INPUT_INTERFACE 0x4b7019 15219#define regAZCONTROLLER1_IMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX 3 15220#define regAZCONTROLLER1_IMMEDIATE_COMMAND_STATUS 0x4b701a 15221#define regAZCONTROLLER1_IMMEDIATE_COMMAND_STATUS_BASE_IDX 3 15222#define regAZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS 0x4b701c 15223#define regAZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX 3 15224#define regAZCONTROLLER1_DMA_POSITION_UPPER_BASE_ADDRESS 0x4b701d 15225#define regAZCONTROLLER1_DMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX 3 15226 15227 15228// addressBlock: dce_dc_hda_azendpoint_azdec 15229// base address: 0x1300000 15230#define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x4b7018 15231#define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 3 15232#define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x4b7018 15233#define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 3 15234 15235 15236// addressBlock: dce_dc_hda_azinputendpoint_azdec 15237// base address: 0x1300000 15238#define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0x4b7018 15239#define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX 3 15240#define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0x4b7018 15241#define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX 3 15242 15243 15244 15245#endif 15246