1/* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26#ifndef __DAL_DCN31_HPO_DP_LINK_ENCODER_H__ 27#define __DAL_DCN31_HPO_DP_LINK_ENCODER_H__ 28 29#include "link_encoder.h" 30 31 32#define DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(hpo_dp_link_encoder)\ 33 container_of(hpo_dp_link_encoder, struct dcn31_hpo_dp_link_encoder, base) 34 35 36#define DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id) \ 37 SRI(DP_LINK_ENC_CLOCK_CONTROL, DP_LINK_ENC, id), \ 38 SRI(DP_DPHY_SYM32_CONTROL, DP_DPHY_SYM32, id), \ 39 SRI(DP_DPHY_SYM32_STATUS, DP_DPHY_SYM32, id), \ 40 SRI(DP_DPHY_SYM32_TP_CONFIG, DP_DPHY_SYM32, id), \ 41 SRI(DP_DPHY_SYM32_TP_PRBS_SEED0, DP_DPHY_SYM32, id), \ 42 SRI(DP_DPHY_SYM32_TP_PRBS_SEED1, DP_DPHY_SYM32, id), \ 43 SRI(DP_DPHY_SYM32_TP_PRBS_SEED2, DP_DPHY_SYM32, id), \ 44 SRI(DP_DPHY_SYM32_TP_PRBS_SEED3, DP_DPHY_SYM32, id), \ 45 SRI(DP_DPHY_SYM32_TP_SQ_PULSE, DP_DPHY_SYM32, id), \ 46 SRI(DP_DPHY_SYM32_TP_CUSTOM0, DP_DPHY_SYM32, id), \ 47 SRI(DP_DPHY_SYM32_TP_CUSTOM1, DP_DPHY_SYM32, id), \ 48 SRI(DP_DPHY_SYM32_TP_CUSTOM2, DP_DPHY_SYM32, id), \ 49 SRI(DP_DPHY_SYM32_TP_CUSTOM3, DP_DPHY_SYM32, id), \ 50 SRI(DP_DPHY_SYM32_TP_CUSTOM4, DP_DPHY_SYM32, id), \ 51 SRI(DP_DPHY_SYM32_TP_CUSTOM5, DP_DPHY_SYM32, id), \ 52 SRI(DP_DPHY_SYM32_TP_CUSTOM6, DP_DPHY_SYM32, id), \ 53 SRI(DP_DPHY_SYM32_TP_CUSTOM7, DP_DPHY_SYM32, id), \ 54 SRI(DP_DPHY_SYM32_TP_CUSTOM8, DP_DPHY_SYM32, id), \ 55 SRI(DP_DPHY_SYM32_TP_CUSTOM9, DP_DPHY_SYM32, id), \ 56 SRI(DP_DPHY_SYM32_TP_CUSTOM10, DP_DPHY_SYM32, id), \ 57 SRI(DP_DPHY_SYM32_SAT_VC0, DP_DPHY_SYM32, id), \ 58 SRI(DP_DPHY_SYM32_SAT_VC1, DP_DPHY_SYM32, id), \ 59 SRI(DP_DPHY_SYM32_SAT_VC2, DP_DPHY_SYM32, id), \ 60 SRI(DP_DPHY_SYM32_SAT_VC3, DP_DPHY_SYM32, id), \ 61 SRI(DP_DPHY_SYM32_VC_RATE_CNTL0, DP_DPHY_SYM32, id), \ 62 SRI(DP_DPHY_SYM32_VC_RATE_CNTL1, DP_DPHY_SYM32, id), \ 63 SRI(DP_DPHY_SYM32_VC_RATE_CNTL2, DP_DPHY_SYM32, id), \ 64 SRI(DP_DPHY_SYM32_VC_RATE_CNTL3, DP_DPHY_SYM32, id), \ 65 SRI(DP_DPHY_SYM32_SAT_UPDATE, DP_DPHY_SYM32, id) 66 67#define DCN3_1_RDPCSTX_REG_LIST(id) \ 68 SRII(RDPCSTX_PHY_CNTL6, RDPCSTX, id) 69 70 71#define DCN3_1_HPO_DP_LINK_ENC_REGS \ 72 uint32_t DP_LINK_ENC_CLOCK_CONTROL;\ 73 uint32_t DP_DPHY_SYM32_CONTROL;\ 74 uint32_t DP_DPHY_SYM32_STATUS;\ 75 uint32_t DP_DPHY_SYM32_TP_CONFIG;\ 76 uint32_t DP_DPHY_SYM32_TP_PRBS_SEED0;\ 77 uint32_t DP_DPHY_SYM32_TP_PRBS_SEED1;\ 78 uint32_t DP_DPHY_SYM32_TP_PRBS_SEED2;\ 79 uint32_t DP_DPHY_SYM32_TP_PRBS_SEED3;\ 80 uint32_t DP_DPHY_SYM32_TP_SQ_PULSE;\ 81 uint32_t DP_DPHY_SYM32_TP_CUSTOM0;\ 82 uint32_t DP_DPHY_SYM32_TP_CUSTOM1;\ 83 uint32_t DP_DPHY_SYM32_TP_CUSTOM2;\ 84 uint32_t DP_DPHY_SYM32_TP_CUSTOM3;\ 85 uint32_t DP_DPHY_SYM32_TP_CUSTOM4;\ 86 uint32_t DP_DPHY_SYM32_TP_CUSTOM5;\ 87 uint32_t DP_DPHY_SYM32_TP_CUSTOM6;\ 88 uint32_t DP_DPHY_SYM32_TP_CUSTOM7;\ 89 uint32_t DP_DPHY_SYM32_TP_CUSTOM8;\ 90 uint32_t DP_DPHY_SYM32_TP_CUSTOM9;\ 91 uint32_t DP_DPHY_SYM32_TP_CUSTOM10;\ 92 uint32_t DP_DPHY_SYM32_SAT_VC0;\ 93 uint32_t DP_DPHY_SYM32_SAT_VC1;\ 94 uint32_t DP_DPHY_SYM32_SAT_VC2;\ 95 uint32_t DP_DPHY_SYM32_SAT_VC3;\ 96 uint32_t DP_DPHY_SYM32_VC_RATE_CNTL0;\ 97 uint32_t DP_DPHY_SYM32_VC_RATE_CNTL1;\ 98 uint32_t DP_DPHY_SYM32_VC_RATE_CNTL2;\ 99 uint32_t DP_DPHY_SYM32_VC_RATE_CNTL3;\ 100 uint32_t DP_DPHY_SYM32_SAT_UPDATE 101 102struct dcn31_hpo_dp_link_encoder_registers { 103 DCN3_1_HPO_DP_LINK_ENC_REGS; 104 uint32_t RDPCSTX_PHY_CNTL6[5]; 105}; 106 107#define DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(mask_sh)\ 108 SE_SF(DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL, DP_LINK_ENC_CLOCK_EN, mask_sh),\ 109 SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL, DPHY_RESET, mask_sh),\ 110 SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL, DPHY_ENABLE, mask_sh),\ 111 SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL, PRECODER_ENABLE, mask_sh),\ 112 SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL, MODE, mask_sh),\ 113 SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL, NUM_LANES, mask_sh),\ 114 SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS, STATUS, mask_sh),\ 115 SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS, SAT_UPDATE_PENDING, mask_sh),\ 116 SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS, RATE_UPDATE_PENDING, mask_sh),\ 117 SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0, TP_CUSTOM, mask_sh),\ 118 SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG, TP_SELECT0, mask_sh),\ 119 SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG, TP_SELECT1, mask_sh),\ 120 SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG, TP_SELECT2, mask_sh),\ 121 SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG, TP_SELECT3, mask_sh),\ 122 SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG, TP_PRBS_SEL0, mask_sh),\ 123 SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG, TP_PRBS_SEL1, mask_sh),\ 124 SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG, TP_PRBS_SEL2, mask_sh),\ 125 SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG, TP_PRBS_SEL3, mask_sh),\ 126 SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE, TP_SQ_PULSE_WIDTH, mask_sh),\ 127 SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0, SAT_STREAM_SOURCE, mask_sh),\ 128 SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0, SAT_SLOT_COUNT, mask_sh),\ 129 SE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, mask_sh),\ 130 SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0, STREAM_VC_RATE_X, mask_sh),\ 131 SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0, STREAM_VC_RATE_Y, mask_sh),\ 132 SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE, SAT_UPDATE, mask_sh) 133 134#define DCN3_1_HPO_DP_LINK_ENC_REG_FIELD_LIST(type) \ 135 type DP_LINK_ENC_CLOCK_EN;\ 136 type DPHY_RESET;\ 137 type DPHY_ENABLE;\ 138 type PRECODER_ENABLE;\ 139 type NUM_LANES;\ 140 type MODE;\ 141 type STATUS;\ 142 type SAT_UPDATE_PENDING;\ 143 type RATE_UPDATE_PENDING;\ 144 type TP_CUSTOM;\ 145 type TP_SELECT0;\ 146 type TP_SELECT1;\ 147 type TP_SELECT2;\ 148 type TP_SELECT3;\ 149 type TP_PRBS_SEL0;\ 150 type TP_PRBS_SEL1;\ 151 type TP_PRBS_SEL2;\ 152 type TP_PRBS_SEL3;\ 153 type TP_SQ_PULSE_WIDTH;\ 154 type SAT_STREAM_SOURCE;\ 155 type SAT_SLOT_COUNT;\ 156 type STREAM_VC_RATE_X;\ 157 type STREAM_VC_RATE_Y;\ 158 type SAT_UPDATE;\ 159 type RDPCS_PHY_DPALT_DISABLE 160 161 162struct dcn31_hpo_dp_link_encoder_shift { 163 DCN3_1_HPO_DP_LINK_ENC_REG_FIELD_LIST(uint8_t); 164}; 165 166struct dcn31_hpo_dp_link_encoder_mask { 167 DCN3_1_HPO_DP_LINK_ENC_REG_FIELD_LIST(uint32_t); 168}; 169 170struct dcn31_hpo_dp_link_encoder { 171 struct hpo_dp_link_encoder base; 172 const struct dcn31_hpo_dp_link_encoder_registers *regs; 173 const struct dcn31_hpo_dp_link_encoder_shift *hpo_le_shift; 174 const struct dcn31_hpo_dp_link_encoder_mask *hpo_le_mask; 175}; 176 177void hpo_dp_link_encoder31_construct(struct dcn31_hpo_dp_link_encoder *enc31, 178 struct dc_context *ctx, 179 uint32_t inst, 180 const struct dcn31_hpo_dp_link_encoder_registers *hpo_le_regs, 181 const struct dcn31_hpo_dp_link_encoder_shift *hpo_le_shift, 182 const struct dcn31_hpo_dp_link_encoder_mask *hpo_le_mask); 183 184void dcn31_hpo_dp_link_enc_enable_dp_output( 185 struct hpo_dp_link_encoder *enc, 186 const struct dc_link_settings *link_settings, 187 enum transmitter transmitter, 188 enum hpd_source_id hpd_source); 189 190void dcn31_hpo_dp_link_enc_disable_output( 191 struct hpo_dp_link_encoder *enc, 192 enum amd_signal_type signal); 193 194void dcn31_hpo_dp_link_enc_enable( 195 struct hpo_dp_link_encoder *enc, 196 enum dc_lane_count num_lanes); 197 198void dcn31_hpo_dp_link_enc_disable( 199 struct hpo_dp_link_encoder *enc); 200 201void dcn31_hpo_dp_link_enc_set_link_test_pattern( 202 struct hpo_dp_link_encoder *enc, 203 struct encoder_set_dp_phy_pattern_param *tp_params); 204 205void dcn31_hpo_dp_link_enc_update_stream_allocation_table( 206 struct hpo_dp_link_encoder *enc, 207 const struct link_mst_stream_allocation_table *table); 208 209void dcn31_hpo_dp_link_enc_set_throttled_vcp_size( 210 struct hpo_dp_link_encoder *enc, 211 uint32_t stream_encoder_inst, 212 struct fixed31_32 avg_time_slots_per_mtp); 213 214void dcn31_hpo_dp_link_enc_read_state( 215 struct hpo_dp_link_encoder *enc, 216 struct hpo_dp_link_enc_state *state); 217 218void dcn31_hpo_dp_link_enc_set_ffe( 219 struct hpo_dp_link_encoder *enc, 220 const struct dc_link_settings *link_settings, 221 uint8_t ffe_preset); 222 223#endif // __DAL_DCN31_HPO_LINK_ENCODER_H__ 224