1// SPDX-License-Identifier: MIT 2/* 3 * Copyright 2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27#include <drm/drm_atomic_helper.h> 28#include <drm/drm_blend.h> 29#include <drm/drm_gem_atomic_helper.h> 30#include <drm/drm_plane_helper.h> 31#include <drm/drm_fourcc.h> 32 33#include "amdgpu.h" 34#include "dal_asic_id.h" 35#include "amdgpu_display.h" 36#include "amdgpu_dm_trace.h" 37#include "amdgpu_dm_plane.h" 38#include "gc/gc_11_0_0_offset.h" 39#include "gc/gc_11_0_0_sh_mask.h" 40 41/* 42 * TODO: these are currently initialized to rgb formats only. 43 * For future use cases we should either initialize them dynamically based on 44 * plane capabilities, or initialize this array to all formats, so internal drm 45 * check will succeed, and let DC implement proper check 46 */ 47static const uint32_t rgb_formats[] = { 48 DRM_FORMAT_XRGB8888, 49 DRM_FORMAT_ARGB8888, 50 DRM_FORMAT_RGBA8888, 51 DRM_FORMAT_XRGB2101010, 52 DRM_FORMAT_XBGR2101010, 53 DRM_FORMAT_ARGB2101010, 54 DRM_FORMAT_ABGR2101010, 55 DRM_FORMAT_XRGB16161616, 56 DRM_FORMAT_XBGR16161616, 57 DRM_FORMAT_ARGB16161616, 58 DRM_FORMAT_ABGR16161616, 59 DRM_FORMAT_XBGR8888, 60 DRM_FORMAT_ABGR8888, 61 DRM_FORMAT_RGB565, 62}; 63 64static const uint32_t overlay_formats[] = { 65 DRM_FORMAT_XRGB8888, 66 DRM_FORMAT_ARGB8888, 67 DRM_FORMAT_RGBA8888, 68 DRM_FORMAT_XBGR8888, 69 DRM_FORMAT_ABGR8888, 70 DRM_FORMAT_RGB565, 71 DRM_FORMAT_NV21, 72 DRM_FORMAT_NV12, 73 DRM_FORMAT_P010 74}; 75 76static const uint32_t video_formats[] = { 77 DRM_FORMAT_NV21, 78 DRM_FORMAT_NV12, 79 DRM_FORMAT_P010 80}; 81 82static const u32 cursor_formats[] = { 83 DRM_FORMAT_ARGB8888 84}; 85 86enum dm_micro_swizzle { 87 MICRO_SWIZZLE_Z = 0, 88 MICRO_SWIZZLE_S = 1, 89 MICRO_SWIZZLE_D = 2, 90 MICRO_SWIZZLE_R = 3 91}; 92 93const struct drm_format_info *amdgpu_dm_plane_get_format_info(const struct drm_mode_fb_cmd2 *cmd) 94{ 95 return amdgpu_lookup_format_info(cmd->pixel_format, cmd->modifier[0]); 96} 97 98void amdgpu_dm_plane_fill_blending_from_plane_state(const struct drm_plane_state *plane_state, 99 bool *per_pixel_alpha, bool *pre_multiplied_alpha, 100 bool *global_alpha, int *global_alpha_value) 101{ 102 *per_pixel_alpha = false; 103 *pre_multiplied_alpha = true; 104 *global_alpha = false; 105 *global_alpha_value = 0xff; 106 107 if (plane_state->plane->type != DRM_PLANE_TYPE_OVERLAY) 108 return; 109 110 if (plane_state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI || 111 plane_state->pixel_blend_mode == DRM_MODE_BLEND_COVERAGE) { 112 static const uint32_t alpha_formats[] = { 113 DRM_FORMAT_ARGB8888, 114 DRM_FORMAT_RGBA8888, 115 DRM_FORMAT_ABGR8888, 116 DRM_FORMAT_ARGB2101010, 117 DRM_FORMAT_ABGR2101010, 118 DRM_FORMAT_ARGB16161616, 119 DRM_FORMAT_ABGR16161616, 120 DRM_FORMAT_ARGB16161616F, 121 }; 122 uint32_t format = plane_state->fb->format->format; 123 unsigned int i; 124 125 for (i = 0; i < ARRAY_SIZE(alpha_formats); ++i) { 126 if (format == alpha_formats[i]) { 127 *per_pixel_alpha = true; 128 break; 129 } 130 } 131 132 if (*per_pixel_alpha && plane_state->pixel_blend_mode == DRM_MODE_BLEND_COVERAGE) 133 *pre_multiplied_alpha = false; 134 } 135 136 if (plane_state->alpha < 0xffff) { 137 *global_alpha = true; 138 *global_alpha_value = plane_state->alpha >> 8; 139 } 140} 141 142static void add_modifier(uint64_t **mods, uint64_t *size, uint64_t *cap, uint64_t mod) 143{ 144 if (!*mods) 145 return; 146 147 if (*cap - *size < 1) { 148 uint64_t new_cap = *cap * 2; 149 uint64_t *new_mods = kmalloc(new_cap * sizeof(uint64_t), GFP_KERNEL); 150 151 if (!new_mods) { 152 kfree(*mods); 153 *mods = NULL; 154 return; 155 } 156 157 memcpy(new_mods, *mods, sizeof(uint64_t) * *size); 158 kfree(*mods); 159 *mods = new_mods; 160 *cap = new_cap; 161 } 162 163 (*mods)[*size] = mod; 164 *size += 1; 165} 166 167static bool modifier_has_dcc(uint64_t modifier) 168{ 169 return IS_AMD_FMT_MOD(modifier) && AMD_FMT_MOD_GET(DCC, modifier); 170} 171 172static unsigned int modifier_gfx9_swizzle_mode(uint64_t modifier) 173{ 174 if (modifier == DRM_FORMAT_MOD_LINEAR) 175 return 0; 176 177 return AMD_FMT_MOD_GET(TILE, modifier); 178} 179 180static void fill_gfx8_tiling_info_from_flags(union dc_tiling_info *tiling_info, 181 uint64_t tiling_flags) 182{ 183 /* Fill GFX8 params */ 184 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) { 185 unsigned int bankw, bankh, mtaspect, tile_split, num_banks; 186 187 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); 188 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); 189 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); 190 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); 191 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); 192 193 /* XXX fix me for VI */ 194 tiling_info->gfx8.num_banks = num_banks; 195 tiling_info->gfx8.array_mode = 196 DC_ARRAY_2D_TILED_THIN1; 197 tiling_info->gfx8.tile_split = tile_split; 198 tiling_info->gfx8.bank_width = bankw; 199 tiling_info->gfx8.bank_height = bankh; 200 tiling_info->gfx8.tile_aspect = mtaspect; 201 tiling_info->gfx8.tile_mode = 202 DC_ADDR_SURF_MICRO_TILING_DISPLAY; 203 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) 204 == DC_ARRAY_1D_TILED_THIN1) { 205 tiling_info->gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1; 206 } 207 208 tiling_info->gfx8.pipe_config = 209 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); 210} 211 212static void fill_gfx9_tiling_info_from_device(const struct amdgpu_device *adev, 213 union dc_tiling_info *tiling_info) 214{ 215 /* Fill GFX9 params */ 216 tiling_info->gfx9.num_pipes = 217 adev->gfx.config.gb_addr_config_fields.num_pipes; 218 tiling_info->gfx9.num_banks = 219 adev->gfx.config.gb_addr_config_fields.num_banks; 220 tiling_info->gfx9.pipe_interleave = 221 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size; 222 tiling_info->gfx9.num_shader_engines = 223 adev->gfx.config.gb_addr_config_fields.num_se; 224 tiling_info->gfx9.max_compressed_frags = 225 adev->gfx.config.gb_addr_config_fields.max_compress_frags; 226 tiling_info->gfx9.num_rb_per_se = 227 adev->gfx.config.gb_addr_config_fields.num_rb_per_se; 228 tiling_info->gfx9.shaderEnable = 1; 229 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) 230 tiling_info->gfx9.num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs; 231} 232 233static void fill_gfx9_tiling_info_from_modifier(const struct amdgpu_device *adev, 234 union dc_tiling_info *tiling_info, 235 uint64_t modifier) 236{ 237 unsigned int mod_bank_xor_bits = AMD_FMT_MOD_GET(BANK_XOR_BITS, modifier); 238 unsigned int mod_pipe_xor_bits = AMD_FMT_MOD_GET(PIPE_XOR_BITS, modifier); 239 unsigned int pkrs_log2 = AMD_FMT_MOD_GET(PACKERS, modifier); 240 unsigned int pipes_log2; 241 242 pipes_log2 = min(5u, mod_pipe_xor_bits); 243 244 fill_gfx9_tiling_info_from_device(adev, tiling_info); 245 246 if (!IS_AMD_FMT_MOD(modifier)) 247 return; 248 249 tiling_info->gfx9.num_pipes = 1u << pipes_log2; 250 tiling_info->gfx9.num_shader_engines = 1u << (mod_pipe_xor_bits - pipes_log2); 251 252 if (adev->family >= AMDGPU_FAMILY_NV) { 253 tiling_info->gfx9.num_pkrs = 1u << pkrs_log2; 254 } else { 255 tiling_info->gfx9.num_banks = 1u << mod_bank_xor_bits; 256 257 /* for DCC we know it isn't rb aligned, so rb_per_se doesn't matter. */ 258 } 259} 260 261static int validate_dcc(struct amdgpu_device *adev, 262 const enum surface_pixel_format format, 263 const enum dc_rotation_angle rotation, 264 const union dc_tiling_info *tiling_info, 265 const struct dc_plane_dcc_param *dcc, 266 const struct dc_plane_address *address, 267 const struct plane_size *plane_size) 268{ 269 struct dc *dc = adev->dm.dc; 270 struct dc_dcc_surface_param input; 271 struct dc_surface_dcc_cap output; 272 273 memset(&input, 0, sizeof(input)); 274 memset(&output, 0, sizeof(output)); 275 276 if (!dcc->enable) 277 return 0; 278 279 if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || 280 !dc->cap_funcs.get_dcc_compression_cap) 281 return -EINVAL; 282 283 input.format = format; 284 input.surface_size.width = plane_size->surface_size.width; 285 input.surface_size.height = plane_size->surface_size.height; 286 input.swizzle_mode = tiling_info->gfx9.swizzle; 287 288 if (rotation == ROTATION_ANGLE_0 || rotation == ROTATION_ANGLE_180) 289 input.scan = SCAN_DIRECTION_HORIZONTAL; 290 else if (rotation == ROTATION_ANGLE_90 || rotation == ROTATION_ANGLE_270) 291 input.scan = SCAN_DIRECTION_VERTICAL; 292 293 if (!dc->cap_funcs.get_dcc_compression_cap(dc, &input, &output)) 294 return -EINVAL; 295 296 if (!output.capable) 297 return -EINVAL; 298 299 if (dcc->independent_64b_blks == 0 && 300 output.grph.rgb.independent_64b_blks != 0) 301 return -EINVAL; 302 303 return 0; 304} 305 306static int fill_gfx9_plane_attributes_from_modifiers(struct amdgpu_device *adev, 307 const struct amdgpu_framebuffer *afb, 308 const enum surface_pixel_format format, 309 const enum dc_rotation_angle rotation, 310 const struct plane_size *plane_size, 311 union dc_tiling_info *tiling_info, 312 struct dc_plane_dcc_param *dcc, 313 struct dc_plane_address *address, 314 const bool force_disable_dcc) 315{ 316 const uint64_t modifier = afb->base.modifier; 317 int ret = 0; 318 319 fill_gfx9_tiling_info_from_modifier(adev, tiling_info, modifier); 320 tiling_info->gfx9.swizzle = modifier_gfx9_swizzle_mode(modifier); 321 322 if (modifier_has_dcc(modifier) && !force_disable_dcc) { 323 uint64_t dcc_address = afb->address + afb->base.offsets[1]; 324 bool independent_64b_blks = AMD_FMT_MOD_GET(DCC_INDEPENDENT_64B, modifier); 325 bool independent_128b_blks = AMD_FMT_MOD_GET(DCC_INDEPENDENT_128B, modifier); 326 327 dcc->enable = 1; 328 dcc->meta_pitch = afb->base.pitches[1]; 329 dcc->independent_64b_blks = independent_64b_blks; 330 if (AMD_FMT_MOD_GET(TILE_VERSION, modifier) >= AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) { 331 if (independent_64b_blks && independent_128b_blks) 332 dcc->dcc_ind_blk = hubp_ind_block_64b_no_128bcl; 333 else if (independent_128b_blks) 334 dcc->dcc_ind_blk = hubp_ind_block_128b; 335 else if (independent_64b_blks && !independent_128b_blks) 336 dcc->dcc_ind_blk = hubp_ind_block_64b; 337 else 338 dcc->dcc_ind_blk = hubp_ind_block_unconstrained; 339 } else { 340 if (independent_64b_blks) 341 dcc->dcc_ind_blk = hubp_ind_block_64b; 342 else 343 dcc->dcc_ind_blk = hubp_ind_block_unconstrained; 344 } 345 346 address->grph.meta_addr.low_part = lower_32_bits(dcc_address); 347 address->grph.meta_addr.high_part = upper_32_bits(dcc_address); 348 } 349 350 ret = validate_dcc(adev, format, rotation, tiling_info, dcc, address, plane_size); 351 if (ret) 352 drm_dbg_kms(adev_to_drm(adev), "validate_dcc: returned error: %d\n", ret); 353 354 return ret; 355} 356 357static void add_gfx10_1_modifiers(const struct amdgpu_device *adev, 358 uint64_t **mods, uint64_t *size, uint64_t *capacity) 359{ 360 int pipe_xor_bits = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes); 361 362 add_modifier(mods, size, capacity, AMD_FMT_MOD | 363 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 364 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) | 365 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 366 AMD_FMT_MOD_SET(DCC, 1) | 367 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) | 368 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 369 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B)); 370 371 add_modifier(mods, size, capacity, AMD_FMT_MOD | 372 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 373 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) | 374 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 375 AMD_FMT_MOD_SET(DCC, 1) | 376 AMD_FMT_MOD_SET(DCC_RETILE, 1) | 377 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) | 378 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 379 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B)); 380 381 add_modifier(mods, size, capacity, AMD_FMT_MOD | 382 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 383 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) | 384 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits)); 385 386 add_modifier(mods, size, capacity, AMD_FMT_MOD | 387 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) | 388 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) | 389 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits)); 390 391 392 /* Only supported for 64bpp, will be filtered in dm_plane_format_mod_supported */ 393 add_modifier(mods, size, capacity, AMD_FMT_MOD | 394 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D) | 395 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9)); 396 397 add_modifier(mods, size, capacity, AMD_FMT_MOD | 398 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S) | 399 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9)); 400} 401 402static void add_gfx9_modifiers(const struct amdgpu_device *adev, 403 uint64_t **mods, uint64_t *size, uint64_t *capacity) 404{ 405 int pipes = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes); 406 int pipe_xor_bits = min(8, pipes + 407 ilog2(adev->gfx.config.gb_addr_config_fields.num_se)); 408 int bank_xor_bits = min(8 - pipe_xor_bits, 409 ilog2(adev->gfx.config.gb_addr_config_fields.num_banks)); 410 int rb = ilog2(adev->gfx.config.gb_addr_config_fields.num_se) + 411 ilog2(adev->gfx.config.gb_addr_config_fields.num_rb_per_se); 412 413 414 if (adev->family == AMDGPU_FAMILY_RV) { 415 /* Raven2 and later */ 416 bool has_constant_encode = adev->asic_type > CHIP_RAVEN || adev->external_rev_id >= 0x81; 417 418 /* 419 * No _D DCC swizzles yet because we only allow 32bpp, which 420 * doesn't support _D on DCN 421 */ 422 423 if (has_constant_encode) { 424 add_modifier(mods, size, capacity, AMD_FMT_MOD | 425 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) | 426 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) | 427 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 428 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) | 429 AMD_FMT_MOD_SET(DCC, 1) | 430 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 431 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) | 432 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1)); 433 } 434 435 add_modifier(mods, size, capacity, AMD_FMT_MOD | 436 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) | 437 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) | 438 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 439 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) | 440 AMD_FMT_MOD_SET(DCC, 1) | 441 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 442 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) | 443 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 0)); 444 445 if (has_constant_encode) { 446 add_modifier(mods, size, capacity, AMD_FMT_MOD | 447 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) | 448 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) | 449 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 450 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) | 451 AMD_FMT_MOD_SET(DCC, 1) | 452 AMD_FMT_MOD_SET(DCC_RETILE, 1) | 453 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 454 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) | 455 456 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) | 457 AMD_FMT_MOD_SET(RB, rb) | 458 AMD_FMT_MOD_SET(PIPE, pipes)); 459 } 460 461 add_modifier(mods, size, capacity, AMD_FMT_MOD | 462 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) | 463 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) | 464 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 465 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) | 466 AMD_FMT_MOD_SET(DCC, 1) | 467 AMD_FMT_MOD_SET(DCC_RETILE, 1) | 468 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 469 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) | 470 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 0) | 471 AMD_FMT_MOD_SET(RB, rb) | 472 AMD_FMT_MOD_SET(PIPE, pipes)); 473 } 474 475 /* 476 * Only supported for 64bpp on Raven, will be filtered on format in 477 * dm_plane_format_mod_supported. 478 */ 479 add_modifier(mods, size, capacity, AMD_FMT_MOD | 480 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D_X) | 481 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) | 482 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 483 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits)); 484 485 if (adev->family == AMDGPU_FAMILY_RV) { 486 add_modifier(mods, size, capacity, AMD_FMT_MOD | 487 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) | 488 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) | 489 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 490 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits)); 491 } 492 493 /* 494 * Only supported for 64bpp on Raven, will be filtered on format in 495 * dm_plane_format_mod_supported. 496 */ 497 add_modifier(mods, size, capacity, AMD_FMT_MOD | 498 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D) | 499 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9)); 500 501 if (adev->family == AMDGPU_FAMILY_RV) { 502 add_modifier(mods, size, capacity, AMD_FMT_MOD | 503 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S) | 504 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9)); 505 } 506} 507 508static void add_gfx10_3_modifiers(const struct amdgpu_device *adev, 509 uint64_t **mods, uint64_t *size, uint64_t *capacity) 510{ 511 int pipe_xor_bits = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes); 512 int pkrs = ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs); 513 514 add_modifier(mods, size, capacity, AMD_FMT_MOD | 515 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 516 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) | 517 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 518 AMD_FMT_MOD_SET(PACKERS, pkrs) | 519 AMD_FMT_MOD_SET(DCC, 1) | 520 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) | 521 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 522 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) | 523 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B)); 524 525 add_modifier(mods, size, capacity, AMD_FMT_MOD | 526 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 527 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) | 528 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 529 AMD_FMT_MOD_SET(PACKERS, pkrs) | 530 AMD_FMT_MOD_SET(DCC, 1) | 531 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) | 532 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) | 533 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B)); 534 535 add_modifier(mods, size, capacity, AMD_FMT_MOD | 536 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 537 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) | 538 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 539 AMD_FMT_MOD_SET(PACKERS, pkrs) | 540 AMD_FMT_MOD_SET(DCC, 1) | 541 AMD_FMT_MOD_SET(DCC_RETILE, 1) | 542 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) | 543 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 544 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) | 545 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B)); 546 547 add_modifier(mods, size, capacity, AMD_FMT_MOD | 548 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 549 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) | 550 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 551 AMD_FMT_MOD_SET(PACKERS, pkrs) | 552 AMD_FMT_MOD_SET(DCC, 1) | 553 AMD_FMT_MOD_SET(DCC_RETILE, 1) | 554 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) | 555 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) | 556 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B)); 557 558 add_modifier(mods, size, capacity, AMD_FMT_MOD | 559 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | 560 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) | 561 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 562 AMD_FMT_MOD_SET(PACKERS, pkrs)); 563 564 add_modifier(mods, size, capacity, AMD_FMT_MOD | 565 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) | 566 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) | 567 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 568 AMD_FMT_MOD_SET(PACKERS, pkrs)); 569 570 /* Only supported for 64bpp, will be filtered in dm_plane_format_mod_supported */ 571 add_modifier(mods, size, capacity, AMD_FMT_MOD | 572 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D) | 573 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9)); 574 575 add_modifier(mods, size, capacity, AMD_FMT_MOD | 576 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S) | 577 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9)); 578} 579 580static void add_gfx11_modifiers(struct amdgpu_device *adev, 581 uint64_t **mods, uint64_t *size, uint64_t *capacity) 582{ 583 int num_pipes = 0; 584 int pipe_xor_bits = 0; 585 int num_pkrs = 0; 586 int pkrs = 0; 587 u32 gb_addr_config; 588 u8 i = 0; 589 unsigned int swizzle_r_x; 590 uint64_t modifier_r_x; 591 uint64_t modifier_dcc_best; 592 uint64_t modifier_dcc_4k; 593 594 /* TODO: GFX11 IP HW init hasnt finish and we get zero if we read from 595 * adev->gfx.config.gb_addr_config_fields.num_{pkrs,pipes} 596 */ 597 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG); 598 ASSERT(gb_addr_config != 0); 599 600 num_pkrs = 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 601 pkrs = ilog2(num_pkrs); 602 num_pipes = 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PIPES); 603 pipe_xor_bits = ilog2(num_pipes); 604 605 for (i = 0; i < 2; i++) { 606 /* Insert the best one first. */ 607 /* R_X swizzle modes are the best for rendering and DCC requires them. */ 608 if (num_pipes > 16) 609 swizzle_r_x = !i ? AMD_FMT_MOD_TILE_GFX11_256K_R_X : AMD_FMT_MOD_TILE_GFX9_64K_R_X; 610 else 611 swizzle_r_x = !i ? AMD_FMT_MOD_TILE_GFX9_64K_R_X : AMD_FMT_MOD_TILE_GFX11_256K_R_X; 612 613 modifier_r_x = AMD_FMT_MOD | 614 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX11) | 615 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 616 AMD_FMT_MOD_SET(TILE, swizzle_r_x) | 617 AMD_FMT_MOD_SET(PACKERS, pkrs); 618 619 /* DCC_CONSTANT_ENCODE is not set because it can't vary with gfx11 (it's implied to be 1). */ 620 modifier_dcc_best = modifier_r_x | AMD_FMT_MOD_SET(DCC, 1) | 621 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 0) | 622 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) | 623 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B); 624 625 /* DCC settings for 4K and greater resolutions. (required by display hw) */ 626 modifier_dcc_4k = modifier_r_x | AMD_FMT_MOD_SET(DCC, 1) | 627 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | 628 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) | 629 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B); 630 631 add_modifier(mods, size, capacity, modifier_dcc_best); 632 add_modifier(mods, size, capacity, modifier_dcc_4k); 633 634 add_modifier(mods, size, capacity, modifier_dcc_best | AMD_FMT_MOD_SET(DCC_RETILE, 1)); 635 add_modifier(mods, size, capacity, modifier_dcc_4k | AMD_FMT_MOD_SET(DCC_RETILE, 1)); 636 637 add_modifier(mods, size, capacity, modifier_r_x); 638 } 639 640 add_modifier(mods, size, capacity, AMD_FMT_MOD | 641 AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX11) | 642 AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D)); 643} 644 645static int get_plane_modifiers(struct amdgpu_device *adev, unsigned int plane_type, uint64_t **mods) 646{ 647 uint64_t size = 0, capacity = 128; 648 *mods = NULL; 649 650 /* We have not hooked up any pre-GFX9 modifiers. */ 651 if (adev->family < AMDGPU_FAMILY_AI) 652 return 0; 653 654 *mods = kmalloc(capacity * sizeof(uint64_t), GFP_KERNEL); 655 656 if (plane_type == DRM_PLANE_TYPE_CURSOR) { 657 add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_LINEAR); 658 add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_INVALID); 659 return *mods ? 0 : -ENOMEM; 660 } 661 662 switch (adev->family) { 663 case AMDGPU_FAMILY_AI: 664 case AMDGPU_FAMILY_RV: 665 add_gfx9_modifiers(adev, mods, &size, &capacity); 666 break; 667 case AMDGPU_FAMILY_NV: 668 case AMDGPU_FAMILY_VGH: 669 case AMDGPU_FAMILY_YC: 670 case AMDGPU_FAMILY_GC_10_3_6: 671 case AMDGPU_FAMILY_GC_10_3_7: 672 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) 673 add_gfx10_3_modifiers(adev, mods, &size, &capacity); 674 else 675 add_gfx10_1_modifiers(adev, mods, &size, &capacity); 676 break; 677 case AMDGPU_FAMILY_GC_11_0_0: 678 case AMDGPU_FAMILY_GC_11_0_1: 679 add_gfx11_modifiers(adev, mods, &size, &capacity); 680 break; 681 } 682 683 add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_LINEAR); 684 685 /* INVALID marks the end of the list. */ 686 add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_INVALID); 687 688 if (!*mods) 689 return -ENOMEM; 690 691 return 0; 692} 693 694static int get_plane_formats(const struct drm_plane *plane, 695 const struct dc_plane_cap *plane_cap, 696 uint32_t *formats, int max_formats) 697{ 698 int i, num_formats = 0; 699 700 /* 701 * TODO: Query support for each group of formats directly from 702 * DC plane caps. This will require adding more formats to the 703 * caps list. 704 */ 705 706 if (plane->type == DRM_PLANE_TYPE_PRIMARY || 707 (plane_cap && plane_cap->type == DC_PLANE_TYPE_DCN_UNIVERSAL && plane->type != DRM_PLANE_TYPE_CURSOR)) { 708 for (i = 0; i < ARRAY_SIZE(rgb_formats); ++i) { 709 if (num_formats >= max_formats) 710 break; 711 712 formats[num_formats++] = rgb_formats[i]; 713 } 714 715 if (plane_cap && plane_cap->pixel_format_support.nv12) 716 formats[num_formats++] = DRM_FORMAT_NV12; 717 if (plane_cap && plane_cap->pixel_format_support.p010) 718 formats[num_formats++] = DRM_FORMAT_P010; 719 if (plane_cap && plane_cap->pixel_format_support.fp16) { 720 formats[num_formats++] = DRM_FORMAT_XRGB16161616F; 721 formats[num_formats++] = DRM_FORMAT_ARGB16161616F; 722 formats[num_formats++] = DRM_FORMAT_XBGR16161616F; 723 formats[num_formats++] = DRM_FORMAT_ABGR16161616F; 724 } 725 } else { 726 switch (plane->type) { 727 case DRM_PLANE_TYPE_OVERLAY: 728 for (i = 0; i < ARRAY_SIZE(overlay_formats); ++i) { 729 if (num_formats >= max_formats) 730 break; 731 732 formats[num_formats++] = overlay_formats[i]; 733 } 734 break; 735 736 case DRM_PLANE_TYPE_CURSOR: 737 for (i = 0; i < ARRAY_SIZE(cursor_formats); ++i) { 738 if (num_formats >= max_formats) 739 break; 740 741 formats[num_formats++] = cursor_formats[i]; 742 } 743 break; 744 745 default: 746 break; 747 } 748 } 749 750 return num_formats; 751} 752 753int amdgpu_dm_plane_fill_plane_buffer_attributes(struct amdgpu_device *adev, 754 const struct amdgpu_framebuffer *afb, 755 const enum surface_pixel_format format, 756 const enum dc_rotation_angle rotation, 757 const uint64_t tiling_flags, 758 union dc_tiling_info *tiling_info, 759 struct plane_size *plane_size, 760 struct dc_plane_dcc_param *dcc, 761 struct dc_plane_address *address, 762 bool tmz_surface, 763 bool force_disable_dcc) 764{ 765 const struct drm_framebuffer *fb = &afb->base; 766 int ret; 767 768 memset(tiling_info, 0, sizeof(*tiling_info)); 769 memset(plane_size, 0, sizeof(*plane_size)); 770 memset(dcc, 0, sizeof(*dcc)); 771 memset(address, 0, sizeof(*address)); 772 773 address->tmz_surface = tmz_surface; 774 775 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { 776 uint64_t addr = afb->address + fb->offsets[0]; 777 778 plane_size->surface_size.x = 0; 779 plane_size->surface_size.y = 0; 780 plane_size->surface_size.width = fb->width; 781 plane_size->surface_size.height = fb->height; 782 plane_size->surface_pitch = 783 fb->pitches[0] / fb->format->cpp[0]; 784 785 address->type = PLN_ADDR_TYPE_GRAPHICS; 786 address->grph.addr.low_part = lower_32_bits(addr); 787 address->grph.addr.high_part = upper_32_bits(addr); 788 } else if (format < SURFACE_PIXEL_FORMAT_INVALID) { 789 uint64_t luma_addr = afb->address + fb->offsets[0]; 790 uint64_t chroma_addr = afb->address + fb->offsets[1]; 791 792 plane_size->surface_size.x = 0; 793 plane_size->surface_size.y = 0; 794 plane_size->surface_size.width = fb->width; 795 plane_size->surface_size.height = fb->height; 796 plane_size->surface_pitch = 797 fb->pitches[0] / fb->format->cpp[0]; 798 799 plane_size->chroma_size.x = 0; 800 plane_size->chroma_size.y = 0; 801 /* TODO: set these based on surface format */ 802 plane_size->chroma_size.width = fb->width / 2; 803 plane_size->chroma_size.height = fb->height / 2; 804 805 plane_size->chroma_pitch = 806 fb->pitches[1] / fb->format->cpp[1]; 807 808 address->type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE; 809 address->video_progressive.luma_addr.low_part = 810 lower_32_bits(luma_addr); 811 address->video_progressive.luma_addr.high_part = 812 upper_32_bits(luma_addr); 813 address->video_progressive.chroma_addr.low_part = 814 lower_32_bits(chroma_addr); 815 address->video_progressive.chroma_addr.high_part = 816 upper_32_bits(chroma_addr); 817 } 818 819 if (adev->family >= AMDGPU_FAMILY_AI) { 820 ret = fill_gfx9_plane_attributes_from_modifiers(adev, afb, format, 821 rotation, plane_size, 822 tiling_info, dcc, 823 address, 824 force_disable_dcc); 825 if (ret) 826 return ret; 827 } else { 828 fill_gfx8_tiling_info_from_flags(tiling_info, tiling_flags); 829 } 830 831 return 0; 832} 833 834static int dm_plane_helper_prepare_fb(struct drm_plane *plane, 835 struct drm_plane_state *new_state) 836{ 837 struct amdgpu_framebuffer *afb; 838 struct drm_gem_object *obj; 839 struct amdgpu_device *adev; 840 struct amdgpu_bo *rbo; 841 struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old; 842 uint32_t domain; 843 int r; 844 845 if (!new_state->fb) { 846 DRM_DEBUG_KMS("No FB bound\n"); 847 return 0; 848 } 849 850 afb = to_amdgpu_framebuffer(new_state->fb); 851 obj = new_state->fb->obj[0]; 852 rbo = gem_to_amdgpu_bo(obj); 853 adev = amdgpu_ttm_adev(rbo->tbo.bdev); 854 855 r = amdgpu_bo_reserve(rbo, true); 856 if (r) { 857 dev_err(adev->dev, "fail to reserve bo (%d)\n", r); 858 return r; 859 } 860 861 r = dma_resv_reserve_fences(rbo->tbo.base.resv, 1); 862 if (r) { 863 dev_err(adev->dev, "reserving fence slot failed (%d)\n", r); 864 goto error_unlock; 865 } 866 867 if (plane->type != DRM_PLANE_TYPE_CURSOR) 868 domain = amdgpu_display_supported_domains(adev, rbo->flags); 869 else 870 domain = AMDGPU_GEM_DOMAIN_VRAM; 871 872 r = amdgpu_bo_pin(rbo, domain); 873 if (unlikely(r != 0)) { 874 if (r != -ERESTARTSYS) 875 DRM_ERROR("Failed to pin framebuffer with error %d\n", r); 876 goto error_unlock; 877 } 878 879 r = amdgpu_ttm_alloc_gart(&rbo->tbo); 880 if (unlikely(r != 0)) { 881 DRM_ERROR("%p bind failed\n", rbo); 882 goto error_unpin; 883 } 884 885 r = drm_gem_plane_helper_prepare_fb(plane, new_state); 886 if (unlikely(r != 0)) 887 goto error_unpin; 888 889 amdgpu_bo_unreserve(rbo); 890 891 afb->address = amdgpu_bo_gpu_offset(rbo); 892 893 amdgpu_bo_ref(rbo); 894 895 /** 896 * We don't do surface updates on planes that have been newly created, 897 * but we also don't have the afb->address during atomic check. 898 * 899 * Fill in buffer attributes depending on the address here, but only on 900 * newly created planes since they're not being used by DC yet and this 901 * won't modify global state. 902 */ 903 dm_plane_state_old = to_dm_plane_state(plane->state); 904 dm_plane_state_new = to_dm_plane_state(new_state); 905 906 if (dm_plane_state_new->dc_state && 907 dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) { 908 struct dc_plane_state *plane_state = 909 dm_plane_state_new->dc_state; 910 bool force_disable_dcc = !plane_state->dcc.enable; 911 912 amdgpu_dm_plane_fill_plane_buffer_attributes( 913 adev, afb, plane_state->format, plane_state->rotation, 914 afb->tiling_flags, 915 &plane_state->tiling_info, &plane_state->plane_size, 916 &plane_state->dcc, &plane_state->address, 917 afb->tmz_surface, force_disable_dcc); 918 } 919 920 return 0; 921 922error_unpin: 923 amdgpu_bo_unpin(rbo); 924 925error_unlock: 926 amdgpu_bo_unreserve(rbo); 927 return r; 928} 929 930static void dm_plane_helper_cleanup_fb(struct drm_plane *plane, 931 struct drm_plane_state *old_state) 932{ 933 struct amdgpu_bo *rbo; 934 int r; 935 936 if (!old_state->fb) 937 return; 938 939 rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]); 940 r = amdgpu_bo_reserve(rbo, false); 941 if (unlikely(r)) { 942 DRM_ERROR("failed to reserve rbo before unpin\n"); 943 return; 944 } 945 946 amdgpu_bo_unpin(rbo); 947 amdgpu_bo_unreserve(rbo); 948 amdgpu_bo_unref(&rbo); 949} 950 951static void get_min_max_dc_plane_scaling(struct drm_device *dev, 952 struct drm_framebuffer *fb, 953 int *min_downscale, int *max_upscale) 954{ 955 struct amdgpu_device *adev = drm_to_adev(dev); 956 struct dc *dc = adev->dm.dc; 957 /* Caps for all supported planes are the same on DCE and DCN 1 - 3 */ 958 struct dc_plane_cap *plane_cap = &dc->caps.planes[0]; 959 960 switch (fb->format->format) { 961 case DRM_FORMAT_P010: 962 case DRM_FORMAT_NV12: 963 case DRM_FORMAT_NV21: 964 *max_upscale = plane_cap->max_upscale_factor.nv12; 965 *min_downscale = plane_cap->max_downscale_factor.nv12; 966 break; 967 968 case DRM_FORMAT_XRGB16161616F: 969 case DRM_FORMAT_ARGB16161616F: 970 case DRM_FORMAT_XBGR16161616F: 971 case DRM_FORMAT_ABGR16161616F: 972 *max_upscale = plane_cap->max_upscale_factor.fp16; 973 *min_downscale = plane_cap->max_downscale_factor.fp16; 974 break; 975 976 default: 977 *max_upscale = plane_cap->max_upscale_factor.argb8888; 978 *min_downscale = plane_cap->max_downscale_factor.argb8888; 979 break; 980 } 981 982 /* 983 * A factor of 1 in the plane_cap means to not allow scaling, ie. use a 984 * scaling factor of 1.0 == 1000 units. 985 */ 986 if (*max_upscale == 1) 987 *max_upscale = 1000; 988 989 if (*min_downscale == 1) 990 *min_downscale = 1000; 991} 992 993int amdgpu_dm_plane_helper_check_state(struct drm_plane_state *state, 994 struct drm_crtc_state *new_crtc_state) 995{ 996 struct drm_framebuffer *fb = state->fb; 997 int min_downscale, max_upscale; 998 int min_scale = 0; 999 int max_scale = INT_MAX; 1000 1001 /* Plane enabled? Validate viewport and get scaling factors from plane caps. */ 1002 if (fb && state->crtc) { 1003 /* Validate viewport to cover the case when only the position changes */ 1004 if (state->plane->type != DRM_PLANE_TYPE_CURSOR) { 1005 int viewport_width = state->crtc_w; 1006 int viewport_height = state->crtc_h; 1007 1008 if (state->crtc_x < 0) 1009 viewport_width += state->crtc_x; 1010 else if (state->crtc_x + state->crtc_w > new_crtc_state->mode.crtc_hdisplay) 1011 viewport_width = new_crtc_state->mode.crtc_hdisplay - state->crtc_x; 1012 1013 if (state->crtc_y < 0) 1014 viewport_height += state->crtc_y; 1015 else if (state->crtc_y + state->crtc_h > new_crtc_state->mode.crtc_vdisplay) 1016 viewport_height = new_crtc_state->mode.crtc_vdisplay - state->crtc_y; 1017 1018 if (viewport_width < 0 || viewport_height < 0) { 1019 DRM_DEBUG_ATOMIC("Plane completely outside of screen\n"); 1020 return -EINVAL; 1021 } else if (viewport_width < MIN_VIEWPORT_SIZE*2) { /* x2 for width is because of pipe-split. */ 1022 DRM_DEBUG_ATOMIC("Viewport width %d smaller than %d\n", viewport_width, MIN_VIEWPORT_SIZE*2); 1023 return -EINVAL; 1024 } else if (viewport_height < MIN_VIEWPORT_SIZE) { 1025 DRM_DEBUG_ATOMIC("Viewport height %d smaller than %d\n", viewport_height, MIN_VIEWPORT_SIZE); 1026 return -EINVAL; 1027 } 1028 1029 } 1030 1031 /* Get min/max allowed scaling factors from plane caps. */ 1032 get_min_max_dc_plane_scaling(state->crtc->dev, fb, 1033 &min_downscale, &max_upscale); 1034 /* 1035 * Convert to drm convention: 16.16 fixed point, instead of dc's 1036 * 1.0 == 1000. Also drm scaling is src/dst instead of dc's 1037 * dst/src, so min_scale = 1.0 / max_upscale, etc. 1038 */ 1039 min_scale = (1000 << 16) / max_upscale; 1040 max_scale = (1000 << 16) / min_downscale; 1041 } 1042 1043 return drm_atomic_helper_check_plane_state( 1044 state, new_crtc_state, min_scale, max_scale, true, true); 1045} 1046 1047int amdgpu_dm_plane_fill_dc_scaling_info(struct amdgpu_device *adev, 1048 const struct drm_plane_state *state, 1049 struct dc_scaling_info *scaling_info) 1050{ 1051 int scale_w, scale_h, min_downscale, max_upscale; 1052 1053 memset(scaling_info, 0, sizeof(*scaling_info)); 1054 1055 /* Source is fixed 16.16 but we ignore mantissa for now... */ 1056 scaling_info->src_rect.x = state->src_x >> 16; 1057 scaling_info->src_rect.y = state->src_y >> 16; 1058 1059 /* 1060 * For reasons we don't (yet) fully understand a non-zero 1061 * src_y coordinate into an NV12 buffer can cause a 1062 * system hang on DCN1x. 1063 * To avoid hangs (and maybe be overly cautious) 1064 * let's reject both non-zero src_x and src_y. 1065 * 1066 * We currently know of only one use-case to reproduce a 1067 * scenario with non-zero src_x and src_y for NV12, which 1068 * is to gesture the YouTube Android app into full screen 1069 * on ChromeOS. 1070 */ 1071 if (((adev->ip_versions[DCE_HWIP][0] == IP_VERSION(1, 0, 0)) || 1072 (adev->ip_versions[DCE_HWIP][0] == IP_VERSION(1, 0, 1))) && 1073 (state->fb && state->fb->format->format == DRM_FORMAT_NV12 && 1074 (scaling_info->src_rect.x != 0 || scaling_info->src_rect.y != 0))) 1075 return -EINVAL; 1076 1077 scaling_info->src_rect.width = state->src_w >> 16; 1078 if (scaling_info->src_rect.width == 0) 1079 return -EINVAL; 1080 1081 scaling_info->src_rect.height = state->src_h >> 16; 1082 if (scaling_info->src_rect.height == 0) 1083 return -EINVAL; 1084 1085 scaling_info->dst_rect.x = state->crtc_x; 1086 scaling_info->dst_rect.y = state->crtc_y; 1087 1088 if (state->crtc_w == 0) 1089 return -EINVAL; 1090 1091 scaling_info->dst_rect.width = state->crtc_w; 1092 1093 if (state->crtc_h == 0) 1094 return -EINVAL; 1095 1096 scaling_info->dst_rect.height = state->crtc_h; 1097 1098 /* DRM doesn't specify clipping on destination output. */ 1099 scaling_info->clip_rect = scaling_info->dst_rect; 1100 1101 /* Validate scaling per-format with DC plane caps */ 1102 if (state->plane && state->plane->dev && state->fb) { 1103 get_min_max_dc_plane_scaling(state->plane->dev, state->fb, 1104 &min_downscale, &max_upscale); 1105 } else { 1106 min_downscale = 250; 1107 max_upscale = 16000; 1108 } 1109 1110 scale_w = scaling_info->dst_rect.width * 1000 / 1111 scaling_info->src_rect.width; 1112 1113 if (scale_w < min_downscale || scale_w > max_upscale) 1114 return -EINVAL; 1115 1116 scale_h = scaling_info->dst_rect.height * 1000 / 1117 scaling_info->src_rect.height; 1118 1119 if (scale_h < min_downscale || scale_h > max_upscale) 1120 return -EINVAL; 1121 1122 /* 1123 * The "scaling_quality" can be ignored for now, quality = 0 has DC 1124 * assume reasonable defaults based on the format. 1125 */ 1126 1127 return 0; 1128} 1129 1130static int dm_plane_atomic_check(struct drm_plane *plane, 1131 struct drm_atomic_state *state) 1132{ 1133 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 1134 plane); 1135 struct amdgpu_device *adev = drm_to_adev(plane->dev); 1136 struct dc *dc = adev->dm.dc; 1137 struct dm_plane_state *dm_plane_state; 1138 struct dc_scaling_info scaling_info; 1139 struct drm_crtc_state *new_crtc_state; 1140 int ret; 1141 1142 trace_amdgpu_dm_plane_atomic_check(new_plane_state); 1143 1144 dm_plane_state = to_dm_plane_state(new_plane_state); 1145 1146 if (!dm_plane_state->dc_state) 1147 return 0; 1148 1149 new_crtc_state = 1150 drm_atomic_get_new_crtc_state(state, 1151 new_plane_state->crtc); 1152 if (!new_crtc_state) 1153 return -EINVAL; 1154 1155 ret = amdgpu_dm_plane_helper_check_state(new_plane_state, new_crtc_state); 1156 if (ret) 1157 return ret; 1158 1159 ret = amdgpu_dm_plane_fill_dc_scaling_info(adev, new_plane_state, &scaling_info); 1160 if (ret) 1161 return ret; 1162 1163 if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK) 1164 return 0; 1165 1166 return -EINVAL; 1167} 1168 1169static int dm_plane_atomic_async_check(struct drm_plane *plane, 1170 struct drm_atomic_state *state) 1171{ 1172 /* Only support async updates on cursor planes. */ 1173 if (plane->type != DRM_PLANE_TYPE_CURSOR) 1174 return -EINVAL; 1175 1176 return 0; 1177} 1178 1179static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc, 1180 struct dc_cursor_position *position) 1181{ 1182 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1183 int x, y; 1184 int xorigin = 0, yorigin = 0; 1185 1186 if (!crtc || !plane->state->fb) 1187 return 0; 1188 1189 if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) || 1190 (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) { 1191 DRM_ERROR("%s: bad cursor width or height %d x %d\n", 1192 __func__, 1193 plane->state->crtc_w, 1194 plane->state->crtc_h); 1195 return -EINVAL; 1196 } 1197 1198 x = plane->state->crtc_x; 1199 y = plane->state->crtc_y; 1200 1201 if (x <= -amdgpu_crtc->max_cursor_width || 1202 y <= -amdgpu_crtc->max_cursor_height) 1203 return 0; 1204 1205 if (x < 0) { 1206 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); 1207 x = 0; 1208 } 1209 if (y < 0) { 1210 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); 1211 y = 0; 1212 } 1213 position->enable = true; 1214 position->translate_by_source = true; 1215 position->x = x; 1216 position->y = y; 1217 position->x_hotspot = xorigin; 1218 position->y_hotspot = yorigin; 1219 1220 return 0; 1221} 1222 1223void amdgpu_dm_plane_handle_cursor_update(struct drm_plane *plane, 1224 struct drm_plane_state *old_plane_state) 1225{ 1226 struct amdgpu_device *adev = drm_to_adev(plane->dev); 1227 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb); 1228 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc; 1229 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL; 1230 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1231 uint64_t address = afb ? afb->address : 0; 1232 struct dc_cursor_position position = {0}; 1233 struct dc_cursor_attributes attributes; 1234 int ret; 1235 1236 if (!plane->state->fb && !old_plane_state->fb) 1237 return; 1238 1239 DC_LOG_CURSOR("%s: crtc_id=%d with size %d to %d\n", 1240 __func__, 1241 amdgpu_crtc->crtc_id, 1242 plane->state->crtc_w, 1243 plane->state->crtc_h); 1244 1245 ret = get_cursor_position(plane, crtc, &position); 1246 if (ret) 1247 return; 1248 1249 if (!position.enable) { 1250 /* turn off cursor */ 1251 if (crtc_state && crtc_state->stream) { 1252 mutex_lock(&adev->dm.dc_lock); 1253 dc_stream_set_cursor_position(crtc_state->stream, 1254 &position); 1255 mutex_unlock(&adev->dm.dc_lock); 1256 } 1257 return; 1258 } 1259 1260 amdgpu_crtc->cursor_width = plane->state->crtc_w; 1261 amdgpu_crtc->cursor_height = plane->state->crtc_h; 1262 1263 memset(&attributes, 0, sizeof(attributes)); 1264 attributes.address.high_part = upper_32_bits(address); 1265 attributes.address.low_part = lower_32_bits(address); 1266 attributes.width = plane->state->crtc_w; 1267 attributes.height = plane->state->crtc_h; 1268 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA; 1269 attributes.rotation_angle = 0; 1270 attributes.attribute_flags.value = 0; 1271 1272 /* Enable cursor degamma ROM on DCN3+ for implicit sRGB degamma in DRM 1273 * legacy gamma setup. 1274 */ 1275 if (crtc_state->cm_is_degamma_srgb && 1276 adev->dm.dc->caps.color.dpp.gamma_corr) 1277 attributes.attribute_flags.bits.ENABLE_CURSOR_DEGAMMA = 1; 1278 1279 attributes.pitch = afb->base.pitches[0] / afb->base.format->cpp[0]; 1280 1281 if (crtc_state->stream) { 1282 mutex_lock(&adev->dm.dc_lock); 1283 if (!dc_stream_set_cursor_attributes(crtc_state->stream, 1284 &attributes)) 1285 DRM_ERROR("DC failed to set cursor attributes\n"); 1286 1287 if (!dc_stream_set_cursor_position(crtc_state->stream, 1288 &position)) 1289 DRM_ERROR("DC failed to set cursor position\n"); 1290 mutex_unlock(&adev->dm.dc_lock); 1291 } 1292} 1293 1294static void dm_plane_atomic_async_update(struct drm_plane *plane, 1295 struct drm_atomic_state *state) 1296{ 1297 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, 1298 plane); 1299 struct drm_plane_state *old_state = 1300 drm_atomic_get_old_plane_state(state, plane); 1301 1302 trace_amdgpu_dm_atomic_update_cursor(new_state); 1303 1304 swap(plane->state->fb, new_state->fb); 1305 1306 plane->state->src_x = new_state->src_x; 1307 plane->state->src_y = new_state->src_y; 1308 plane->state->src_w = new_state->src_w; 1309 plane->state->src_h = new_state->src_h; 1310 plane->state->crtc_x = new_state->crtc_x; 1311 plane->state->crtc_y = new_state->crtc_y; 1312 plane->state->crtc_w = new_state->crtc_w; 1313 plane->state->crtc_h = new_state->crtc_h; 1314 1315 amdgpu_dm_plane_handle_cursor_update(plane, old_state); 1316} 1317 1318static const struct drm_plane_helper_funcs dm_plane_helper_funcs = { 1319 .prepare_fb = dm_plane_helper_prepare_fb, 1320 .cleanup_fb = dm_plane_helper_cleanup_fb, 1321 .atomic_check = dm_plane_atomic_check, 1322 .atomic_async_check = dm_plane_atomic_async_check, 1323 .atomic_async_update = dm_plane_atomic_async_update 1324}; 1325 1326static void dm_drm_plane_reset(struct drm_plane *plane) 1327{ 1328 struct dm_plane_state *amdgpu_state = NULL; 1329 1330 if (plane->state) 1331 plane->funcs->atomic_destroy_state(plane, plane->state); 1332 1333 amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL); 1334 WARN_ON(amdgpu_state == NULL); 1335 1336 if (amdgpu_state) 1337 __drm_atomic_helper_plane_reset(plane, &amdgpu_state->base); 1338} 1339 1340static struct drm_plane_state * 1341dm_drm_plane_duplicate_state(struct drm_plane *plane) 1342{ 1343 struct dm_plane_state *dm_plane_state, *old_dm_plane_state; 1344 1345 old_dm_plane_state = to_dm_plane_state(plane->state); 1346 dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL); 1347 if (!dm_plane_state) 1348 return NULL; 1349 1350 __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base); 1351 1352 if (old_dm_plane_state->dc_state) { 1353 dm_plane_state->dc_state = old_dm_plane_state->dc_state; 1354 dc_plane_state_retain(dm_plane_state->dc_state); 1355 } 1356 1357 return &dm_plane_state->base; 1358} 1359 1360static bool dm_plane_format_mod_supported(struct drm_plane *plane, 1361 uint32_t format, 1362 uint64_t modifier) 1363{ 1364 struct amdgpu_device *adev = drm_to_adev(plane->dev); 1365 const struct drm_format_info *info = drm_format_info(format); 1366 int i; 1367 1368 enum dm_micro_swizzle microtile = modifier_gfx9_swizzle_mode(modifier) & 3; 1369 1370 if (!info) 1371 return false; 1372 1373 /* 1374 * We always have to allow these modifiers: 1375 * 1. Core DRM checks for LINEAR support if userspace does not provide modifiers. 1376 * 2. Not passing any modifiers is the same as explicitly passing INVALID. 1377 */ 1378 if (modifier == DRM_FORMAT_MOD_LINEAR || 1379 modifier == DRM_FORMAT_MOD_INVALID) { 1380 return true; 1381 } 1382 1383 /* Check that the modifier is on the list of the plane's supported modifiers. */ 1384 for (i = 0; i < plane->modifier_count; i++) { 1385 if (modifier == plane->modifiers[i]) 1386 break; 1387 } 1388 if (i == plane->modifier_count) 1389 return false; 1390 1391 /* 1392 * For D swizzle the canonical modifier depends on the bpp, so check 1393 * it here. 1394 */ 1395 if (AMD_FMT_MOD_GET(TILE_VERSION, modifier) == AMD_FMT_MOD_TILE_VER_GFX9 && 1396 adev->family >= AMDGPU_FAMILY_NV) { 1397 if (microtile == MICRO_SWIZZLE_D && info->cpp[0] == 4) 1398 return false; 1399 } 1400 1401 if (adev->family >= AMDGPU_FAMILY_RV && microtile == MICRO_SWIZZLE_D && 1402 info->cpp[0] < 8) 1403 return false; 1404 1405 if (modifier_has_dcc(modifier)) { 1406 /* Per radeonsi comments 16/64 bpp are more complicated. */ 1407 if (info->cpp[0] != 4) 1408 return false; 1409 /* We support multi-planar formats, but not when combined with 1410 * additional DCC metadata planes. 1411 */ 1412 if (info->num_planes > 1) 1413 return false; 1414 } 1415 1416 return true; 1417} 1418 1419static void dm_drm_plane_destroy_state(struct drm_plane *plane, 1420 struct drm_plane_state *state) 1421{ 1422 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state); 1423 1424 if (dm_plane_state->dc_state) 1425 dc_plane_state_release(dm_plane_state->dc_state); 1426 1427 drm_atomic_helper_plane_destroy_state(plane, state); 1428} 1429 1430static const struct drm_plane_funcs dm_plane_funcs = { 1431 .update_plane = drm_atomic_helper_update_plane, 1432 .disable_plane = drm_atomic_helper_disable_plane, 1433 .destroy = drm_plane_helper_destroy, 1434 .reset = dm_drm_plane_reset, 1435 .atomic_duplicate_state = dm_drm_plane_duplicate_state, 1436 .atomic_destroy_state = dm_drm_plane_destroy_state, 1437 .format_mod_supported = dm_plane_format_mod_supported, 1438}; 1439 1440int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, 1441 struct drm_plane *plane, 1442 unsigned long possible_crtcs, 1443 const struct dc_plane_cap *plane_cap) 1444{ 1445 uint32_t formats[32]; 1446 int num_formats; 1447 int res = -EPERM; 1448 unsigned int supported_rotations; 1449 uint64_t *modifiers = NULL; 1450 1451 num_formats = get_plane_formats(plane, plane_cap, formats, 1452 ARRAY_SIZE(formats)); 1453 1454 res = get_plane_modifiers(dm->adev, plane->type, &modifiers); 1455 if (res) 1456 return res; 1457 1458 if (modifiers == NULL) 1459 adev_to_drm(dm->adev)->mode_config.fb_modifiers_not_supported = true; 1460 1461 res = drm_universal_plane_init(adev_to_drm(dm->adev), plane, possible_crtcs, 1462 &dm_plane_funcs, formats, num_formats, 1463 modifiers, plane->type, NULL); 1464 kfree(modifiers); 1465 if (res) 1466 return res; 1467 1468 if (plane->type == DRM_PLANE_TYPE_OVERLAY && 1469 plane_cap && plane_cap->per_pixel_alpha) { 1470 unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) | 1471 BIT(DRM_MODE_BLEND_PREMULTI) | 1472 BIT(DRM_MODE_BLEND_COVERAGE); 1473 1474 drm_plane_create_alpha_property(plane); 1475 drm_plane_create_blend_mode_property(plane, blend_caps); 1476 } 1477 1478 if (plane->type == DRM_PLANE_TYPE_PRIMARY) { 1479 drm_plane_create_zpos_immutable_property(plane, 0); 1480 } else if (plane->type == DRM_PLANE_TYPE_OVERLAY) { 1481 unsigned int zpos = 1 + drm_plane_index(plane); 1482 drm_plane_create_zpos_property(plane, zpos, 1, 254); 1483 } else if (plane->type == DRM_PLANE_TYPE_CURSOR) { 1484 drm_plane_create_zpos_immutable_property(plane, 255); 1485 } 1486 1487 if (plane->type == DRM_PLANE_TYPE_PRIMARY && 1488 plane_cap && 1489 (plane_cap->pixel_format_support.nv12 || 1490 plane_cap->pixel_format_support.p010)) { 1491 /* This only affects YUV formats. */ 1492 drm_plane_create_color_properties( 1493 plane, 1494 BIT(DRM_COLOR_YCBCR_BT601) | 1495 BIT(DRM_COLOR_YCBCR_BT709) | 1496 BIT(DRM_COLOR_YCBCR_BT2020), 1497 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | 1498 BIT(DRM_COLOR_YCBCR_FULL_RANGE), 1499 DRM_COLOR_YCBCR_BT709, DRM_COLOR_YCBCR_LIMITED_RANGE); 1500 } 1501 1502 supported_rotations = 1503 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 | 1504 DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270; 1505 1506 if (dm->adev->asic_type >= CHIP_BONAIRE && 1507 plane->type != DRM_PLANE_TYPE_CURSOR) 1508 drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0, 1509 supported_rotations); 1510 1511 if (dm->adev->ip_versions[DCE_HWIP][0] > IP_VERSION(3, 0, 1) && 1512 plane->type != DRM_PLANE_TYPE_CURSOR) 1513 drm_plane_enable_fb_damage_clips(plane); 1514 1515 drm_plane_helper_add(plane, &dm_plane_helper_funcs); 1516 1517 /* Create (reset) the plane state */ 1518 if (plane->funcs->reset) 1519 plane->funcs->reset(plane); 1520 1521 return 0; 1522} 1523 1524bool is_video_format(uint32_t format) 1525{ 1526 int i; 1527 1528 for (i = 0; i < ARRAY_SIZE(video_formats); i++) 1529 if (format == video_formats[i]) 1530 return true; 1531 1532 return false; 1533} 1534 1535