1/* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26#include <linux/string_helpers.h> 27#include <linux/uaccess.h> 28 29#include "dc.h" 30#include "amdgpu.h" 31#include "amdgpu_dm.h" 32#include "amdgpu_dm_debugfs.h" 33#include "dm_helpers.h" 34#include "dmub/dmub_srv.h" 35#include "resource.h" 36#include "dsc.h" 37#include "link_hwss.h" 38#include "dc/dc_dmub_srv.h" 39#include "link/protocols/link_dp_capability.h" 40 41#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 42#include "amdgpu_dm_psr.h" 43#endif 44 45struct dmub_debugfs_trace_header { 46 uint32_t entry_count; 47 uint32_t reserved[3]; 48}; 49 50struct dmub_debugfs_trace_entry { 51 uint32_t trace_code; 52 uint32_t tick_count; 53 uint32_t param0; 54 uint32_t param1; 55}; 56 57static const char *const mst_progress_status[] = { 58 "probe", 59 "remote_edid", 60 "allocate_new_payload", 61 "clear_allocated_payload", 62}; 63 64/* parse_write_buffer_into_params - Helper function to parse debugfs write buffer into an array 65 * 66 * Function takes in attributes passed to debugfs write entry 67 * and writes into param array. 68 * The user passes max_param_num to identify maximum number of 69 * parameters that could be parsed. 70 * 71 */ 72static int parse_write_buffer_into_params(char *wr_buf, uint32_t wr_buf_size, 73 long *param, const char __user *buf, 74 int max_param_num, 75 uint8_t *param_nums) 76{ 77 char *wr_buf_ptr = NULL; 78 uint32_t wr_buf_count = 0; 79 int r; 80 char *sub_str = NULL; 81 const char delimiter[3] = {' ', '\n', '\0'}; 82 uint8_t param_index = 0; 83 84 *param_nums = 0; 85 86 wr_buf_ptr = wr_buf; 87 88 /* r is bytes not be copied */ 89 if (copy_from_user(wr_buf_ptr, buf, wr_buf_size)) { 90 DRM_DEBUG_DRIVER("user data could not be read successfully\n"); 91 return -EFAULT; 92 } 93 94 /* check number of parameters. isspace could not differ space and \n */ 95 while ((*wr_buf_ptr != 0xa) && (wr_buf_count < wr_buf_size)) { 96 /* skip space*/ 97 while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) { 98 wr_buf_ptr++; 99 wr_buf_count++; 100 } 101 102 if (wr_buf_count == wr_buf_size) 103 break; 104 105 /* skip non-space*/ 106 while ((!isspace(*wr_buf_ptr)) && (wr_buf_count < wr_buf_size)) { 107 wr_buf_ptr++; 108 wr_buf_count++; 109 } 110 111 (*param_nums)++; 112 113 if (wr_buf_count == wr_buf_size) 114 break; 115 } 116 117 if (*param_nums > max_param_num) 118 *param_nums = max_param_num; 119 120 wr_buf_ptr = wr_buf; /* reset buf pointer */ 121 wr_buf_count = 0; /* number of char already checked */ 122 123 while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) { 124 wr_buf_ptr++; 125 wr_buf_count++; 126 } 127 128 while (param_index < *param_nums) { 129 /* after strsep, wr_buf_ptr will be moved to after space */ 130 sub_str = strsep(&wr_buf_ptr, delimiter); 131 132 r = kstrtol(sub_str, 16, &(param[param_index])); 133 134 if (r) 135 DRM_DEBUG_DRIVER("string to int convert error code: %d\n", r); 136 137 param_index++; 138 } 139 140 return 0; 141} 142 143/* function description 144 * get/ set DP configuration: lane_count, link_rate, spread_spectrum 145 * 146 * valid lane count value: 1, 2, 4 147 * valid link rate value: 148 * 06h = 1.62Gbps per lane 149 * 0Ah = 2.7Gbps per lane 150 * 0Ch = 3.24Gbps per lane 151 * 14h = 5.4Gbps per lane 152 * 1Eh = 8.1Gbps per lane 153 * 154 * debugfs is located at /sys/kernel/debug/dri/0/DP-x/link_settings 155 * 156 * --- to get dp configuration 157 * 158 * cat /sys/kernel/debug/dri/0/DP-x/link_settings 159 * 160 * It will list current, verified, reported, preferred dp configuration. 161 * current -- for current video mode 162 * verified --- maximum configuration which pass link training 163 * reported --- DP rx report caps (DPCD register offset 0, 1 2) 164 * preferred --- user force settings 165 * 166 * --- set (or force) dp configuration 167 * 168 * echo <lane_count> <link_rate> > link_settings 169 * 170 * for example, to force to 2 lane, 2.7GHz, 171 * echo 4 0xa > /sys/kernel/debug/dri/0/DP-x/link_settings 172 * 173 * spread_spectrum could not be changed dynamically. 174 * 175 * in case invalid lane count, link rate are force, no hw programming will be 176 * done. please check link settings after force operation to see if HW get 177 * programming. 178 * 179 * cat /sys/kernel/debug/dri/0/DP-x/link_settings 180 * 181 * check current and preferred settings. 182 * 183 */ 184static ssize_t dp_link_settings_read(struct file *f, char __user *buf, 185 size_t size, loff_t *pos) 186{ 187 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 188 struct dc_link *link = connector->dc_link; 189 char *rd_buf = NULL; 190 char *rd_buf_ptr = NULL; 191 const uint32_t rd_buf_size = 100; 192 uint32_t result = 0; 193 uint8_t str_len = 0; 194 int r; 195 196 if (*pos & 3 || size & 3) 197 return -EINVAL; 198 199 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 200 if (!rd_buf) 201 return 0; 202 203 rd_buf_ptr = rd_buf; 204 205 str_len = strlen("Current: %d 0x%x %d "); 206 snprintf(rd_buf_ptr, str_len, "Current: %d 0x%x %d ", 207 link->cur_link_settings.lane_count, 208 link->cur_link_settings.link_rate, 209 link->cur_link_settings.link_spread); 210 rd_buf_ptr += str_len; 211 212 str_len = strlen("Verified: %d 0x%x %d "); 213 snprintf(rd_buf_ptr, str_len, "Verified: %d 0x%x %d ", 214 link->verified_link_cap.lane_count, 215 link->verified_link_cap.link_rate, 216 link->verified_link_cap.link_spread); 217 rd_buf_ptr += str_len; 218 219 str_len = strlen("Reported: %d 0x%x %d "); 220 snprintf(rd_buf_ptr, str_len, "Reported: %d 0x%x %d ", 221 link->reported_link_cap.lane_count, 222 link->reported_link_cap.link_rate, 223 link->reported_link_cap.link_spread); 224 rd_buf_ptr += str_len; 225 226 str_len = strlen("Preferred: %d 0x%x %d "); 227 snprintf(rd_buf_ptr, str_len, "Preferred: %d 0x%x %d\n", 228 link->preferred_link_setting.lane_count, 229 link->preferred_link_setting.link_rate, 230 link->preferred_link_setting.link_spread); 231 232 while (size) { 233 if (*pos >= rd_buf_size) 234 break; 235 236 r = put_user(*(rd_buf + result), buf); 237 if (r) { 238 kfree(rd_buf); 239 return r; /* r = -EFAULT */ 240 } 241 242 buf += 1; 243 size -= 1; 244 *pos += 1; 245 result += 1; 246 } 247 248 kfree(rd_buf); 249 return result; 250} 251 252static ssize_t dp_link_settings_write(struct file *f, const char __user *buf, 253 size_t size, loff_t *pos) 254{ 255 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 256 struct dc_link *link = connector->dc_link; 257 struct amdgpu_device *adev = drm_to_adev(connector->base.dev); 258 struct dc *dc = (struct dc *)link->dc; 259 struct dc_link_settings prefer_link_settings; 260 char *wr_buf = NULL; 261 const uint32_t wr_buf_size = 40; 262 /* 0: lane_count; 1: link_rate */ 263 int max_param_num = 2; 264 uint8_t param_nums = 0; 265 long param[2]; 266 bool valid_input = true; 267 268 if (size == 0) 269 return -EINVAL; 270 271 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 272 if (!wr_buf) 273 return -ENOSPC; 274 275 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 276 (long *)param, buf, 277 max_param_num, 278 ¶m_nums)) { 279 kfree(wr_buf); 280 return -EINVAL; 281 } 282 283 if (param_nums <= 0) { 284 kfree(wr_buf); 285 DRM_DEBUG_DRIVER("user data not be read\n"); 286 return -EINVAL; 287 } 288 289 switch (param[0]) { 290 case LANE_COUNT_ONE: 291 case LANE_COUNT_TWO: 292 case LANE_COUNT_FOUR: 293 break; 294 default: 295 valid_input = false; 296 break; 297 } 298 299 switch (param[1]) { 300 case LINK_RATE_LOW: 301 case LINK_RATE_HIGH: 302 case LINK_RATE_RBR2: 303 case LINK_RATE_HIGH2: 304 case LINK_RATE_HIGH3: 305 case LINK_RATE_UHBR10: 306 case LINK_RATE_UHBR13_5: 307 case LINK_RATE_UHBR20: 308 break; 309 default: 310 valid_input = false; 311 break; 312 } 313 314 if (!valid_input) { 315 kfree(wr_buf); 316 DRM_DEBUG_DRIVER("Invalid Input value No HW will be programmed\n"); 317 mutex_lock(&adev->dm.dc_lock); 318 dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false); 319 mutex_unlock(&adev->dm.dc_lock); 320 return size; 321 } 322 323 /* save user force lane_count, link_rate to preferred settings 324 * spread spectrum will not be changed 325 */ 326 prefer_link_settings.link_spread = link->cur_link_settings.link_spread; 327 prefer_link_settings.use_link_rate_set = false; 328 prefer_link_settings.lane_count = param[0]; 329 prefer_link_settings.link_rate = param[1]; 330 331 mutex_lock(&adev->dm.dc_lock); 332 dc_link_set_preferred_training_settings(dc, &prefer_link_settings, NULL, link, false); 333 mutex_unlock(&adev->dm.dc_lock); 334 335 kfree(wr_buf); 336 return size; 337} 338 339static bool dp_mst_is_end_device(struct amdgpu_dm_connector *aconnector) 340{ 341 bool is_end_device = false; 342 struct drm_dp_mst_topology_mgr *mgr = NULL; 343 struct drm_dp_mst_port *port = NULL; 344 345 if (aconnector->mst_root && aconnector->mst_root->mst_mgr.mst_state) { 346 mgr = &aconnector->mst_root->mst_mgr; 347 port = aconnector->mst_output_port; 348 349 drm_modeset_lock(&mgr->base.lock, NULL); 350 if (port->pdt == DP_PEER_DEVICE_SST_SINK || 351 port->pdt == DP_PEER_DEVICE_DP_LEGACY_CONV) 352 is_end_device = true; 353 drm_modeset_unlock(&mgr->base.lock); 354 } 355 356 return is_end_device; 357} 358 359/* Change MST link setting 360 * 361 * valid lane count value: 1, 2, 4 362 * valid link rate value: 363 * 06h = 1.62Gbps per lane 364 * 0Ah = 2.7Gbps per lane 365 * 0Ch = 3.24Gbps per lane 366 * 14h = 5.4Gbps per lane 367 * 1Eh = 8.1Gbps per lane 368 * 3E8h = 10.0Gbps per lane 369 * 546h = 13.5Gbps per lane 370 * 7D0h = 20.0Gbps per lane 371 * 372 * debugfs is located at /sys/kernel/debug/dri/0/DP-x/mst_link_settings 373 * 374 * for example, to force to 2 lane, 10.0GHz, 375 * echo 2 0x3e8 > /sys/kernel/debug/dri/0/DP-x/mst_link_settings 376 * 377 * Valid input will trigger hotplug event to get new link setting applied 378 * Invalid input will trigger training setting reset 379 * 380 * The usage can be referred to link_settings entry 381 * 382 */ 383static ssize_t dp_mst_link_setting(struct file *f, const char __user *buf, 384 size_t size, loff_t *pos) 385{ 386 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 387 struct dc_link *link = aconnector->dc_link; 388 struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev); 389 struct dc *dc = (struct dc *)link->dc; 390 struct dc_link_settings prefer_link_settings; 391 char *wr_buf = NULL; 392 const uint32_t wr_buf_size = 40; 393 /* 0: lane_count; 1: link_rate */ 394 int max_param_num = 2; 395 uint8_t param_nums = 0; 396 long param[2]; 397 bool valid_input = true; 398 399 if (!dp_mst_is_end_device(aconnector)) 400 return -EINVAL; 401 402 if (size == 0) 403 return -EINVAL; 404 405 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 406 if (!wr_buf) 407 return -ENOSPC; 408 409 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 410 (long *)param, buf, 411 max_param_num, 412 ¶m_nums)) { 413 kfree(wr_buf); 414 return -EINVAL; 415 } 416 417 if (param_nums <= 0) { 418 kfree(wr_buf); 419 DRM_DEBUG_DRIVER("user data not be read\n"); 420 return -EINVAL; 421 } 422 423 switch (param[0]) { 424 case LANE_COUNT_ONE: 425 case LANE_COUNT_TWO: 426 case LANE_COUNT_FOUR: 427 break; 428 default: 429 valid_input = false; 430 break; 431 } 432 433 switch (param[1]) { 434 case LINK_RATE_LOW: 435 case LINK_RATE_HIGH: 436 case LINK_RATE_RBR2: 437 case LINK_RATE_HIGH2: 438 case LINK_RATE_HIGH3: 439 case LINK_RATE_UHBR10: 440 case LINK_RATE_UHBR13_5: 441 case LINK_RATE_UHBR20: 442 break; 443 default: 444 valid_input = false; 445 break; 446 } 447 448 if (!valid_input) { 449 kfree(wr_buf); 450 DRM_DEBUG_DRIVER("Invalid Input value No HW will be programmed\n"); 451 mutex_lock(&adev->dm.dc_lock); 452 dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false); 453 mutex_unlock(&adev->dm.dc_lock); 454 return -EINVAL; 455 } 456 457 /* save user force lane_count, link_rate to preferred settings 458 * spread spectrum will not be changed 459 */ 460 prefer_link_settings.link_spread = link->cur_link_settings.link_spread; 461 prefer_link_settings.use_link_rate_set = false; 462 prefer_link_settings.lane_count = param[0]; 463 prefer_link_settings.link_rate = param[1]; 464 465 /* skip immediate retrain, and train to new link setting after hotplug event triggered */ 466 mutex_lock(&adev->dm.dc_lock); 467 dc_link_set_preferred_training_settings(dc, &prefer_link_settings, NULL, link, true); 468 mutex_unlock(&adev->dm.dc_lock); 469 470 mutex_lock(&aconnector->base.dev->mode_config.mutex); 471 aconnector->base.force = DRM_FORCE_OFF; 472 mutex_unlock(&aconnector->base.dev->mode_config.mutex); 473 drm_kms_helper_hotplug_event(aconnector->base.dev); 474 475 drm_msleep(100); 476 477 mutex_lock(&aconnector->base.dev->mode_config.mutex); 478 aconnector->base.force = DRM_FORCE_UNSPECIFIED; 479 mutex_unlock(&aconnector->base.dev->mode_config.mutex); 480 drm_kms_helper_hotplug_event(aconnector->base.dev); 481 482 kfree(wr_buf); 483 return size; 484} 485 486/* function: get current DP PHY settings: voltage swing, pre-emphasis, 487 * post-cursor2 (defined by VESA DP specification) 488 * 489 * valid values 490 * voltage swing: 0,1,2,3 491 * pre-emphasis : 0,1,2,3 492 * post cursor2 : 0,1,2,3 493 * 494 * 495 * how to use this debugfs 496 * 497 * debugfs is located at /sys/kernel/debug/dri/0/DP-x 498 * 499 * there will be directories, like DP-1, DP-2,DP-3, etc. for DP display 500 * 501 * To figure out which DP-x is the display for DP to be check, 502 * cd DP-x 503 * ls -ll 504 * There should be debugfs file, like link_settings, phy_settings. 505 * cat link_settings 506 * from lane_count, link_rate to figure which DP-x is for display to be worked 507 * on 508 * 509 * To get current DP PHY settings, 510 * cat phy_settings 511 * 512 * To change DP PHY settings, 513 * echo <voltage_swing> <pre-emphasis> <post_cursor2> > phy_settings 514 * for examle, to change voltage swing to 2, pre-emphasis to 3, post_cursor2 to 515 * 0, 516 * echo 2 3 0 > phy_settings 517 * 518 * To check if change be applied, get current phy settings by 519 * cat phy_settings 520 * 521 * In case invalid values are set by user, like 522 * echo 1 4 0 > phy_settings 523 * 524 * HW will NOT be programmed by these settings. 525 * cat phy_settings will show the previous valid settings. 526 */ 527static ssize_t dp_phy_settings_read(struct file *f, char __user *buf, 528 size_t size, loff_t *pos) 529{ 530 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 531 struct dc_link *link = connector->dc_link; 532 char *rd_buf = NULL; 533 const uint32_t rd_buf_size = 20; 534 uint32_t result = 0; 535 int r; 536 537 if (*pos & 3 || size & 3) 538 return -EINVAL; 539 540 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 541 if (!rd_buf) 542 return -EINVAL; 543 544 snprintf(rd_buf, rd_buf_size, " %d %d %d\n", 545 link->cur_lane_setting[0].VOLTAGE_SWING, 546 link->cur_lane_setting[0].PRE_EMPHASIS, 547 link->cur_lane_setting[0].POST_CURSOR2); 548 549 while (size) { 550 if (*pos >= rd_buf_size) 551 break; 552 553 r = put_user((*(rd_buf + result)), buf); 554 if (r) { 555 kfree(rd_buf); 556 return r; /* r = -EFAULT */ 557 } 558 559 buf += 1; 560 size -= 1; 561 *pos += 1; 562 result += 1; 563 } 564 565 kfree(rd_buf); 566 return result; 567} 568 569static int dp_lttpr_status_show(struct seq_file *m, void *unused) 570{ 571 struct drm_connector *connector = m->private; 572 struct amdgpu_dm_connector *aconnector = 573 to_amdgpu_dm_connector(connector); 574 struct dc_lttpr_caps caps = aconnector->dc_link->dpcd_caps.lttpr_caps; 575 576 if (connector->status != connector_status_connected) 577 return -ENODEV; 578 579 seq_printf(m, "phy repeater count: %u (raw: 0x%x)\n", 580 dp_parse_lttpr_repeater_count(caps.phy_repeater_cnt), 581 caps.phy_repeater_cnt); 582 583 seq_puts(m, "phy repeater mode: "); 584 585 switch (caps.mode) { 586 case DP_PHY_REPEATER_MODE_TRANSPARENT: 587 seq_puts(m, "transparent"); 588 break; 589 case DP_PHY_REPEATER_MODE_NON_TRANSPARENT: 590 seq_puts(m, "non-transparent"); 591 break; 592 case 0x00: 593 seq_puts(m, "non lttpr"); 594 break; 595 default: 596 seq_printf(m, "read error (raw: 0x%x)", caps.mode); 597 break; 598 } 599 600 seq_puts(m, "\n"); 601 return 0; 602} 603 604static ssize_t dp_phy_settings_write(struct file *f, const char __user *buf, 605 size_t size, loff_t *pos) 606{ 607 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 608 struct dc_link *link = connector->dc_link; 609 struct dc *dc = (struct dc *)link->dc; 610 char *wr_buf = NULL; 611 uint32_t wr_buf_size = 40; 612 long param[3]; 613 bool use_prefer_link_setting; 614 struct link_training_settings link_lane_settings; 615 int max_param_num = 3; 616 uint8_t param_nums = 0; 617 int r = 0; 618 619 620 if (size == 0) 621 return -EINVAL; 622 623 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 624 if (!wr_buf) 625 return -ENOSPC; 626 627 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 628 (long *)param, buf, 629 max_param_num, 630 ¶m_nums)) { 631 kfree(wr_buf); 632 return -EINVAL; 633 } 634 635 if (param_nums <= 0) { 636 kfree(wr_buf); 637 DRM_DEBUG_DRIVER("user data not be read\n"); 638 return -EINVAL; 639 } 640 641 if ((param[0] > VOLTAGE_SWING_MAX_LEVEL) || 642 (param[1] > PRE_EMPHASIS_MAX_LEVEL) || 643 (param[2] > POST_CURSOR2_MAX_LEVEL)) { 644 kfree(wr_buf); 645 DRM_DEBUG_DRIVER("Invalid Input No HW will be programmed\n"); 646 return size; 647 } 648 649 /* get link settings: lane count, link rate */ 650 use_prefer_link_setting = 651 ((link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN) && 652 (link->test_pattern_enabled)); 653 654 memset(&link_lane_settings, 0, sizeof(link_lane_settings)); 655 656 if (use_prefer_link_setting) { 657 link_lane_settings.link_settings.lane_count = 658 link->preferred_link_setting.lane_count; 659 link_lane_settings.link_settings.link_rate = 660 link->preferred_link_setting.link_rate; 661 link_lane_settings.link_settings.link_spread = 662 link->preferred_link_setting.link_spread; 663 } else { 664 link_lane_settings.link_settings.lane_count = 665 link->cur_link_settings.lane_count; 666 link_lane_settings.link_settings.link_rate = 667 link->cur_link_settings.link_rate; 668 link_lane_settings.link_settings.link_spread = 669 link->cur_link_settings.link_spread; 670 } 671 672 /* apply phy settings from user */ 673 for (r = 0; r < link_lane_settings.link_settings.lane_count; r++) { 674 link_lane_settings.hw_lane_settings[r].VOLTAGE_SWING = 675 (enum dc_voltage_swing) (param[0]); 676 link_lane_settings.hw_lane_settings[r].PRE_EMPHASIS = 677 (enum dc_pre_emphasis) (param[1]); 678 link_lane_settings.hw_lane_settings[r].POST_CURSOR2 = 679 (enum dc_post_cursor2) (param[2]); 680 } 681 682 /* program ASIC registers and DPCD registers */ 683 dc_link_set_drive_settings(dc, &link_lane_settings, link); 684 685 kfree(wr_buf); 686 return size; 687} 688 689/* function description 690 * 691 * set PHY layer or Link layer test pattern 692 * PHY test pattern is used for PHY SI check. 693 * Link layer test will not affect PHY SI. 694 * 695 * Reset Test Pattern: 696 * 0 = DP_TEST_PATTERN_VIDEO_MODE 697 * 698 * PHY test pattern supported: 699 * 1 = DP_TEST_PATTERN_D102 700 * 2 = DP_TEST_PATTERN_SYMBOL_ERROR 701 * 3 = DP_TEST_PATTERN_PRBS7 702 * 4 = DP_TEST_PATTERN_80BIT_CUSTOM 703 * 5 = DP_TEST_PATTERN_CP2520_1 704 * 6 = DP_TEST_PATTERN_CP2520_2 = DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE 705 * 7 = DP_TEST_PATTERN_CP2520_3 706 * 707 * DP PHY Link Training Patterns 708 * 8 = DP_TEST_PATTERN_TRAINING_PATTERN1 709 * 9 = DP_TEST_PATTERN_TRAINING_PATTERN2 710 * a = DP_TEST_PATTERN_TRAINING_PATTERN3 711 * b = DP_TEST_PATTERN_TRAINING_PATTERN4 712 * 713 * DP Link Layer Test pattern 714 * c = DP_TEST_PATTERN_COLOR_SQUARES 715 * d = DP_TEST_PATTERN_COLOR_SQUARES_CEA 716 * e = DP_TEST_PATTERN_VERTICAL_BARS 717 * f = DP_TEST_PATTERN_HORIZONTAL_BARS 718 * 10= DP_TEST_PATTERN_COLOR_RAMP 719 * 720 * debugfs phy_test_pattern is located at /syskernel/debug/dri/0/DP-x 721 * 722 * --- set test pattern 723 * echo <test pattern #> > test_pattern 724 * 725 * If test pattern # is not supported, NO HW programming will be done. 726 * for DP_TEST_PATTERN_80BIT_CUSTOM, it needs extra 10 bytes of data 727 * for the user pattern. input 10 bytes data are separated by space 728 * 729 * echo 0x4 0x11 0x22 0x33 0x44 0x55 0x66 0x77 0x88 0x99 0xaa > test_pattern 730 * 731 * --- reset test pattern 732 * echo 0 > test_pattern 733 * 734 * --- HPD detection is disabled when set PHY test pattern 735 * 736 * when PHY test pattern (pattern # within [1,7]) is set, HPD pin of HW ASIC 737 * is disable. User could unplug DP display from DP connected and plug scope to 738 * check test pattern PHY SI. 739 * If there is need unplug scope and plug DP display back, do steps below: 740 * echo 0 > phy_test_pattern 741 * unplug scope 742 * plug DP display. 743 * 744 * "echo 0 > phy_test_pattern" will re-enable HPD pin again so that video sw 745 * driver could detect "unplug scope" and "plug DP display" 746 */ 747static ssize_t dp_phy_test_pattern_debugfs_write(struct file *f, const char __user *buf, 748 size_t size, loff_t *pos) 749{ 750 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 751 struct dc_link *link = connector->dc_link; 752 char *wr_buf = NULL; 753 uint32_t wr_buf_size = 100; 754 long param[11] = {0x0}; 755 int max_param_num = 11; 756 enum dp_test_pattern test_pattern = DP_TEST_PATTERN_UNSUPPORTED; 757 bool disable_hpd = false; 758 bool valid_test_pattern = false; 759 uint8_t param_nums = 0; 760 /* init with default 80bit custom pattern */ 761 uint8_t custom_pattern[10] = { 762 0x1f, 0x7c, 0xf0, 0xc1, 0x07, 763 0x1f, 0x7c, 0xf0, 0xc1, 0x07 764 }; 765 struct dc_link_settings prefer_link_settings = {LANE_COUNT_UNKNOWN, 766 LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED}; 767 struct dc_link_settings cur_link_settings = {LANE_COUNT_UNKNOWN, 768 LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED}; 769 struct link_training_settings link_training_settings; 770 int i; 771 772 if (size == 0) 773 return -EINVAL; 774 775 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 776 if (!wr_buf) 777 return -ENOSPC; 778 779 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 780 (long *)param, buf, 781 max_param_num, 782 ¶m_nums)) { 783 kfree(wr_buf); 784 return -EINVAL; 785 } 786 787 if (param_nums <= 0) { 788 kfree(wr_buf); 789 DRM_DEBUG_DRIVER("user data not be read\n"); 790 return -EINVAL; 791 } 792 793 794 test_pattern = param[0]; 795 796 switch (test_pattern) { 797 case DP_TEST_PATTERN_VIDEO_MODE: 798 case DP_TEST_PATTERN_COLOR_SQUARES: 799 case DP_TEST_PATTERN_COLOR_SQUARES_CEA: 800 case DP_TEST_PATTERN_VERTICAL_BARS: 801 case DP_TEST_PATTERN_HORIZONTAL_BARS: 802 case DP_TEST_PATTERN_COLOR_RAMP: 803 valid_test_pattern = true; 804 break; 805 806 case DP_TEST_PATTERN_D102: 807 case DP_TEST_PATTERN_SYMBOL_ERROR: 808 case DP_TEST_PATTERN_PRBS7: 809 case DP_TEST_PATTERN_80BIT_CUSTOM: 810 case DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE: 811 case DP_TEST_PATTERN_TRAINING_PATTERN4: 812 disable_hpd = true; 813 valid_test_pattern = true; 814 break; 815 816 default: 817 valid_test_pattern = false; 818 test_pattern = DP_TEST_PATTERN_UNSUPPORTED; 819 break; 820 } 821 822 if (!valid_test_pattern) { 823 kfree(wr_buf); 824 DRM_DEBUG_DRIVER("Invalid Test Pattern Parameters\n"); 825 return size; 826 } 827 828 if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM) { 829 for (i = 0; i < 10; i++) { 830 if ((uint8_t) param[i + 1] != 0x0) 831 break; 832 } 833 834 if (i < 10) { 835 /* not use default value */ 836 for (i = 0; i < 10; i++) 837 custom_pattern[i] = (uint8_t) param[i + 1]; 838 } 839 } 840 841 /* Usage: set DP physical test pattern using debugfs with normal DP 842 * panel. Then plug out DP panel and connect a scope to measure 843 * For normal video mode and test pattern generated from CRCT, 844 * they are visibile to user. So do not disable HPD. 845 * Video Mode is also set to clear the test pattern, so enable HPD 846 * because it might have been disabled after a test pattern was set. 847 * AUX depends on HPD * sequence dependent, do not move! 848 */ 849 if (!disable_hpd) 850 dc_link_enable_hpd(link); 851 852 prefer_link_settings.lane_count = link->verified_link_cap.lane_count; 853 prefer_link_settings.link_rate = link->verified_link_cap.link_rate; 854 prefer_link_settings.link_spread = link->verified_link_cap.link_spread; 855 856 cur_link_settings.lane_count = link->cur_link_settings.lane_count; 857 cur_link_settings.link_rate = link->cur_link_settings.link_rate; 858 cur_link_settings.link_spread = link->cur_link_settings.link_spread; 859 860 link_training_settings.link_settings = cur_link_settings; 861 862 863 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) { 864 if (prefer_link_settings.lane_count != LANE_COUNT_UNKNOWN && 865 prefer_link_settings.link_rate != LINK_RATE_UNKNOWN && 866 (prefer_link_settings.lane_count != cur_link_settings.lane_count || 867 prefer_link_settings.link_rate != cur_link_settings.link_rate)) 868 link_training_settings.link_settings = prefer_link_settings; 869 } 870 871 for (i = 0; i < (unsigned int)(link_training_settings.link_settings.lane_count); i++) 872 link_training_settings.hw_lane_settings[i] = link->cur_lane_setting[i]; 873 874 dc_link_dp_set_test_pattern( 875 link, 876 test_pattern, 877 DP_TEST_PATTERN_COLOR_SPACE_RGB, 878 &link_training_settings, 879 custom_pattern, 880 10); 881 882 /* Usage: Set DP physical test pattern using AMDDP with normal DP panel 883 * Then plug out DP panel and connect a scope to measure DP PHY signal. 884 * Need disable interrupt to avoid SW driver disable DP output. This is 885 * done after the test pattern is set. 886 */ 887 if (valid_test_pattern && disable_hpd) 888 dc_link_disable_hpd(link); 889 890 kfree(wr_buf); 891 892 return size; 893} 894 895/* 896 * Returns the DMCUB tracebuffer contents. 897 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_tracebuffer 898 */ 899static int dmub_tracebuffer_show(struct seq_file *m, void *data) 900{ 901 struct amdgpu_device *adev = m->private; 902 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info; 903 struct dmub_debugfs_trace_entry *entries; 904 uint8_t *tbuf_base; 905 uint32_t tbuf_size, max_entries, num_entries, i; 906 907 if (!fb_info) 908 return 0; 909 910 tbuf_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr; 911 if (!tbuf_base) 912 return 0; 913 914 tbuf_size = fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size; 915 max_entries = (tbuf_size - sizeof(struct dmub_debugfs_trace_header)) / 916 sizeof(struct dmub_debugfs_trace_entry); 917 918 num_entries = 919 ((struct dmub_debugfs_trace_header *)tbuf_base)->entry_count; 920 921 num_entries = min(num_entries, max_entries); 922 923 entries = (struct dmub_debugfs_trace_entry 924 *)(tbuf_base + 925 sizeof(struct dmub_debugfs_trace_header)); 926 927 for (i = 0; i < num_entries; ++i) { 928 struct dmub_debugfs_trace_entry *entry = &entries[i]; 929 930 seq_printf(m, 931 "trace_code=%u tick_count=%u param0=%u param1=%u\n", 932 entry->trace_code, entry->tick_count, entry->param0, 933 entry->param1); 934 } 935 936 return 0; 937} 938 939/* 940 * Returns the DMCUB firmware state contents. 941 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_fw_state 942 */ 943static int dmub_fw_state_show(struct seq_file *m, void *data) 944{ 945 struct amdgpu_device *adev = m->private; 946 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info; 947 uint8_t *state_base; 948 uint32_t state_size; 949 950 if (!fb_info) 951 return 0; 952 953 state_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr; 954 if (!state_base) 955 return 0; 956 957 state_size = fb_info->fb[DMUB_WINDOW_6_FW_STATE].size; 958 959 return seq_write(m, state_base, state_size); 960} 961 962/* psr_capability_show() - show eDP panel PSR capability 963 * 964 * The read function: sink_psr_capability_show 965 * Shows if sink has PSR capability or not. 966 * If yes - the PSR version is appended 967 * 968 * cat /sys/kernel/debug/dri/0/eDP-X/psr_capability 969 * 970 * Expected output: 971 * "Sink support: no\n" - if panel doesn't support PSR 972 * "Sink support: yes [0x01]\n" - if panel supports PSR1 973 * "Driver support: no\n" - if driver doesn't support PSR 974 * "Driver support: yes [0x01]\n" - if driver supports PSR1 975 */ 976static int psr_capability_show(struct seq_file *m, void *data) 977{ 978 struct drm_connector *connector = m->private; 979 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 980 struct dc_link *link = aconnector->dc_link; 981 982 if (!link) 983 return -ENODEV; 984 985 if (link->type == dc_connection_none) 986 return -ENODEV; 987 988 if (!(link->connector_signal & SIGNAL_TYPE_EDP)) 989 return -ENODEV; 990 991 seq_printf(m, "Sink support: %s", str_yes_no(link->dpcd_caps.psr_info.psr_version != 0)); 992 if (link->dpcd_caps.psr_info.psr_version) 993 seq_printf(m, " [0x%02x]", link->dpcd_caps.psr_info.psr_version); 994 seq_puts(m, "\n"); 995 996 seq_printf(m, "Driver support: %s", str_yes_no(link->psr_settings.psr_feature_enabled)); 997 if (link->psr_settings.psr_version) 998 seq_printf(m, " [0x%02x]", link->psr_settings.psr_version); 999 seq_puts(m, "\n"); 1000 1001 return 0; 1002} 1003 1004/* 1005 * Returns the current bpc for the crtc. 1006 * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/amdgpu_current_bpc 1007 */ 1008static int amdgpu_current_bpc_show(struct seq_file *m, void *data) 1009{ 1010 struct drm_crtc *crtc = m->private; 1011 struct drm_device *dev = crtc->dev; 1012 struct dm_crtc_state *dm_crtc_state = NULL; 1013 int res = -ENODEV; 1014 unsigned int bpc; 1015 1016 mutex_lock(&dev->mode_config.mutex); 1017 drm_modeset_lock(&crtc->mutex, NULL); 1018 if (crtc->state == NULL) 1019 goto unlock; 1020 1021 dm_crtc_state = to_dm_crtc_state(crtc->state); 1022 if (dm_crtc_state->stream == NULL) 1023 goto unlock; 1024 1025 switch (dm_crtc_state->stream->timing.display_color_depth) { 1026 case COLOR_DEPTH_666: 1027 bpc = 6; 1028 break; 1029 case COLOR_DEPTH_888: 1030 bpc = 8; 1031 break; 1032 case COLOR_DEPTH_101010: 1033 bpc = 10; 1034 break; 1035 case COLOR_DEPTH_121212: 1036 bpc = 12; 1037 break; 1038 case COLOR_DEPTH_161616: 1039 bpc = 16; 1040 break; 1041 default: 1042 goto unlock; 1043 } 1044 1045 seq_printf(m, "Current: %u\n", bpc); 1046 res = 0; 1047 1048unlock: 1049 drm_modeset_unlock(&crtc->mutex); 1050 mutex_unlock(&dev->mode_config.mutex); 1051 1052 return res; 1053} 1054DEFINE_SHOW_ATTRIBUTE(amdgpu_current_bpc); 1055 1056/* 1057 * Returns the current colorspace for the crtc. 1058 * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/amdgpu_current_colorspace 1059 */ 1060static int amdgpu_current_colorspace_show(struct seq_file *m, void *data) 1061{ 1062 struct drm_crtc *crtc = m->private; 1063 struct drm_device *dev = crtc->dev; 1064 struct dm_crtc_state *dm_crtc_state = NULL; 1065 int res = -ENODEV; 1066 1067 mutex_lock(&dev->mode_config.mutex); 1068 drm_modeset_lock(&crtc->mutex, NULL); 1069 if (crtc->state == NULL) 1070 goto unlock; 1071 1072 dm_crtc_state = to_dm_crtc_state(crtc->state); 1073 if (dm_crtc_state->stream == NULL) 1074 goto unlock; 1075 1076 switch (dm_crtc_state->stream->output_color_space) { 1077 case COLOR_SPACE_SRGB: 1078 seq_puts(m, "sRGB"); 1079 break; 1080 case COLOR_SPACE_YCBCR601: 1081 case COLOR_SPACE_YCBCR601_LIMITED: 1082 seq_puts(m, "BT601_YCC"); 1083 break; 1084 case COLOR_SPACE_YCBCR709: 1085 case COLOR_SPACE_YCBCR709_LIMITED: 1086 seq_puts(m, "BT709_YCC"); 1087 break; 1088 case COLOR_SPACE_ADOBERGB: 1089 seq_puts(m, "opRGB"); 1090 break; 1091 case COLOR_SPACE_2020_RGB_FULLRANGE: 1092 seq_puts(m, "BT2020_RGB"); 1093 break; 1094 case COLOR_SPACE_2020_YCBCR: 1095 seq_puts(m, "BT2020_YCC"); 1096 break; 1097 default: 1098 goto unlock; 1099 } 1100 res = 0; 1101 1102unlock: 1103 drm_modeset_unlock(&crtc->mutex); 1104 mutex_unlock(&dev->mode_config.mutex); 1105 1106 return res; 1107} 1108DEFINE_SHOW_ATTRIBUTE(amdgpu_current_colorspace); 1109 1110 1111/* 1112 * Example usage: 1113 * Disable dsc passthrough, i.e.,: have dsc decoding at converver, not external RX 1114 * echo 1 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough 1115 * Enable dsc passthrough, i.e.,: have dsc passthrough to external RX 1116 * echo 0 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough 1117 */ 1118static ssize_t dp_dsc_passthrough_set(struct file *f, const char __user *buf, 1119 size_t size, loff_t *pos) 1120{ 1121 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1122 char *wr_buf = NULL; 1123 uint32_t wr_buf_size = 42; 1124 int max_param_num = 1; 1125 long param; 1126 uint8_t param_nums = 0; 1127 1128 if (size == 0) 1129 return -EINVAL; 1130 1131 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1132 1133 if (!wr_buf) { 1134 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1135 return -ENOSPC; 1136 } 1137 1138 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 1139 ¶m, buf, 1140 max_param_num, 1141 ¶m_nums)) { 1142 kfree(wr_buf); 1143 return -EINVAL; 1144 } 1145 1146 aconnector->dsc_settings.dsc_force_disable_passthrough = param; 1147 1148 kfree(wr_buf); 1149 return 0; 1150} 1151 1152/* 1153 * Returns the HDCP capability of the Display (1.4 for now). 1154 * 1155 * NOTE* Not all HDMI displays report their HDCP caps even when they are capable. 1156 * Since its rare for a display to not be HDCP 1.4 capable, we set HDMI as always capable. 1157 * 1158 * Example usage: cat /sys/kernel/debug/dri/0/DP-1/hdcp_sink_capability 1159 * or cat /sys/kernel/debug/dri/0/HDMI-A-1/hdcp_sink_capability 1160 */ 1161static int hdcp_sink_capability_show(struct seq_file *m, void *data) 1162{ 1163 struct drm_connector *connector = m->private; 1164 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 1165 bool hdcp_cap, hdcp2_cap; 1166 1167 if (connector->status != connector_status_connected) 1168 return -ENODEV; 1169 1170 seq_printf(m, "%s:%d HDCP version: ", connector->name, connector->base.id); 1171 1172 hdcp_cap = dc_link_is_hdcp14(aconnector->dc_link, aconnector->dc_sink->sink_signal); 1173 hdcp2_cap = dc_link_is_hdcp22(aconnector->dc_link, aconnector->dc_sink->sink_signal); 1174 1175 1176 if (hdcp_cap) 1177 seq_printf(m, "%s ", "HDCP1.4"); 1178 if (hdcp2_cap) 1179 seq_printf(m, "%s ", "HDCP2.2"); 1180 1181 if (!hdcp_cap && !hdcp2_cap) 1182 seq_printf(m, "%s ", "None"); 1183 1184 seq_puts(m, "\n"); 1185 1186 return 0; 1187} 1188 1189/* 1190 * Returns whether the connected display is internal and not hotpluggable. 1191 * Example usage: cat /sys/kernel/debug/dri/0/DP-1/internal_display 1192 */ 1193static int internal_display_show(struct seq_file *m, void *data) 1194{ 1195 struct drm_connector *connector = m->private; 1196 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 1197 struct dc_link *link = aconnector->dc_link; 1198 1199 seq_printf(m, "Internal: %u\n", link->is_internal_display); 1200 1201 return 0; 1202} 1203 1204/* function description 1205 * 1206 * generic SDP message access for testing 1207 * 1208 * debugfs sdp_message is located at /syskernel/debug/dri/0/DP-x 1209 * 1210 * SDP header 1211 * Hb0 : Secondary-Data Packet ID 1212 * Hb1 : Secondary-Data Packet type 1213 * Hb2 : Secondary-Data-packet-specific header, Byte 0 1214 * Hb3 : Secondary-Data-packet-specific header, Byte 1 1215 * 1216 * for using custom sdp message: input 4 bytes SDP header and 32 bytes raw data 1217 */ 1218static ssize_t dp_sdp_message_debugfs_write(struct file *f, const char __user *buf, 1219 size_t size, loff_t *pos) 1220{ 1221 int r; 1222 uint8_t data[36]; 1223 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 1224 struct dm_crtc_state *acrtc_state; 1225 uint32_t write_size = 36; 1226 1227 if (connector->base.status != connector_status_connected) 1228 return -ENODEV; 1229 1230 if (size == 0) 1231 return 0; 1232 1233 acrtc_state = to_dm_crtc_state(connector->base.state->crtc->state); 1234 1235 r = copy_from_user(data, buf, write_size); 1236 1237 write_size -= r; 1238 1239 dc_stream_send_dp_sdp(acrtc_state->stream, data, write_size); 1240 1241 return write_size; 1242} 1243 1244/* function: Read link's DSC & FEC capabilities 1245 * 1246 * 1247 * Access it with the following command (you need to specify 1248 * connector like DP-1): 1249 * 1250 * cat /sys/kernel/debug/dri/0/DP-X/dp_dsc_fec_support 1251 * 1252 */ 1253static int dp_dsc_fec_support_show(struct seq_file *m, void *data) 1254{ 1255 struct drm_connector *connector = m->private; 1256 struct drm_modeset_acquire_ctx ctx; 1257 struct drm_device *dev = connector->dev; 1258 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 1259 int ret = 0; 1260 bool try_again = false; 1261 bool is_fec_supported = false; 1262 bool is_dsc_supported = false; 1263 struct dpcd_caps dpcd_caps; 1264 1265 drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE); 1266 do { 1267 try_again = false; 1268 ret = drm_modeset_lock(&dev->mode_config.connection_mutex, &ctx); 1269 if (ret) { 1270 if (ret == -EDEADLK) { 1271 ret = drm_modeset_backoff(&ctx); 1272 if (!ret) { 1273 try_again = true; 1274 continue; 1275 } 1276 } 1277 break; 1278 } 1279 if (connector->status != connector_status_connected) { 1280 ret = -ENODEV; 1281 break; 1282 } 1283 dpcd_caps = aconnector->dc_link->dpcd_caps; 1284 if (aconnector->mst_output_port) { 1285 /* aconnector sets dsc_aux during get_modes call 1286 * if MST connector has it means it can either 1287 * enable DSC on the sink device or on MST branch 1288 * its connected to. 1289 */ 1290 if (aconnector->dsc_aux) { 1291 is_fec_supported = true; 1292 is_dsc_supported = true; 1293 } 1294 } else { 1295 is_fec_supported = dpcd_caps.fec_cap.raw & 0x1; 1296 is_dsc_supported = dpcd_caps.dsc_caps.dsc_basic_caps.raw[0] & 0x1; 1297 } 1298 } while (try_again); 1299 1300 drm_modeset_drop_locks(&ctx); 1301 drm_modeset_acquire_fini(&ctx); 1302 1303 seq_printf(m, "FEC_Sink_Support: %s\n", str_yes_no(is_fec_supported)); 1304 seq_printf(m, "DSC_Sink_Support: %s\n", str_yes_no(is_dsc_supported)); 1305 1306 return ret; 1307} 1308 1309/* function: Trigger virtual HPD redetection on connector 1310 * 1311 * This function will perform link rediscovery, link disable 1312 * and enable, and dm connector state update. 1313 * 1314 * Retrigger HPD on an existing connector by echoing 1 into 1315 * its respectful "trigger_hotplug" debugfs entry: 1316 * 1317 * echo 1 > /sys/kernel/debug/dri/0/DP-X/trigger_hotplug 1318 * 1319 * This function can perform HPD unplug: 1320 * 1321 * echo 0 > /sys/kernel/debug/dri/0/DP-X/trigger_hotplug 1322 * 1323 */ 1324static ssize_t trigger_hotplug(struct file *f, const char __user *buf, 1325 size_t size, loff_t *pos) 1326{ 1327 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1328 struct drm_connector *connector = &aconnector->base; 1329 struct dc_link *link = NULL; 1330 struct drm_device *dev = connector->dev; 1331 struct amdgpu_device *adev = drm_to_adev(dev); 1332 enum dc_connection_type new_connection_type = dc_connection_none; 1333 char *wr_buf = NULL; 1334 uint32_t wr_buf_size = 42; 1335 int max_param_num = 1; 1336 long param[1] = {0}; 1337 uint8_t param_nums = 0; 1338 bool ret = false; 1339 1340 if (!aconnector || !aconnector->dc_link) 1341 return -EINVAL; 1342 1343 if (size == 0) 1344 return -EINVAL; 1345 1346 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1347 1348 if (!wr_buf) { 1349 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1350 return -ENOSPC; 1351 } 1352 1353 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 1354 (long *)param, buf, 1355 max_param_num, 1356 ¶m_nums)) { 1357 kfree(wr_buf); 1358 return -EINVAL; 1359 } 1360 1361 kfree(wr_buf); 1362 1363 if (param_nums <= 0) { 1364 DRM_DEBUG_DRIVER("user data not be read\n"); 1365 return -EINVAL; 1366 } 1367 1368 mutex_lock(&aconnector->hpd_lock); 1369 1370 /* Don't support for mst end device*/ 1371 if (aconnector->mst_root) { 1372 mutex_unlock(&aconnector->hpd_lock); 1373 return -EINVAL; 1374 } 1375 1376 if (param[0] == 1) { 1377 1378 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type) && 1379 new_connection_type != dc_connection_none) 1380 goto unlock; 1381 1382 mutex_lock(&adev->dm.dc_lock); 1383 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); 1384 mutex_unlock(&adev->dm.dc_lock); 1385 1386 if (!ret) 1387 goto unlock; 1388 1389 amdgpu_dm_update_connector_after_detect(aconnector); 1390 1391 drm_modeset_lock_all(dev); 1392 dm_restore_drm_connector_state(dev, connector); 1393 drm_modeset_unlock_all(dev); 1394 1395 drm_kms_helper_connector_hotplug_event(connector); 1396 } else if (param[0] == 0) { 1397 if (!aconnector->dc_link) 1398 goto unlock; 1399 1400 link = aconnector->dc_link; 1401 1402 if (link->local_sink) { 1403 dc_sink_release(link->local_sink); 1404 link->local_sink = NULL; 1405 } 1406 1407 link->dpcd_sink_count = 0; 1408 link->type = dc_connection_none; 1409 link->dongle_max_pix_clk = 0; 1410 1411 amdgpu_dm_update_connector_after_detect(aconnector); 1412 1413 /* If the aconnector is the root node in mst topology */ 1414 if (aconnector->mst_mgr.mst_state == true) 1415 dc_link_reset_cur_dp_mst_topology(link); 1416 1417 drm_modeset_lock_all(dev); 1418 dm_restore_drm_connector_state(dev, connector); 1419 drm_modeset_unlock_all(dev); 1420 1421 drm_kms_helper_connector_hotplug_event(connector); 1422 } 1423 1424unlock: 1425 mutex_unlock(&aconnector->hpd_lock); 1426 1427 return size; 1428} 1429 1430/* function: read DSC status on the connector 1431 * 1432 * The read function: dp_dsc_clock_en_read 1433 * returns current status of DSC clock on the connector. 1434 * The return is a boolean flag: 1 or 0. 1435 * 1436 * Access it with the following command (you need to specify 1437 * connector like DP-1): 1438 * 1439 * cat /sys/kernel/debug/dri/0/DP-X/dsc_clock_en 1440 * 1441 * Expected output: 1442 * 1 - means that DSC is currently enabled 1443 * 0 - means that DSC is disabled 1444 */ 1445static ssize_t dp_dsc_clock_en_read(struct file *f, char __user *buf, 1446 size_t size, loff_t *pos) 1447{ 1448 char *rd_buf = NULL; 1449 char *rd_buf_ptr = NULL; 1450 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1451 struct display_stream_compressor *dsc; 1452 struct dcn_dsc_state dsc_state = {0}; 1453 const uint32_t rd_buf_size = 10; 1454 struct pipe_ctx *pipe_ctx; 1455 ssize_t result = 0; 1456 int i, r, str_len = 10; 1457 1458 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 1459 1460 if (!rd_buf) 1461 return -ENOMEM; 1462 1463 rd_buf_ptr = rd_buf; 1464 1465 for (i = 0; i < MAX_PIPES; i++) { 1466 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1467 if (pipe_ctx->stream && 1468 pipe_ctx->stream->link == aconnector->dc_link && 1469 pipe_ctx->stream->sink && 1470 pipe_ctx->stream->sink == aconnector->dc_sink) 1471 break; 1472 } 1473 1474 dsc = pipe_ctx->stream_res.dsc; 1475 if (dsc) 1476 dsc->funcs->dsc_read_state(dsc, &dsc_state); 1477 1478 snprintf(rd_buf_ptr, str_len, 1479 "%d\n", 1480 dsc_state.dsc_clock_en); 1481 rd_buf_ptr += str_len; 1482 1483 while (size) { 1484 if (*pos >= rd_buf_size) 1485 break; 1486 1487 r = put_user(*(rd_buf + result), buf); 1488 if (r) { 1489 kfree(rd_buf); 1490 return r; /* r = -EFAULT */ 1491 } 1492 1493 buf += 1; 1494 size -= 1; 1495 *pos += 1; 1496 result += 1; 1497 } 1498 1499 kfree(rd_buf); 1500 return result; 1501} 1502 1503/* function: write force DSC on the connector 1504 * 1505 * The write function: dp_dsc_clock_en_write 1506 * enables to force DSC on the connector. 1507 * User can write to either force enable or force disable DSC 1508 * on the next modeset or set it to driver default 1509 * 1510 * Accepted inputs: 1511 * 0 - default DSC enablement policy 1512 * 1 - force enable DSC on the connector 1513 * 2 - force disable DSC on the connector (might cause fail in atomic_check) 1514 * 1515 * Writing DSC settings is done with the following command: 1516 * - To force enable DSC (you need to specify 1517 * connector like DP-1): 1518 * 1519 * echo 0x1 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en 1520 * 1521 * - To return to default state set the flag to zero and 1522 * let driver deal with DSC automatically 1523 * (you need to specify connector like DP-1): 1524 * 1525 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en 1526 * 1527 */ 1528static ssize_t dp_dsc_clock_en_write(struct file *f, const char __user *buf, 1529 size_t size, loff_t *pos) 1530{ 1531 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1532 struct drm_connector *connector = &aconnector->base; 1533 struct drm_device *dev = connector->dev; 1534 struct drm_crtc *crtc = NULL; 1535 struct dm_crtc_state *dm_crtc_state = NULL; 1536 struct pipe_ctx *pipe_ctx; 1537 int i; 1538 char *wr_buf = NULL; 1539 uint32_t wr_buf_size = 42; 1540 int max_param_num = 1; 1541 long param[1] = {0}; 1542 uint8_t param_nums = 0; 1543 1544 if (size == 0) 1545 return -EINVAL; 1546 1547 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1548 1549 if (!wr_buf) { 1550 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1551 return -ENOSPC; 1552 } 1553 1554 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 1555 (long *)param, buf, 1556 max_param_num, 1557 ¶m_nums)) { 1558 kfree(wr_buf); 1559 return -EINVAL; 1560 } 1561 1562 if (param_nums <= 0) { 1563 DRM_DEBUG_DRIVER("user data not be read\n"); 1564 kfree(wr_buf); 1565 return -EINVAL; 1566 } 1567 1568 for (i = 0; i < MAX_PIPES; i++) { 1569 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1570 if (pipe_ctx->stream && 1571 pipe_ctx->stream->link == aconnector->dc_link && 1572 pipe_ctx->stream->sink && 1573 pipe_ctx->stream->sink == aconnector->dc_sink) 1574 break; 1575 } 1576 1577 if (!pipe_ctx->stream) 1578 goto done; 1579 1580 // Get CRTC state 1581 mutex_lock(&dev->mode_config.mutex); 1582 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 1583 1584 if (connector->state == NULL) 1585 goto unlock; 1586 1587 crtc = connector->state->crtc; 1588 if (crtc == NULL) 1589 goto unlock; 1590 1591 drm_modeset_lock(&crtc->mutex, NULL); 1592 if (crtc->state == NULL) 1593 goto unlock; 1594 1595 dm_crtc_state = to_dm_crtc_state(crtc->state); 1596 if (dm_crtc_state->stream == NULL) 1597 goto unlock; 1598 1599 if (param[0] == 1) 1600 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_ENABLE; 1601 else if (param[0] == 2) 1602 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_DISABLE; 1603 else 1604 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_DEFAULT; 1605 1606 dm_crtc_state->dsc_force_changed = true; 1607 1608unlock: 1609 if (crtc) 1610 drm_modeset_unlock(&crtc->mutex); 1611 drm_modeset_unlock(&dev->mode_config.connection_mutex); 1612 mutex_unlock(&dev->mode_config.mutex); 1613 1614done: 1615 kfree(wr_buf); 1616 return size; 1617} 1618 1619/* function: read DSC slice width parameter on the connector 1620 * 1621 * The read function: dp_dsc_slice_width_read 1622 * returns dsc slice width used in the current configuration 1623 * The return is an integer: 0 or other positive number 1624 * 1625 * Access the status with the following command: 1626 * 1627 * cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_width 1628 * 1629 * 0 - means that DSC is disabled 1630 * 1631 * Any other number more than zero represents the 1632 * slice width currently used by DSC in pixels 1633 * 1634 */ 1635static ssize_t dp_dsc_slice_width_read(struct file *f, char __user *buf, 1636 size_t size, loff_t *pos) 1637{ 1638 char *rd_buf = NULL; 1639 char *rd_buf_ptr = NULL; 1640 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1641 struct display_stream_compressor *dsc; 1642 struct dcn_dsc_state dsc_state = {0}; 1643 const uint32_t rd_buf_size = 100; 1644 struct pipe_ctx *pipe_ctx; 1645 ssize_t result = 0; 1646 int i, r, str_len = 30; 1647 1648 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 1649 1650 if (!rd_buf) 1651 return -ENOMEM; 1652 1653 rd_buf_ptr = rd_buf; 1654 1655 for (i = 0; i < MAX_PIPES; i++) { 1656 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1657 if (pipe_ctx->stream && 1658 pipe_ctx->stream->link == aconnector->dc_link && 1659 pipe_ctx->stream->sink && 1660 pipe_ctx->stream->sink == aconnector->dc_sink) 1661 break; 1662 } 1663 1664 dsc = pipe_ctx->stream_res.dsc; 1665 if (dsc) 1666 dsc->funcs->dsc_read_state(dsc, &dsc_state); 1667 1668 snprintf(rd_buf_ptr, str_len, 1669 "%d\n", 1670 dsc_state.dsc_slice_width); 1671 rd_buf_ptr += str_len; 1672 1673 while (size) { 1674 if (*pos >= rd_buf_size) 1675 break; 1676 1677 r = put_user(*(rd_buf + result), buf); 1678 if (r) { 1679 kfree(rd_buf); 1680 return r; /* r = -EFAULT */ 1681 } 1682 1683 buf += 1; 1684 size -= 1; 1685 *pos += 1; 1686 result += 1; 1687 } 1688 1689 kfree(rd_buf); 1690 return result; 1691} 1692 1693/* function: write DSC slice width parameter 1694 * 1695 * The write function: dp_dsc_slice_width_write 1696 * overwrites automatically generated DSC configuration 1697 * of slice width. 1698 * 1699 * The user has to write the slice width divisible by the 1700 * picture width. 1701 * 1702 * Also the user has to write width in hexidecimal 1703 * rather than in decimal. 1704 * 1705 * Writing DSC settings is done with the following command: 1706 * - To force overwrite slice width: (example sets to 1920 pixels) 1707 * 1708 * echo 0x780 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width 1709 * 1710 * - To stop overwriting and let driver find the optimal size, 1711 * set the width to zero: 1712 * 1713 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width 1714 * 1715 */ 1716static ssize_t dp_dsc_slice_width_write(struct file *f, const char __user *buf, 1717 size_t size, loff_t *pos) 1718{ 1719 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1720 struct pipe_ctx *pipe_ctx; 1721 struct drm_connector *connector = &aconnector->base; 1722 struct drm_device *dev = connector->dev; 1723 struct drm_crtc *crtc = NULL; 1724 struct dm_crtc_state *dm_crtc_state = NULL; 1725 int i; 1726 char *wr_buf = NULL; 1727 uint32_t wr_buf_size = 42; 1728 int max_param_num = 1; 1729 long param[1] = {0}; 1730 uint8_t param_nums = 0; 1731 1732 if (size == 0) 1733 return -EINVAL; 1734 1735 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1736 1737 if (!wr_buf) { 1738 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1739 return -ENOSPC; 1740 } 1741 1742 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 1743 (long *)param, buf, 1744 max_param_num, 1745 ¶m_nums)) { 1746 kfree(wr_buf); 1747 return -EINVAL; 1748 } 1749 1750 if (param_nums <= 0) { 1751 DRM_DEBUG_DRIVER("user data not be read\n"); 1752 kfree(wr_buf); 1753 return -EINVAL; 1754 } 1755 1756 for (i = 0; i < MAX_PIPES; i++) { 1757 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1758 if (pipe_ctx->stream && 1759 pipe_ctx->stream->link == aconnector->dc_link && 1760 pipe_ctx->stream->sink && 1761 pipe_ctx->stream->sink == aconnector->dc_sink) 1762 break; 1763 } 1764 1765 if (!pipe_ctx->stream) 1766 goto done; 1767 1768 // Safely get CRTC state 1769 mutex_lock(&dev->mode_config.mutex); 1770 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 1771 1772 if (connector->state == NULL) 1773 goto unlock; 1774 1775 crtc = connector->state->crtc; 1776 if (crtc == NULL) 1777 goto unlock; 1778 1779 drm_modeset_lock(&crtc->mutex, NULL); 1780 if (crtc->state == NULL) 1781 goto unlock; 1782 1783 dm_crtc_state = to_dm_crtc_state(crtc->state); 1784 if (dm_crtc_state->stream == NULL) 1785 goto unlock; 1786 1787 if (param[0] > 0) 1788 aconnector->dsc_settings.dsc_num_slices_h = DIV_ROUND_UP( 1789 pipe_ctx->stream->timing.h_addressable, 1790 param[0]); 1791 else 1792 aconnector->dsc_settings.dsc_num_slices_h = 0; 1793 1794 dm_crtc_state->dsc_force_changed = true; 1795 1796unlock: 1797 if (crtc) 1798 drm_modeset_unlock(&crtc->mutex); 1799 drm_modeset_unlock(&dev->mode_config.connection_mutex); 1800 mutex_unlock(&dev->mode_config.mutex); 1801 1802done: 1803 kfree(wr_buf); 1804 return size; 1805} 1806 1807/* function: read DSC slice height parameter on the connector 1808 * 1809 * The read function: dp_dsc_slice_height_read 1810 * returns dsc slice height used in the current configuration 1811 * The return is an integer: 0 or other positive number 1812 * 1813 * Access the status with the following command: 1814 * 1815 * cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_height 1816 * 1817 * 0 - means that DSC is disabled 1818 * 1819 * Any other number more than zero represents the 1820 * slice height currently used by DSC in pixels 1821 * 1822 */ 1823static ssize_t dp_dsc_slice_height_read(struct file *f, char __user *buf, 1824 size_t size, loff_t *pos) 1825{ 1826 char *rd_buf = NULL; 1827 char *rd_buf_ptr = NULL; 1828 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1829 struct display_stream_compressor *dsc; 1830 struct dcn_dsc_state dsc_state = {0}; 1831 const uint32_t rd_buf_size = 100; 1832 struct pipe_ctx *pipe_ctx; 1833 ssize_t result = 0; 1834 int i, r, str_len = 30; 1835 1836 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 1837 1838 if (!rd_buf) 1839 return -ENOMEM; 1840 1841 rd_buf_ptr = rd_buf; 1842 1843 for (i = 0; i < MAX_PIPES; i++) { 1844 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1845 if (pipe_ctx->stream && 1846 pipe_ctx->stream->link == aconnector->dc_link && 1847 pipe_ctx->stream->sink && 1848 pipe_ctx->stream->sink == aconnector->dc_sink) 1849 break; 1850 } 1851 1852 dsc = pipe_ctx->stream_res.dsc; 1853 if (dsc) 1854 dsc->funcs->dsc_read_state(dsc, &dsc_state); 1855 1856 snprintf(rd_buf_ptr, str_len, 1857 "%d\n", 1858 dsc_state.dsc_slice_height); 1859 rd_buf_ptr += str_len; 1860 1861 while (size) { 1862 if (*pos >= rd_buf_size) 1863 break; 1864 1865 r = put_user(*(rd_buf + result), buf); 1866 if (r) { 1867 kfree(rd_buf); 1868 return r; /* r = -EFAULT */ 1869 } 1870 1871 buf += 1; 1872 size -= 1; 1873 *pos += 1; 1874 result += 1; 1875 } 1876 1877 kfree(rd_buf); 1878 return result; 1879} 1880 1881/* function: write DSC slice height parameter 1882 * 1883 * The write function: dp_dsc_slice_height_write 1884 * overwrites automatically generated DSC configuration 1885 * of slice height. 1886 * 1887 * The user has to write the slice height divisible by the 1888 * picture height. 1889 * 1890 * Also the user has to write height in hexidecimal 1891 * rather than in decimal. 1892 * 1893 * Writing DSC settings is done with the following command: 1894 * - To force overwrite slice height (example sets to 128 pixels): 1895 * 1896 * echo 0x80 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height 1897 * 1898 * - To stop overwriting and let driver find the optimal size, 1899 * set the height to zero: 1900 * 1901 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height 1902 * 1903 */ 1904static ssize_t dp_dsc_slice_height_write(struct file *f, const char __user *buf, 1905 size_t size, loff_t *pos) 1906{ 1907 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1908 struct drm_connector *connector = &aconnector->base; 1909 struct drm_device *dev = connector->dev; 1910 struct drm_crtc *crtc = NULL; 1911 struct dm_crtc_state *dm_crtc_state = NULL; 1912 struct pipe_ctx *pipe_ctx; 1913 int i; 1914 char *wr_buf = NULL; 1915 uint32_t wr_buf_size = 42; 1916 int max_param_num = 1; 1917 uint8_t param_nums = 0; 1918 long param[1] = {0}; 1919 1920 if (size == 0) 1921 return -EINVAL; 1922 1923 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1924 1925 if (!wr_buf) { 1926 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1927 return -ENOSPC; 1928 } 1929 1930 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 1931 (long *)param, buf, 1932 max_param_num, 1933 ¶m_nums)) { 1934 kfree(wr_buf); 1935 return -EINVAL; 1936 } 1937 1938 if (param_nums <= 0) { 1939 DRM_DEBUG_DRIVER("user data not be read\n"); 1940 kfree(wr_buf); 1941 return -EINVAL; 1942 } 1943 1944 for (i = 0; i < MAX_PIPES; i++) { 1945 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1946 if (pipe_ctx->stream && 1947 pipe_ctx->stream->link == aconnector->dc_link && 1948 pipe_ctx->stream->sink && 1949 pipe_ctx->stream->sink == aconnector->dc_sink) 1950 break; 1951 } 1952 1953 if (!pipe_ctx->stream) 1954 goto done; 1955 1956 // Get CRTC state 1957 mutex_lock(&dev->mode_config.mutex); 1958 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 1959 1960 if (connector->state == NULL) 1961 goto unlock; 1962 1963 crtc = connector->state->crtc; 1964 if (crtc == NULL) 1965 goto unlock; 1966 1967 drm_modeset_lock(&crtc->mutex, NULL); 1968 if (crtc->state == NULL) 1969 goto unlock; 1970 1971 dm_crtc_state = to_dm_crtc_state(crtc->state); 1972 if (dm_crtc_state->stream == NULL) 1973 goto unlock; 1974 1975 if (param[0] > 0) 1976 aconnector->dsc_settings.dsc_num_slices_v = DIV_ROUND_UP( 1977 pipe_ctx->stream->timing.v_addressable, 1978 param[0]); 1979 else 1980 aconnector->dsc_settings.dsc_num_slices_v = 0; 1981 1982 dm_crtc_state->dsc_force_changed = true; 1983 1984unlock: 1985 if (crtc) 1986 drm_modeset_unlock(&crtc->mutex); 1987 drm_modeset_unlock(&dev->mode_config.connection_mutex); 1988 mutex_unlock(&dev->mode_config.mutex); 1989 1990done: 1991 kfree(wr_buf); 1992 return size; 1993} 1994 1995/* function: read DSC target rate on the connector in bits per pixel 1996 * 1997 * The read function: dp_dsc_bits_per_pixel_read 1998 * returns target rate of compression in bits per pixel 1999 * The return is an integer: 0 or other positive integer 2000 * 2001 * Access it with the following command: 2002 * 2003 * cat /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel 2004 * 2005 * 0 - means that DSC is disabled 2006 */ 2007static ssize_t dp_dsc_bits_per_pixel_read(struct file *f, char __user *buf, 2008 size_t size, loff_t *pos) 2009{ 2010 char *rd_buf = NULL; 2011 char *rd_buf_ptr = NULL; 2012 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2013 struct display_stream_compressor *dsc; 2014 struct dcn_dsc_state dsc_state = {0}; 2015 const uint32_t rd_buf_size = 100; 2016 struct pipe_ctx *pipe_ctx; 2017 ssize_t result = 0; 2018 int i, r, str_len = 30; 2019 2020 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2021 2022 if (!rd_buf) 2023 return -ENOMEM; 2024 2025 rd_buf_ptr = rd_buf; 2026 2027 for (i = 0; i < MAX_PIPES; i++) { 2028 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2029 if (pipe_ctx->stream && 2030 pipe_ctx->stream->link == aconnector->dc_link && 2031 pipe_ctx->stream->sink && 2032 pipe_ctx->stream->sink == aconnector->dc_sink) 2033 break; 2034 } 2035 2036 dsc = pipe_ctx->stream_res.dsc; 2037 if (dsc) 2038 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2039 2040 snprintf(rd_buf_ptr, str_len, 2041 "%d\n", 2042 dsc_state.dsc_bits_per_pixel); 2043 rd_buf_ptr += str_len; 2044 2045 while (size) { 2046 if (*pos >= rd_buf_size) 2047 break; 2048 2049 r = put_user(*(rd_buf + result), buf); 2050 if (r) { 2051 kfree(rd_buf); 2052 return r; /* r = -EFAULT */ 2053 } 2054 2055 buf += 1; 2056 size -= 1; 2057 *pos += 1; 2058 result += 1; 2059 } 2060 2061 kfree(rd_buf); 2062 return result; 2063} 2064 2065/* function: write DSC target rate in bits per pixel 2066 * 2067 * The write function: dp_dsc_bits_per_pixel_write 2068 * overwrites automatically generated DSC configuration 2069 * of DSC target bit rate. 2070 * 2071 * Also the user has to write bpp in hexidecimal 2072 * rather than in decimal. 2073 * 2074 * Writing DSC settings is done with the following command: 2075 * - To force overwrite rate (example sets to 256 bpp x 1/16): 2076 * 2077 * echo 0x100 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel 2078 * 2079 * - To stop overwriting and let driver find the optimal rate, 2080 * set the rate to zero: 2081 * 2082 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel 2083 * 2084 */ 2085static ssize_t dp_dsc_bits_per_pixel_write(struct file *f, const char __user *buf, 2086 size_t size, loff_t *pos) 2087{ 2088 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2089 struct drm_connector *connector = &aconnector->base; 2090 struct drm_device *dev = connector->dev; 2091 struct drm_crtc *crtc = NULL; 2092 struct dm_crtc_state *dm_crtc_state = NULL; 2093 struct pipe_ctx *pipe_ctx; 2094 int i; 2095 char *wr_buf = NULL; 2096 uint32_t wr_buf_size = 42; 2097 int max_param_num = 1; 2098 uint8_t param_nums = 0; 2099 long param[1] = {0}; 2100 2101 if (size == 0) 2102 return -EINVAL; 2103 2104 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 2105 2106 if (!wr_buf) { 2107 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 2108 return -ENOSPC; 2109 } 2110 2111 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 2112 (long *)param, buf, 2113 max_param_num, 2114 ¶m_nums)) { 2115 kfree(wr_buf); 2116 return -EINVAL; 2117 } 2118 2119 if (param_nums <= 0) { 2120 DRM_DEBUG_DRIVER("user data not be read\n"); 2121 kfree(wr_buf); 2122 return -EINVAL; 2123 } 2124 2125 for (i = 0; i < MAX_PIPES; i++) { 2126 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2127 if (pipe_ctx->stream && 2128 pipe_ctx->stream->link == aconnector->dc_link && 2129 pipe_ctx->stream->sink && 2130 pipe_ctx->stream->sink == aconnector->dc_sink) 2131 break; 2132 } 2133 2134 if (!pipe_ctx->stream) 2135 goto done; 2136 2137 // Get CRTC state 2138 mutex_lock(&dev->mode_config.mutex); 2139 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 2140 2141 if (connector->state == NULL) 2142 goto unlock; 2143 2144 crtc = connector->state->crtc; 2145 if (crtc == NULL) 2146 goto unlock; 2147 2148 drm_modeset_lock(&crtc->mutex, NULL); 2149 if (crtc->state == NULL) 2150 goto unlock; 2151 2152 dm_crtc_state = to_dm_crtc_state(crtc->state); 2153 if (dm_crtc_state->stream == NULL) 2154 goto unlock; 2155 2156 aconnector->dsc_settings.dsc_bits_per_pixel = param[0]; 2157 2158 dm_crtc_state->dsc_force_changed = true; 2159 2160unlock: 2161 if (crtc) 2162 drm_modeset_unlock(&crtc->mutex); 2163 drm_modeset_unlock(&dev->mode_config.connection_mutex); 2164 mutex_unlock(&dev->mode_config.mutex); 2165 2166done: 2167 kfree(wr_buf); 2168 return size; 2169} 2170 2171/* function: read DSC picture width parameter on the connector 2172 * 2173 * The read function: dp_dsc_pic_width_read 2174 * returns dsc picture width used in the current configuration 2175 * It is the same as h_addressable of the current 2176 * display's timing 2177 * The return is an integer: 0 or other positive integer 2178 * If 0 then DSC is disabled. 2179 * 2180 * Access it with the following command: 2181 * 2182 * cat /sys/kernel/debug/dri/0/DP-X/dsc_pic_width 2183 * 2184 * 0 - means that DSC is disabled 2185 */ 2186static ssize_t dp_dsc_pic_width_read(struct file *f, char __user *buf, 2187 size_t size, loff_t *pos) 2188{ 2189 char *rd_buf = NULL; 2190 char *rd_buf_ptr = NULL; 2191 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2192 struct display_stream_compressor *dsc; 2193 struct dcn_dsc_state dsc_state = {0}; 2194 const uint32_t rd_buf_size = 100; 2195 struct pipe_ctx *pipe_ctx; 2196 ssize_t result = 0; 2197 int i, r, str_len = 30; 2198 2199 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2200 2201 if (!rd_buf) 2202 return -ENOMEM; 2203 2204 rd_buf_ptr = rd_buf; 2205 2206 for (i = 0; i < MAX_PIPES; i++) { 2207 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2208 if (pipe_ctx->stream && 2209 pipe_ctx->stream->link == aconnector->dc_link && 2210 pipe_ctx->stream->sink && 2211 pipe_ctx->stream->sink == aconnector->dc_sink) 2212 break; 2213 } 2214 2215 dsc = pipe_ctx->stream_res.dsc; 2216 if (dsc) 2217 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2218 2219 snprintf(rd_buf_ptr, str_len, 2220 "%d\n", 2221 dsc_state.dsc_pic_width); 2222 rd_buf_ptr += str_len; 2223 2224 while (size) { 2225 if (*pos >= rd_buf_size) 2226 break; 2227 2228 r = put_user(*(rd_buf + result), buf); 2229 if (r) { 2230 kfree(rd_buf); 2231 return r; /* r = -EFAULT */ 2232 } 2233 2234 buf += 1; 2235 size -= 1; 2236 *pos += 1; 2237 result += 1; 2238 } 2239 2240 kfree(rd_buf); 2241 return result; 2242} 2243 2244static ssize_t dp_dsc_pic_height_read(struct file *f, char __user *buf, 2245 size_t size, loff_t *pos) 2246{ 2247 char *rd_buf = NULL; 2248 char *rd_buf_ptr = NULL; 2249 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2250 struct display_stream_compressor *dsc; 2251 struct dcn_dsc_state dsc_state = {0}; 2252 const uint32_t rd_buf_size = 100; 2253 struct pipe_ctx *pipe_ctx; 2254 ssize_t result = 0; 2255 int i, r, str_len = 30; 2256 2257 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2258 2259 if (!rd_buf) 2260 return -ENOMEM; 2261 2262 rd_buf_ptr = rd_buf; 2263 2264 for (i = 0; i < MAX_PIPES; i++) { 2265 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2266 if (pipe_ctx->stream && 2267 pipe_ctx->stream->link == aconnector->dc_link && 2268 pipe_ctx->stream->sink && 2269 pipe_ctx->stream->sink == aconnector->dc_sink) 2270 break; 2271 } 2272 2273 dsc = pipe_ctx->stream_res.dsc; 2274 if (dsc) 2275 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2276 2277 snprintf(rd_buf_ptr, str_len, 2278 "%d\n", 2279 dsc_state.dsc_pic_height); 2280 rd_buf_ptr += str_len; 2281 2282 while (size) { 2283 if (*pos >= rd_buf_size) 2284 break; 2285 2286 r = put_user(*(rd_buf + result), buf); 2287 if (r) { 2288 kfree(rd_buf); 2289 return r; /* r = -EFAULT */ 2290 } 2291 2292 buf += 1; 2293 size -= 1; 2294 *pos += 1; 2295 result += 1; 2296 } 2297 2298 kfree(rd_buf); 2299 return result; 2300} 2301 2302/* function: read DSC chunk size parameter on the connector 2303 * 2304 * The read function: dp_dsc_chunk_size_read 2305 * returns dsc chunk size set in the current configuration 2306 * The value is calculated automatically by DSC code 2307 * and depends on slice parameters and bpp target rate 2308 * The return is an integer: 0 or other positive integer 2309 * If 0 then DSC is disabled. 2310 * 2311 * Access it with the following command: 2312 * 2313 * cat /sys/kernel/debug/dri/0/DP-X/dsc_chunk_size 2314 * 2315 * 0 - means that DSC is disabled 2316 */ 2317static ssize_t dp_dsc_chunk_size_read(struct file *f, char __user *buf, 2318 size_t size, loff_t *pos) 2319{ 2320 char *rd_buf = NULL; 2321 char *rd_buf_ptr = NULL; 2322 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2323 struct display_stream_compressor *dsc; 2324 struct dcn_dsc_state dsc_state = {0}; 2325 const uint32_t rd_buf_size = 100; 2326 struct pipe_ctx *pipe_ctx; 2327 ssize_t result = 0; 2328 int i, r, str_len = 30; 2329 2330 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2331 2332 if (!rd_buf) 2333 return -ENOMEM; 2334 2335 rd_buf_ptr = rd_buf; 2336 2337 for (i = 0; i < MAX_PIPES; i++) { 2338 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2339 if (pipe_ctx->stream && 2340 pipe_ctx->stream->link == aconnector->dc_link && 2341 pipe_ctx->stream->sink && 2342 pipe_ctx->stream->sink == aconnector->dc_sink) 2343 break; 2344 } 2345 2346 dsc = pipe_ctx->stream_res.dsc; 2347 if (dsc) 2348 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2349 2350 snprintf(rd_buf_ptr, str_len, 2351 "%d\n", 2352 dsc_state.dsc_chunk_size); 2353 rd_buf_ptr += str_len; 2354 2355 while (size) { 2356 if (*pos >= rd_buf_size) 2357 break; 2358 2359 r = put_user(*(rd_buf + result), buf); 2360 if (r) { 2361 kfree(rd_buf); 2362 return r; /* r = -EFAULT */ 2363 } 2364 2365 buf += 1; 2366 size -= 1; 2367 *pos += 1; 2368 result += 1; 2369 } 2370 2371 kfree(rd_buf); 2372 return result; 2373} 2374 2375/* function: read DSC slice bpg offset on the connector 2376 * 2377 * The read function: dp_dsc_slice_bpg_offset_read 2378 * returns dsc bpg slice offset set in the current configuration 2379 * The value is calculated automatically by DSC code 2380 * and depends on slice parameters and bpp target rate 2381 * The return is an integer: 0 or other positive integer 2382 * If 0 then DSC is disabled. 2383 * 2384 * Access it with the following command: 2385 * 2386 * cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_bpg_offset 2387 * 2388 * 0 - means that DSC is disabled 2389 */ 2390static ssize_t dp_dsc_slice_bpg_offset_read(struct file *f, char __user *buf, 2391 size_t size, loff_t *pos) 2392{ 2393 char *rd_buf = NULL; 2394 char *rd_buf_ptr = NULL; 2395 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2396 struct display_stream_compressor *dsc; 2397 struct dcn_dsc_state dsc_state = {0}; 2398 const uint32_t rd_buf_size = 100; 2399 struct pipe_ctx *pipe_ctx; 2400 ssize_t result = 0; 2401 int i, r, str_len = 30; 2402 2403 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2404 2405 if (!rd_buf) 2406 return -ENOMEM; 2407 2408 rd_buf_ptr = rd_buf; 2409 2410 for (i = 0; i < MAX_PIPES; i++) { 2411 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2412 if (pipe_ctx->stream && 2413 pipe_ctx->stream->link == aconnector->dc_link && 2414 pipe_ctx->stream->sink && 2415 pipe_ctx->stream->sink == aconnector->dc_sink) 2416 break; 2417 } 2418 2419 dsc = pipe_ctx->stream_res.dsc; 2420 if (dsc) 2421 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2422 2423 snprintf(rd_buf_ptr, str_len, 2424 "%d\n", 2425 dsc_state.dsc_slice_bpg_offset); 2426 rd_buf_ptr += str_len; 2427 2428 while (size) { 2429 if (*pos >= rd_buf_size) 2430 break; 2431 2432 r = put_user(*(rd_buf + result), buf); 2433 if (r) { 2434 kfree(rd_buf); 2435 return r; /* r = -EFAULT */ 2436 } 2437 2438 buf += 1; 2439 size -= 1; 2440 *pos += 1; 2441 result += 1; 2442 } 2443 2444 kfree(rd_buf); 2445 return result; 2446} 2447 2448 2449/* 2450 * function description: Read max_requested_bpc property from the connector 2451 * 2452 * Access it with the following command: 2453 * 2454 * cat /sys/kernel/debug/dri/0/DP-X/max_bpc 2455 * 2456 */ 2457static ssize_t dp_max_bpc_read(struct file *f, char __user *buf, 2458 size_t size, loff_t *pos) 2459{ 2460 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2461 struct drm_connector *connector = &aconnector->base; 2462 struct drm_device *dev = connector->dev; 2463 struct dm_connector_state *state; 2464 ssize_t result = 0; 2465 char *rd_buf = NULL; 2466 char *rd_buf_ptr = NULL; 2467 const uint32_t rd_buf_size = 10; 2468 int r; 2469 2470 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2471 2472 if (!rd_buf) 2473 return -ENOMEM; 2474 2475 mutex_lock(&dev->mode_config.mutex); 2476 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 2477 2478 if (connector->state == NULL) 2479 goto unlock; 2480 2481 state = to_dm_connector_state(connector->state); 2482 2483 rd_buf_ptr = rd_buf; 2484 snprintf(rd_buf_ptr, rd_buf_size, 2485 "%u\n", 2486 state->base.max_requested_bpc); 2487 2488 while (size) { 2489 if (*pos >= rd_buf_size) 2490 break; 2491 2492 r = put_user(*(rd_buf + result), buf); 2493 if (r) { 2494 result = r; /* r = -EFAULT */ 2495 goto unlock; 2496 } 2497 buf += 1; 2498 size -= 1; 2499 *pos += 1; 2500 result += 1; 2501 } 2502unlock: 2503 drm_modeset_unlock(&dev->mode_config.connection_mutex); 2504 mutex_unlock(&dev->mode_config.mutex); 2505 kfree(rd_buf); 2506 return result; 2507} 2508 2509 2510/* 2511 * function description: Set max_requested_bpc property on the connector 2512 * 2513 * This function will not force the input BPC on connector, it will only 2514 * change the max value. This is equivalent to setting max_bpc through 2515 * xrandr. 2516 * 2517 * The BPC value written must be >= 6 and <= 16. Values outside of this 2518 * range will result in errors. 2519 * 2520 * BPC values: 2521 * 0x6 - 6 BPC 2522 * 0x8 - 8 BPC 2523 * 0xa - 10 BPC 2524 * 0xc - 12 BPC 2525 * 0x10 - 16 BPC 2526 * 2527 * Write the max_bpc in the following way: 2528 * 2529 * echo 0x6 > /sys/kernel/debug/dri/0/DP-X/max_bpc 2530 * 2531 */ 2532static ssize_t dp_max_bpc_write(struct file *f, const char __user *buf, 2533 size_t size, loff_t *pos) 2534{ 2535 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2536 struct drm_connector *connector = &aconnector->base; 2537 struct dm_connector_state *state; 2538 struct drm_device *dev = connector->dev; 2539 char *wr_buf = NULL; 2540 uint32_t wr_buf_size = 42; 2541 int max_param_num = 1; 2542 long param[1] = {0}; 2543 uint8_t param_nums = 0; 2544 2545 if (size == 0) 2546 return -EINVAL; 2547 2548 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 2549 2550 if (!wr_buf) { 2551 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 2552 return -ENOSPC; 2553 } 2554 2555 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 2556 (long *)param, buf, 2557 max_param_num, 2558 ¶m_nums)) { 2559 kfree(wr_buf); 2560 return -EINVAL; 2561 } 2562 2563 if (param_nums <= 0) { 2564 DRM_DEBUG_DRIVER("user data not be read\n"); 2565 kfree(wr_buf); 2566 return -EINVAL; 2567 } 2568 2569 if (param[0] < 6 || param[0] > 16) { 2570 DRM_DEBUG_DRIVER("bad max_bpc value\n"); 2571 kfree(wr_buf); 2572 return -EINVAL; 2573 } 2574 2575 mutex_lock(&dev->mode_config.mutex); 2576 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 2577 2578 if (connector->state == NULL) 2579 goto unlock; 2580 2581 state = to_dm_connector_state(connector->state); 2582 state->base.max_requested_bpc = param[0]; 2583unlock: 2584 drm_modeset_unlock(&dev->mode_config.connection_mutex); 2585 mutex_unlock(&dev->mode_config.mutex); 2586 2587 kfree(wr_buf); 2588 return size; 2589} 2590 2591/* 2592 * Backlight at this moment. Read only. 2593 * As written to display, taking ABM and backlight lut into account. 2594 * Ranges from 0x0 to 0x10000 (= 100% PWM) 2595 * 2596 * Example usage: cat /sys/kernel/debug/dri/0/eDP-1/current_backlight 2597 */ 2598static int current_backlight_show(struct seq_file *m, void *unused) 2599{ 2600 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private); 2601 struct dc_link *link = aconnector->dc_link; 2602 unsigned int backlight; 2603 2604 backlight = dc_link_get_backlight_level(link); 2605 seq_printf(m, "0x%x\n", backlight); 2606 2607 return 0; 2608} 2609 2610/* 2611 * Backlight value that is being approached. Read only. 2612 * As written to display, taking ABM and backlight lut into account. 2613 * Ranges from 0x0 to 0x10000 (= 100% PWM) 2614 * 2615 * Example usage: cat /sys/kernel/debug/dri/0/eDP-1/target_backlight 2616 */ 2617static int target_backlight_show(struct seq_file *m, void *unused) 2618{ 2619 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private); 2620 struct dc_link *link = aconnector->dc_link; 2621 unsigned int backlight; 2622 2623 backlight = dc_link_get_target_backlight_pwm(link); 2624 seq_printf(m, "0x%x\n", backlight); 2625 2626 return 0; 2627} 2628 2629/* 2630 * function description: Determine if the connector is mst connector 2631 * 2632 * This function helps to determine whether a connector is a mst connector. 2633 * - "root" stands for the root connector of the topology 2634 * - "branch" stands for branch device of the topology 2635 * - "end" stands for leaf node connector of the topology 2636 * - "no" stands for the connector is not a device of a mst topology 2637 * Access it with the following command: 2638 * 2639 * cat /sys/kernel/debug/dri/0/DP-X/is_mst_connector 2640 * 2641 */ 2642static int dp_is_mst_connector_show(struct seq_file *m, void *unused) 2643{ 2644 struct drm_connector *connector = m->private; 2645 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 2646 struct drm_dp_mst_topology_mgr *mgr = NULL; 2647 struct drm_dp_mst_port *port = NULL; 2648 char *role = NULL; 2649 2650 mutex_lock(&aconnector->hpd_lock); 2651 2652 if (aconnector->mst_mgr.mst_state) { 2653 role = "root"; 2654 } else if (aconnector->mst_root && 2655 aconnector->mst_root->mst_mgr.mst_state) { 2656 2657 role = "end"; 2658 2659 mgr = &aconnector->mst_root->mst_mgr; 2660 port = aconnector->mst_output_port; 2661 2662 drm_modeset_lock(&mgr->base.lock, NULL); 2663 if (port->pdt == DP_PEER_DEVICE_MST_BRANCHING && 2664 port->mcs) 2665 role = "branch"; 2666 drm_modeset_unlock(&mgr->base.lock); 2667 2668 } else { 2669 role = "no"; 2670 } 2671 2672 seq_printf(m, "%s\n", role); 2673 2674 mutex_unlock(&aconnector->hpd_lock); 2675 2676 return 0; 2677} 2678 2679/* 2680 * function description: Read out the mst progress status 2681 * 2682 * This function helps to determine the mst progress status of 2683 * a mst connector. 2684 * 2685 * Access it with the following command: 2686 * 2687 * cat /sys/kernel/debug/dri/0/DP-X/mst_progress_status 2688 * 2689 */ 2690static int dp_mst_progress_status_show(struct seq_file *m, void *unused) 2691{ 2692 struct drm_connector *connector = m->private; 2693 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 2694 struct amdgpu_device *adev = drm_to_adev(connector->dev); 2695 int i; 2696 2697 mutex_lock(&aconnector->hpd_lock); 2698 mutex_lock(&adev->dm.dc_lock); 2699 2700 if (aconnector->mst_status == MST_STATUS_DEFAULT) { 2701 seq_puts(m, "disabled\n"); 2702 } else { 2703 for (i = 0; i < sizeof(mst_progress_status)/sizeof(char *); i++) 2704 seq_printf(m, "%s:%s\n", 2705 mst_progress_status[i], 2706 aconnector->mst_status & BIT(i) ? "done" : "not_done"); 2707 } 2708 2709 mutex_unlock(&adev->dm.dc_lock); 2710 mutex_unlock(&aconnector->hpd_lock); 2711 2712 return 0; 2713} 2714 2715/* 2716 * Reports whether the connected display is a USB4 DPIA tunneled display 2717 * Example usage: cat /sys/kernel/debug/dri/0/DP-8/is_dpia_link 2718 */ 2719static int is_dpia_link_show(struct seq_file *m, void *data) 2720{ 2721 struct drm_connector *connector = m->private; 2722 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 2723 struct dc_link *link = aconnector->dc_link; 2724 2725 if (connector->status != connector_status_connected) 2726 return -ENODEV; 2727 2728 seq_printf(m, "%s\n", (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) ? "yes" : 2729 (link->ep_type == DISPLAY_ENDPOINT_PHY) ? "no" : "unknown"); 2730 2731 return 0; 2732} 2733 2734DEFINE_SHOW_ATTRIBUTE(dp_dsc_fec_support); 2735DEFINE_SHOW_ATTRIBUTE(dmub_fw_state); 2736DEFINE_SHOW_ATTRIBUTE(dmub_tracebuffer); 2737DEFINE_SHOW_ATTRIBUTE(dp_lttpr_status); 2738DEFINE_SHOW_ATTRIBUTE(hdcp_sink_capability); 2739DEFINE_SHOW_ATTRIBUTE(internal_display); 2740DEFINE_SHOW_ATTRIBUTE(psr_capability); 2741DEFINE_SHOW_ATTRIBUTE(dp_is_mst_connector); 2742DEFINE_SHOW_ATTRIBUTE(dp_mst_progress_status); 2743DEFINE_SHOW_ATTRIBUTE(is_dpia_link); 2744 2745static const struct file_operations dp_dsc_clock_en_debugfs_fops = { 2746 .owner = THIS_MODULE, 2747 .read = dp_dsc_clock_en_read, 2748 .write = dp_dsc_clock_en_write, 2749 .llseek = default_llseek 2750}; 2751 2752static const struct file_operations dp_dsc_slice_width_debugfs_fops = { 2753 .owner = THIS_MODULE, 2754 .read = dp_dsc_slice_width_read, 2755 .write = dp_dsc_slice_width_write, 2756 .llseek = default_llseek 2757}; 2758 2759static const struct file_operations dp_dsc_slice_height_debugfs_fops = { 2760 .owner = THIS_MODULE, 2761 .read = dp_dsc_slice_height_read, 2762 .write = dp_dsc_slice_height_write, 2763 .llseek = default_llseek 2764}; 2765 2766static const struct file_operations dp_dsc_bits_per_pixel_debugfs_fops = { 2767 .owner = THIS_MODULE, 2768 .read = dp_dsc_bits_per_pixel_read, 2769 .write = dp_dsc_bits_per_pixel_write, 2770 .llseek = default_llseek 2771}; 2772 2773static const struct file_operations dp_dsc_pic_width_debugfs_fops = { 2774 .owner = THIS_MODULE, 2775 .read = dp_dsc_pic_width_read, 2776 .llseek = default_llseek 2777}; 2778 2779static const struct file_operations dp_dsc_pic_height_debugfs_fops = { 2780 .owner = THIS_MODULE, 2781 .read = dp_dsc_pic_height_read, 2782 .llseek = default_llseek 2783}; 2784 2785static const struct file_operations dp_dsc_chunk_size_debugfs_fops = { 2786 .owner = THIS_MODULE, 2787 .read = dp_dsc_chunk_size_read, 2788 .llseek = default_llseek 2789}; 2790 2791static const struct file_operations dp_dsc_slice_bpg_offset_debugfs_fops = { 2792 .owner = THIS_MODULE, 2793 .read = dp_dsc_slice_bpg_offset_read, 2794 .llseek = default_llseek 2795}; 2796 2797static const struct file_operations trigger_hotplug_debugfs_fops = { 2798 .owner = THIS_MODULE, 2799 .write = trigger_hotplug, 2800 .llseek = default_llseek 2801}; 2802 2803static const struct file_operations dp_link_settings_debugfs_fops = { 2804 .owner = THIS_MODULE, 2805 .read = dp_link_settings_read, 2806 .write = dp_link_settings_write, 2807 .llseek = default_llseek 2808}; 2809 2810static const struct file_operations dp_phy_settings_debugfs_fop = { 2811 .owner = THIS_MODULE, 2812 .read = dp_phy_settings_read, 2813 .write = dp_phy_settings_write, 2814 .llseek = default_llseek 2815}; 2816 2817static const struct file_operations dp_phy_test_pattern_fops = { 2818 .owner = THIS_MODULE, 2819 .write = dp_phy_test_pattern_debugfs_write, 2820 .llseek = default_llseek 2821}; 2822 2823static const struct file_operations sdp_message_fops = { 2824 .owner = THIS_MODULE, 2825 .write = dp_sdp_message_debugfs_write, 2826 .llseek = default_llseek 2827}; 2828 2829static const struct file_operations dp_max_bpc_debugfs_fops = { 2830 .owner = THIS_MODULE, 2831 .read = dp_max_bpc_read, 2832 .write = dp_max_bpc_write, 2833 .llseek = default_llseek 2834}; 2835 2836static const struct file_operations dp_dsc_disable_passthrough_debugfs_fops = { 2837 .owner = THIS_MODULE, 2838 .write = dp_dsc_passthrough_set, 2839 .llseek = default_llseek 2840}; 2841 2842static const struct file_operations dp_mst_link_settings_debugfs_fops = { 2843 .owner = THIS_MODULE, 2844 .write = dp_mst_link_setting, 2845 .llseek = default_llseek 2846}; 2847 2848static const struct { 2849 char *name; 2850 const struct file_operations *fops; 2851} dp_debugfs_entries[] = { 2852 {"link_settings", &dp_link_settings_debugfs_fops}, 2853 {"phy_settings", &dp_phy_settings_debugfs_fop}, 2854 {"lttpr_status", &dp_lttpr_status_fops}, 2855 {"test_pattern", &dp_phy_test_pattern_fops}, 2856 {"hdcp_sink_capability", &hdcp_sink_capability_fops}, 2857 {"sdp_message", &sdp_message_fops}, 2858 {"dsc_clock_en", &dp_dsc_clock_en_debugfs_fops}, 2859 {"dsc_slice_width", &dp_dsc_slice_width_debugfs_fops}, 2860 {"dsc_slice_height", &dp_dsc_slice_height_debugfs_fops}, 2861 {"dsc_bits_per_pixel", &dp_dsc_bits_per_pixel_debugfs_fops}, 2862 {"dsc_pic_width", &dp_dsc_pic_width_debugfs_fops}, 2863 {"dsc_pic_height", &dp_dsc_pic_height_debugfs_fops}, 2864 {"dsc_chunk_size", &dp_dsc_chunk_size_debugfs_fops}, 2865 {"dsc_slice_bpg", &dp_dsc_slice_bpg_offset_debugfs_fops}, 2866 {"dp_dsc_fec_support", &dp_dsc_fec_support_fops}, 2867 {"max_bpc", &dp_max_bpc_debugfs_fops}, 2868 {"dsc_disable_passthrough", &dp_dsc_disable_passthrough_debugfs_fops}, 2869 {"is_mst_connector", &dp_is_mst_connector_fops}, 2870 {"mst_progress_status", &dp_mst_progress_status_fops}, 2871 {"is_dpia_link", &is_dpia_link_fops}, 2872 {"mst_link_settings", &dp_mst_link_settings_debugfs_fops} 2873}; 2874 2875static const struct { 2876 char *name; 2877 const struct file_operations *fops; 2878} hdmi_debugfs_entries[] = { 2879 {"hdcp_sink_capability", &hdcp_sink_capability_fops} 2880}; 2881 2882/* 2883 * Force YUV420 output if available from the given mode 2884 */ 2885static int force_yuv420_output_set(void *data, u64 val) 2886{ 2887 struct amdgpu_dm_connector *connector = data; 2888 2889 connector->force_yuv420_output = (bool)val; 2890 2891 return 0; 2892} 2893 2894/* 2895 * Check if YUV420 is forced when available from the given mode 2896 */ 2897static int force_yuv420_output_get(void *data, u64 *val) 2898{ 2899 struct amdgpu_dm_connector *connector = data; 2900 2901 *val = connector->force_yuv420_output; 2902 2903 return 0; 2904} 2905 2906DEFINE_DEBUGFS_ATTRIBUTE(force_yuv420_output_fops, force_yuv420_output_get, 2907 force_yuv420_output_set, "%llu\n"); 2908 2909/* 2910 * Read PSR state 2911 */ 2912static int psr_get(void *data, u64 *val) 2913{ 2914 struct amdgpu_dm_connector *connector = data; 2915 struct dc_link *link = connector->dc_link; 2916 enum dc_psr_state state = PSR_STATE0; 2917 2918 dc_link_get_psr_state(link, &state); 2919 2920 *val = state; 2921 2922 return 0; 2923} 2924 2925/* 2926 * Read PSR state residency 2927 */ 2928static int psr_read_residency(void *data, u64 *val) 2929{ 2930 struct amdgpu_dm_connector *connector = data; 2931 struct dc_link *link = connector->dc_link; 2932 u32 residency; 2933 2934 link->dc->link_srv->edp_get_psr_residency(link, &residency); 2935 2936 *val = (u64)residency; 2937 2938 return 0; 2939} 2940 2941/* read allow_edp_hotplug_detection */ 2942static int allow_edp_hotplug_detection_get(void *data, u64 *val) 2943{ 2944 struct amdgpu_dm_connector *aconnector = data; 2945 struct drm_connector *connector = &aconnector->base; 2946 struct drm_device *dev = connector->dev; 2947 struct amdgpu_device *adev = drm_to_adev(dev); 2948 2949 *val = adev->dm.dc->config.allow_edp_hotplug_detection; 2950 2951 return 0; 2952} 2953 2954/* set allow_edp_hotplug_detection */ 2955static int allow_edp_hotplug_detection_set(void *data, u64 val) 2956{ 2957 struct amdgpu_dm_connector *aconnector = data; 2958 struct drm_connector *connector = &aconnector->base; 2959 struct drm_device *dev = connector->dev; 2960 struct amdgpu_device *adev = drm_to_adev(dev); 2961 2962 adev->dm.dc->config.allow_edp_hotplug_detection = (uint32_t) val; 2963 2964 return 0; 2965} 2966 2967/* 2968 * Set dmcub trace event IRQ enable or disable. 2969 * Usage to enable dmcub trace event IRQ: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en 2970 * Usage to disable dmcub trace event IRQ: echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en 2971 */ 2972static int dmcub_trace_event_state_set(void *data, u64 val) 2973{ 2974 struct amdgpu_device *adev = data; 2975 2976 if (val == 1 || val == 0) { 2977 dc_dmub_trace_event_control(adev->dm.dc, val); 2978 adev->dm.dmcub_trace_event_en = (bool)val; 2979 } else 2980 return 0; 2981 2982 return 0; 2983} 2984 2985/* 2986 * The interface doesn't need get function, so it will return the 2987 * value of zero 2988 * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en 2989 */ 2990static int dmcub_trace_event_state_get(void *data, u64 *val) 2991{ 2992 struct amdgpu_device *adev = data; 2993 2994 *val = adev->dm.dmcub_trace_event_en; 2995 return 0; 2996} 2997 2998DEFINE_DEBUGFS_ATTRIBUTE(dmcub_trace_event_state_fops, dmcub_trace_event_state_get, 2999 dmcub_trace_event_state_set, "%llu\n"); 3000 3001DEFINE_DEBUGFS_ATTRIBUTE(psr_fops, psr_get, NULL, "%llu\n"); 3002DEFINE_DEBUGFS_ATTRIBUTE(psr_residency_fops, psr_read_residency, NULL, 3003 "%llu\n"); 3004 3005DEFINE_DEBUGFS_ATTRIBUTE(allow_edp_hotplug_detection_fops, 3006 allow_edp_hotplug_detection_get, 3007 allow_edp_hotplug_detection_set, "%llu\n"); 3008 3009DEFINE_SHOW_ATTRIBUTE(current_backlight); 3010DEFINE_SHOW_ATTRIBUTE(target_backlight); 3011 3012static const struct { 3013 char *name; 3014 const struct file_operations *fops; 3015} connector_debugfs_entries[] = { 3016 {"force_yuv420_output", &force_yuv420_output_fops}, 3017 {"trigger_hotplug", &trigger_hotplug_debugfs_fops}, 3018 {"internal_display", &internal_display_fops} 3019}; 3020 3021/* 3022 * Returns supported customized link rates by this eDP panel. 3023 * Example usage: cat /sys/kernel/debug/dri/0/eDP-x/ilr_setting 3024 */ 3025static int edp_ilr_show(struct seq_file *m, void *unused) 3026{ 3027 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private); 3028 struct dc_link *link = aconnector->dc_link; 3029 uint8_t supported_link_rates[16]; 3030 uint32_t link_rate_in_khz; 3031 uint32_t entry = 0; 3032 uint8_t dpcd_rev; 3033 3034 memset(supported_link_rates, 0, sizeof(supported_link_rates)); 3035 dm_helpers_dp_read_dpcd(link->ctx, link, DP_SUPPORTED_LINK_RATES, 3036 supported_link_rates, sizeof(supported_link_rates)); 3037 3038 dpcd_rev = link->dpcd_caps.dpcd_rev.raw; 3039 3040 if (dpcd_rev >= DP_DPCD_REV_13 && 3041 (supported_link_rates[entry+1] != 0 || supported_link_rates[entry] != 0)) { 3042 3043 for (entry = 0; entry < 16; entry += 2) { 3044 link_rate_in_khz = (supported_link_rates[entry+1] * 0x100 + 3045 supported_link_rates[entry]) * 200; 3046 seq_printf(m, "[%d] %d kHz\n", entry/2, link_rate_in_khz); 3047 } 3048 } else { 3049 seq_puts(m, "ILR is not supported by this eDP panel.\n"); 3050 } 3051 3052 return 0; 3053} 3054 3055/* 3056 * Set supported customized link rate to eDP panel. 3057 * 3058 * echo <lane_count> <link_rate option> > ilr_setting 3059 * 3060 * for example, supported ILR : [0] 1620000 kHz [1] 2160000 kHz [2] 2430000 kHz ... 3061 * echo 4 1 > /sys/kernel/debug/dri/0/eDP-x/ilr_setting 3062 * to set 4 lanes and 2.16 GHz 3063 */ 3064static ssize_t edp_ilr_write(struct file *f, const char __user *buf, 3065 size_t size, loff_t *pos) 3066{ 3067 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 3068 struct dc_link *link = connector->dc_link; 3069 struct amdgpu_device *adev = drm_to_adev(connector->base.dev); 3070 struct dc *dc = (struct dc *)link->dc; 3071 struct dc_link_settings prefer_link_settings; 3072 char *wr_buf = NULL; 3073 const uint32_t wr_buf_size = 40; 3074 /* 0: lane_count; 1: link_rate */ 3075 int max_param_num = 2; 3076 uint8_t param_nums = 0; 3077 long param[2]; 3078 bool valid_input = true; 3079 3080 if (size == 0) 3081 return -EINVAL; 3082 3083 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 3084 if (!wr_buf) 3085 return -ENOMEM; 3086 3087 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 3088 (long *)param, buf, 3089 max_param_num, 3090 ¶m_nums)) { 3091 kfree(wr_buf); 3092 return -EINVAL; 3093 } 3094 3095 if (param_nums <= 0) { 3096 kfree(wr_buf); 3097 return -EINVAL; 3098 } 3099 3100 switch (param[0]) { 3101 case LANE_COUNT_ONE: 3102 case LANE_COUNT_TWO: 3103 case LANE_COUNT_FOUR: 3104 break; 3105 default: 3106 valid_input = false; 3107 break; 3108 } 3109 3110 if (param[1] >= link->dpcd_caps.edp_supported_link_rates_count) 3111 valid_input = false; 3112 3113 if (!valid_input) { 3114 kfree(wr_buf); 3115 DRM_DEBUG_DRIVER("Invalid Input value. No HW will be programmed\n"); 3116 prefer_link_settings.use_link_rate_set = false; 3117 mutex_lock(&adev->dm.dc_lock); 3118 dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false); 3119 mutex_unlock(&adev->dm.dc_lock); 3120 return size; 3121 } 3122 3123 /* save user force lane_count, link_rate to preferred settings 3124 * spread spectrum will not be changed 3125 */ 3126 prefer_link_settings.link_spread = link->cur_link_settings.link_spread; 3127 prefer_link_settings.lane_count = param[0]; 3128 prefer_link_settings.use_link_rate_set = true; 3129 prefer_link_settings.link_rate_set = param[1]; 3130 prefer_link_settings.link_rate = link->dpcd_caps.edp_supported_link_rates[param[1]]; 3131 3132 mutex_lock(&adev->dm.dc_lock); 3133 dc_link_set_preferred_training_settings(dc, &prefer_link_settings, 3134 NULL, link, false); 3135 mutex_unlock(&adev->dm.dc_lock); 3136 3137 kfree(wr_buf); 3138 return size; 3139} 3140 3141static int edp_ilr_open(struct inode *inode, struct file *file) 3142{ 3143 return single_open(file, edp_ilr_show, inode->i_private); 3144} 3145 3146static const struct file_operations edp_ilr_debugfs_fops = { 3147 .owner = THIS_MODULE, 3148 .open = edp_ilr_open, 3149 .read = seq_read, 3150 .llseek = seq_lseek, 3151 .release = single_release, 3152 .write = edp_ilr_write 3153}; 3154 3155void connector_debugfs_init(struct amdgpu_dm_connector *connector) 3156{ 3157 int i; 3158 struct dentry *dir = connector->base.debugfs_entry; 3159 3160 if (connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort || 3161 connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) { 3162 for (i = 0; i < ARRAY_SIZE(dp_debugfs_entries); i++) { 3163 debugfs_create_file(dp_debugfs_entries[i].name, 3164 0644, dir, connector, 3165 dp_debugfs_entries[i].fops); 3166 } 3167 } 3168 if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) { 3169 debugfs_create_file_unsafe("psr_capability", 0444, dir, connector, &psr_capability_fops); 3170 debugfs_create_file_unsafe("psr_state", 0444, dir, connector, &psr_fops); 3171 debugfs_create_file_unsafe("psr_residency", 0444, dir, 3172 connector, &psr_residency_fops); 3173 debugfs_create_file("amdgpu_current_backlight_pwm", 0444, dir, connector, 3174 ¤t_backlight_fops); 3175 debugfs_create_file("amdgpu_target_backlight_pwm", 0444, dir, connector, 3176 &target_backlight_fops); 3177 debugfs_create_file("ilr_setting", 0644, dir, connector, 3178 &edp_ilr_debugfs_fops); 3179 debugfs_create_file("allow_edp_hotplug_detection", 0644, dir, connector, 3180 &allow_edp_hotplug_detection_fops); 3181 } 3182 3183 for (i = 0; i < ARRAY_SIZE(connector_debugfs_entries); i++) { 3184 debugfs_create_file(connector_debugfs_entries[i].name, 3185 0644, dir, connector, 3186 connector_debugfs_entries[i].fops); 3187 } 3188 3189 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) { 3190 for (i = 0; i < ARRAY_SIZE(hdmi_debugfs_entries); i++) { 3191 debugfs_create_file(hdmi_debugfs_entries[i].name, 3192 0644, dir, connector, 3193 hdmi_debugfs_entries[i].fops); 3194 } 3195 } 3196} 3197 3198#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 3199/* 3200 * Set crc window coordinate x start 3201 */ 3202static int crc_win_x_start_set(void *data, u64 val) 3203{ 3204 struct drm_crtc *crtc = data; 3205 struct drm_device *drm_dev = crtc->dev; 3206 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3207 3208 spin_lock_irq(&drm_dev->event_lock); 3209 acrtc->dm_irq_params.window_param.x_start = (uint16_t) val; 3210 acrtc->dm_irq_params.window_param.update_win = false; 3211 spin_unlock_irq(&drm_dev->event_lock); 3212 3213 return 0; 3214} 3215 3216/* 3217 * Get crc window coordinate x start 3218 */ 3219static int crc_win_x_start_get(void *data, u64 *val) 3220{ 3221 struct drm_crtc *crtc = data; 3222 struct drm_device *drm_dev = crtc->dev; 3223 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3224 3225 spin_lock_irq(&drm_dev->event_lock); 3226 *val = acrtc->dm_irq_params.window_param.x_start; 3227 spin_unlock_irq(&drm_dev->event_lock); 3228 3229 return 0; 3230} 3231 3232DEFINE_DEBUGFS_ATTRIBUTE(crc_win_x_start_fops, crc_win_x_start_get, 3233 crc_win_x_start_set, "%llu\n"); 3234 3235 3236/* 3237 * Set crc window coordinate y start 3238 */ 3239static int crc_win_y_start_set(void *data, u64 val) 3240{ 3241 struct drm_crtc *crtc = data; 3242 struct drm_device *drm_dev = crtc->dev; 3243 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3244 3245 spin_lock_irq(&drm_dev->event_lock); 3246 acrtc->dm_irq_params.window_param.y_start = (uint16_t) val; 3247 acrtc->dm_irq_params.window_param.update_win = false; 3248 spin_unlock_irq(&drm_dev->event_lock); 3249 3250 return 0; 3251} 3252 3253/* 3254 * Get crc window coordinate y start 3255 */ 3256static int crc_win_y_start_get(void *data, u64 *val) 3257{ 3258 struct drm_crtc *crtc = data; 3259 struct drm_device *drm_dev = crtc->dev; 3260 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3261 3262 spin_lock_irq(&drm_dev->event_lock); 3263 *val = acrtc->dm_irq_params.window_param.y_start; 3264 spin_unlock_irq(&drm_dev->event_lock); 3265 3266 return 0; 3267} 3268 3269DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_start_fops, crc_win_y_start_get, 3270 crc_win_y_start_set, "%llu\n"); 3271 3272/* 3273 * Set crc window coordinate x end 3274 */ 3275static int crc_win_x_end_set(void *data, u64 val) 3276{ 3277 struct drm_crtc *crtc = data; 3278 struct drm_device *drm_dev = crtc->dev; 3279 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3280 3281 spin_lock_irq(&drm_dev->event_lock); 3282 acrtc->dm_irq_params.window_param.x_end = (uint16_t) val; 3283 acrtc->dm_irq_params.window_param.update_win = false; 3284 spin_unlock_irq(&drm_dev->event_lock); 3285 3286 return 0; 3287} 3288 3289/* 3290 * Get crc window coordinate x end 3291 */ 3292static int crc_win_x_end_get(void *data, u64 *val) 3293{ 3294 struct drm_crtc *crtc = data; 3295 struct drm_device *drm_dev = crtc->dev; 3296 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3297 3298 spin_lock_irq(&drm_dev->event_lock); 3299 *val = acrtc->dm_irq_params.window_param.x_end; 3300 spin_unlock_irq(&drm_dev->event_lock); 3301 3302 return 0; 3303} 3304 3305DEFINE_DEBUGFS_ATTRIBUTE(crc_win_x_end_fops, crc_win_x_end_get, 3306 crc_win_x_end_set, "%llu\n"); 3307 3308/* 3309 * Set crc window coordinate y end 3310 */ 3311static int crc_win_y_end_set(void *data, u64 val) 3312{ 3313 struct drm_crtc *crtc = data; 3314 struct drm_device *drm_dev = crtc->dev; 3315 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3316 3317 spin_lock_irq(&drm_dev->event_lock); 3318 acrtc->dm_irq_params.window_param.y_end = (uint16_t) val; 3319 acrtc->dm_irq_params.window_param.update_win = false; 3320 spin_unlock_irq(&drm_dev->event_lock); 3321 3322 return 0; 3323} 3324 3325/* 3326 * Get crc window coordinate y end 3327 */ 3328static int crc_win_y_end_get(void *data, u64 *val) 3329{ 3330 struct drm_crtc *crtc = data; 3331 struct drm_device *drm_dev = crtc->dev; 3332 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3333 3334 spin_lock_irq(&drm_dev->event_lock); 3335 *val = acrtc->dm_irq_params.window_param.y_end; 3336 spin_unlock_irq(&drm_dev->event_lock); 3337 3338 return 0; 3339} 3340 3341DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_end_fops, crc_win_y_end_get, 3342 crc_win_y_end_set, "%llu\n"); 3343/* 3344 * Trigger to commit crc window 3345 */ 3346static int crc_win_update_set(void *data, u64 val) 3347{ 3348 struct drm_crtc *crtc = data; 3349 struct amdgpu_crtc *acrtc; 3350 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 3351 3352 if (val) { 3353 acrtc = to_amdgpu_crtc(crtc); 3354 mutex_lock(&adev->dm.dc_lock); 3355 /* PSR may write to OTG CRC window control register, 3356 * so close it before starting secure_display. 3357 */ 3358 amdgpu_dm_psr_disable(acrtc->dm_irq_params.stream); 3359 3360 spin_lock_irq(&adev_to_drm(adev)->event_lock); 3361 3362 acrtc->dm_irq_params.window_param.activated = true; 3363 acrtc->dm_irq_params.window_param.update_win = true; 3364 acrtc->dm_irq_params.window_param.skip_frame_cnt = 0; 3365 3366 spin_unlock_irq(&adev_to_drm(adev)->event_lock); 3367 mutex_unlock(&adev->dm.dc_lock); 3368 } 3369 3370 return 0; 3371} 3372 3373/* 3374 * Get crc window update flag 3375 */ 3376static int crc_win_update_get(void *data, u64 *val) 3377{ 3378 *val = 0; 3379 return 0; 3380} 3381 3382DEFINE_DEBUGFS_ATTRIBUTE(crc_win_update_fops, crc_win_update_get, 3383 crc_win_update_set, "%llu\n"); 3384#endif 3385void crtc_debugfs_init(struct drm_crtc *crtc) 3386{ 3387#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 3388 struct dentry *dir = debugfs_lookup("crc", crtc->debugfs_entry); 3389 3390 if (!dir) 3391 return; 3392 3393 debugfs_create_file_unsafe("crc_win_x_start", 0644, dir, crtc, 3394 &crc_win_x_start_fops); 3395 debugfs_create_file_unsafe("crc_win_y_start", 0644, dir, crtc, 3396 &crc_win_y_start_fops); 3397 debugfs_create_file_unsafe("crc_win_x_end", 0644, dir, crtc, 3398 &crc_win_x_end_fops); 3399 debugfs_create_file_unsafe("crc_win_y_end", 0644, dir, crtc, 3400 &crc_win_y_end_fops); 3401 debugfs_create_file_unsafe("crc_win_update", 0644, dir, crtc, 3402 &crc_win_update_fops); 3403 dput(dir); 3404#endif 3405 debugfs_create_file("amdgpu_current_bpc", 0644, crtc->debugfs_entry, 3406 crtc, &amdgpu_current_bpc_fops); 3407 debugfs_create_file("amdgpu_current_colorspace", 0644, crtc->debugfs_entry, 3408 crtc, &amdgpu_current_colorspace_fops); 3409} 3410 3411/* 3412 * Writes DTN log state to the user supplied buffer. 3413 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log 3414 */ 3415static ssize_t dtn_log_read( 3416 struct file *f, 3417 char __user *buf, 3418 size_t size, 3419 loff_t *pos) 3420{ 3421 struct amdgpu_device *adev = file_inode(f)->i_private; 3422 struct dc *dc = adev->dm.dc; 3423 struct dc_log_buffer_ctx log_ctx = { 0 }; 3424 ssize_t result = 0; 3425 3426 if (!buf || !size) 3427 return -EINVAL; 3428 3429 if (!dc->hwss.log_hw_state) 3430 return 0; 3431 3432 dc->hwss.log_hw_state(dc, &log_ctx); 3433 3434 if (*pos < log_ctx.pos) { 3435 size_t to_copy = log_ctx.pos - *pos; 3436 3437 to_copy = min(to_copy, size); 3438 3439 if (!copy_to_user(buf, log_ctx.buf + *pos, to_copy)) { 3440 *pos += to_copy; 3441 result = to_copy; 3442 } 3443 } 3444 3445 kfree(log_ctx.buf); 3446 3447 return result; 3448} 3449 3450/* 3451 * Writes DTN log state to dmesg when triggered via a write. 3452 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log 3453 */ 3454static ssize_t dtn_log_write( 3455 struct file *f, 3456 const char __user *buf, 3457 size_t size, 3458 loff_t *pos) 3459{ 3460 struct amdgpu_device *adev = file_inode(f)->i_private; 3461 struct dc *dc = adev->dm.dc; 3462 3463 /* Write triggers log output via dmesg. */ 3464 if (size == 0) 3465 return 0; 3466 3467 if (dc->hwss.log_hw_state) 3468 dc->hwss.log_hw_state(dc, NULL); 3469 3470 return size; 3471} 3472 3473static int mst_topo_show(struct seq_file *m, void *unused) 3474{ 3475 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 3476 struct drm_device *dev = adev_to_drm(adev); 3477 struct drm_connector *connector; 3478 struct drm_connector_list_iter conn_iter; 3479 struct amdgpu_dm_connector *aconnector; 3480 3481 drm_connector_list_iter_begin(dev, &conn_iter); 3482 drm_for_each_connector_iter(connector, &conn_iter) { 3483 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) 3484 continue; 3485 3486 aconnector = to_amdgpu_dm_connector(connector); 3487 3488 /* Ensure we're only dumping the topology of a root mst node */ 3489 if (!aconnector->mst_mgr.mst_state) 3490 continue; 3491 3492 seq_printf(m, "\nMST topology for connector %d\n", aconnector->connector_id); 3493 drm_dp_mst_dump_topology(m, &aconnector->mst_mgr); 3494 } 3495 drm_connector_list_iter_end(&conn_iter); 3496 3497 return 0; 3498} 3499 3500/* 3501 * Sets trigger hpd for MST topologies. 3502 * All connected connectors will be rediscovered and re started as needed if val of 1 is sent. 3503 * All topologies will be disconnected if val of 0 is set . 3504 * Usage to enable topologies: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst 3505 * Usage to disable topologies: echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst 3506 */ 3507static int trigger_hpd_mst_set(void *data, u64 val) 3508{ 3509 struct amdgpu_device *adev = data; 3510 struct drm_device *dev = adev_to_drm(adev); 3511 struct drm_connector_list_iter iter; 3512 struct amdgpu_dm_connector *aconnector; 3513 struct drm_connector *connector; 3514 struct dc_link *link = NULL; 3515 3516 if (val == 1) { 3517 drm_connector_list_iter_begin(dev, &iter); 3518 drm_for_each_connector_iter(connector, &iter) { 3519 aconnector = to_amdgpu_dm_connector(connector); 3520 if (aconnector->dc_link->type == dc_connection_mst_branch && 3521 aconnector->mst_mgr.aux) { 3522 mutex_lock(&adev->dm.dc_lock); 3523 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); 3524 mutex_unlock(&adev->dm.dc_lock); 3525 3526 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true); 3527 } 3528 } 3529 } else if (val == 0) { 3530 drm_connector_list_iter_begin(dev, &iter); 3531 drm_for_each_connector_iter(connector, &iter) { 3532 aconnector = to_amdgpu_dm_connector(connector); 3533 if (!aconnector->dc_link) 3534 continue; 3535 3536 if (!aconnector->mst_root) 3537 continue; 3538 3539 link = aconnector->dc_link; 3540 dc_link_dp_receiver_power_ctrl(link, false); 3541 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_root->mst_mgr, false); 3542 link->mst_stream_alloc_table.stream_count = 0; 3543 memset(link->mst_stream_alloc_table.stream_allocations, 0, 3544 sizeof(link->mst_stream_alloc_table.stream_allocations)); 3545 } 3546 } else { 3547 return 0; 3548 } 3549 drm_kms_helper_hotplug_event(dev); 3550 3551 return 0; 3552} 3553 3554/* 3555 * The interface doesn't need get function, so it will return the 3556 * value of zero 3557 * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst 3558 */ 3559static int trigger_hpd_mst_get(void *data, u64 *val) 3560{ 3561 *val = 0; 3562 return 0; 3563} 3564 3565DEFINE_DEBUGFS_ATTRIBUTE(trigger_hpd_mst_ops, trigger_hpd_mst_get, 3566 trigger_hpd_mst_set, "%llu\n"); 3567 3568 3569/* 3570 * Sets the force_timing_sync debug option from the given string. 3571 * All connected displays will be force synchronized immediately. 3572 * Usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync 3573 */ 3574static int force_timing_sync_set(void *data, u64 val) 3575{ 3576 struct amdgpu_device *adev = data; 3577 3578 adev->dm.force_timing_sync = (bool)val; 3579 3580 amdgpu_dm_trigger_timing_sync(adev_to_drm(adev)); 3581 3582 return 0; 3583} 3584 3585/* 3586 * Gets the force_timing_sync debug option value into the given buffer. 3587 * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync 3588 */ 3589static int force_timing_sync_get(void *data, u64 *val) 3590{ 3591 struct amdgpu_device *adev = data; 3592 3593 *val = adev->dm.force_timing_sync; 3594 3595 return 0; 3596} 3597 3598DEFINE_DEBUGFS_ATTRIBUTE(force_timing_sync_ops, force_timing_sync_get, 3599 force_timing_sync_set, "%llu\n"); 3600 3601 3602/* 3603 * Disables all HPD and HPD RX interrupt handling in the 3604 * driver when set to 1. Default is 0. 3605 */ 3606static int disable_hpd_set(void *data, u64 val) 3607{ 3608 struct amdgpu_device *adev = data; 3609 3610 adev->dm.disable_hpd_irq = (bool)val; 3611 3612 return 0; 3613} 3614 3615 3616/* 3617 * Returns 1 if HPD and HPRX interrupt handling is disabled, 3618 * 0 otherwise. 3619 */ 3620static int disable_hpd_get(void *data, u64 *val) 3621{ 3622 struct amdgpu_device *adev = data; 3623 3624 *val = adev->dm.disable_hpd_irq; 3625 3626 return 0; 3627} 3628 3629DEFINE_DEBUGFS_ATTRIBUTE(disable_hpd_ops, disable_hpd_get, 3630 disable_hpd_set, "%llu\n"); 3631 3632/* 3633 * Temporary w/a to force sst sequence in M42D DP2 mst receiver 3634 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dp_set_mst_en_for_sst 3635 */ 3636static int dp_force_sst_set(void *data, u64 val) 3637{ 3638 struct amdgpu_device *adev = data; 3639 3640 adev->dm.dc->debug.set_mst_en_for_sst = val; 3641 3642 return 0; 3643} 3644 3645static int dp_force_sst_get(void *data, u64 *val) 3646{ 3647 struct amdgpu_device *adev = data; 3648 3649 *val = adev->dm.dc->debug.set_mst_en_for_sst; 3650 3651 return 0; 3652} 3653DEFINE_DEBUGFS_ATTRIBUTE(dp_set_mst_en_for_sst_ops, dp_force_sst_get, 3654 dp_force_sst_set, "%llu\n"); 3655 3656/* 3657 * Force DP2 sequence without VESA certified cable. 3658 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dp_ignore_cable_id 3659 */ 3660static int dp_ignore_cable_id_set(void *data, u64 val) 3661{ 3662 struct amdgpu_device *adev = data; 3663 3664 adev->dm.dc->debug.ignore_cable_id = val; 3665 3666 return 0; 3667} 3668 3669static int dp_ignore_cable_id_get(void *data, u64 *val) 3670{ 3671 struct amdgpu_device *adev = data; 3672 3673 *val = adev->dm.dc->debug.ignore_cable_id; 3674 3675 return 0; 3676} 3677DEFINE_DEBUGFS_ATTRIBUTE(dp_ignore_cable_id_ops, dp_ignore_cable_id_get, 3678 dp_ignore_cable_id_set, "%llu\n"); 3679 3680/* 3681 * Sets the DC visual confirm debug option from the given string. 3682 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_visual_confirm 3683 */ 3684static int visual_confirm_set(void *data, u64 val) 3685{ 3686 struct amdgpu_device *adev = data; 3687 3688 adev->dm.dc->debug.visual_confirm = (enum visual_confirm)val; 3689 3690 return 0; 3691} 3692 3693/* 3694 * Reads the DC visual confirm debug option value into the given buffer. 3695 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_visual_confirm 3696 */ 3697static int visual_confirm_get(void *data, u64 *val) 3698{ 3699 struct amdgpu_device *adev = data; 3700 3701 *val = adev->dm.dc->debug.visual_confirm; 3702 3703 return 0; 3704} 3705 3706DEFINE_SHOW_ATTRIBUTE(mst_topo); 3707DEFINE_DEBUGFS_ATTRIBUTE(visual_confirm_fops, visual_confirm_get, 3708 visual_confirm_set, "%llu\n"); 3709 3710 3711/* 3712 * Sets the DC skip_detection_link_training debug option from the given string. 3713 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_skip_detection_link_training 3714 */ 3715static int skip_detection_link_training_set(void *data, u64 val) 3716{ 3717 struct amdgpu_device *adev = data; 3718 3719 if (val == 0) 3720 adev->dm.dc->debug.skip_detection_link_training = false; 3721 else 3722 adev->dm.dc->debug.skip_detection_link_training = true; 3723 3724 return 0; 3725} 3726 3727/* 3728 * Reads the DC skip_detection_link_training debug option value into the given buffer. 3729 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_skip_detection_link_training 3730 */ 3731static int skip_detection_link_training_get(void *data, u64 *val) 3732{ 3733 struct amdgpu_device *adev = data; 3734 3735 *val = adev->dm.dc->debug.skip_detection_link_training; 3736 3737 return 0; 3738} 3739 3740DEFINE_DEBUGFS_ATTRIBUTE(skip_detection_link_training_fops, 3741 skip_detection_link_training_get, 3742 skip_detection_link_training_set, "%llu\n"); 3743 3744/* 3745 * Dumps the DCC_EN bit for each pipe. 3746 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dcc_en 3747 */ 3748static ssize_t dcc_en_bits_read( 3749 struct file *f, 3750 char __user *buf, 3751 size_t size, 3752 loff_t *pos) 3753{ 3754 struct amdgpu_device *adev = file_inode(f)->i_private; 3755 struct dc *dc = adev->dm.dc; 3756 char *rd_buf = NULL; 3757 const uint32_t rd_buf_size = 32; 3758 uint32_t result = 0; 3759 int offset = 0; 3760 int num_pipes = dc->res_pool->pipe_count; 3761 int *dcc_en_bits; 3762 int i, r; 3763 3764 dcc_en_bits = kcalloc(num_pipes, sizeof(int), GFP_KERNEL); 3765 if (!dcc_en_bits) 3766 return -ENOMEM; 3767 3768 if (!dc->hwss.get_dcc_en_bits) { 3769 kfree(dcc_en_bits); 3770 return 0; 3771 } 3772 3773 dc->hwss.get_dcc_en_bits(dc, dcc_en_bits); 3774 3775 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 3776 if (!rd_buf) { 3777 kfree(dcc_en_bits); 3778 return -ENOMEM; 3779 } 3780 3781 for (i = 0; i < num_pipes; i++) 3782 offset += snprintf(rd_buf + offset, rd_buf_size - offset, 3783 "%d ", dcc_en_bits[i]); 3784 rd_buf[strlen(rd_buf)] = '\n'; 3785 3786 kfree(dcc_en_bits); 3787 3788 while (size) { 3789 if (*pos >= rd_buf_size) 3790 break; 3791 r = put_user(*(rd_buf + result), buf); 3792 if (r) { 3793 kfree(rd_buf); 3794 return r; /* r = -EFAULT */ 3795 } 3796 buf += 1; 3797 size -= 1; 3798 *pos += 1; 3799 result += 1; 3800 } 3801 3802 kfree(rd_buf); 3803 return result; 3804} 3805 3806void dtn_debugfs_init(struct amdgpu_device *adev) 3807{ 3808 static const struct file_operations dtn_log_fops = { 3809 .owner = THIS_MODULE, 3810 .read = dtn_log_read, 3811 .write = dtn_log_write, 3812 .llseek = default_llseek 3813 }; 3814 static const struct file_operations dcc_en_bits_fops = { 3815 .owner = THIS_MODULE, 3816 .read = dcc_en_bits_read, 3817 .llseek = default_llseek 3818 }; 3819 3820 struct drm_minor *minor = adev_to_drm(adev)->primary; 3821 struct dentry *root = minor->debugfs_root; 3822 3823 debugfs_create_file("amdgpu_mst_topology", 0444, root, 3824 adev, &mst_topo_fops); 3825 debugfs_create_file("amdgpu_dm_dtn_log", 0644, root, adev, 3826 &dtn_log_fops); 3827 debugfs_create_file("amdgpu_dm_dp_set_mst_en_for_sst", 0644, root, adev, 3828 &dp_set_mst_en_for_sst_ops); 3829 debugfs_create_file("amdgpu_dm_dp_ignore_cable_id", 0644, root, adev, 3830 &dp_ignore_cable_id_ops); 3831 3832 debugfs_create_file_unsafe("amdgpu_dm_visual_confirm", 0644, root, adev, 3833 &visual_confirm_fops); 3834 3835 debugfs_create_file_unsafe("amdgpu_dm_skip_detection_link_training", 0644, root, adev, 3836 &skip_detection_link_training_fops); 3837 3838 debugfs_create_file_unsafe("amdgpu_dm_dmub_tracebuffer", 0644, root, 3839 adev, &dmub_tracebuffer_fops); 3840 3841 debugfs_create_file_unsafe("amdgpu_dm_dmub_fw_state", 0644, root, 3842 adev, &dmub_fw_state_fops); 3843 3844 debugfs_create_file_unsafe("amdgpu_dm_force_timing_sync", 0644, root, 3845 adev, &force_timing_sync_ops); 3846 3847 debugfs_create_file_unsafe("amdgpu_dm_dmcub_trace_event_en", 0644, root, 3848 adev, &dmcub_trace_event_state_fops); 3849 3850 debugfs_create_file_unsafe("amdgpu_dm_trigger_hpd_mst", 0644, root, 3851 adev, &trigger_hpd_mst_ops); 3852 3853 debugfs_create_file_unsafe("amdgpu_dm_dcc_en", 0644, root, adev, 3854 &dcc_en_bits_fops); 3855 3856 debugfs_create_file_unsafe("amdgpu_dm_disable_hpd", 0644, root, adev, 3857 &disable_hpd_ops); 3858 3859} 3860