1/* $OpenBSD: tlphyreg.h,v 1.4 2022/01/09 05:42:44 jsg Exp $ */ 2/* $NetBSD: tlphyreg.h,v 1.1 1998/08/10 23:59:58 thorpej Exp $ */ 3 4/* 5 * Copyright (c) 1997 Manuel Bouyer. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28#ifndef _DEV_MII_TLPHYREG_H_ 29#define _DEV_MII_TLPHYREG_H_ 30 31/* 32 * Registers for the TI ThunderLAN internal PHY. 33 */ 34 35#define MII_TLPHY_ID 0x10 /* ThunderLAN PHY ID */ 36#define ID_10BASETAUI 0x0001 /* 10baseT/AUI PHY */ 37 38#define MII_TLPHY_CTRL 0x11 /* Control register */ 39#define CTRL_ILINK 0x8000 /* Ignore link */ 40#define CTRL_SWPOL 0x4000 /* swap polarity */ 41#define CTRL_AUISEL 0x2000 /* Select AUI */ 42#define CTRL_SQEEN 0x1000 /* Enable SQE */ 43#define CTRL_NFEW 0x0004 /* Not far end wrap */ 44#define CTRL_INTEN 0x0002 /* Interrupts enable */ 45#define CTRL_TINT 0x0001 /* Test Interrupts */ 46 47#define MII_TLPHY_ST 0x12 /* Status register */ 48#define ST_MII_INT 0x8000 /* MII interrupt */ 49#define ST_PHOK 0x4000 /* Power high OK */ 50#define ST_POLOK 0x2000 /* Polarity OK */ 51#define ST_TPE 0x1000 /* Twisted pair energy */ 52 53#endif /* _DEV_MII_TLPHYREG_H_ */ 54