1/* $OpenBSD: ad1848.c,v 1.50 2024/05/28 09:27:08 jsg Exp $ */ 2/* $NetBSD: ad1848.c,v 1.45 1998/01/30 02:02:38 augustss Exp $ */ 3 4/* 5 * Copyright (c) 1994 John Brezak 6 * Copyright (c) 1991-1993 Regents of the University of California. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the Computer Systems 20 * Engineering Group at Lawrence Berkeley Laboratory. 21 * 4. Neither the name of the University nor of the Laboratory may be used 22 * to endorse or promote products derived from this software without 23 * specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 */ 38 39/* 40 * Copyright by Hannu Savolainen 1994 41 * 42 * Redistribution and use in source and binary forms, with or without 43 * modification, are permitted provided that the following conditions are 44 * met: 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 2. 46 * Redistributions in binary form must reproduce the above copyright notice, 47 * this list of conditions and the following disclaimer in the documentation 48 * and/or other materials provided with the distribution. 49 * 50 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY 51 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 52 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 53 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 54 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 55 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 56 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 57 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 58 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 59 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 60 * SUCH DAMAGE. 61 * 62 */ 63/* 64 * Portions of this code are from the VOXware support for the ad1848 65 * by Hannu Savolainen <hannu@voxware.pp.fi> 66 * 67 * Portions also supplied from the SoundBlaster driver for NetBSD. 68 */ 69 70#include <sys/param.h> 71#include <sys/systm.h> 72#include <sys/errno.h> 73#include <sys/ioctl.h> 74#include <sys/syslog.h> 75#include <sys/device.h> 76#include <sys/buf.h> 77#include <sys/fcntl.h> 78 79#include <machine/cpu.h> 80#include <machine/bus.h> 81 82#include <sys/audioio.h> 83 84#include <dev/audio_if.h> 85 86#include <dev/isa/isavar.h> 87#include <dev/isa/isadmavar.h> 88 89#include <dev/ic/ad1848reg.h> 90#include <dev/ic/cs4231reg.h> 91#include <dev/isa/ad1848var.h> 92 93#ifdef AUDIO_DEBUG 94#define DPRINTF(x) do { if (ad1848debug) printf x; } while (0); 95int ad1848debug = 0; 96#else 97#define DPRINTF(x) 98#endif 99 100/* 101 * Initial values for the indirect registers of CS4248/AD1848. 102 */ 103static int ad1848_init_values[] = { 104 GAIN_12 | INPUT_MIC_GAIN_ENABLE, /* Left Input Control */ 105 GAIN_12 | INPUT_MIC_GAIN_ENABLE, /* Right Input Control */ 106 ATTEN_12, /* Left Aux #1 Input Control */ 107 ATTEN_12, /* Right Aux #1 Input Control */ 108 ATTEN_12, /* Left Aux #2 Input Control */ 109 ATTEN_12, /* Right Aux #2 Input Control */ 110 /* bits 5-0 are attenuation select */ 111 ATTEN_12, /* Left DAC output Control */ 112 ATTEN_12, /* Right DAC output Control */ 113 CLOCK_XTAL1 | FMT_PCM8, /* Clock and Data Format */ 114 SINGLE_DMA | AUTO_CAL_ENABLE, /* Interface Config */ 115 INTERRUPT_ENABLE, /* Pin control */ 116 0x00, /* Test and Init */ 117 MODE2, /* Misc control */ 118 ATTEN_0 << 2, /* Digital Mix Control */ 119 0, /* Upper base Count */ 120 0, /* Lower base Count */ 121 122 /* These are for CS4231 &c. only (additional registers): */ 123 0, /* Alt feature 1 */ 124 0, /* Alt feature 2 */ 125 ATTEN_12, /* Left line in */ 126 ATTEN_12, /* Right line in */ 127 0, /* Timer low */ 128 0, /* Timer high */ 129 0, /* unused */ 130 0, /* unused */ 131 0, /* IRQ status */ 132 0, /* unused */ 133 134 /* Mono input (a.k.a speaker) (mic) Control */ 135 MONO_INPUT_MUTE|ATTEN_6, /* mute speaker by default */ 136 0, /* unused */ 137 0, /* record format */ 138 0, /* Crystal Clock Select */ 139 0, /* upper record count */ 140 0 /* lower record count */ 141}; 142 143static struct audio_params ad1848_audio_default = 144 {48000, AUDIO_ENCODING_SLINEAR_LE, 16, 2, 1, 2}; 145 146void ad1848_reset(struct ad1848_softc *); 147int ad1848_set_speed(struct ad1848_softc *, u_long *); 148void ad1848_mute_monitor(void *, int); 149 150/* indirect register access */ 151static int ad_read(struct ad1848_softc *, int); 152static void ad_write(struct ad1848_softc *, int, int); 153static void ad_set_MCE(struct ad1848_softc *, int); 154static void wait_for_calibration(struct ad1848_softc *); 155 156/* direct register (AD1848_{IADDR,IDATA,STATUS} only) access */ 157#define ADREAD(sc, addr) bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, (sc)->sc_iooffs+(addr)) 158#define ADWRITE(sc, addr, data) bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (sc)->sc_iooffs+(addr), (data)) 159 160static int 161ad_read(struct ad1848_softc *sc, int reg) 162{ 163 int x; 164 165 ADWRITE(sc, AD1848_IADDR, (reg & 0xff) | sc->MCE_bit); 166 x = ADREAD(sc, AD1848_IDATA); 167 /* printf("(%02x<-%02x) ", reg|sc->MCE_bit, x); */ 168 169 return x; 170} 171 172static void 173ad_write(struct ad1848_softc *sc, int reg, int data) 174{ 175 ADWRITE(sc, AD1848_IADDR, (reg & 0xff) | sc->MCE_bit); 176 ADWRITE(sc, AD1848_IDATA, data & 0xff); 177 /* printf("(%02x->%02x) ", reg|sc->MCE_bit, data); */ 178} 179 180static void 181ad_set_MCE(struct ad1848_softc *sc, int state) 182{ 183 if (state) 184 sc->MCE_bit = MODE_CHANGE_ENABLE; 185 else 186 sc->MCE_bit = 0; 187 188 ADWRITE(sc, AD1848_IADDR, sc->MCE_bit); 189} 190 191static void 192wait_for_calibration(struct ad1848_softc *sc) 193{ 194 int timeout; 195 196 DPRINTF(("ad1848: Auto calibration started.\n")); 197 /* 198 * Wait until the auto calibration process has finished. 199 * 200 * 1) Wait until the chip becomes ready (reads don't return SP_IN_INIT). 201 * 2) Wait until the ACI bit of I11 goes hi and then lo. 202 * a) With AD1848 alike, ACI goes hi within 5 sample cycles 203 * and remains hi for ~384 sample periods. 204 * b) With CS4231 alike, ACI goes hi immediately and remains 205 * hi for at least 168 sample periods. 206 */ 207 timeout = AD1848_TIMO; 208 while (timeout > 0 && ADREAD(sc, AD1848_IADDR) == SP_IN_INIT) 209 timeout--; 210 211 if (ADREAD(sc, AD1848_IADDR) == SP_IN_INIT) 212 DPRINTF(("ad1848: Auto calibration timed out(1).\n")); 213 214 if (!(sc->sc_flags & AD1848_FLAG_32REGS)) { 215 timeout = AD1848_TIMO; 216 while (timeout > 0 && 217 !(ad_read(sc, SP_TEST_AND_INIT) & AUTO_CAL_IN_PROG)) 218 timeout--; 219 220 if (!(ad_read(sc, SP_TEST_AND_INIT) & AUTO_CAL_IN_PROG)) { 221 DPRINTF(("ad1848: Auto calibration timed out(2).\n")); 222 } 223 } 224 225 timeout = AD1848_TIMO; 226 while (timeout > 0 && ad_read(sc, SP_TEST_AND_INIT) & AUTO_CAL_IN_PROG) 227 timeout--; 228 if (ad_read(sc, SP_TEST_AND_INIT) & AUTO_CAL_IN_PROG) 229 DPRINTF(("ad1848: Auto calibration timed out(3).\n")); 230} 231 232#ifdef AUDIO_DEBUG 233void ad1848_dump_regs(struct ad1848_softc *); 234 235void 236ad1848_dump_regs(struct ad1848_softc *sc) 237{ 238 int i; 239 u_char r; 240 241 printf("ad1848 status=%02x", ADREAD(sc, AD1848_STATUS)); 242 printf(" regs: "); 243 for (i = 0; i < 16; i++) { 244 r = ad_read(sc, i); 245 printf("%02x ", r); 246 } 247 if (sc->mode == 2) { 248 for (i = 16; i < 32; i++) { 249 r = ad_read(sc, i); 250 printf("%02x ", r); 251 } 252 } 253 printf("\n"); 254} 255#endif 256 257/* 258 * Map and probe for the ad1848 chip 259 */ 260int 261ad1848_mapprobe(struct ad1848_softc *sc, int iobase) 262{ 263 if (!AD1848_BASE_VALID(iobase)) { 264#ifdef AUDIO_DEBUG 265 printf("ad1848: configured iobase %04x invalid\n", iobase); 266#endif 267 return 0; 268 } 269 270 sc->sc_iooffs = 0; 271 /* Map the AD1848 ports */ 272 if (bus_space_map(sc->sc_iot, iobase, AD1848_NPORT, 0, &sc->sc_ioh)) 273 return 0; 274 275 if (!ad1848_probe(sc)) { 276 bus_space_unmap(sc->sc_iot, sc->sc_ioh, AD1848_NPORT); 277 return 0; 278 } else 279 return 1; 280} 281 282/* 283 * Probe for the ad1848 chip 284 */ 285int 286ad1848_probe(struct ad1848_softc *sc) 287{ 288 u_char tmp, tmp1 = 0xff, tmp2 = 0xff; 289#if 0 290 int i; 291#endif 292 293 /* Is there an ad1848 chip ? */ 294 sc->MCE_bit = MODE_CHANGE_ENABLE; 295 sc->mode = 1; /* MODE 1 = original ad1848/ad1846/cs4248 */ 296 sc->sc_flags = 0; 297 298 /* 299 * Check that the I/O address is in use. 300 * 301 * The SP_IN_INIT bit of the base I/O port is known to be 0 after the 302 * chip has performed its power-on initialization. Just assume 303 * this has happened before the OS is starting. 304 * 305 * If the I/O address is unused, inb() typically returns 0xff. 306 */ 307 tmp = ADREAD(sc, AD1848_IADDR); 308 if (tmp & SP_IN_INIT) { /* Not a AD1848 */ 309#if 0 310 DPRINTF(("ad_detect_A %x\n", tmp)); 311#endif 312 goto bad; 313 } 314 315 /* 316 * Test if it's possible to change contents of the indirect registers. 317 * Registers 0 and 1 are ADC volume registers. The bit 0x10 is read 318 * only so try to avoid using it. 319 */ 320 ad_write(sc, 0, 0xaa); 321 ad_write(sc, 1, 0x45); /* 0x55 with bit 0x10 clear */ 322 323 if ((tmp1 = ad_read(sc, 0)) != 0xaa || 324 (tmp2 = ad_read(sc, 1)) != 0x45) { 325 DPRINTF(("ad_detect_B (%x/%x)\n", tmp1, tmp2)); 326 goto bad; 327 } 328 329 ad_write(sc, 0, 0x45); 330 ad_write(sc, 1, 0xaa); 331 332 if ((tmp1 = ad_read(sc, 0)) != 0x45 || 333 (tmp2 = ad_read(sc, 1)) != 0xaa) { 334 DPRINTF(("ad_detect_C (%x/%x)\n", tmp1, tmp2)); 335 goto bad; 336 } 337 338 /* 339 * The indirect register I12 has some read only bits. Lets 340 * try to change them. 341 */ 342 tmp = ad_read(sc, SP_MISC_INFO); 343 ad_write(sc, SP_MISC_INFO, (~tmp) & 0x0f); 344 345 if ((tmp & 0x0f) != ((tmp1 = ad_read(sc, SP_MISC_INFO)) & 0x0f)) { 346 DPRINTF(("ad_detect_D (%x)\n", tmp1)); 347 goto bad; 348 } 349 350 /* 351 * MSB and 4 LSBs of the reg I12 tell the chip revision. 352 * 353 * A preliminary version of the AD1846 data sheet stated that it 354 * used an ID field of 0x0B. The current version, however, 355 * states that the AD1846 uses ID 0x0A, just like the AD1848K. 356 * 357 * this switch statement will need updating as newer clones arrive.... 358 */ 359 switch (tmp1 & 0x8f) { 360 case 0x09: 361 sc->chip_name = "AD1848J"; 362 break; 363 case 0x0A: 364 sc->chip_name = "AD1848K"; 365 break; 366#if 0 /* See above */ 367 case 0x0B: 368 sc->chip_name = "AD1846"; 369 break; 370#endif 371 case 0x81: 372 sc->chip_name = "CS4248revB"; /* or CS4231 rev B; see below */ 373 break; 374 case 0x89: 375 sc->chip_name = "CS4248"; 376 break; 377 case 0x8A: 378 sc->chip_name = "broken"; /* CS4231/AD1845; see below */ 379 break; 380 default: 381 sc->chip_name = "unknown"; 382 DPRINTF(("ad1848: unknown codec version %#02X\n", (tmp1 & 0x8f))); 383 } 384 385#if 0 386 /* 387 * XXX I don't know why, but this probe fails on an otherwise 388 * well-working AW35/pro card, so I'll just take it out for now. 389 * [niklas@openbsd.org] 390 */ 391 392 /* 393 * The original AD1848/CS4248 has just 16 indirect registers. This 394 * means that I0 and I16 should return the same value (etc.). 395 * Ensure that the Mode2 enable bit of I12 is 0. Otherwise this test 396 * fails with CS4231, AD1845, etc. 397 */ 398 ad_write(sc, SP_MISC_INFO, 0); /* Mode2 = disabled */ 399 400 for (i = 0; i < 16; i++) { 401 if ((tmp1 = ad_read(sc, i)) != (tmp2 = ad_read(sc, i + 16))) { 402 if (i != SP_TEST_AND_INIT) { 403 DPRINTF(("ad_detect_F(%d/%x/%x)\n", i, tmp1, tmp2)); 404 goto bad; 405 } 406 } 407 } 408#endif 409 410 /* 411 * Try to switch the chip to mode2 (CS4231) by setting the MODE2 bit 412 * The bit 0x80 is always 1 in CS4248, CS4231, and AD1845. 413 */ 414 ad_write(sc, SP_MISC_INFO, MODE2); /* Set mode2, clear 0x80 */ 415 416 tmp1 = ad_read(sc, SP_MISC_INFO); 417 if ((tmp1 & 0xc0) == (0x80 | MODE2)) { 418 /* 419 * CS4231 or AD1845 detected - is it? 420 * 421 * Verify that setting I2 doesn't change I18. 422 */ 423 ad_write(sc, 18, 0x88); /* Set I18 to known value */ 424 425 ad_write(sc, 2, 0x45); 426 if ((tmp2 = ad_read(sc, 18)) != 0x45) { 427 /* No change -> CS4231? */ 428 ad_write(sc, 2, 0xaa); 429 if ((tmp2 = ad_read(sc, 18)) == 0xaa) { 430 /* Rotten bits? */ 431 DPRINTF(("ad_detect_H(%x)\n", tmp2)); 432 goto bad; 433 } 434 435 /* 436 * It's a CS4231, or another clone with 32 registers. 437 * Let's find out which by checking I25. 438 */ 439 if ((tmp1 & 0x8f) == 0x8a) { 440 tmp1 = ad_read(sc, CS_VERSION_ID); 441 switch (tmp1 & 0xe7) { 442 case 0xA0: 443 sc->chip_name = "CS4231A"; 444 break; 445 case 0x80: 446 /* I25 no good, AD1845 same as CS4231 */ 447 sc->chip_name = "CS4231 or AD1845"; 448 break; 449 case 0x82: 450 sc->chip_name = "CS4232"; 451 break; 452 case 0xa2: 453 sc->chip_name = "CS4232C"; 454 break; 455 case 0x03: 456 sc->chip_name = "CS4236/CS4236B"; 457 break; 458 } 459 } 460 sc->mode = 2; 461 sc->sc_flags |= AD1848_FLAG_32REGS; 462 } 463 } 464 465 /* Wait for 1848 to init */ 466 while(ADREAD(sc, AD1848_IADDR) & SP_IN_INIT) 467 ; 468 469 /* Wait for 1848 to autocal */ 470 ADWRITE(sc, AD1848_IADDR, SP_TEST_AND_INIT); 471 while(ADREAD(sc, AD1848_IDATA) & AUTO_CAL_IN_PROG) 472 ; 473 474 return 1; 475bad: 476 return 0; 477} 478 479/* Unmap the I/O ports */ 480void 481ad1848_unmap(struct ad1848_softc *sc) 482{ 483 bus_space_unmap(sc->sc_iot, sc->sc_ioh, AD1848_NPORT); 484} 485 486/* 487 * Attach hardware to driver, attach hardware driver to audio 488 * pseudo-device driver . 489 */ 490void 491ad1848_attach(struct ad1848_softc *sc) 492{ 493 int i; 494 struct ad1848_volume vol_mid = {220, 220}; 495 struct ad1848_volume vol_0 = {0, 0}; 496 struct audio_params pparams, rparams; 497 int timeout; 498 499 sc->sc_playrun = 0; 500 sc->sc_recrun = 0; 501 502 if (sc->sc_drq != -1) { 503 if (isa_dmamap_create(sc->sc_isa, sc->sc_drq, MAX_ISADMA, 504 BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW)) { 505 printf("ad1848_attach: can't create map for drq %d\n", 506 sc->sc_drq); 507 return; 508 } 509 } 510 if (sc->sc_recdrq != -1 && sc->sc_recdrq != sc->sc_drq) { 511 if (isa_dmamap_create(sc->sc_isa, sc->sc_recdrq, MAX_ISADMA, 512 BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW)) { 513 printf("ad1848_attach: can't create map for second drq %d\n", 514 sc->sc_recdrq); 515 return; 516 } 517 } 518 519 /* Initialize the ad1848... */ 520 for (i = 0; i < 0x10; i++) { 521 ad_write(sc, i, ad1848_init_values[i]); 522 timeout = AD1848_TIMO; 523 while (timeout > 0 && ADREAD(sc, AD1848_IADDR) & SP_IN_INIT) 524 timeout--; 525 } 526 /* need 2 separate drqs for mode 2 */ 527 if ((sc->mode == 2) && 528 ((sc->sc_recdrq == -1) || (sc->sc_recdrq == sc->sc_drq))) { 529 ad_write(sc, SP_MISC_INFO, ad_read(sc, SP_MISC_INFO) & ~MODE2); 530 if (!(ad_read(sc, SP_MISC_INFO) & MODE2)) 531 sc->mode = 1; 532 } 533 /* ...and additional CS4231 stuff too */ 534 if (sc->mode == 2) { 535 ad_write(sc, SP_INTERFACE_CONFIG, 0); /* disable SINGLE_DMA */ 536 for (i = 0x10; i < 0x20; i++) { 537 if (ad1848_init_values[i] != 0) { 538 ad_write(sc, i, ad1848_init_values[i]); 539 timeout = AD1848_TIMO; 540 while (timeout > 0 && 541 ADREAD(sc, AD1848_IADDR) & SP_IN_INIT) 542 timeout--; 543 } 544 } 545 } 546 ad1848_reset(sc); 547 548 pparams = ad1848_audio_default; 549 rparams = ad1848_audio_default; 550 (void) ad1848_set_params(sc, AUMODE_RECORD|AUMODE_PLAY, 0, 551 &pparams, &rparams); 552 553 /* Set default gains */ 554 (void) ad1848_set_rec_gain(sc, &vol_mid); 555 (void) ad1848_set_channel_gain(sc, AD1848_DAC_CHANNEL, &vol_mid); 556 (void) ad1848_set_channel_gain(sc, AD1848_MONITOR_CHANNEL, &vol_0); 557 /* CD volume */ 558 (void) ad1848_set_channel_gain(sc, AD1848_AUX1_CHANNEL, &vol_mid); 559 if (sc->mode == 2) { 560 /* CD volume */ 561 (void) ad1848_set_channel_gain(sc, AD1848_AUX2_CHANNEL, &vol_mid); 562 (void) ad1848_set_channel_gain(sc, AD1848_LINE_CHANNEL, &vol_mid); 563 (void) ad1848_set_channel_gain(sc, AD1848_MONO_CHANNEL, &vol_0); 564 sc->mute[AD1848_MONO_CHANNEL] = MUTE_ALL; 565 } else 566 (void) ad1848_set_channel_gain(sc, AD1848_AUX2_CHANNEL, &vol_0); 567 568 /* Set default port */ 569 (void) ad1848_set_rec_port(sc, MIC_IN_PORT); 570 571 if (sc->chip_name) 572 printf(": %s", sc->chip_name); 573} 574 575/* 576 * Various routines to interface to higher level audio driver 577 */ 578struct ad1848_mixerinfo { 579 int left_reg; 580 int right_reg; 581 int atten_bits; 582 int atten_mask; 583} mixer_channel_info[] = { 584 { SP_LEFT_AUX2_CONTROL, SP_RIGHT_AUX2_CONTROL, AUX_INPUT_ATTEN_BITS, 585 AUX_INPUT_ATTEN_MASK }, 586 { SP_LEFT_AUX1_CONTROL, SP_RIGHT_AUX1_CONTROL, AUX_INPUT_ATTEN_BITS, 587 AUX_INPUT_ATTEN_MASK }, 588 { SP_LEFT_OUTPUT_CONTROL, SP_RIGHT_OUTPUT_CONTROL, OUTPUT_ATTEN_BITS, 589 OUTPUT_ATTEN_MASK }, 590 { CS_LEFT_LINE_CONTROL, CS_RIGHT_LINE_CONTROL, LINE_INPUT_ATTEN_BITS, 591 LINE_INPUT_ATTEN_MASK }, 592 { CS_MONO_IO_CONTROL, 0, MONO_INPUT_ATTEN_BITS, MONO_INPUT_ATTEN_MASK }, 593 { SP_DIGITAL_MIX, 0, OUTPUT_ATTEN_BITS, MIX_ATTEN_MASK } 594}; 595 596/* 597 * This function doesn't set the mute flags but does use them. 598 * The mute flags reflect the mutes that have been applied by the user. 599 * However, the driver occasionally wants to mute devices (e.g. when changing 600 * sampling rate). These operations should not affect the mute flags. 601 */ 602void 603ad1848_mute_channel(struct ad1848_softc *sc, int device, int mute) 604{ 605 u_char reg; 606 607 reg = ad_read(sc, mixer_channel_info[device].left_reg); 608 609 if (mute & MUTE_LEFT) { 610 if (device == AD1848_MONITOR_CHANNEL) { 611 ad_write(sc, mixer_channel_info[device].left_reg, 612 reg & 0xFE); 613 } else { 614 ad_write(sc, mixer_channel_info[device].left_reg, 615 reg | 0x80); 616 } 617 } else if (!(sc->mute[device] & MUTE_LEFT)) { 618 if (device == AD1848_MONITOR_CHANNEL) { 619 ad_write(sc, mixer_channel_info[device].left_reg, 620 reg | 0x01); 621 } else { 622 ad_write(sc, mixer_channel_info[device].left_reg, 623 reg & ~0x80); 624 } 625 } 626 627 if (!mixer_channel_info[device].right_reg) { 628 return; 629 } 630 631 reg = ad_read(sc, mixer_channel_info[device].right_reg); 632 633 if (mute & MUTE_RIGHT) { 634 ad_write(sc, mixer_channel_info[device].right_reg, reg | 0x80); 635 } else if (!(sc->mute[device] & MUTE_RIGHT)) { 636 ad_write(sc, mixer_channel_info[device].right_reg, reg & ~0x80); 637 } 638} 639 640int 641ad1848_set_channel_gain(struct ad1848_softc *sc, int device, 642 struct ad1848_volume *gp) 643{ 644 struct ad1848_mixerinfo *info = &mixer_channel_info[device]; 645 u_char reg; 646 u_int atten; 647 648 sc->gains[device] = *gp; 649 650 atten = ((AUDIO_MAX_GAIN - gp->left) * info->atten_bits) / 651 AUDIO_MAX_GAIN; 652 653 reg = ad_read(sc, info->left_reg) & (info->atten_mask); 654 if (device == AD1848_MONITOR_CHANNEL) 655 reg |= ((atten & info->atten_bits) << 2); 656 else 657 reg |= ((atten & info->atten_bits)); 658 659 ad_write(sc, info->left_reg, reg); 660 661 if (!info->right_reg) 662 return 0; 663 664 atten = ((AUDIO_MAX_GAIN - gp->right) * info->atten_bits) / 665 AUDIO_MAX_GAIN; 666 reg = ad_read(sc, info->right_reg); 667 reg &= (info->atten_mask); 668 ad_write(sc, info->right_reg, (atten & info->atten_bits) | reg); 669 670 return 0; 671} 672 673int 674ad1848_get_device_gain(struct ad1848_softc *sc, int device, 675 struct ad1848_volume *gp) 676{ 677 *gp = sc->gains[device]; 678 return 0; 679} 680 681int 682ad1848_get_rec_gain(struct ad1848_softc *sc, struct ad1848_volume *gp) 683{ 684 *gp = sc->rec_gain; 685 return 0; 686} 687 688int 689ad1848_set_rec_gain(struct ad1848_softc *sc, struct ad1848_volume *gp) 690{ 691 u_char reg, gain; 692 693 DPRINTF(("ad1848_set_rec_gain: %d:%d\n", gp->left, gp->right)); 694 695 sc->rec_gain = *gp; 696 697 gain = (gp->left * GAIN_22_5) / AUDIO_MAX_GAIN; 698 reg = ad_read(sc, SP_LEFT_INPUT_CONTROL); 699 reg &= INPUT_GAIN_MASK; 700 ad_write(sc, SP_LEFT_INPUT_CONTROL, (gain & 0x0f) | reg); 701 702 gain = (gp->right * GAIN_22_5) / AUDIO_MAX_GAIN; 703 reg = ad_read(sc, SP_RIGHT_INPUT_CONTROL); 704 reg &= INPUT_GAIN_MASK; 705 ad_write(sc, SP_RIGHT_INPUT_CONTROL, (gain & 0x0f) | reg); 706 707 return 0; 708} 709 710void 711ad1848_mute_monitor(void *addr, int mute) 712{ 713 struct ad1848_softc *sc = addr; 714 715 DPRINTF(("ad1848_mute_monitor: %smuting\n", mute ? "" : "un")); 716 if (sc->mode == 2) { 717 ad1848_mute_channel(sc, AD1848_DAC_CHANNEL, 718 mute ? MUTE_ALL : 0); 719 ad1848_mute_channel(sc, AD1848_MONO_CHANNEL, 720 mute ? MUTE_MONO : 0); 721 ad1848_mute_channel(sc, AD1848_LINE_CHANNEL, 722 mute ? MUTE_ALL : 0); 723 } 724 725 ad1848_mute_channel(sc, AD1848_AUX2_CHANNEL, mute ? MUTE_ALL : 0); 726 ad1848_mute_channel(sc, AD1848_AUX1_CHANNEL, mute ? MUTE_ALL : 0); 727} 728 729int 730ad1848_set_mic_gain(struct ad1848_softc *sc, struct ad1848_volume *gp) 731{ 732 u_char reg; 733 734 DPRINTF(("cs4231_set_mic_gain: %d\n", gp->left)); 735 736 if (gp->left > AUDIO_MAX_GAIN / 2) { 737 sc->mic_gain_on = 1; 738 reg = ad_read(sc, SP_LEFT_INPUT_CONTROL); 739 ad_write(sc, SP_LEFT_INPUT_CONTROL, 740 reg | INPUT_MIC_GAIN_ENABLE); 741 } else { 742 sc->mic_gain_on = 0; 743 reg = ad_read(sc, SP_LEFT_INPUT_CONTROL); 744 ad_write(sc, SP_LEFT_INPUT_CONTROL, 745 reg & ~INPUT_MIC_GAIN_ENABLE); 746 } 747 748 return 0; 749} 750 751int 752ad1848_get_mic_gain(struct ad1848_softc *sc, struct ad1848_volume *gp) 753{ 754 if (sc->mic_gain_on) 755 gp->left = gp->right = AUDIO_MAX_GAIN; 756 else 757 gp->left = gp->right = AUDIO_MIN_GAIN; 758 759 return 0; 760} 761 762 763static ad1848_devmap_t *ad1848_mixer_find_dev(ad1848_devmap_t *, int, mixer_ctrl_t *); 764 765static ad1848_devmap_t * 766ad1848_mixer_find_dev(ad1848_devmap_t *map, int cnt, mixer_ctrl_t *cp) 767{ 768 int idx; 769 770 for (idx = 0; idx < cnt; idx++) { 771 if (map[idx].id == cp->dev) { 772 return &map[idx]; 773 } 774 } 775 return NULL; 776} 777 778int 779ad1848_mixer_get_port(struct ad1848_softc *ac, struct ad1848_devmap *map, 780 int cnt, mixer_ctrl_t *cp) 781{ 782 ad1848_devmap_t *entry; 783 struct ad1848_volume vol; 784 int error = EINVAL; 785 int dev; 786 787 if (!(entry = ad1848_mixer_find_dev(map, cnt, cp))) 788 return (ENXIO); 789 790 dev = entry->dev; 791 mtx_enter(&audio_lock); 792 switch (entry->kind) { 793 case AD1848_KIND_LVL: 794 if (cp->type != AUDIO_MIXER_VALUE) 795 break; 796 if (dev < AD1848_AUX2_CHANNEL || 797 dev > AD1848_MONITOR_CHANNEL) 798 break; 799 if (cp->un.value.num_channels != 1 && 800 mixer_channel_info[dev].right_reg == 0) 801 break; 802 error = ad1848_get_device_gain(ac, dev, &vol); 803 if (!error) 804 ad1848_from_vol(cp, &vol); 805 break; 806 807 case AD1848_KIND_MUTE: 808 if (cp->type != AUDIO_MIXER_ENUM) 809 break; 810 cp->un.ord = ac->mute[dev] ? 1 : 0; 811 error = 0; 812 break; 813 814 case AD1848_KIND_RECORDGAIN: 815 if (cp->type != AUDIO_MIXER_VALUE) 816 break; 817 error = ad1848_get_rec_gain(ac, &vol); 818 if (!error) 819 ad1848_from_vol(cp, &vol); 820 break; 821 822 case AD1848_KIND_MICGAIN: 823 if (cp->type != AUDIO_MIXER_VALUE) 824 break; 825 error = ad1848_get_mic_gain(ac, &vol); 826 if (!error) 827 ad1848_from_vol(cp, &vol); 828 break; 829 830 case AD1848_KIND_RECORDSOURCE: 831 if (cp->type != AUDIO_MIXER_ENUM) 832 break; 833 cp->un.ord = ad1848_get_rec_port(ac); 834 error = 0; 835 break; 836 837 default: 838 printf("Invalid kind\n"); 839 break; 840 } 841 mtx_leave(&audio_lock); 842 return error; 843} 844 845int 846ad1848_mixer_set_port(struct ad1848_softc *ac, struct ad1848_devmap *map, 847 int cnt, mixer_ctrl_t *cp) 848{ 849 ad1848_devmap_t *entry; 850 struct ad1848_volume vol; 851 int error = EINVAL; 852 int dev; 853 854 if (!(entry = ad1848_mixer_find_dev(map, cnt, cp))) 855 return (ENXIO); 856 857 dev = entry->dev; 858 mtx_enter(&audio_lock); 859 switch (entry->kind) { 860 case AD1848_KIND_LVL: 861 if (cp->type != AUDIO_MIXER_VALUE) 862 break; 863 if (dev < AD1848_AUX2_CHANNEL || 864 dev > AD1848_MONITOR_CHANNEL) 865 break; 866 if (cp->un.value.num_channels != 1 && 867 mixer_channel_info[dev].right_reg == 0) 868 break; 869 ad1848_to_vol(cp, &vol); 870 error = ad1848_set_channel_gain(ac, dev, &vol); 871 break; 872 873 case AD1848_KIND_MUTE: 874 if (cp->type != AUDIO_MIXER_ENUM) 875 break; 876 ac->mute[dev] = (cp->un.ord ? MUTE_ALL : 0); 877 ad1848_mute_channel(ac, dev, ac->mute[dev]); 878 error = 0; 879 break; 880 881 case AD1848_KIND_RECORDGAIN: 882 if (cp->type != AUDIO_MIXER_VALUE) 883 break; 884 ad1848_to_vol(cp, &vol); 885 error = ad1848_set_rec_gain(ac, &vol); 886 break; 887 888 case AD1848_KIND_MICGAIN: 889 if (cp->type != AUDIO_MIXER_VALUE) 890 break; 891 ad1848_to_vol(cp, &vol); 892 error = ad1848_set_mic_gain(ac, &vol); 893 break; 894 895 case AD1848_KIND_RECORDSOURCE: 896 if (cp->type != AUDIO_MIXER_ENUM) 897 break; 898 error = ad1848_set_rec_port(ac, cp->un.ord); 899 break; 900 901 default: 902 printf("Invalid kind\n"); 903 break; 904 } 905 mtx_leave(&audio_lock); 906 return (error); 907} 908 909int 910ad1848_set_params(void *addr, int setmode, int usemode, struct audio_params *p, 911 struct audio_params *r) 912{ 913 struct ad1848_softc *sc = addr; 914 int error, bits, enc; 915 916 DPRINTF(("ad1848_set_params: %d %d %d %ld\n", 917 p->encoding, p->precision, p->channels, p->sample_rate)); 918 919 enc = p->encoding; 920 switch (enc) { 921 case AUDIO_ENCODING_SLINEAR_LE: 922 if (p->precision == 8) 923 return EINVAL; 924 break; 925 case AUDIO_ENCODING_SLINEAR_BE: 926 if (p->precision == 16) 927 return EINVAL; 928 break; 929 case AUDIO_ENCODING_ULINEAR_LE: 930 if (p->precision == 16) 931 return EINVAL; 932 break; 933 case AUDIO_ENCODING_ULINEAR_BE: 934 if (p->precision == 16) 935 return EINVAL; 936 break; 937 } 938 switch (enc) { 939 case AUDIO_ENCODING_ULAW: 940 p->precision = 8; 941 bits = FMT_ULAW; 942 break; 943 case AUDIO_ENCODING_ALAW: 944 p->precision = 8; 945 bits = FMT_ALAW; 946 break; 947 case AUDIO_ENCODING_SLINEAR_LE: 948 if (p->precision == 16) 949 bits = FMT_TWOS_COMP; 950 else 951 return EINVAL; 952 break; 953 case AUDIO_ENCODING_SLINEAR_BE: 954 if (p->precision == 16) 955 bits = FMT_TWOS_COMP_BE; 956 else 957 return EINVAL; 958 break; 959 case AUDIO_ENCODING_ULINEAR_LE: 960 if (p->precision == 8) 961 bits = FMT_PCM8; 962 else 963 return EINVAL; 964 break; 965 default: 966 return EINVAL; 967 } 968 969 if (p->channels < 1 || p->channels > 2) 970 return EINVAL; 971 972 error = ad1848_set_speed(sc, &p->sample_rate); 973 if (error) 974 return error; 975 976 p->bps = AUDIO_BPS(p->precision); 977 r->bps = AUDIO_BPS(r->precision); 978 p->msb = 1; 979 r->msb = 1; 980 981 sc->format_bits = bits; 982 sc->channels = p->channels; 983 sc->precision = p->precision; 984 sc->need_commit = 1; 985 986 DPRINTF(("ad1848_set_params succeeded, bits=%x\n", bits)); 987 return (0); 988} 989 990int 991ad1848_set_rec_port(struct ad1848_softc *sc, int port) 992{ 993 u_char inp, reg; 994 995 DPRINTF(("ad1848_set_rec_port: 0x%x\n", port)); 996 997 if (port == MIC_IN_PORT) { 998 inp = MIC_INPUT; 999 } else if (port == LINE_IN_PORT) { 1000 inp = LINE_INPUT; 1001 } else if (port == DAC_IN_PORT) { 1002 inp = MIXED_DAC_INPUT; 1003 } else if (sc->mode == 2 && port == AUX1_IN_PORT) { 1004 inp = AUX_INPUT; 1005 } else 1006 return EINVAL; 1007 1008 reg = ad_read(sc, SP_LEFT_INPUT_CONTROL); 1009 reg &= INPUT_SOURCE_MASK; 1010 ad_write(sc, SP_LEFT_INPUT_CONTROL, (inp | reg)); 1011 1012 reg = ad_read(sc, SP_RIGHT_INPUT_CONTROL); 1013 reg &= INPUT_SOURCE_MASK; 1014 ad_write(sc, SP_RIGHT_INPUT_CONTROL, (inp | reg)); 1015 1016 sc->rec_port = port; 1017 1018 return 0; 1019} 1020 1021int 1022ad1848_get_rec_port(struct ad1848_softc *sc) 1023{ 1024 return sc->rec_port; 1025} 1026 1027int 1028ad1848_round_blocksize(void *addr, int blk) 1029{ 1030 /* Round to a multiple of the biggest sample size. */ 1031 blk = (blk + 3) & -4; 1032 1033 return blk; 1034} 1035 1036int 1037ad1848_open(void *addr, int flags) 1038{ 1039 struct ad1848_softc *sc = addr; 1040 1041 DPRINTF(("ad1848_open: sc=%p\n", sc)); 1042 1043 if ((flags & (FWRITE | FREAD)) == (FWRITE | FREAD) && sc->mode != 2) 1044 return ENXIO; 1045 1046 sc->sc_pintr = sc->sc_parg = NULL; 1047 sc->sc_rintr = sc->sc_rarg = NULL; 1048 1049 /* Enable interrupts */ 1050 DPRINTF(("ad1848_open: enable intrs\n")); 1051 ad_write(sc, SP_PIN_CONTROL, 1052 INTERRUPT_ENABLE | ad_read(sc, SP_PIN_CONTROL)); 1053 1054#ifdef AUDIO_DEBUG 1055 if (ad1848debug > 2) 1056 ad1848_dump_regs(sc); 1057#endif 1058 1059 return 0; 1060} 1061 1062/* 1063 * Close function is called at splaudio(). 1064 */ 1065void 1066ad1848_close(void *addr) 1067{ 1068 struct ad1848_softc *sc = addr; 1069 u_char r; 1070 1071 ad1848_halt_output(sc); 1072 ad1848_halt_input(sc); 1073 1074 sc->sc_pintr = NULL; 1075 sc->sc_rintr = NULL; 1076 1077 DPRINTF(("ad1848_close: stop DMA\n")); 1078 1079 ad_write(sc, SP_LOWER_BASE_COUNT, (u_char)0); 1080 ad_write(sc, SP_UPPER_BASE_COUNT, (u_char)0); 1081 1082 /* Disable interrupts */ 1083 DPRINTF(("ad1848_close: disable intrs\n")); 1084 ad_write(sc, SP_PIN_CONTROL, 1085 ad_read(sc, SP_PIN_CONTROL) & ~INTERRUPT_ENABLE); 1086 1087 DPRINTF(("ad1848_close: disable capture and playback\n")); 1088 r = ad_read(sc, SP_INTERFACE_CONFIG); 1089 r &= ~(CAPTURE_ENABLE | PLAYBACK_ENABLE); 1090 ad_write(sc, SP_INTERFACE_CONFIG, r); 1091 1092#ifdef AUDIO_DEBUG 1093 if (ad1848debug > 2) 1094 ad1848_dump_regs(sc); 1095#endif 1096} 1097 1098/* 1099 * Lower-level routines 1100 */ 1101int 1102ad1848_commit_settings(void *addr) 1103{ 1104 struct ad1848_softc *sc = addr; 1105 int timeout; 1106 u_char fs; 1107 1108 if (!sc->need_commit) 1109 return 0; 1110 1111 mtx_enter(&audio_lock); 1112 1113 ad1848_mute_monitor(sc, 1); 1114 1115 /* Enables changes to the format select reg */ 1116 ad_set_MCE(sc, 1); 1117 1118 fs = sc->speed_bits | sc->format_bits; 1119 1120 if (sc->channels == 2) 1121 fs |= FMT_STEREO; 1122 1123 ad_write(sc, SP_CLOCK_DATA_FORMAT, fs); 1124 1125 /* 1126 * If mode == 2 (CS4231), set I28 also. It's the capture format 1127 * register. 1128 */ 1129 if (sc->mode == 2) { 1130 /* Gravis Ultrasound MAX SDK sources says something about 1131 * errata sheets, with the implication that these inb()s 1132 * are necessary. 1133 */ 1134 (void)ADREAD(sc, AD1848_IDATA); 1135 (void)ADREAD(sc, AD1848_IDATA); 1136 1137 /* 1138 * Write to I8 starts resynchronization. Wait until it 1139 * completes. 1140 */ 1141 timeout = AD1848_TIMO; 1142 while (timeout > 0 && ADREAD(sc, AD1848_IADDR) == SP_IN_INIT) 1143 timeout--; 1144 1145 ad_write(sc, CS_REC_FORMAT, fs); 1146 /* Gravis Ultrasound MAX SDK sources says something about 1147 * errata sheets, with the implication that these inb()s 1148 * are necessary. 1149 */ 1150 (void)ADREAD(sc, AD1848_IDATA); 1151 (void)ADREAD(sc, AD1848_IDATA); 1152 /* Now wait for resync for capture side of the house */ 1153 } 1154 /* 1155 * Write to I8 starts resynchronization. Wait until it completes. 1156 */ 1157 timeout = AD1848_TIMO; 1158 while (timeout > 0 && ADREAD(sc, AD1848_IADDR) == SP_IN_INIT) 1159 timeout--; 1160 1161 if (ADREAD(sc, AD1848_IADDR) == SP_IN_INIT) 1162 printf("ad1848_commit: Auto calibration timed out\n"); 1163 1164 /* 1165 * Starts the calibration process and enters playback mode after it. 1166 */ 1167 ad_set_MCE(sc, 0); 1168 wait_for_calibration(sc); 1169 1170 ad1848_mute_monitor(sc, 0); 1171 1172 mtx_leave(&audio_lock); 1173 1174 sc->need_commit = 0; 1175 1176 return 0; 1177} 1178 1179void 1180ad1848_reset(struct ad1848_softc *sc) 1181{ 1182 u_char r; 1183 1184 DPRINTF(("ad1848_reset\n")); 1185 1186 /* Clear the PEN and CEN bits */ 1187 r = ad_read(sc, SP_INTERFACE_CONFIG); 1188 r &= ~(CAPTURE_ENABLE | PLAYBACK_ENABLE); 1189 ad_write(sc, SP_INTERFACE_CONFIG, r); 1190 1191 /* Clear interrupt status */ 1192 if (sc->mode == 2) 1193 ad_write(sc, CS_IRQ_STATUS, 0); 1194 ADWRITE(sc, AD1848_STATUS, 0); 1195 1196#ifdef AUDIO_DEBUG 1197 if (ad1848debug > 2) 1198 ad1848_dump_regs(sc); 1199#endif 1200} 1201 1202int 1203ad1848_set_speed(struct ad1848_softc *sc, u_long *argp) 1204{ 1205 /* 1206 * The sampling speed is encoded in the least significant nible of I8. 1207 * The LSB selects the clock source (0=24.576 MHz, 1=16.9344 MHz) and 1208 * other three bits select the divisor (indirectly): 1209 * 1210 * The available speeds are in the following table. Keep the speeds in 1211 * the increasing order. 1212 */ 1213 typedef struct { 1214 int speed; 1215 u_char bits; 1216 } speed_struct; 1217 u_long arg = *argp; 1218 1219 static speed_struct speed_table[] = { 1220 {5510, (0 << 1) | 1}, 1221 {5510, (0 << 1) | 1}, 1222 {6620, (7 << 1) | 1}, 1223 {8000, (0 << 1) | 0}, 1224 {9600, (7 << 1) | 0}, 1225 {11025, (1 << 1) | 1}, 1226 {16000, (1 << 1) | 0}, 1227 {18900, (2 << 1) | 1}, 1228 {22050, (3 << 1) | 1}, 1229 {27420, (2 << 1) | 0}, 1230 {32000, (3 << 1) | 0}, 1231 {33075, (6 << 1) | 1}, 1232 {37800, (4 << 1) | 1}, 1233 {44100, (5 << 1) | 1}, 1234 {48000, (6 << 1) | 0} 1235 }; 1236 1237 int i, n, selected = -1; 1238 1239 n = sizeof(speed_table) / sizeof(speed_struct); 1240 1241 if (arg < speed_table[0].speed) 1242 selected = 0; 1243 if (arg > speed_table[n - 1].speed) 1244 selected = n - 1; 1245 1246 for (i = 1 /*really*/ ; selected == -1 && i < n; i++) { 1247 if (speed_table[i].speed == arg) 1248 selected = i; 1249 else if (speed_table[i].speed > arg) { 1250 int diff1, diff2; 1251 1252 diff1 = arg - speed_table[i - 1].speed; 1253 diff2 = speed_table[i].speed - arg; 1254 1255 if (diff1 < diff2) 1256 selected = i - 1; 1257 else 1258 selected = i; 1259 } 1260 } 1261 1262 if (selected == -1) { 1263 printf("ad1848: Can't find speed???\n"); 1264 selected = 3; 1265 } 1266 1267 sc->speed_bits = speed_table[selected].bits; 1268 sc->need_commit = 1; 1269 *argp = speed_table[selected].speed; 1270 1271 return 0; 1272} 1273 1274/* 1275 * Halt a DMA in progress. 1276 */ 1277int 1278ad1848_halt_output(void *addr) 1279{ 1280 struct ad1848_softc *sc = addr; 1281 u_char reg; 1282 1283 DPRINTF(("ad1848: ad1848_halt_output\n")); 1284 mtx_enter(&audio_lock); 1285 reg = ad_read(sc, SP_INTERFACE_CONFIG); 1286 ad_write(sc, SP_INTERFACE_CONFIG, (reg & ~PLAYBACK_ENABLE)); 1287 1288 if (sc->sc_playrun == 1) { 1289 isa_dmaabort(sc->sc_isa, sc->sc_drq); 1290 sc->sc_playrun = 0; 1291 } 1292 mtx_leave(&audio_lock); 1293 return 0; 1294} 1295 1296int 1297ad1848_halt_input(void *addr) 1298{ 1299 struct ad1848_softc *sc = addr; 1300 u_char reg; 1301 1302 DPRINTF(("ad1848: ad1848_halt_input\n")); 1303 mtx_enter(&audio_lock); 1304 reg = ad_read(sc, SP_INTERFACE_CONFIG); 1305 ad_write(sc, SP_INTERFACE_CONFIG, (reg & ~CAPTURE_ENABLE)); 1306 1307 if (sc->sc_recrun == 1) { 1308 isa_dmaabort(sc->sc_isa, sc->sc_recdrq); 1309 sc->sc_recrun = 0; 1310 } 1311 mtx_leave(&audio_lock); 1312 return 0; 1313} 1314 1315int 1316ad1848_trigger_input(void *addr, void *start, void *end, int blksize, 1317 void (*intr)(void *), void *arg, struct audio_params *param) 1318{ 1319 struct ad1848_softc *sc = addr; 1320 u_char reg; 1321 1322 if (sc->sc_recdrq == -1) { 1323 DPRINTF(("ad1848_trigger_input: invalid recording drq\n")); 1324 return ENXIO; 1325 } 1326 mtx_enter(&audio_lock); 1327 isa_dmastart(sc->sc_isa, sc->sc_recdrq, start, 1328 (char *)end - (char *)start, NULL, DMAMODE_READ | DMAMODE_LOOP, 1329 BUS_DMA_NOWAIT); 1330 1331 sc->sc_recrun = 1; 1332 sc->sc_rintr = intr; 1333 sc->sc_rarg = arg; 1334 1335 blksize = (blksize * NBBY) / (param->precision * param->channels) - 1; 1336 1337 if (sc->mode == 2) { 1338 ad_write(sc, CS_LOWER_REC_CNT, (blksize & 0xff)); 1339 ad_write(sc, CS_UPPER_REC_CNT, ((blksize >> 8) & 0xff)); 1340 } else { 1341 ad_write(sc, SP_LOWER_BASE_COUNT, blksize & 0xff); 1342 ad_write(sc, SP_UPPER_BASE_COUNT, (blksize >> 8) & 0xff); 1343 } 1344 1345 reg = ad_read(sc, SP_INTERFACE_CONFIG); 1346 ad_write(sc, SP_INTERFACE_CONFIG, (CAPTURE_ENABLE | reg)); 1347 1348#ifdef AUDIO_DEBUG 1349 if (ad1848debug > 1) 1350 printf("ad1848_trigger_input: started capture\n"); 1351#endif 1352 mtx_leave(&audio_lock); 1353 return 0; 1354} 1355 1356int 1357ad1848_trigger_output(void *addr, void *start, void *end, int blksize, 1358 void (*intr)(void *), void *arg, struct audio_params *param) 1359{ 1360 struct ad1848_softc *sc = addr; 1361 u_char reg; 1362 1363 mtx_enter(&audio_lock); 1364 isa_dmastart(sc->sc_isa, sc->sc_drq, start, 1365 (char *)end - (char *)start, NULL, 1366 DMAMODE_WRITE | DMAMODE_LOOP, BUS_DMA_NOWAIT); 1367 1368 sc->sc_playrun = 1; 1369 sc->sc_pintr = intr; 1370 sc->sc_parg = arg; 1371 1372 blksize = (blksize * NBBY) / (param->precision * param->channels) - 1; 1373 1374 ad_write(sc, SP_LOWER_BASE_COUNT, blksize & 0xff); 1375 ad_write(sc, SP_UPPER_BASE_COUNT, (blksize >> 8) & 0xff); 1376 1377 reg = ad_read(sc, SP_INTERFACE_CONFIG); 1378 ad_write(sc, SP_INTERFACE_CONFIG, (PLAYBACK_ENABLE | reg)); 1379 1380#ifdef AUDIO_DEBUG 1381 if (ad1848debug > 1) 1382 printf("ad1848_trigger_output: started playback\n"); 1383#endif 1384 mtx_leave(&audio_lock); 1385 return 0; 1386} 1387 1388int 1389ad1848_intr(void *arg) 1390{ 1391 struct ad1848_softc *sc = arg; 1392 int retval = 0; 1393 u_char status; 1394 1395 mtx_enter(&audio_lock); 1396 /* Get intr status */ 1397 status = ADREAD(sc, AD1848_STATUS); 1398 1399#ifdef AUDIO_DEBUG 1400 if (ad1848debug > 1) 1401 printf("ad1848_intr: mode=%d pintr=%p prun=%d rintr=%p rrun=%d status=0x%x\n", 1402 sc->mode, sc->sc_pintr, sc->sc_playrun, sc->sc_rintr, sc->sc_recrun, status); 1403#endif 1404 1405 /* Handle interrupt */ 1406 if ((status & INTERRUPT_STATUS) != 0) { 1407 if (sc->mode == 2) { 1408 status = ad_read(sc, CS_IRQ_STATUS); 1409#ifdef AUDIO_DEBUG 1410 if (ad1848debug > 2) 1411 printf("ad1848_intr: cs_irq_status=0x%x (play=0x%x rec0x%x)\n", 1412 status, CS_IRQ_PI, CS_IRQ_CI); 1413#endif 1414 if ((status & CS_IRQ_PI) && sc->sc_playrun) { 1415 (*sc->sc_pintr)(sc->sc_parg); 1416 retval = 1; 1417 } 1418 if ((status & CS_IRQ_CI) && sc->sc_recrun) { 1419 (*sc->sc_rintr)(sc->sc_rarg); 1420 retval = 1; 1421 } 1422 } else { 1423 if (sc->sc_playrun) { 1424 (*sc->sc_pintr)(sc->sc_parg); 1425 retval = 1; 1426 } else if (sc->sc_recrun) { 1427 (*sc->sc_rintr)(sc->sc_rarg); 1428 retval = 1; 1429 } 1430 } 1431 /* clear interrupt */ 1432 ADWRITE(sc, AD1848_STATUS, 0); 1433 } 1434 mtx_leave(&audio_lock); 1435 return(retval); 1436} 1437 1438void * 1439ad1848_malloc(void *addr, int direction, size_t size, int pool, int flags) 1440{ 1441 struct ad1848_softc *sc = addr; 1442 int drq; 1443 1444 if (direction == AUMODE_PLAY) 1445 drq = sc->sc_drq; 1446 else 1447 drq = sc->sc_recdrq; 1448 1449 return isa_malloc(sc->sc_isa, drq, size, pool, flags); 1450} 1451 1452void 1453ad1848_free(void *addr, void *ptr, int pool) 1454{ 1455 isa_free(ptr, pool); 1456} 1457 1458size_t 1459ad1848_round(void *addr, int direction, size_t size) 1460{ 1461 if (size > MAX_ISADMA) 1462 size = MAX_ISADMA; 1463 return size; 1464} 1465