1/*	$OpenBSD: qlwvar.h,v 1.11 2020/07/22 13:16:04 krw Exp $ */
2
3/*
4 * Copyright (c) 2013, 2014 Jonathan Matthew <jmatthew@openbsd.org>
5 * Copyright (c) 2014 Mark Kettenis <kettenis@openbsd.org>
6 *
7 * Permission to use, copy, modify, and distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20#include <sys/task.h>
21
22#define QLW_MAX_TARGETS			16
23#define QLW_MAX_LUNS			8
24
25/* maximum number of segments allowed for in a single io */
26#define QLW_MAX_SEGS			16
27
28struct qlw_softc;
29
30enum qlw_isp_gen {
31	QLW_GEN_ISP1000 = 1,
32	QLW_GEN_ISP1040,
33	QLW_GEN_ISP1080,
34	QLW_GEN_ISP12160,
35};
36
37enum qlw_isp_type {
38	QLW_ISP1000 = 1,
39	QLW_ISP1020,
40	QLW_ISP1020A,
41	QLW_ISP1040,
42	QLW_ISP1040A,
43	QLW_ISP1040B,
44	QLW_ISP1040C,
45	QLW_ISP1240,
46	QLW_ISP1080,
47	QLW_ISP1280,
48	QLW_ISP10160,
49	QLW_ISP12160,
50};
51
52/* request/response queue stuff */
53#define QLW_QUEUE_ENTRY_SIZE		64
54
55struct qlw_ccb {
56	struct qlw_softc 	*ccb_sc;
57	int			ccb_id;
58	struct scsi_xfer	*ccb_xs;
59
60	bus_dmamap_t		ccb_dmamap;
61
62	SIMPLEQ_ENTRY(qlw_ccb)	ccb_link;
63};
64
65SIMPLEQ_HEAD(qlw_ccb_list, qlw_ccb);
66
67struct qlw_dmamem {
68	bus_dmamap_t		qdm_map;
69	bus_dma_segment_t	qdm_seg;
70	size_t			qdm_size;
71	caddr_t			qdm_kva;
72};
73#define QLW_DMA_MAP(_qdm)	((_qdm)->qdm_map)
74#define QLW_DMA_LEN(_qdm)	((_qdm)->qdm_size)
75#define QLW_DMA_DVA(_qdm)	((u_int64_t)(_qdm)->qdm_map->dm_segs[0].ds_addr)
76#define QLW_DMA_KVA(_qdm)	((void *)(_qdm)->qdm_kva)
77
78struct qlw_target {
79	u_int16_t		qt_params;
80	u_int8_t		qt_exec_throttle;
81	u_int8_t		qt_sync_period;
82	u_int8_t		qt_sync_offset;
83};
84
85struct qlw_softc {
86	struct device		sc_dev;
87
88	int			sc_flags;
89#define QLW_FLAG_INITIATOR	0x0001
90
91	bus_space_tag_t		sc_iot;
92	bus_space_handle_t	sc_ioh;
93	bus_size_t		sc_ios;
94	bus_dma_tag_t		sc_dmat;
95
96	struct scsibus_softc	*sc_scsibus[2];
97	int			sc_running;
98
99	enum qlw_isp_type	sc_isp_type;
100	enum qlw_isp_gen	sc_isp_gen;
101	const u_int16_t		*sc_firmware;
102	int			sc_numbusses;
103	int			sc_clock;
104
105	int			sc_host_cmd_ctrl;
106	int			sc_mbox_base;
107	u_int16_t		sc_mbox[8];
108	int			sc_mbox_pending;
109
110	int			sc_maxrequests;
111	struct qlw_dmamem	*sc_requests;
112	int			sc_maxresponses;
113	struct qlw_dmamem	*sc_responses;
114	int			sc_maxccbs;
115	struct qlw_ccb		*sc_ccbs;
116	struct qlw_ccb_list	sc_ccb_free;
117	struct mutex		sc_ccb_mtx;
118	struct mutex		sc_queue_mtx;
119	struct scsi_iopool	sc_iopool;
120	u_int16_t		sc_next_req_id;
121	u_int16_t		sc_last_resp_id;
122	int			sc_marker_required[2];
123	u_int			sc_update_required[2];
124	struct task		sc_update_task;
125
126	struct qlw_nvram	sc_nvram;
127	int			sc_nvram_size;
128	int			sc_nvram_minversion;
129
130	u_int16_t		sc_isp_config;
131	u_int16_t		sc_fw_features;
132
133	u_int8_t		sc_initiator[2];
134	u_int8_t		sc_retry_count[2];
135	u_int8_t		sc_retry_delay[2];
136	u_int8_t		sc_reset_delay[2];
137	u_int8_t		sc_tag_age_limit[2];
138	u_int16_t		sc_selection_timeout[2];
139	u_int16_t		sc_max_queue_depth[2];
140	u_int8_t		sc_async_data_setup[2];
141	u_int8_t		sc_req_ack_active_neg[2];
142	u_int8_t		sc_data_line_active_neg[2];
143	struct qlw_target	sc_target[2][QLW_MAX_TARGETS];
144};
145#define DEVNAME(_sc) ((_sc)->sc_dev.dv_xname)
146
147int	qlw_attach(struct qlw_softc *);
148int	qlw_detach(struct qlw_softc *, int);
149
150int	qlw_intr(void *);
151