1/* $OpenBSD: hmereg.h,v 1.10 2022/01/09 05:42:38 jsg Exp $ */ 2/* $NetBSD: hmereg.h,v 1.8 2001/04/30 12:22:42 bouyer Exp $ */ 3 4/*- 5 * Copyright (c) 1999 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Paul Kranenburg. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* 34 * HME Shared Ethernet Block register offsets 35 */ 36#define HME_SEBI_RESET (0*4) 37#define HME_SEBI_CFG (1*4) 38#define HME_SEBI_STAT (64*4) 39#define HME_SEBI_IMASK (65*4) 40 41/* HME SEB bits. */ 42#define HME_SEB_RESET_ETX 0x00000001 /* reset external transmitter */ 43#define HME_SEB_RESET_ERX 0x00000002 /* reset external receiver */ 44 45#define HME_SEB_CFG_BURSTMASK 0x00000003 /* covers all burst bits */ 46#define HME_SEB_CFG_BURST16 0x00000000 /* 16 byte bursts */ 47#define HME_SEB_CFG_BURST32 0x00000001 /* 32 byte bursts */ 48#define HME_SEB_CFG_BURST64 0x00000002 /* 64 byte bursts */ 49#define HME_SEB_CFG_64BIT 0x00000004 /* ? */ 50#define HME_SEB_CFG_PARITY 0x00000008 /* ? */ 51 52#define HME_SEB_STAT_GOTFRAME 0x00000001 /* frame received */ 53#define HME_SEB_STAT_RCNTEXP 0x00000002 /* rx frame count expired */ 54#define HME_SEB_STAT_ACNTEXP 0x00000004 /* align error count expired */ 55#define HME_SEB_STAT_CCNTEXP 0x00000008 /* crc error count expired */ 56#define HME_SEB_STAT_LCNTEXP 0x00000010 /* length error count expired */ 57#define HME_SEB_STAT_RFIFOVF 0x00000020 /* rx fifo overflow */ 58#define HME_SEB_STAT_CVCNTEXP 0x00000040 /* code violation counter exp */ 59#define HME_SEB_STAT_STSTERR 0x00000080 /* xif sqe test failed */ 60#define HME_SEB_STAT_SENTFRAME 0x00000100 /* frame sent */ 61#define HME_SEB_STAT_TFIFO_UND 0x00000200 /* tx fifo underrun */ 62#define HME_SEB_STAT_MAXPKTERR 0x00000400 /* max-packet size error */ 63#define HME_SEB_STAT_NCNTEXP 0x00000800 /* normal collision count exp */ 64#define HME_SEB_STAT_ECNTEXP 0x00001000 /* excess collision count exp */ 65#define HME_SEB_STAT_LCCNTEXP 0x00002000 /* late collision count exp */ 66#define HME_SEB_STAT_FCNTEXP 0x00004000 /* first collision count exp */ 67#define HME_SEB_STAT_DTIMEXP 0x00008000 /* defer timer expired */ 68#define HME_SEB_STAT_RXTOHOST 0x00010000 /* pkt moved from rx fifo->memory */ 69#define HME_SEB_STAT_NORXD 0x00020000 /* out of receive descriptors */ 70#define HME_SEB_STAT_RXERR 0x00040000 /* rx dma error */ 71#define HME_SEB_STAT_RXLATERR 0x00080000 /* late error during rx dma */ 72#define HME_SEB_STAT_RXPERR 0x00100000 /* parity error during rx dma */ 73#define HME_SEB_STAT_RXTERR 0x00200000 /* tag error during rx dma */ 74#define HME_SEB_STAT_EOPERR 0x00400000 /* tx descriptor did not set EOP */ 75#define HME_SEB_STAT_MIFIRQ 0x00800000 /* mif needs attention */ 76#define HME_SEB_STAT_HOSTTOTX 0x01000000 /* pkt moved from memory->tx fifo */ 77#define HME_SEB_STAT_TXALL 0x02000000 /* all pkts in fifo transmitted */ 78#define HME_SEB_STAT_TXEACK 0x04000000 /* error during tx dma */ 79#define HME_SEB_STAT_TXLERR 0x08000000 /* late error during tx dma */ 80#define HME_SEB_STAT_TXPERR 0x10000000 /* parity error during tx dma */ 81#define HME_SEB_STAT_TXTERR 0x20000000 /* tag error during tx dma */ 82#define HME_SEB_STAT_SLVERR 0x40000000 /* pio access error */ 83#define HME_SEB_STAT_SLVPERR 0x80000000 /* pio access parity error */ 84#define HME_SEB_STAT_BITS \ 85 "\020\1RX\2RCNT\3ACNT\4CCNT\5LCNT\6RFIFO\7CVCNT\10STST" \ 86 "\11TX\12TFIFO\13MAXPKT\14NCNT\15ECNT\16LCCNT\17FCNT" \ 87 "\20DTIME\21RXHOST\22NORXD\23RXE\24EXLATE\25RXP\26RXT\27EOP" \ 88 "\30MIF\31TXHOST\32TXALL\33TXE\34TXL\35TXP\36TXT\37SLV" \ 89 "\40SLVP" 90 91 92#define HME_SEB_STAT_ALL_ERRORS \ 93 (HME_SEB_STAT_SLVPERR | HME_SEB_STAT_SLVERR | HME_SEB_STAT_TXTERR |\ 94 HME_SEB_STAT_TXPERR | HME_SEB_STAT_TXLERR | HME_SEB_STAT_TXEACK |\ 95 HME_SEB_STAT_EOPERR | HME_SEB_STAT_RXTERR | HME_SEB_STAT_RXPERR |\ 96 HME_SEB_STAT_RXLATERR | HME_SEB_STAT_RXERR | HME_SEB_STAT_NORXD |\ 97 HME_SEB_STAT_DTIMEXP | HME_SEB_STAT_FCNTEXP | HME_SEB_STAT_LCCNTEXP |\ 98 HME_SEB_STAT_ECNTEXP | HME_SEB_STAT_NCNTEXP | HME_SEB_STAT_MAXPKTERR|\ 99 HME_SEB_STAT_TFIFO_UND| HME_SEB_STAT_STSTERR | HME_SEB_STAT_CVCNTEXP |\ 100 HME_SEB_STAT_LCNTEXP | HME_SEB_STAT_CCNTEXP| HME_SEB_STAT_ACNTEXP) 101 102#define HME_SEB_STAT_VLAN_ERRORS \ 103 (HME_SEB_STAT_SLVPERR | HME_SEB_STAT_SLVERR | HME_SEB_STAT_TXTERR |\ 104 HME_SEB_STAT_TXPERR | HME_SEB_STAT_TXLERR | HME_SEB_STAT_TXEACK |\ 105 HME_SEB_STAT_EOPERR | HME_SEB_STAT_RXTERR | HME_SEB_STAT_RXPERR |\ 106 HME_SEB_STAT_RXLATERR | HME_SEB_STAT_RXERR | HME_SEB_STAT_NORXD |\ 107 HME_SEB_STAT_DTIMEXP | HME_SEB_STAT_FCNTEXP | HME_SEB_STAT_LCCNTEXP |\ 108 HME_SEB_STAT_ECNTEXP | HME_SEB_STAT_NCNTEXP | \ 109 HME_SEB_STAT_TFIFO_UND| HME_SEB_STAT_STSTERR | HME_SEB_STAT_CVCNTEXP |\ 110 HME_SEB_STAT_LCNTEXP | HME_SEB_STAT_CCNTEXP | HME_SEB_STAT_ACNTEXP) 111 112/* 113 * HME Transmitter register offsets 114 */ 115#define HME_ETXI_PENDING (0*4) /* Pending/wakeup */ 116#define HME_ETXI_CFG (1*4) 117#define HME_ETXI_RING (2*4) /* Descriptor Ring pointer */ 118#define HME_ETXI_BBASE (3*4) /* Buffer base address (ro) */ 119#define HME_ETXI_BDISP (4*4) /* Buffer displacement (ro) */ 120#define HME_ETXI_FIFO_WPTR (5*4) /* FIFO write pointer */ 121#define HME_ETXI_FIFO_SWPTR (6*4) /* FIFO shadow write pointer */ 122#define HME_ETXI_FIFO_RPTR (7*4) /* FIFO read pointer */ 123#define HME_ETXI_FIFO_SRPTR (8*4) /* FIFO shadow read pointer */ 124#define HME_ETXI_FIFO_PKTCNT (9*4) /* FIFO packet counter */ 125#define HME_ETXI_STATEMACHINE (10*4) /* State machine */ 126#define HME_ETXI_RSIZE (11*4) /* Ring size */ 127#define HME_ETXI_BPTR (12*4) /* Buffer pointer */ 128 129 130/* TXI_PENDING bits */ 131#define HME_ETX_TP_DMAWAKEUP 0x00000001 /* Start tx (rw, auto-clear) */ 132 133/* TXI_CFG bits */ 134#define HME_ETX_CFG_DMAENABLE 0x00000001 /* Enable TX dma */ 135#define HME_ETX_CFG_FIFOTHRESH 0x000003fe /* TX fifo threshold */ 136#define HME_ETX_CFG_IRQDAFTER 0x00000400 /* Intr after tx-fifo empty */ 137#define HME_ETX_CFG_IRQDBEFORE 0x00000000 /* Intr before tx-fifo empty */ 138 139 140/* 141 * HME Receiver register offsets 142 */ 143#define HME_ERXI_CFG (0*4) 144#define HME_ERXI_RING (1*4) /* Descriptor Ring pointer */ 145#define HME_ERXI_BPTR (2*4) /* Data Buffer pointer (ro) */ 146#define HME_ERXI_FIFO_WPTR (3*4) /* FIFO write pointer */ 147#define HME_ERXI_FIFO_SWPTR (4*4) /* FIFO shadow write pointer */ 148#define HME_ERXI_FIFO_RPTR (5*4) /* FIFO read pointer */ 149#define HME_ERXI_FIFO_SRPTR (6*4) /* FIFO shadow read pointer */ 150#define HME_ERXI_STATEMACHINE (7*4) /* State machine */ 151 152/* RXI_CFG bits */ 153#define HME_ERX_CFG_DMAENABLE 0x00000001 /* Enable RX dma */ 154#define HME_ERX_CFG_BYTEOFFSET 0x00000038 /* RX first byte offset */ 155#define HME_ERX_CFG_RINGSIZE32 0x00000000 /* Descriptor ring size: 32 */ 156#define HME_ERX_CFG_RINGSIZE64 0x00000200 /* Descriptor ring size: 64 */ 157#define HME_ERX_CFG_RINGSIZE128 0x00000400 /* Descriptor ring size: 128 */ 158#define HME_ERX_CFG_RINGSIZE256 0x00000600 /* Descriptor ring size: 256 */ 159#define HME_ERX_CFG_CSUMSTART 0x007f0000 /* cksum offset */ 160#define HME_ERX_CFG_CSUM_SHIFT 16 161 162/* 163 * HME MAC-core register offsets 164 */ 165#define HME_MACI_XIF (0*4) 166#define HME_MACI_TXSWRST (130*4) /* TX reset */ 167#define HME_MACI_TXCFG (131*4) /* TX config */ 168#define HME_MACI_JSIZE (139*4) /* TX jam size */ 169#define HME_MACI_TXSIZE (140*4) /* TX max size */ 170#define HME_MACI_NCCNT (144*4) /* TX normal collision cnt */ 171#define HME_MACI_FCCNT (145*4) /* TX first collision cnt */ 172#define HME_MACI_EXCNT (146*4) /* TX excess collision cnt */ 173#define HME_MACI_LTCNT (147*4) /* TX late collision cnt */ 174#define HME_MACI_RANDSEED (148*4) /* */ 175#define HME_MACI_RXSWRST (194*4) /* RX reset */ 176#define HME_MACI_RXCFG (195*4) /* RX config */ 177#define HME_MACI_RXSIZE (196*4) /* RX max size */ 178#define HME_MACI_MACADDR2 (198*4) /* MAC address */ 179#define HME_MACI_MACADDR1 (199*4) 180#define HME_MACI_MACADDR0 (200*4) 181#define HME_MACI_HASHTAB3 (208*4) /* Address hash table */ 182#define HME_MACI_HASHTAB2 (209*4) 183#define HME_MACI_HASHTAB1 (210*4) 184#define HME_MACI_HASHTAB0 (211*4) 185#define HME_MACI_AFILTER2 (212*4) /* Address filter */ 186#define HME_MACI_AFILTER1 (213*4) 187#define HME_MACI_AFILTER0 (214*4) 188#define HME_MACI_AFILTER_MASK (215*4) 189 190/* XIF config register. */ 191#define HME_MAC_XIF_OE 0x00000001 /* Output driver enable */ 192#define HME_MAC_XIF_XLBACK 0x00000002 /* Loopback-mode XIF enable */ 193#define HME_MAC_XIF_MLBACK 0x00000004 /* Loopback-mode MII enable */ 194#define HME_MAC_XIF_MIIENABLE 0x00000008 /* MII receive buffer enable */ 195#define HME_MAC_XIF_SQENABLE 0x00000010 /* SQE test enable */ 196#define HME_MAC_XIF_SQETWIN 0x000003e0 /* SQE time window */ 197#define HME_MAC_XIF_LANCE 0x00000010 /* Lance mode enable */ 198#define HME_MAC_XIF_LIPG0 0x000003e0 /* Lance mode IPG0 */ 199 200/* Transmit config register. */ 201#define HME_MAC_TXCFG_ENABLE 0x00000001 /* Enable the transmitter */ 202#define HME_MAC_TXCFG_SMODE 0x00000020 /* Enable slow transmit mode */ 203#define HME_MAC_TXCFG_CIGN 0x00000040 /* Ignore transmit collisions */ 204#define HME_MAC_TXCFG_FCSOFF 0x00000080 /* Do not emit FCS */ 205#define HME_MAC_TXCFG_DBACKOFF 0x00000100 /* Disable backoff */ 206#define HME_MAC_TXCFG_FULLDPLX 0x00000200 /* Enable full-duplex */ 207#define HME_MAC_TXCFG_DGIVEUP 0x00000400 /* Don't give up on transmits */ 208 209/* Receive config register. */ 210#define HME_MAC_RXCFG_ENABLE 0x00000001 /* Enable the receiver */ 211#define HME_MAC_RXCFG_PSTRIP 0x00000020 /* Pad byte strip enable */ 212#define HME_MAC_RXCFG_PMISC 0x00000040 /* Enable promiscuous mode */ 213#define HME_MAC_RXCFG_DERR 0x00000080 /* Disable error checking */ 214#define HME_MAC_RXCFG_DCRCS 0x00000100 /* Disable CRC stripping */ 215#define HME_MAC_RXCFG_ME 0x00000200 /* Receive packets addressed to me */ 216#define HME_MAC_RXCFG_PGRP 0x00000400 /* Enable promisc group mode */ 217#define HME_MAC_RXCFG_HENABLE 0x00000800 /* Enable the hash filter */ 218#define HME_MAC_RXCFG_AENABLE 0x00001000 /* Enable the address filter */ 219 220/* 221 * HME MIF register offsets 222 */ 223#define HME_MIFI_BB_CLK (0*4) /* bit-bang clock */ 224#define HME_MIFI_BB_DATA (1*4) /* bit-bang data */ 225#define HME_MIFI_BB_OE (2*4) /* bit-bang output enable */ 226#define HME_MIFI_FO (3*4) /* frame output */ 227#define HME_MIFI_CFG (4*4) /* mif configuration */ 228#define HME_MIFI_IMASK (5*4) /* Interrupt mask for status change */ 229#define HME_MIFI_STAT (6*4) /* Status (ro, auto-clear) */ 230#define HME_MIFI_SM (7*4) /* State machine (ro) */ 231 232/* MIF Configuration register */ 233#define HME_MIF_CFG_PHY 0x00000001 /* PHY select */ 234#define HME_MIF_CFG_PE 0x00000002 /* Poll enable */ 235#define HME_MIF_CFG_BBMODE 0x00000004 /* Bit-bang mode */ 236#define HME_MIF_CFG_PRADDR 0x000000f8 /* Poll register address */ 237#define HME_MIF_CFG_MDI0 0x00000100 /* MDI_0 (ro) */ 238#define HME_MIF_CFG_MDI1 0x00000200 /* MDI_1 (ro) */ 239#define HME_MIF_CFG_PPADDR 0x00007c00 /* Poll phy address */ 240 241/* MIF Frame/Output register */ 242#define HME_MIF_FO_ST 0xc0000000 /* Start of frame */ 243#define HME_MIF_FO_ST_SHIFT 30 /* */ 244#define HME_MIF_FO_OPC 0x30000000 /* Opcode */ 245#define HME_MIF_FO_OPC_SHIFT 28 /* */ 246#define HME_MIF_FO_PHYAD 0x0f800000 /* PHY Address */ 247#define HME_MIF_FO_PHYAD_SHIFT 23 /* */ 248#define HME_MIF_FO_REGAD 0x007c0000 /* Register Address */ 249#define HME_MIF_FO_REGAD_SHIFT 18 /* */ 250#define HME_MIF_FO_TAMSB 0x00020000 /* Turn-around MSB */ 251#define HME_MIF_FO_TALSB 0x00010000 /* Turn-around LSB */ 252#define HME_MIF_FO_DATA 0x0000ffff /* data to read or write */ 253 254/* Wired HME PHY addresses */ 255#define HME_PHYAD_INTERNAL 1 256#define HME_PHYAD_EXTERNAL 0 257 258/* 259 * Buffer Descriptors. 260 */ 261#ifdef notdef 262struct hme_xd { 263 volatile u_int32_t xd_flags; 264 volatile u_int32_t xd_addr; /* Buffer address (DMA) */ 265}; 266#endif 267#define HME_XD_SIZE 8 268#define HME_XD_FLAGS(base, index) ((base) + ((index) * HME_XD_SIZE) + 0) 269#define HME_XD_ADDR(base, index) ((base) + ((index) * HME_XD_SIZE) + 4) 270#define HME_XD_GETFLAGS(p, b, i) \ 271 (p) ? letoh32(*((u_int32_t *)HME_XD_FLAGS(b,i))) : \ 272 (*((u_int32_t *)HME_XD_FLAGS(b,i))) 273#define HME_XD_SETFLAGS(p, b, i, f) do { \ 274 *((u_int32_t *)HME_XD_FLAGS(b,i)) = ((p) ? htole32(f) : (f)); \ 275} while(0) 276#define HME_XD_SETADDR(p, b, i, a) do { \ 277 *((u_int32_t *)HME_XD_ADDR(b,i)) = ((p) ? htole32(a) : (a)); \ 278} while(0) 279 280/* Descriptor flag values */ 281#define HME_XD_OWN 0x80000000 /* ownership: 1=hw, 0=sw */ 282#define HME_XD_SOP 0x40000000 /* start of packet marker (tx) */ 283#define HME_XD_OFL 0x40000000 /* buffer overflow (rx) */ 284#define HME_XD_EOP 0x20000000 /* end of packet marker (tx) */ 285#define HME_XD_TXCKSUM 0x10000000 /* checksum enable (tx) */ 286#define HME_XD_RXLENMSK 0x3fff0000 /* packet length mask (rx) */ 287#define HME_XD_RXLENSHIFT 16 288#define HME_XD_TXLENMSK 0x00003fff /* packet length mask (tx) */ 289#define HME_XD_RXCKSUM 0x0000ffff /* packet checksum (rx) */ 290 291/* Macros to encode/decode the receive buffer size from the flags field */ 292#define HME_XD_ENCODE_RSIZE(sz) \ 293 (((sz) << HME_XD_RXLENSHIFT) & HME_XD_RXLENMSK) 294#define HME_XD_DECODE_RSIZE(flags) \ 295 (((flags) & HME_XD_RXLENMSK) >> HME_XD_RXLENSHIFT) 296 297/* Provide encode/decode macros for the transmit buffers for symmetry */ 298#define HME_XD_ENCODE_TSIZE(sz) \ 299 (((sz) << 0) & HME_XD_TXLENMSK) 300#define HME_XD_DECODE_TSIZE(flags) \ 301 (((flags) & HME_XD_TXLENMSK) >> 0) 302