1/* $OpenBSD: fxpreg.h,v 1.14 2012/04/03 23:39:09 deraadt Exp $ */ 2 3/* 4 * Copyright (c) 1995, David Greenman 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD: if_fxpreg.h,v 1.13 1998/06/08 09:47:46 bde Exp $ 30 */ 31 32#define FXP_VENDORID_INTEL 0x8086 33#define FXP_DEVICEID_i82557 0x1229 34 35#define FXP_PCI_MMBA 0x10 36#define FXP_PCI_IOBA 0x14 37 38/* 39 * Control/status registers. 40 */ 41#define FXP_CSR_SCB_STATUS 0 /* scb_status (2 byte) */ 42#define FXP_CSR_SCB_COMMAND 2 /* scb_command (2 byte) */ 43#define FXP_CSR_SCB_GENERAL 4 /* scb_general (4 bytes) */ 44#define FXP_CSR_PORT 8 /* port (4 bytes) */ 45#define FXP_CSR_FLASHCONTROL 12 /* flash control (2 bytes) */ 46#define FXP_CSR_EEPROMCONTROL 14 /* eeprom control (2 bytes) */ 47#define FXP_CSR_MDICONTROL 16 /* mdi control (4 bytes) */ 48 49/* 50 * FOR REFERENCE ONLY, the old definition of FXP_CSR_SCB_RUSCUS: 51 * 52 * volatile u_int8_t :2, 53 * scb_rus:4, 54 * scb_cus:2; 55 */ 56 57#define FXP_PORT_SOFTWARE_RESET 0 58#define FXP_PORT_SELFTEST 1 59#define FXP_PORT_SELECTIVE_RESET 2 60#define FXP_PORT_DUMP 3 61 62#define FXP_SCB_RUS_IDLE 0x0000 63#define FXP_SCB_RUS_SUSPENDED 0x0001 64#define FXP_SCB_RUS_NORESOURCES 0x0002 65#define FXP_SCB_RUS_READY 0x0004 66#define FXP_SCB_RUS_SUSP_NORBDS 0x0009 67#define FXP_SCB_RUS_NORES_NORBDS 0x000a 68#define FXP_SCB_RUS_READY_NORBDS 0x000c 69 70#define FXP_SCB_CUS_IDLE 0x0000 71#define FXP_SCB_CUS_SUSPENDED 0x0040 72#define FXP_SCB_CUS_ACTIVE 0x0080 73#define FXP_SCB_CUS_MASK 0x00c0 74 75#define FXP_SCB_STATACK_SWI 0x0400 76#define FXP_SCB_STATACK_MDI 0x0800 77#define FXP_SCB_STATACK_RNR 0x1000 78#define FXP_SCB_STATACK_CNA 0x2000 79#define FXP_SCB_STATACK_FR 0x4000 80#define FXP_SCB_STATACK_CXTNO 0x8000 81#define FXP_SCB_STATACK_MASK 0xfc00 82 83#define FXP_SCB_COMMAND_CU_NOP 0x0000 84#define FXP_SCB_COMMAND_CU_START 0x0010 85#define FXP_SCB_COMMAND_CU_RESUME 0x0020 86#define FXP_SCB_COMMAND_CU_DUMP_ADR 0x0040 87#define FXP_SCB_COMMAND_CU_DUMP 0x0050 88#define FXP_SCB_COMMAND_CU_BASE 0x0060 89#define FXP_SCB_COMMAND_CU_DUMPRESET 0x0070 90 91#define FXP_SCB_COMMAND_RU_NOP 0x0000 92#define FXP_SCB_COMMAND_RU_START 0x0001 93#define FXP_SCB_COMMAND_RU_RESUME 0x0002 94#define FXP_SCB_COMMAND_RU_ABORT 0x0004 95#define FXP_SCB_COMMAND_RU_LOADHDS 0x0005 96#define FXP_SCB_COMMAND_RU_BASE 0x0006 97#define FXP_SCB_COMMAND_RU_RBDRESUME 0x0007 98 99#define FXP_SCB_INTRCNTL_REQUEST_SWI 0x0200 100 101#define FXP_CMD_TMO (10000) 102 103/* 104 * Command block definitions 105 */ 106struct fxp_cb_nop { 107 void *fill[2]; 108 volatile u_int16_t cb_status; 109 volatile u_int16_t cb_command; 110 volatile u_int32_t link_addr; 111}; 112struct fxp_cb_ias { 113 volatile u_int16_t cb_status; 114 volatile u_int16_t cb_command; 115 volatile u_int32_t link_addr; 116 volatile u_int8_t macaddr[6]; 117}; 118/* I hate bit-fields :-( */ /* SO WHY USE IT, EH? */ 119 120/* 121 * Bitfields cleaned out since it is not endian compatible. OK 122 * you can define a big endian structure but can never be 100% safe... 123 * 124 * ANY PROGRAMER TRYING THE STUNT WITH BITFIELDS IN A DEVICE DRIVER 125 * SHOULD BE PUT UP AGAINST THE WALL, BLINDFOLDED AND SHOT! 126 */ 127struct fxp_cb_config { 128 volatile u_int16_t cb_status; 129 volatile u_int16_t cb_command; 130 volatile u_int32_t link_addr; 131 volatile u_int8_t byte_count; 132 volatile u_int8_t fifo_limit; 133 volatile u_int8_t adaptive_ifs; 134 volatile u_int8_t ctrl0; 135 volatile u_int8_t rx_dma_bytecount; 136 volatile u_int8_t tx_dma_bytecount; 137 volatile u_int8_t ctrl1; 138 volatile u_int8_t ctrl2; 139 volatile u_int8_t mediatype; 140 volatile u_int8_t void2; 141 volatile u_int8_t ctrl3; 142 volatile u_int8_t linear_priority; 143 volatile u_int8_t interfrm_spacing; 144 volatile u_int8_t void3; 145 volatile u_int8_t void4; 146 volatile u_int8_t promiscuous; 147 volatile u_int8_t void5; 148 volatile u_int8_t void6; 149 volatile u_int8_t stripping; 150 volatile u_int8_t fdx_pin; 151 volatile u_int8_t multi_ia; 152 volatile u_int8_t mc_all; 153}; 154 155#define MAXMCADDR 80 156struct fxp_cb_mcs { 157 volatile u_int16_t cb_status; 158 volatile u_int16_t cb_command; 159 volatile u_int32_t link_addr; 160 volatile u_int16_t mc_cnt; 161 volatile u_int8_t mc_addr[MAXMCADDR][6]; 162}; 163 164/* 165 * Number of DMA segments in a TxCB. Note that this is carefully 166 * chosen to make the total struct size an even power of two. It's 167 * critical that no TxCB be split across a page boundary since 168 * no attempt is made to allocate physically contiguous memory. 169 */ 170#define SZ_TXCB 16 /* TX control block head size = 4 32 bit words */ 171#define SZ_TBD 8 /* Fragment ptr/size block size */ 172#define FXP_NTXSEG ((256 - SZ_TXCB) / SZ_TBD) 173 174struct fxp_tbd { 175 volatile u_int32_t tb_addr; 176 volatile u_int32_t tb_size; 177}; 178struct fxp_cb_tx { 179 volatile u_int16_t cb_status; 180 volatile u_int16_t cb_command; 181 volatile u_int32_t link_addr; 182 volatile u_int32_t tbd_array_addr; 183 volatile u_int16_t byte_count; 184 volatile u_int8_t tx_threshold; 185 volatile u_int8_t tbd_number; 186 /* 187 * The following isn't actually part of the TxCB. 188 */ 189 volatile struct fxp_tbd tbd[FXP_NTXSEG]; 190}; 191 192/* 193 * Control Block (CB) definitions 194 */ 195 196/* status */ 197#define FXP_CB_STATUS_OK 0x2000 198#define FXP_CB_STATUS_C 0x8000 199/* commands */ 200#define FXP_CB_COMMAND_NOP 0x0 201#define FXP_CB_COMMAND_IAS 0x1 202#define FXP_CB_COMMAND_CONFIG 0x2 203#define FXP_CB_COMMAND_MCAS 0x3 204#define FXP_CB_COMMAND_XMIT 0x4 205#define FXP_CB_COMMAND_UCODE 0x5 206#define FXP_CB_COMMAND_DUMP 0x6 207#define FXP_CB_COMMAND_DIAG 0x7 208/* command flags */ 209#define FXP_CB_COMMAND_SF 0x0008 /* simple/flexible mode */ 210#define FXP_CB_COMMAND_I 0x2000 /* generate interrupt on completion */ 211#define FXP_CB_COMMAND_S 0x4000 /* suspend on completion */ 212#define FXP_CB_COMMAND_EL 0x8000 /* end of list */ 213 214/* 215 * RFA definitions 216 */ 217 218struct fxp_rfa { 219 volatile u_int16_t rfa_status; 220 volatile u_int16_t rfa_control; 221 volatile u_int32_t link_addr; 222 volatile u_int32_t rbd_addr; 223 volatile u_int16_t actual_size; 224 volatile u_int16_t size; 225}; 226#define FXP_RFA_STATUS_RCOL 0x0001 /* receive collision */ 227#define FXP_RFA_STATUS_IAMATCH 0x0002 /* 0 = matches station address */ 228#define FXP_RFA_STATUS_S4 0x0010 /* receive error from PHY */ 229#define FXP_RFA_STATUS_TL 0x0020 /* type/length */ 230#define FXP_RFA_STATUS_FTS 0x0080 /* frame too short */ 231#define FXP_RFA_STATUS_OVERRUN 0x0100 /* DMA overrun */ 232#define FXP_RFA_STATUS_RNR 0x0200 /* RU not ready */ 233#define FXP_RFA_STATUS_ALIGN 0x0400 /* alignment error */ 234#define FXP_RFA_STATUS_CRC 0x0800 /* CRC error */ 235#define FXP_RFA_STATUS_OK 0x2000 /* packet received okay */ 236#define FXP_RFA_STATUS_C 0x8000 /* packet reception complete */ 237#define FXP_RFA_CONTROL_SF 0x08 /* simple/flexible memory mode */ 238#define FXP_RFA_CONTROL_H 0x10 /* header RFD */ 239#define FXP_RFA_CONTROL_S 0x4000 /* suspend after reception */ 240#define FXP_RFA_CONTROL_EL 0x8000 /* end of list */ 241 242/* 243 * Statistics dump area definitions 244 */ 245struct fxp_stats { 246 volatile u_int32_t tx_good; 247 volatile u_int32_t tx_maxcols; 248 volatile u_int32_t tx_latecols; 249 volatile u_int32_t tx_underruns; 250 volatile u_int32_t tx_lostcrs; 251 volatile u_int32_t tx_deffered; 252 volatile u_int32_t tx_single_collisions; 253 volatile u_int32_t tx_multiple_collisions; 254 volatile u_int32_t tx_total_collisions; 255 volatile u_int32_t rx_good; 256 volatile u_int32_t rx_crc_errors; 257 volatile u_int32_t rx_alignment_errors; 258 volatile u_int32_t rx_rnr_errors; 259 volatile u_int32_t rx_overrun_errors; 260 volatile u_int32_t rx_cdt_errors; 261 volatile u_int32_t rx_shortframes; 262 volatile u_int32_t completion_status; 263}; 264#define FXP_STATS_DUMP_COMPLETE 0xa005 265#define FXP_STATS_DR_COMPLETE 0xa007 266 267/* 268 * Serial EEPROM control register bits 269 */ 270/* shift clock */ 271#define FXP_EEPROM_EESK 0x01 272/* chip select */ 273#define FXP_EEPROM_EECS 0x02 274/* data in */ 275#define FXP_EEPROM_EEDI 0x04 276/* data out */ 277#define FXP_EEPROM_EEDO 0x08 278 279/* 280 * Serial EEPROM opcodes, including start bit 281 */ 282#define FXP_EEPROM_OPC_ERASE 0x4 283#define FXP_EEPROM_OPC_WRITE 0x5 284#define FXP_EEPROM_OPC_READ 0x6 285 286/* 287 * Serial EEPROM registers. A subset of them from Intel's 288 * "82559 EEPROM Map and Programming Information" document. 289 */ 290#define FXP_EEPROM_REG_MAC 0x00 291#define FXP_EEPROM_REG_COMPAT 0x03 292#define FXP_EEPROM_REG_COMPAT_MC10 0x0001 293#define FXP_EEPROM_REG_COMPAT_MC100 0x0002 294#define FXP_EEPROM_REG_COMPAT_SRV 0x0400 295#define FXP_EEPROM_REG_PHY 0x06 296#define FXP_EEPROM_REG_ID 0x0a 297#define FXP_EEPROM_REG_ID_STB 0x0002 298 299/* 300 * Management Data Interface opcodes 301 */ 302#define FXP_MDI_WRITE 0x1 303#define FXP_MDI_READ 0x2 304 305/* 306 * PHY device types 307 */ 308#define FXP_PHY_DEVICE_MASK 0x3f00 309#define FXP_PHY_SERIAL_ONLY 0x8000 310#define FXP_PHY_NONE 0 311#define FXP_PHY_82553A 1 312#define FXP_PHY_82553C 2 313#define FXP_PHY_82503 3 314#define FXP_PHY_DP83840 4 315#define FXP_PHY_80C240 5 316#define FXP_PHY_80C24 6 317#define FXP_PHY_82555 7 318#define FXP_PHY_DP83840A 10 319#define FXP_PHY_82555B 11 320 321/* 322 * PHY BMCR Basic Mode Control Register 323 */ 324#define FXP_PHY_BMCR 0x0 325#define FXP_PHY_BMCR_FULLDUPLEX 0x0100 326#define FXP_PHY_BMCR_AUTOEN 0x1000 327#define FXP_PHY_BMCR_SPEED_100M 0x2000 328 329/* 330 * DP84830 PHY, PCS Configuration Register 331 */ 332#define FXP_DP83840_PCR 0x17 333#define FXP_DP83840_PCR_LED4_MODE 0x0002 /* 1 = LED4 always indicates full duplex */ 334#define FXP_DP83840_PCR_F_CONNECT 0x0020 /* 1 = force link disconnect function bypass */ 335#define FXP_DP83840_PCR_BIT8 0x0100 336#define FXP_DP83840_PCR_BIT10 0x0400 337 338#define MAXUCODESIZE 192 339struct fxp_cb_ucode { 340 volatile u_int16_t cb_status; 341 volatile u_int16_t cb_command; 342 volatile u_int32_t link_addr; 343 volatile u_int32_t ucode[MAXUCODESIZE]; 344}; 345 346/* 347 * Chip revision values. 348 */ 349#define FXP_REV_82557_A 0 /* 82557 A */ 350#define FXP_REV_82557_B 1 /* 82557 B */ 351#define FXP_REV_82557_C 2 /* 82557 C */ 352#define FXP_REV_82558_A4 4 /* 82558 A4 stepping */ 353#define FXP_REV_82558_B0 5 /* 82558 B0 stepping */ 354#define FXP_REV_82559_A0 8 /* 82559 A0 stepping */ 355#define FXP_REV_82559S_A 9 /* 82559S A stepping */ 356#define FXP_REV_82550 12 357#define FXP_REV_82550_C 13 /* 82550 C stepping */ 358#define FXP_REV_82551_E 14 /* 82551 */ 359#define FXP_REV_82551_F 15 /* 82551 */ 360#define FXP_REV_82551_10 16 /* 82551 */ 361