1/* $OpenBSD: dcreg.h,v 1.54 2022/01/09 05:42:38 jsg Exp $ */ 2 3/* 4 * Copyright (c) 1997, 1998, 1999 5 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: src/sys/pci/if_dcreg.h,v 1.12 2000/10/05 17:36:14 wpaul Exp $ 35 */ 36 37/* 38 * 21143 and clone common register definitions. 39 */ 40 41#ifdef __alpha__ 42#define SRM_MEDIA 43#endif 44 45#define DC_BUSCTL 0x00 /* bus control */ 46#define DC_TXSTART 0x08 /* tx start demand */ 47#define DC_RXSTART 0x10 /* rx start demand */ 48#define DC_RXADDR 0x18 /* rx descriptor list start addr */ 49#define DC_TXADDR 0x20 /* tx descriptor list start addr */ 50#define DC_ISR 0x28 /* interrupt status register */ 51#define DC_NETCFG 0x30 /* network config register */ 52#define DC_IMR 0x38 /* interrupt mask */ 53#define DC_FRAMESDISCARDED 0x40 /* # of discarded frames */ 54#define DC_SIO 0x48 /* MII and ROM/EEPROM access */ 55#define DC_ROM 0x50 /* ROM programming address */ 56#define DC_TIMER 0x58 /* general timer */ 57#define DC_10BTSTAT 0x60 /* SIA status */ 58#define DC_SIARESET 0x68 /* SIA connectivity */ 59#define DC_10BTCTRL 0x70 /* SIA transmit and receive */ 60#define DC_WATCHDOG 0x78 /* SIA and general purpose port */ 61#define DC_SIAGP 0x78 /* SIA and general purpose port (X3201) */ 62 63/* 64 * There are two general 'types' of MX chips that we need to be 65 * concerned with. One is the original 98713, which has its internal 66 * NWAY support controlled via the MDIO bits in the serial I/O 67 * register. The other is everything else (from the 98713A on up), 68 * which has its internal NWAY controlled via CSR13, CSR14 and CSR15, 69 * just like the 21143. This type setting also governs which of the 70 * 'magic' numbers we write to CSR16. The PNIC II falls into the 71 * 98713A/98715/98715A/98725 category. 72 */ 73#define DC_TYPE_98713 0x1 74#define DC_TYPE_98713A 0x2 75#define DC_TYPE_987x5 0x3 76 77/* Other type of supported chips. */ 78#define DC_TYPE_21143 0x4 /* Intel 21143 */ 79#define DC_TYPE_ASIX 0x5 /* ASIX AX88140A/AX88141 */ 80#define DC_TYPE_AL981 0x6 /* ADMtek AL981 Comet */ 81#define DC_TYPE_AN983 0x7 /* ADMtek AN983 Centaur */ 82#define DC_TYPE_DM9102 0x8 /* Davicom DM9102 */ 83#define DC_TYPE_PNICII 0x9 /* 82c115 PNIC II */ 84#define DC_TYPE_PNIC 0xA /* 82c168/82c169 PNIC I */ 85#define DC_TYPE_XIRCOM 0xB /* Xircom X3201 */ 86#define DC_TYPE_CONEXANT 0xC /* Conexant LANfinity RS7112 */ 87#define DC_TYPE_21145 0xD /* Intel 21145 */ 88 89#define DC_IS_MACRONIX(x) \ 90 (x->dc_type == DC_TYPE_98713 || \ 91 x->dc_type == DC_TYPE_98713A || \ 92 x->dc_type == DC_TYPE_987x5) 93 94#define DC_IS_ADMTEK(x) \ 95 (x->dc_type == DC_TYPE_AL981 || \ 96 x->dc_type == DC_TYPE_AN983) 97 98#define DC_IS_CENTAUR(x) \ 99 (x->dc_type == DC_TYPE_AN983) 100 101#define DC_IS_INTEL(x) \ 102 (x->dc_type == DC_TYPE_21143 || \ 103 x->dc_type == DC_TYPE_21145) 104 105#define DC_IS_ASIX(x) (x->dc_type == DC_TYPE_ASIX) 106#define DC_IS_COMET(x) (x->dc_type == DC_TYPE_AL981) 107#define DC_IS_CENTAUR(x) (x->dc_type == DC_TYPE_AN983) 108#define DC_IS_DAVICOM(x) (x->dc_type == DC_TYPE_DM9102) 109#define DC_IS_PNICII(x) (x->dc_type == DC_TYPE_PNICII) 110#define DC_IS_PNIC(x) (x->dc_type == DC_TYPE_PNIC) 111#define DC_IS_XIRCOM(x) (x->dc_type == DC_TYPE_XIRCOM) 112#define DC_IS_CONEXANT(x) (x->dc_type == DC_TYPE_CONEXANT) 113 114/* MII/symbol mode port types */ 115#define DC_PMODE_MII 0x1 116#define DC_PMODE_SYM 0x2 117#define DC_PMODE_SIA 0x3 118 119/* 120 * Bus control bits. 121 */ 122#define DC_BUSCTL_RESET 0x00000001 123#define DC_BUSCTL_ARBITRATION 0x00000002 124#define DC_BUSCTL_SKIPLEN 0x0000007C 125#define DC_BUSCTL_BUF_BIGENDIAN 0x00000080 126#define DC_BUSCTL_BURSTLEN 0x00003F00 127#define DC_BUSCTL_CACHEALIGN 0x0000C000 128#define DC_BUSCTL_TXPOLL 0x000E0000 129#define DC_BUSCTL_DBO 0x00100000 130#define DC_BUSCTL_MRME 0x00200000 131#define DC_BUSCTL_MRLE 0x00800000 132#define DC_BUSCTL_MWIE 0x01000000 133#define DC_BUSCTL_ONNOW_ENB 0x04000000 134 135#define DC_SKIPLEN_1LONG 0x00000004 136#define DC_SKIPLEN_2LONG 0x00000008 137#define DC_SKIPLEN_3LONG 0x00000010 138#define DC_SKIPLEN_4LONG 0x00000020 139#define DC_SKIPLEN_5LONG 0x00000040 140 141#define DC_CACHEALIGN_NONE 0x00000000 142#define DC_CACHEALIGN_8LONG 0x00004000 143#define DC_CACHEALIGN_16LONG 0x00008000 144#define DC_CACHEALIGN_32LONG 0x0000C000 145 146#define DC_BURSTLEN_USECA 0x00000000 147#define DC_BURSTLEN_1LONG 0x00000100 148#define DC_BURSTLEN_2LONG 0x00000200 149#define DC_BURSTLEN_4LONG 0x00000400 150#define DC_BURSTLEN_8LONG 0x00000800 151#define DC_BURSTLEN_16LONG 0x00001000 152#define DC_BURSTLEN_32LONG 0x00002000 153 154#define DC_TXPOLL_OFF 0x00000000 155#define DC_TXPOLL_1 0x00020000 156#define DC_TXPOLL_2 0x00040000 157#define DC_TXPOLL_3 0x00060000 158#define DC_TXPOLL_4 0x00080000 159#define DC_TXPOLL_5 0x000A0000 160#define DC_TXPOLL_6 0x000C0000 161#define DC_TXPOLL_7 0x000E0000 162 163/* 164 * Interrupt status bits. 165 */ 166#define DC_ISR_TX_OK 0x00000001 167#define DC_ISR_TX_IDLE 0x00000002 168#define DC_ISR_TX_NOBUF 0x00000004 169#define DC_ISR_TX_JABBERTIMEO 0x00000008 170#define DC_ISR_LINKGOOD 0x00000010 171#define DC_ISR_TX_UNDERRUN 0x00000020 172#define DC_ISR_RX_OK 0x00000040 173#define DC_ISR_RX_NOBUF 0x00000080 174#define DC_ISR_RX_READ 0x00000100 175#define DC_ISR_RX_WATDOGTIMEO 0x00000200 176#define DC_ISR_TX_EARLY 0x00000400 177#define DC_ISR_TIMER_EXPIRED 0x00000800 178#define DC_ISR_LINKFAIL 0x00001000 179#define DC_ISR_BUS_ERR 0x00002000 180#define DC_ISR_RX_EARLY 0x00004000 181#define DC_ISR_ABNORMAL 0x00008000 182#define DC_ISR_NORMAL 0x00010000 183#define DC_ISR_RX_STATE 0x000E0000 184#define DC_ISR_TX_STATE 0x00700000 185#define DC_ISR_BUSERRTYPE 0x03800000 186#define DC_ISR_100MBPSLINK 0x08000000 187#define DC_ISR_MAGICKPACK 0x10000000 188 189#define DC_RXSTATE_STOPPED 0x00000000 /* 000 - Stopped */ 190#define DC_RXSTATE_FETCH 0x00020000 /* 001 - Fetching descriptor */ 191#define DC_RXSTATE_ENDCHECK 0x00040000 /* 010 - check for rx end */ 192#define DC_RXSTATE_WAIT 0x00060000 /* 011 - waiting for packet */ 193#define DC_RXSTATE_SUSPEND 0x00080000 /* 100 - suspend rx */ 194#define DC_RXSTATE_CLOSE 0x000A0000 /* 101 - close tx desc */ 195#define DC_RXSTATE_FLUSH 0x000C0000 /* 110 - flush from FIFO */ 196#define DC_RXSTATE_DEQUEUE 0x000E0000 /* 111 - dequeue from FIFO */ 197 198#define DC_HAS_BROKEN_RXSTATE(x) \ 199 (DC_IS_CENTAUR(x) || DC_IS_CONEXANT(x) || (DC_IS_DAVICOM(x) && \ 200 sc->dc_revision >= DC_REVISION_DM9102A)) 201 202#define DC_TXSTATE_RESET 0x00000000 /* 000 - reset */ 203#define DC_TXSTATE_FETCH 0x00100000 /* 001 - fetching descriptor */ 204#define DC_TXSTATE_WAITEND 0x00200000 /* 010 - wait for tx end */ 205#define DC_TXSTATE_READING 0x00300000 /* 011 - read and enqueue */ 206#define DC_TXSTATE_RSVD 0x00400000 /* 100 - reserved */ 207#define DC_TXSTATE_SETUP 0x00500000 /* 101 - setup packet */ 208#define DC_TXSTATE_SUSPEND 0x00600000 /* 110 - suspend tx */ 209#define DC_TXSTATE_CLOSE 0x00700000 /* 111 - close tx desc */ 210 211/* 212 * Network config bits. 213 */ 214#define DC_NETCFG_RX_HASHPERF 0x00000001 215#define DC_NETCFG_RX_ON 0x00000002 216#define DC_NETCFG_RX_HASHONLY 0x00000004 217#define DC_NETCFG_RX_BADFRAMES 0x00000008 218#define DC_NETCFG_RX_INVFILT 0x00000010 219#define DC_NETCFG_BACKOFFCNT 0x00000020 220#define DC_NETCFG_RX_PROMISC 0x00000040 221#define DC_NETCFG_RX_ALLMULTI 0x00000080 222#define DC_NETCFG_FULLDUPLEX 0x00000200 223#define DC_NETCFG_LOOPBACK 0x00000C00 224#define DC_NETCFG_FORCECOLL 0x00001000 225#define DC_NETCFG_TX_ON 0x00002000 226#define DC_NETCFG_TX_THRESH 0x0000C000 227#define DC_NETCFG_TX_BACKOFF 0x00020000 228#define DC_NETCFG_PORTSEL 0x00040000 /* 0 == 10, 1 == 100 */ 229#define DC_NETCFG_HEARTBEAT 0x00080000 230#define DC_NETCFG_STORENFWD 0x00200000 231#define DC_NETCFG_SPEEDSEL 0x00400000 /* 1 == 10, 0 == 100 */ 232#define DC_NETCFG_PCS 0x00800000 233#define DC_NETCFG_SCRAMBLER 0x01000000 234#define DC_NETCFG_NO_RXCRC 0x02000000 235#define DC_NETCFG_RX_ALL 0x40000000 236#define DC_NETCFG_CAPEFFECT 0x80000000 237 238#define DC_OPMODE_NORM 0x00000000 239#define DC_OPMODE_INTLOOP 0x00000400 240#define DC_OPMODE_EXTLOOP 0x00000800 241 242#if 0 243#define DC_TXTHRESH_72BYTES 0x00000000 244#define DC_TXTHRESH_96BYTES 0x00004000 245#define DC_TXTHRESH_128BYTES 0x00008000 246#define DC_TXTHRESH_160BYTES 0x0000C000 247#endif 248 249#define DC_TXTHRESH_MIN 0x00000000 250#define DC_TXTHRESH_INC 0x00004000 251#define DC_TXTHRESH_MAX 0x0000C000 252 253/* 254 * Interrupt mask bits. 255 */ 256#define DC_IMR_TX_OK 0x00000001 257#define DC_IMR_TX_IDLE 0x00000002 258#define DC_IMR_TX_NOBUF 0x00000004 259#define DC_IMR_TX_JABBERTIMEO 0x00000008 260#define DC_IMR_LINKGOOD 0x00000010 261#define DC_IMR_TX_UNDERRUN 0x00000020 262#define DC_IMR_RX_OK 0x00000040 263#define DC_IMR_RX_NOBUF 0x00000080 264#define DC_IMR_RX_READ 0x00000100 265#define DC_IMR_RX_WATDOGTIMEO 0x00000200 266#define DC_IMR_TX_EARLY 0x00000400 267#define DC_IMR_TIMER_EXPIRED 0x00000800 268#define DC_IMR_LINKFAIL 0x00001000 269#define DC_IMR_BUS_ERR 0x00002000 270#define DC_IMR_RX_EARLY 0x00004000 271#define DC_IMR_ABNORMAL 0x00008000 272#define DC_IMR_NORMAL 0x00010000 273#define DC_IMR_100MBPSLINK 0x08000000 274#define DC_IMR_MAGICKPACK 0x10000000 275 276#define DC_INTRS \ 277 (DC_IMR_RX_OK|DC_IMR_TX_OK|DC_IMR_RX_NOBUF|DC_IMR_RX_WATDOGTIMEO|\ 278 DC_IMR_TX_IDLE|DC_IMR_TX_NOBUF|DC_IMR_TX_UNDERRUN|DC_IMR_BUS_ERR|\ 279 DC_IMR_ABNORMAL|DC_IMR_NORMAL/*|DC_IMR_TX_EARLY*/) 280/* 281 * Serial I/O (EEPROM/ROM) bits. 282 */ 283#define DC_SIO_EE_CS 0x00000001 /* EEPROM chip select */ 284#define DC_SIO_EE_CLK 0x00000002 /* EEPROM clock */ 285#define DC_SIO_EE_DATAIN 0x00000004 /* EEPROM data output */ 286#define DC_SIO_EE_DATAOUT 0x00000008 /* EEPROM data input */ 287#define DC_SIO_ROMDATA4 0x00000010 288#define DC_SIO_ROMDATA5 0x00000020 289#define DC_SIO_ROMDATA6 0x00000040 290#define DC_SIO_ROMDATA7 0x00000080 291#define DC_SIO_EESEL 0x00000800 292#define DC_SIO_ROMSEL 0x00001000 293#define DC_SIO_ROMCTL_WRITE 0x00002000 294#define DC_SIO_ROMCTL_READ 0x00004000 295#define DC_SIO_MII_CLK 0x00010000 /* MDIO clock */ 296#define DC_SIO_MII_DATAOUT 0x00020000 /* MDIO data out */ 297#define DC_SIO_MII_DIR 0x00040000 /* MDIO dir */ 298#define DC_SIO_MII_DATAIN 0x00080000 /* MDIO data in */ 299 300#define DC_EECMD_WRITE 0x140 301#define DC_EECMD_READ 0x180 302#define DC_EECMD_ERASE 0x1c0 303 304#define DC_EE_NODEADDR_OFFSET 0x70 305#define DC_EE_NODEADDR 10 306 307/* 308 * General purpose timer register 309 * (upper 15 bits exist on rev 0x41 chips only) 310 */ 311#define DC_TIMER_CLKDIV 0x80000000 /* clock/16 */ 312#define DC_TIMER_TXTIMER 0x78000000 /* TX intr delay timer */ 313#define DC_TIMER_TXCOUNT 0x07000000 /* TX intr delay counter */ 314#define DC_TIMER_RXTIMER 0x00F00000 /* RX intr delay timer */ 315#define DC_TIMER_RXCOUNT 0x000E0000 /* RX intr delay counter */ 316#define DC_TIMER_CONTINUOUS 0x00010000 317#define DC_TIMER_VALUE 0x0000FFFF /* 81.92us */ 318 319/* 320 * 10baseT status register 321 */ 322#define DC_TSTAT_MIIACT 0x00000001 /* MII port activity */ 323#define DC_TSTAT_LS100 0x00000002 /* link status of 100baseTX */ 324#define DC_TSTAT_LS10 0x00000004 /* link status of 10baseT */ 325#define DC_TSTAT_AUTOPOLARITY 0x00000008 326#define DC_TSTAT_AUIACT 0x00000100 /* AUI activity */ 327#define DC_TSTAT_10BTACT 0x00000200 /* 10baseT activity */ 328#define DC_TSTAT_NSN 0x00000400 /* non-stable FLPs detected */ 329#define DC_TSTAT_REMFAULT 0x00000800 330#define DC_TSTAT_ANEGSTAT 0x00007000 331#define DC_TSTAT_LP_CAN_NWAY 0x00008000 /* link partner supports NWAY */ 332#define DC_TSTAT_LPCODEWORD 0xFFFF0000 /* link partner's code word */ 333 334#define DC_ASTAT_DISABLE 0x00000000 335#define DC_ASTAT_TXDISABLE 0x00001000 336#define DC_ASTAT_ABDETECT 0x00002000 337#define DC_ASTAT_ACKDETECT 0x00003000 338#define DC_ASTAT_CMPACKDETECT 0x00004000 339#define DC_ASTAT_AUTONEGCMP 0x00005000 340#define DC_ASTAT_LINKCHECK 0x00006000 341 342/* 343 * PHY reset register 344 */ 345#define DC_SIA_RESET 0x00000001 346#define DC_SIA_AUI 0x00000008 /* AUI or 10baseT */ 347 348/* 349 * 10baseT control register 350 */ 351#define DC_TCTL_ENCODER_ENB 0x00000001 352#define DC_TCTL_LOOPBACK 0x00000002 353#define DC_TCTL_DRIVER_ENB 0x00000004 354#define DC_TCTL_LNKPULSE_ENB 0x00000008 355#define DC_TCTL_HALFDUPLEX 0x00000040 356#define DC_TCTL_AUTONEGENBL 0x00000080 357#define DC_TCTL_RX_SQUELCH 0x00000100 358#define DC_TCTL_COLL_SQUELCH 0x00000200 359#define DC_TCTL_COLL_DETECT 0x00000400 360#define DC_TCTL_SQE_ENB 0x00000800 361#define DC_TCTL_LINKTEST 0x00001000 362#define DC_TCTL_AUTOPOLARITY 0x00002000 363#define DC_TCTL_SET_POL_PLUS 0x00004000 364#define DC_TCTL_AUTOSENSE 0x00008000 /* 10bt/AUI autosense */ 365#define DC_TCTL_100BTXHALF 0x00010000 366#define DC_TCTL_100BTXFULL 0x00020000 367#define DC_TCTL_100BT4 0x00040000 368 369/* 370 * Watchdog timer register 371 */ 372#define DC_WDOG_JABBERDIS 0x00000001 373#define DC_WDOG_HOSTUNJAB 0x00000002 374#define DC_WDOG_JABBERCLK 0x00000004 375#define DC_WDOG_RXWDOGDIS 0x00000010 376#define DC_WDOG_RXWDOGCLK 0x00000020 377#define DC_WDOG_MUSTBEZERO 0x00000100 378#define DC_WDOG_AUIBNC 0x00100000 379#define DC_WDOG_ACTIVITY 0x00200000 380#define DC_WDOG_LINK 0x00800000 381#define DC_WDOG_CTLWREN 0x08000000 382 383/* 384 * SIA and General Purpose Port register (X3201) 385 */ 386#define DC_SIAGP_RXMATCH 0x40000000 387#define DC_SIAGP_INT1 0x20000000 388#define DC_SIAGP_INT0 0x10000000 389#define DC_SIAGP_WRITE_EN 0x08000000 390#define DC_SIAGP_RXMATCH_EN 0x04000000 391#define DC_SIAGP_INT1_EN 0x02000000 392#define DC_SIAGP_INT0_EN 0x01000000 393#define DC_SIAGP_LED3 0x00800000 394#define DC_SIAGP_LED2 0x00400000 395#define DC_SIAGP_LED1 0x00200000 396#define DC_SIAGP_LED0 0x00100000 397#define DC_SIAGP_MD_GP3_OUTPUT 0x00080000 398#define DC_SIAGP_MD_GP2_OUTPUT 0x00040000 399#define DC_SIAGP_MD_GP1_OUTPUT 0x00020000 400#define DC_SIAGP_MD_GP0_OUTPUT 0x00010000 401 402/* 403 * Size of a setup frame. 404 */ 405#define DC_SFRAME_LEN 192 406 407/* 408 * 21x4x TX/RX list structure. 409 */ 410 411struct dc_desc { 412 u_int32_t dc_status; 413 u_int32_t dc_ctl; 414 u_int32_t dc_ptr1; 415 u_int32_t dc_ptr2; 416 u_int32_t dc_pad[4]; 417}; 418 419#define dc_data dc_ptr1 420#define dc_next dc_ptr2 421 422#define DC_RXSTAT_FIFOOFLOW 0x00000001 423#define DC_RXSTAT_CRCERR 0x00000002 424#define DC_RXSTAT_DRIBBLE 0x00000004 425#define DC_RXSTAT_MIIERE 0x00000008 426#define DC_RXSTAT_WATCHDOG 0x00000010 427#define DC_RXSTAT_FRAMETYPE 0x00000020 /* 0 == IEEE 802.3 */ 428#define DC_RXSTAT_COLLSEEN 0x00000040 429#define DC_RXSTAT_GIANT 0x00000080 430#define DC_RXSTAT_LASTFRAG 0x00000100 431#define DC_RXSTAT_FIRSTFRAG 0x00000200 432#define DC_RXSTAT_MULTICAST 0x00000400 433#define DC_RXSTAT_RUNT 0x00000800 434#define DC_RXSTAT_RXTYPE 0x00003000 435#define DC_RXSTAT_DE 0x00004000 436#define DC_RXSTAT_RXERR 0x00008000 437#define DC_RXSTAT_RXLEN 0x3FFF0000 438#define DC_RXSTAT_OWN 0x80000000 439 440#define DC_RXBYTES(x) ((x & DC_RXSTAT_RXLEN) >> 16) 441#define DC_RXSTAT (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG|DC_RXSTAT_OWN) 442 443#define DC_RXCTL_BUFLEN1 0x00000FFF 444#define DC_RXCTL_BUFLEN2 0x00FFF000 445#define DC_RXCTL_RLINK 0x01000000 446#define DC_RXCTL_RLAST 0x02000000 447 448#define DC_TXSTAT_DEFER 0x00000001 449#define DC_TXSTAT_UNDERRUN 0x00000002 450#define DC_TXSTAT_LINKFAIL 0x00000003 451#define DC_TXSTAT_COLLCNT 0x00000078 452#define DC_TXSTAT_SQE 0x00000080 453#define DC_TXSTAT_EXCESSCOLL 0x00000100 454#define DC_TXSTAT_LATECOLL 0x00000200 455#define DC_TXSTAT_NOCARRIER 0x00000400 456#define DC_TXSTAT_CARRLOST 0x00000800 457#define DC_TXSTAT_JABTIMEO 0x00004000 458#define DC_TXSTAT_ERRSUM 0x00008000 459#define DC_TXSTAT_OWN 0x80000000 460 461#define DC_TXCTL_BUFLEN1 0x000007FF 462#define DC_TXCTL_BUFLEN2 0x003FF800 463#define DC_TXCTL_FILTTYPE0 0x00400000 464#define DC_TXCTL_PAD 0x00800000 465#define DC_TXCTL_TLINK 0x01000000 466#define DC_TXCTL_TLAST 0x02000000 467#define DC_TXCTL_NOCRC 0x04000000 468#define DC_TXCTL_SETUP 0x08000000 469#define DC_TXCTL_FILTTYPE1 0x10000000 470#define DC_TXCTL_FIRSTFRAG 0x20000000 471#define DC_TXCTL_LASTFRAG 0x40000000 472#define DC_TXCTL_FINT 0x80000000 473 474#define DC_FILTER_PERFECT 0x00000000 475#define DC_FILTER_HASHPERF 0x00400000 476#define DC_FILTER_INVERSE 0x10000000 477#define DC_FILTER_HASHONLY 0x10400000 478 479#define DC_MAXFRAGS 16 480#define DC_RX_LIST_CNT 64 481#define DC_TX_LIST_CNT 256 482 483#define DC_INC(x, y) (x) = (x + 1) % y 484 485struct dc_list_data { 486 struct dc_desc dc_rx_list[DC_RX_LIST_CNT]; 487 struct dc_desc dc_tx_list[DC_TX_LIST_CNT]; 488 u_int32_t dc_sbuf[DC_SFRAME_LEN/sizeof(u_int32_t)]; 489 u_int8_t dc_pad[ETHER_MIN_LEN]; 490}; 491 492/* software descriptor */ 493struct dc_swdesc { 494 bus_dmamap_t sd_map; 495 struct mbuf *sd_mbuf; 496}; 497 498struct dc_chain_data { 499 struct dc_swdesc dc_rx_chain[DC_RX_LIST_CNT]; 500 struct dc_swdesc dc_tx_chain[DC_TX_LIST_CNT]; 501 int dc_tx_prod; 502 int dc_tx_cons; 503 int dc_tx_cnt; 504 int dc_rx_prod; 505}; 506 507struct dc_mediainfo { 508 uint64_t dc_media; 509 u_int8_t *dc_gp_ptr; 510 u_int8_t dc_gp_len; 511 u_int8_t *dc_reset_ptr; 512 u_int8_t dc_reset_len; 513 struct dc_mediainfo *dc_next; 514}; 515 516struct dc_type { 517 u_int16_t dc_vid; 518 u_int16_t dc_did; 519}; 520 521struct dc_mii_frame { 522 u_int8_t mii_stdelim; 523 u_int8_t mii_opcode; 524 u_int8_t mii_phyaddr; 525 u_int8_t mii_regaddr; 526 u_int8_t mii_turnaround; 527 u_int16_t mii_data; 528}; 529 530/* 531 * MII constants 532 */ 533#define DC_MII_STARTDELIM 0x01 534#define DC_MII_READOP 0x02 535#define DC_MII_WRITEOP 0x01 536#define DC_MII_TURNAROUND 0x02 537 538 539/* 540 * Registers specific to clone devices. 541 * This mainly relates to RX filter programming: not all 21x4x clones 542 * use the standard DEC filter programming mechanism. 543 */ 544 545/* 546 * ADMtek specific registers and constants for the AL981 and AN983. 547 * The AN983 doesn't use the magic PHY registers. 548 */ 549#define DC_AL_CR 0x88 /* Command register */ 550#define DC_AL_PAR0 0xA4 /* station address */ 551#define DC_AL_PAR1 0xA8 /* station address */ 552#define DC_AL_MAR0 0xAC /* multicast hash filter */ 553#define DC_AL_MAR1 0xB0 /* multicast hash filter */ 554#define DC_AL_BMCR 0xB4 /* built in PHY control */ 555#define DC_AL_BMSR 0xB8 /* built in PHY status */ 556#define DC_AL_VENID 0xBC /* built in PHY ID0 */ 557#define DC_AL_DEVID 0xC0 /* built in PHY ID1 */ 558#define DC_AL_ANAR 0xC4 /* built in PHY autoneg advert */ 559#define DC_AL_LPAR 0xC8 /* bnilt in PHY link part. ability */ 560#define DC_AL_ANER 0xCC /* built in PHY autoneg expansion */ 561 562#define DC_ADMTEK_PHYADDR 0x1 563#define DC_AL_EE_NODEADDR 8 564#define DC_AL_CR_ATUR 0x00000001 /* Enable automatic TX underrun recovery */ 565/* End of ADMtek specific registers */ 566 567/* 568 * ASIX specific registers. 569 */ 570#define DC_AX_FILTIDX 0x68 /* RX filter index */ 571#define DC_AX_FILTDATA 0x70 /* RX filter data */ 572 573/* 574 * Special ASIX-specific bits in the ASIX NETCFG register (CSR6). 575 */ 576#define DC_AX_NETCFG_RX_BROAD 0x00000100 577 578/* 579 * RX Filter Index Register values 580 */ 581#define DC_AX_FILTIDX_PAR0 0x00000000 582#define DC_AX_FILTIDX_PAR1 0x00000001 583#define DC_AX_FILTIDX_MAR0 0x00000002 584#define DC_AX_FILTIDX_MAR1 0x00000003 585/* End of ASIX specific registers */ 586 587/* 588 * Macronix specific registers. The Macronix chips have a special 589 * register for reading the NWAY status, which we don't use, plus 590 * a magic packet register, which we need to tweak a bit per the 591 * Macronix application notes. 592 */ 593#define DC_MX_MAGICPACKET 0x80 594#define DC_MX_NWAYSTAT 0xA0 595 596/* 597 * Magic packet register 598 */ 599#define DC_MX_MPACK_DISABLE 0x00400000 600 601/* 602 * NWAY status register. 603 */ 604#define DC_MX_NWAY_10BTHALF 0x08000000 605#define DC_MX_NWAY_10BTFULL 0x10000000 606#define DC_MX_NWAY_100BTHALF 0x20000000 607#define DC_MX_NWAY_100BTFULL 0x40000000 608#define DC_MX_NWAY_100BT4 0x80000000 609 610/* 611 * These are magic values that must be written into CSR16 612 * (DC_MX_MAGICPACKET) in order to put the chip into proper 613 * operating mode. The magic numbers are documented in the 614 * Macronix 98715 application notes. 615 */ 616#define DC_MX_MAGIC_98713 0x0F370000 617#define DC_MX_MAGIC_98713A 0x0B3C0000 618#define DC_MX_MAGIC_98715 0x0B3C0000 619#define DC_MX_MAGIC_98725 0x0B3C0000 620/* End of Macronix specific registers */ 621 622/* 623 * PNIC 82c168/82c169 specific registers. 624 * The PNIC has its own special NWAY support, which doesn't work, 625 * and shortcut ways of reading the EEPROM and MII bus. 626 */ 627#define DC_PN_GPIO 0x60 /* general purpose pins control */ 628#define DC_PN_PWRUP_CFG 0x90 /* config register, set by EEPROM */ 629#define DC_PN_SIOCTL 0x98 /* serial EEPROM control register */ 630#define DC_PN_MII 0xA0 /* MII access register */ 631#define DC_PN_NWAY 0xB8 /* Internal NWAY register */ 632 633/* Serial I/O EEPROM register */ 634#define DC_PN_SIOCTL_DATA 0x0000003F 635#define DC_PN_SIOCTL_OPCODE 0x00000300 636#define DC_PN_SIOCTL_BUSY 0x80000000 637 638#define DC_PN_EEOPCODE_ERASE 0x00000300 639#define DC_PN_EEOPCODE_READ 0x00000600 640#define DC_PN_EEOPCODE_WRITE 0x00000100 641 642/* 643 * The first two general purpose pins control speed selection and 644 * 100Mbps loopback on the 82c168 chip. The control bits should always 645 * be set (to make the data pins outputs) and the speed selection and 646 * loopback bits set accordingly when changing media. Physically, this 647 * will set the state of a relay mounted on the card. 648 */ 649#define DC_PN_GPIO_DATA0 0x000000001 650#define DC_PN_GPIO_DATA1 0x000000002 651#define DC_PN_GPIO_DATA2 0x000000004 652#define DC_PN_GPIO_DATA3 0x000000008 653#define DC_PN_GPIO_CTL0 0x000000010 654#define DC_PN_GPIO_CTL1 0x000000020 655#define DC_PN_GPIO_CTL2 0x000000040 656#define DC_PN_GPIO_CTL3 0x000000080 657#define DC_PN_GPIO_SPEEDSEL DC_PN_GPIO_DATA0/* 1 == 100Mbps, 0 == 10Mbps */ 658#define DC_PN_GPIO_100TX_LOOP DC_PN_GPIO_DATA1/* 1 == normal, 0 == loop */ 659#define DC_PN_GPIO_BNC_ENB DC_PN_GPIO_DATA2 660#define DC_PN_GPIO_100TX_LNK DC_PN_GPIO_DATA3 661#define DC_PN_GPIO_SETBIT(sc, r) \ 662 DC_SETBIT(sc, DC_PN_GPIO, ((r) | (r << 4))) 663#define DC_PN_GPIO_CLRBIT(sc, r) \ 664 { \ 665 DC_SETBIT(sc, DC_PN_GPIO, ((r) << 4)); \ 666 DC_CLRBIT(sc, DC_PN_GPIO, (r)); \ 667 } 668 669/* shortcut MII access register */ 670#define DC_PN_MII_DATA 0x0000FFFF 671#define DC_PN_MII_RESERVER 0x00020000 672#define DC_PN_MII_REGADDR 0x007C0000 673#define DC_PN_MII_PHYADDR 0x0F800000 674#define DC_PN_MII_OPCODE 0x30000000 675#define DC_PN_MII_BUSY 0x80000000 676 677#define DC_PN_MIIOPCODE_READ 0x60020000 678#define DC_PN_MIIOPCODE_WRITE 0x50020000 679 680/* Internal NWAY bits */ 681#define DC_PN_NWAY_RESET 0x00000001 /* reset */ 682#define DC_PN_NWAY_PDOWN 0x00000002 /* power down */ 683#define DC_PN_NWAY_BYPASS 0x00000004 /* bypass */ 684#define DC_PN_NWAY_AUILOWCUR 0x00000008 /* AUI low current */ 685#define DC_PN_NWAY_TPEXTEND 0x00000010 /* low squelch voltage */ 686#define DC_PN_NWAY_POLARITY 0x00000020 /* 0 == on, 1 == off */ 687#define DC_PN_NWAY_TP 0x00000040 /* 1 == tp, 0 == AUI */ 688#define DC_PN_NWAY_AUIVOLT 0x00000080 /* 1 == full, 0 == half */ 689#define DC_PN_NWAY_DUPLEX 0x00000100 /* LED, 1 == full, 0 == half */ 690#define DC_PN_NWAY_LINKTEST 0x00000200 /* 0 == on, 1 == off */ 691#define DC_PN_NWAY_AUTODETECT 0x00000400 /* 1 == off, 0 == on */ 692#define DC_PN_NWAY_SPEEDSEL 0x00000800 /* LED, 0 = 10, 1 == 100 */ 693#define DC_PN_NWAY_NWAY_ENB 0x00001000 /* 0 == off, 1 == on */ 694#define DC_PN_NWAY_CAP10HDX 0x00002000 695#define DC_PN_NWAY_CAP10FDX 0x00004000 696#define DC_PN_NWAY_CAP100FDX 0x00008000 697#define DC_PN_NWAY_CAP100HDX 0x00010000 698#define DC_PN_NWAY_CAP100T4 0x00020000 699#define DC_PN_NWAY_ANEGRESTART 0x02000000 /* resets when aneg done */ 700#define DC_PN_NWAY_REMFAULT 0x04000000 701#define DC_PN_NWAY_LPAR10HDX 0x08000000 702#define DC_PN_NWAY_LPAR10FDX 0x10000000 703#define DC_PN_NWAY_LPAR100FDX 0x20000000 704#define DC_PN_NWAY_LPAR100HDX 0x40000000 705#define DC_PN_NWAY_LPAR100T4 0x80000000 706 707/* End of PNIC specific registers */ 708 709/* 710 * CONEXANT specific registers. 711 */ 712 713#define DC_CONEXANT_PHYADDR 0x1 714#define DC_CONEXANT_EE_NODEADDR 0x19A 715 716/* End of CONEXANT specific register */ 717 718struct dc_softc { 719 struct device sc_dev; 720 void *sc_ih; 721 struct arpcom sc_arpcom; /* interface info */ 722 mii_data_t sc_mii; 723 bus_space_handle_t dc_bhandle; /* bus space handle */ 724 bus_space_tag_t dc_btag; /* bus space tag */ 725 u_int8_t dc_type; 726 u_int8_t dc_pmode; 727 u_int8_t dc_link; 728 u_int8_t dc_cachesize; 729 int dc_romwidth; 730 int dc_pnic_rx_bug_save; 731 unsigned char *dc_pnic_rx_buf; 732 uint64_t dc_if_media; 733 u_int32_t dc_flags; 734 u_int32_t dc_txthresh; 735 u_int8_t *dc_srom; 736 size_t dc_sromsize; 737 struct dc_mediainfo *dc_mi; 738 struct dc_list_data *dc_ldata; 739 struct dc_chain_data dc_cdata; 740 u_int32_t dc_csid; 741 u_int dc_revision; 742 struct timeout dc_tick_tmo; 743#ifdef SRM_MEDIA 744 uint64_t dc_srm_media; 745#endif 746 bus_dma_tag_t sc_dmat; 747 bus_dmamap_t sc_listmap; 748 bus_dma_segment_t sc_listseg[1]; 749 int sc_listnseg; 750 caddr_t sc_listkva; 751 bus_dmamap_t sc_rx_sparemap; 752 bus_dmamap_t sc_tx_sparemap; 753 int sc_hasmac; 754}; 755 756#define DC_TX_POLL 0x00000001 757#define DC_TX_COALESCE 0x00000002 758#define DC_TX_ADMTEK_WAR 0x00000004 759#define DC_TX_USE_TX_INTR 0x00000008 760#define DC_RX_FILTER_TULIP 0x00000010 761#define DC_TX_INTR_FIRSTFRAG 0x00000020 762#define DC_PNIC_RX_BUG_WAR 0x00000040 763#define DC_TX_FIXED_RING 0x00000080 764#define DC_TX_STORENFWD 0x00000100 765#define DC_REDUCED_MII_POLL 0x00000200 766#define DC_TX_INTR_ALWAYS 0x00000400 767#define DC_21143_NWAY 0x00000800 768#define DC_128BIT_HASH 0x00001000 769#define DC_64BIT_HASH 0x00002000 770#define DC_TULIP_LEDS 0x00004000 771#define DC_TX_ONE 0x00008000 772#define DC_TX_ALIGN 0x00010000 /* align mbuf on tx */ 773#define DC_MOMENCO_BOTCH 0x00020000 774 775/* 776 * register space access macros 777 */ 778#define CSR_WRITE_4(sc, reg, val) \ 779 bus_space_write_4(sc->dc_btag, sc->dc_bhandle, reg, val) 780 781#define CSR_READ_4(sc, reg) \ 782 bus_space_read_4(sc->dc_btag, sc->dc_bhandle, reg) 783 784#define DC_TIMEOUT 1000 785 786/* 787 * General constants that are fun to know. 788 */ 789 790/* Macronix PCI revision codes. */ 791#define DC_REVISION_98713 0x00 792#define DC_REVISION_98713A 0x10 793#define DC_REVISION_98715 0x20 794#define DC_REVISION_98715AEC_C 0x25 795#define DC_REVISION_98725 0x30 796 797/* 798 * 82c168/82c169 PNIC device IDs. Both chips have the same device 799 * ID but different revisions. Revision 0x10 is the 82c168, and 800 * 0x20 is the 82c169. 801 */ 802#define DC_REVISION_82C168 0x10 803#define DC_REVISION_82C169 0x20 804 805/* 806 * The ASIX AX88140 and ASIX AX88141 have the same vendor and 807 * device IDs but different revision values. 808 */ 809#define DC_REVISION_88140 0x00 810#define DC_REVISION_88141 0x10 811 812/* 813 * The DMA9102A has the same PCI device ID as the DM9102, 814 * but a higher revision code. 815 */ 816#define DC_REVISION_DM9102 0x10 817#define DC_REVISION_DM9102A 0x30 818 819/* 820 * PCI low memory base and low I/O base register, and 821 * other PCI registers. 822 */ 823 824#define DC_PCI_CFID 0x00 /* Id */ 825#define DC_PCI_CFCS 0x04 /* Command and status */ 826#define DC_PCI_CFRV 0x08 /* Revision */ 827#define DC_PCI_CFLT 0x0C /* Latency timer */ 828#define DC_PCI_CFBIO 0x10 /* Base I/O address */ 829#define DC_PCI_CFBMA 0x14 /* Base memory address */ 830#define DC_PCI_CCIS 0x28 /* Card info struct */ 831#define DC_PCI_CSID 0x2C /* Subsystem ID */ 832#define DC_PCI_CBER 0x30 /* Expansion ROM base address */ 833#define DC_PCI_CCAP 0x34 /* Caps pointer - PD/TD chip only */ 834#define DC_PCI_CFIT 0x3C /* Interrupt */ 835#define DC_PCI_CFDD 0x40 /* Device and driver area */ 836#define DC_PCI_CWUA0 0x44 /* Wake-Up LAN addr 0 */ 837#define DC_PCI_CWUA1 0x48 /* Wake-Up LAN addr 1 */ 838#define DC_PCI_SOP0 0x4C /* SecureON passwd 0 */ 839#define DC_PCI_SOP1 0x50 /* SecureON passwd 1 */ 840#define DC_PCI_CWUC 0x54 /* Configuration Wake-Up cmd */ 841#define DC_PCI_CCID 0xDC /* Capability ID - PD/TD only */ 842#define DC_PCI_CPMC 0xE0 /* Pwrmgmt ctl & sts - PD/TD only */ 843 844/* PCI ID register */ 845#define DC_CFID_VENDOR 0x0000FFFF 846#define DC_CFID_DEVICE 0xFFFF0000 847 848/* PCI command/status register */ 849#define DC_CFCS_IOSPACE 0x00000001 /* I/O space enable */ 850#define DC_CFCS_MEMSPACE 0x00000002 /* memory space enable */ 851#define DC_CFCS_BUSMASTER 0x00000004 /* bus master enable */ 852#define DC_CFCS_MWI_ENB 0x00000010 /* mem write and inval enable */ 853#define DC_CFCS_PARITYERR_ENB 0x00000040 /* parity error enable */ 854#define DC_CFCS_SYSERR_ENB 0x00000100 /* system error enable */ 855#define DC_CFCS_NEWCAPS 0x00100000 /* new capabilities */ 856#define DC_CFCS_FAST_B2B 0x00800000 /* fast back-to-back capable */ 857#define DC_CFCS_DATAPARITY 0x01000000 /* Parity error report */ 858#define DC_CFCS_DEVSELTIM 0x06000000 /* devsel timing */ 859#define DC_CFCS_TGTABRT 0x10000000 /* received target abort */ 860#define DC_CFCS_MASTERABRT 0x20000000 /* received master abort */ 861#define DC_CFCS_SYSERR 0x40000000 /* asserted system error */ 862#define DC_CFCS_PARITYERR 0x80000000 /* asserted parity error */ 863 864/* PCI revision register */ 865#define DC_CFRV_STEPPING 0x0000000F 866#define DC_CFRV_REVISION 0x000000F0 867#define DC_CFRV_SUBCLASS 0x00FF0000 868#define DC_CFRV_BASECLASS 0xFF000000 869 870#define DC_21143_PB_REV 0x00000030 871#define DC_21143_TB_REV 0x00000030 872#define DC_21143_PC_REV 0x00000030 873#define DC_21143_TC_REV 0x00000030 874#define DC_21143_PD_REV 0x00000041 875#define DC_21143_TD_REV 0x00000041 876 877/* PCI latency timer register */ 878#define DC_CFLT_CACHELINESIZE 0x000000FF 879#define DC_CFLT_LATENCYTIMER 0x0000FF00 880 881/* PCI subsystem ID register */ 882#define DC_CSID_VENDOR 0x0000FFFF 883#define DC_CSID_DEVICE 0xFFFF0000 884 885/* PCI capabilities pointer */ 886#define DC_CCAP_OFFSET 0x000000FF 887 888/* PCI interrupt config register */ 889#define DC_CFIT_INTLINE 0x000000FF 890#define DC_CFIT_INTPIN 0x0000FF00 891#define DC_CFIT_MIN_GNT 0x00FF0000 892#define DC_CFIT_MAX_LAT 0xFF000000 893 894/* PCI capability register */ 895#define DC_CCID_CAPID 0x000000FF 896#define DC_CCID_NEXTPTR 0x0000FF00 897#define DC_CCID_PM_VERS 0x00070000 898#define DC_CCID_PME_CLK 0x00080000 899#define DC_CCID_DVSPEC_INT 0x00200000 900#define DC_CCID_STATE_D1 0x02000000 901#define DC_CCID_STATE_D2 0x04000000 902#define DC_CCID_PME_D0 0x08000000 903#define DC_CCID_PME_D1 0x10000000 904#define DC_CCID_PME_D2 0x20000000 905#define DC_CCID_PME_D3HOT 0x40000000 906#define DC_CCID_PME_D3COLD 0x80000000 907 908/* PCI power management control/status register */ 909#define DC_CPMC_STATE 0x00000003 910#define DC_CPMC_PME_ENB 0x00000100 911#define DC_CPMC_PME_STS 0x00008000 912 913#define DC_PSTATE_D0 0x0 914#define DC_PSTATE_D1 0x1 915#define DC_PSTATE_D2 0x2 916#define DC_PSTATE_D3 0x3 917 918/* Device specific region */ 919/* Configuration and driver area */ 920#define DC_CFDD_DRVUSE 0x0000FFFF 921#define DC_CFDD_SNOOZE_MODE 0x40000000 922#define DC_CFDD_SLEEP_MODE 0x80000000 923 924/* Configuration wake-up command register */ 925#define DC_CWUC_MUST_BE_ZERO 0x00000001 926#define DC_CWUC_SECUREON_ENB 0x00000002 927#define DC_CWUC_FORCE_WUL 0x00000004 928#define DC_CWUC_BNC_ABILITY 0x00000008 929#define DC_CWUC_AUI_ABILITY 0x00000010 930#define DC_CWUC_TP10_ABILITY 0x00000020 931#define DC_CWUC_MII_ABILITY 0x00000040 932#define DC_CWUC_SYM_ABILITY 0x00000080 933#define DC_CWUC_LOCK 0x00000100 934 935/* 936 * SROM nonsense. 937 */ 938 939#define DC_IB_CTLRCNT 0x13 940#define DC_IB_LEAF0_CNUM 0x1A 941#define DC_IB_LEAF0_OFFSET 0x1B 942 943struct dc_info_leaf { 944 u_int16_t dc_conntype; 945 u_int8_t dc_blkcnt; 946 u_int8_t dc_rsvd; 947 u_int16_t dc_infoblk; 948}; 949 950#define DC_CTYPE_10BT 0x0000 951#define DC_CTYPE_10BT_NWAY 0x0100 952#define DC_CTYPE_10BT_FDX 0x0204 953#define DC_CTYPE_10B2 0x0001 954#define DC_CTYPE_10B5 0x0002 955#define DC_CTYPE_100BT 0x0003 956#define DC_CTYPE_100BT_FDX 0x0205 957#define DC_CTYPE_100T4 0x0006 958#define DC_CTYPE_100FX 0x0007 959#define DC_CTYPE_100FX_FDX 0x0208 960#define DC_CTYPE_MII_10BT 0x0009 961#define DC_CTYPE_MII_10BT_FDX 0x020A 962#define DC_CTYPE_MII_100BT 0x000D 963#define DC_CTYPE_MII_100BT_FDX 0x020E 964#define DC_CTYPE_MII_100T4 0x000F 965#define DC_CTYPE_MII_100FX 0x0010 966#define DC_CTYPE_MII_100FX_FDX 0x0211 967#define DC_CTYPE_DYN_PUP_AUTOSENSE 0x0800 968#define DC_CTYPE_PUP_AUTOSENSE 0x8800 969#define DC_CTYPE_NOMEDIA 0xFFFF 970 971#define DC_EBLOCK_SIA 0x0002 972#define DC_EBLOCK_MII 0x0003 973#define DC_EBLOCK_SYM 0x0004 974#define DC_EBLOCK_RESET 0x0005 975#define DC_EBLOCK_PHY_SHUTDOWN 0x0006 976 977struct dc_leaf_hdr { 978 u_int16_t dc_mtype; 979 u_int8_t dc_mcnt; 980 u_int8_t dc_rsvd; 981}; 982 983struct dc_eblock_hdr { 984 u_int8_t dc_len; 985 u_int8_t dc_type; 986}; 987 988struct dc_eblock_sia { 989 struct dc_eblock_hdr dc_sia_hdr; 990 u_int8_t dc_sia_code; 991 union { 992 struct dc_sia_ext { /* if (dc_sia_code & DC_SIA_CODE_EXT) */ 993 u_int8_t dc_sia_mediaspec[6]; /* CSR13, CSR14, CSR15 */ 994 u_int8_t dc_sia_gpio_ctl[2]; 995 u_int8_t dc_sia_gpio_dat[2]; 996 } dc_sia_ext; 997 struct dc_sia_noext { 998 u_int8_t dc_sia_gpio_ctl[2]; 999 u_int8_t dc_sia_gpio_dat[2]; 1000 } dc_sia_noext; 1001 } dc_un; 1002}; 1003 1004#define DC_SIA_CODE_10BT 0x00 1005#define DC_SIA_CODE_10B2 0x01 1006#define DC_SIA_CODE_10B5 0x02 1007#define DC_SIA_CODE_10BT_FDX 0x04 1008#define DC_SIA_CODE_EXT 0x40 1009 1010/* 1011 * Note that the first word in the gpr and reset 1012 * sequences is always a control word. 1013 */ 1014struct dc_eblock_mii { 1015 struct dc_eblock_hdr dc_mii_hdr; 1016 u_int8_t dc_mii_phynum; 1017 u_int8_t dc_gpr_len; 1018/* u_int16_t dc_gpr_dat[n]; */ 1019/* u_int8_t dc_reset_len; */ 1020/* u_int16_t dc_reset_dat[n]; */ 1021/* There are other fields after these, but we don't 1022 * care about them since they can be determined by looking 1023 * at the PHY. 1024 */ 1025}; 1026 1027struct dc_eblock_sym { 1028 struct dc_eblock_hdr dc_sym_hdr; 1029 u_int8_t dc_sym_code; 1030 u_int8_t dc_sym_gpio_ctl[2]; 1031 u_int8_t dc_sym_gpio_dat[2]; 1032 u_int8_t dc_sym_cmd[2]; 1033}; 1034 1035#define DC_SYM_CODE_100BT 0x03 1036#define DC_SYM_CODE_100BT_FDX 0x05 1037#define DC_SYM_CODE_100T4 0x06 1038#define DC_SYM_CODE_100FX 0x07 1039#define DC_SYM_CODE_100FX_FDX 0x08 1040 1041struct dc_eblock_reset { 1042 struct dc_eblock_hdr dc_reset_hdr; 1043 u_int8_t dc_reset_len; 1044/* u_int16_t dc_reset_dat[n]; */ 1045}; 1046 1047extern void dc_attach(struct dc_softc *); 1048extern int dc_detach(struct dc_softc *); 1049extern int dc_activate(struct device *, int); 1050extern int dc_intr(void *); 1051 1052void dc_init(void *); 1053void dc_stop(struct dc_softc *, int); 1054 1055extern void dc_reset(struct dc_softc *); 1056extern void dc_eeprom_width(struct dc_softc *); 1057extern void dc_read_srom(struct dc_softc *, int); 1058extern void dc_parse_21143_srom(struct dc_softc *); 1059 1060#if BYTE_ORDER == BIG_ENDIAN 1061#define DC_SP_FIELD_C(x) ((x) << 16) 1062#else 1063#define DC_SP_FIELD_C(x) (x) 1064#endif 1065#define DC_SP_FIELD(x,f) DC_SP_FIELD_C(((u_int16_t *)(x))[(f)]) 1066