ar5008reg.h revision 1.5
1/* $OpenBSD: ar5008reg.h,v 1.5 2017/11/28 04:33:03 stsp Exp $ */ 2 3/*- 4 * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2008-2009 Atheros Communications Inc. 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20/* 21 * MAC registers. 22 */ 23#define AR_ISR_S2_S 0x00cc 24#define AR_ISR_S3_S 0x00d0 25#define AR_ISR_S4_S 0x00d4 26#define AR_ISR_S5_S 0x00d8 27#define AR_GPIO_IN_OUT 0x4048 28#define AR_GPIO_OE_OUT 0x404c 29#define AR_GPIO_INTR_POL 0x4050 30#define AR_GPIO_INPUT_EN_VAL 0x4054 31#define AR_GPIO_INPUT_MUX1 0x4058 32#define AR_GPIO_INPUT_MUX2 0x405c 33#define AR_GPIO_OUTPUT_MUX(i) (0x4060 + (i) * 4) 34#define AR_INPUT_STATE 0x406c 35#define AR_EEPROM_STATUS_DATA 0x407c 36#define AR_OBS 0x4080 37#define AR_GPIO_PDPU 0x4088 38#define AR_PCIE_MSI 0x4094 39 40/* 41 * Analog registers. 42 */ 43#define AR_IS_ANALOG_REG(reg) ((reg) >= 0x7800 && (reg) <= 0x78b4) 44#define AR_AN_RF2G1_CH0 0x7810 45#define AR_AN_RF5G1_CH0 0x7818 46#define AR_AN_RF2G1_CH1 0x7834 47#define AR_AN_RF5G1_CH1 0x783c 48#define AR_AN_SYNTH9 0x7868 49#define AR_AN_TOP1 0x7890 50#define AR_AN_TOP2 0x7894 51 52/* 53 * PHY registers. 54 */ 55#define AR_PHY_BASE 0x9800 56#define AR_PHY(i) (AR_PHY_BASE + (i) * 4) 57#define AR_PHY_TEST 0x9800 58#define AR_PHY_TURBO 0x9804 59#define AR_PHY_TEST2 0x9808 60#define AR_PHY_TIMING2 0x9810 61#define AR_PHY_TIMING3 0x9814 62#define AR_PHY_CHIP_ID 0x9818 63#define AR_PHY_ACTIVE 0x981c 64#define AR_PHY_RF_CTL2 0x9824 65#define AR_PHY_RF_CTL3 0x9828 66#define AR_PHY_ADC_CTL 0x982c 67#define AR_PHY_ADC_SERIAL_CTL 0x9830 68#define AR_PHY_RF_CTL4 0x9834 69#define AR_PHY_TSTDAC_CONST 0x983c 70#define AR_PHY_SETTLING 0x9844 71#define AR_PHY_RXGAIN 0x9848 72#define AR_PHY_DESIRED_SZ 0x9850 73#define AR_PHY_FIND_SIG 0x9858 74#define AR_PHY_AGC_CTL1 0x985c 75#define AR_PHY_AGC_CONTROL 0x9860 76#define AR_PHY_CCA(i) (0x9864 + (i) * 0x1000) 77#define AR_PHY_SFCORR 0x9868 78#define AR_PHY_SFCORR_LOW 0x986c 79#define AR_PHY_SLEEP_CTR_CONTROL 0x9870 80#define AR_PHY_SLEEP_CTR_LIMIT 0x9874 81#define AR_PHY_SLEEP_SCAL 0x9878 82#define AR_PHY_PLL_CTL 0x987c 83#define AR_PHY_BIN_MASK_1 0x9900 84#define AR_PHY_BIN_MASK_2 0x9904 85#define AR_PHY_BIN_MASK_3 0x9908 86#define AR_PHY_MASK_CTL 0x990c 87#define AR_PHY_RX_DELAY 0x9914 88#define AR_PHY_SEARCH_START_DELAY 0x9918 89#define AR_PHY_TIMING_CTRL4_0 0x9920 90#define AR_PHY_TIMING_CTRL4(i) (0x9920 + (i) * 0x1000) 91#define AR_PHY_TIMING5 0x9924 92#define AR_PHY_POWER_TX_RATE1 0x9934 93#define AR_PHY_POWER_TX_RATE2 0x9938 94#define AR_PHY_POWER_TX_RATE_MAX 0x993c 95#define AR_PHY_RADAR_EXT 0x9940 96#define AR_PHY_FRAME_CTL 0x9944 97#define AR_PHY_SPUR_REG 0x994c 98#define AR_PHY_RADAR_0 0x9954 99#define AR_PHY_RADAR_1 0x9958 100#define AR_PHY_SWITCH_CHAIN_0 0x9960 101#define AR_PHY_SWITCH_COM 0x9964 102#define AR_PHY_SIGMA_DELTA 0x996c 103#define AR_PHY_RESTART 0x9970 104#define AR_PHY_RFBUS_REQ 0x997c 105#define AR_PHY_TIMING7 0x9980 106#define AR_PHY_TIMING8 0x9984 107#define AR_PHY_BIN_MASK2_1 0x9988 108#define AR_PHY_BIN_MASK2_2 0x998c 109#define AR_PHY_BIN_MASK2_3 0x9990 110#define AR_PHY_BIN_MASK2_4 0x9994 111#define AR_PHY_TIMING9 0x9998 112#define AR_PHY_TIMING10 0x999c 113#define AR_PHY_TIMING11 0x99a0 114#define AR_PHY_RX_CHAINMASK 0x99a4 115#define AR_PHY_MULTICHAIN_GAIN_CTL 0x99ac 116#define AR_PHY_NEW_ADC_DC_GAIN_CORR(i) (0x99b4 + (i) * 0x1000) 117#define AR_PHY_EXT_CCA0 0x99b8 118#define AR_PHY_EXT_CCA(i) (0x99bc + (i) * 0x1000) 119#define AR_PHY_SFCORR_EXT 0x99c0 120#define AR_PHY_HALFGI 0x99d0 121#define AR_PHY_CHANNEL_MASK_01_30 0x99d4 122#define AR_PHY_CHANNEL_MASK_31_60 0x99d8 123#define AR_PHY_CHAN_INFO_MEMORY 0x99dc 124#define AR_PHY_HEAVY_CLIP_ENABLE 0x99e0 125#define AR_PHY_HEAVY_CLIP_FACTOR_RIFS 0x99ec 126#define AR_PHY_CALMODE 0x99f0 127#define AR_PHY_REFCLKDLY 0x99f4 128#define AR_PHY_REFCLKPD 0x99f8 129#define AR_PHY_BB_RFGAIN(i) (0x9a00 + (i) * 4) 130#define AR_PHY_CAL_MEAS_0(i) (0x9c10 + (i) * 0x1000) 131#define AR_PHY_CAL_MEAS_1(i) (0x9c14 + (i) * 0x1000) 132#define AR_PHY_CAL_MEAS_2(i) (0x9c18 + (i) * 0x1000) 133#define AR_PHY_CAL_MEAS_3(i) (0x9c1c + (i) * 0x1000) 134#define AR_PHY_CURRENT_RSSI 0x9c1c 135#define AR_PHY_RFBUS_GRANT 0x9c20 136#define AR9280_PHY_CURRENT_RSSI 0x9c3c 137#define AR_PHY_CHAN_INFO_GAIN_DIFF 0x9cf4 138#define AR_PHY_CHAN_INFO_GAIN 0x9cfc 139#define AR_PHY_MODE 0xa200 140#define AR_PHY_CCK_TX_CTRL 0xa204 141#define AR_PHY_CCK_DETECT 0xa208 142#define AR_PHY_GAIN_2GHZ 0xa20c 143#define AR_PHY_CCK_RXCTRL4 0xa21c 144#define AR_PHY_DAG_CTRLCCK 0xa228 145#define AR_PHY_FORCE_CLKEN_CCK 0xa22c 146#define AR_PHY_POWER_TX_RATE3 0xa234 147#define AR_PHY_POWER_TX_RATE4 0xa238 148#define AR_PHY_SCRM_SEQ_XR 0xa23c 149#define AR_PHY_HEADER_DETECT_XR 0xa240 150#define AR_PHY_CHIRP_DETECTED_XR 0xa244 151#define AR_PHY_BLUETOOTH 0xa254 152#define AR_PHY_TPCRG1 0xa258 153#define AR_PHY_TX_PWRCTRL4 0xa264 154#define AR_PHY_ANALOG_SWAP 0xa268 155#define AR_PHY_TPCRG5 0xa26c 156#define AR_PHY_TX_PWRCTRL6_0 0xa270 157#define AR_PHY_TX_PWRCTRL7 0xa274 158#define AR_PHY_TX_PWRCTRL9 0xa27c 159#define AR_PHY_PDADC_TBL_BASE 0xa280 160#define AR_PHY_TX_GAIN_TBL(i) (0xa300 + (i) * 4) 161#define AR_PHY_CL_CAL_CTL 0xa358 162#define AR_PHY_CLC_TBL(i) (0xa35c + (i) * 4) 163#define AR_PHY_POWER_TX_RATE5 0xa38c 164#define AR_PHY_POWER_TX_RATE6 0xa390 165#define AR_PHY_CH0_TX_PWRCTRL11 0xa398 166#define AR_PHY_CAL_CHAINMASK 0xa39c 167#define AR_PHY_VIT_MASK2_M_46_61 0xa3a0 168#define AR_PHY_VIT_MASK2_M_31_45 0xa3a4 169#define AR_PHY_VIT_MASK2_M_16_30 0xa3a8 170#define AR_PHY_VIT_MASK2_M_00_15 0xa3ac 171#define AR_PHY_PILOT_MASK_01_30 0xa3b0 172#define AR_PHY_PILOT_MASK_31_60 0xa3b4 173#define AR_PHY_VIT_MASK2_P_15_01 0xa3b8 174#define AR_PHY_VIT_MASK2_P_30_16 0xa3bc 175#define AR_PHY_VIT_MASK2_P_45_31 0xa3c0 176#define AR_PHY_VIT_MASK2_P_61_46 0xa3c4 177#define AR_PHY_POWER_TX_SUB 0xa3c8 178#define AR_PHY_POWER_TX_RATE7 0xa3cc 179#define AR_PHY_POWER_TX_RATE8 0xa3d0 180#define AR_PHY_POWER_TX_RATE9 0xa3d4 181#define AR_PHY_XPA_CFG 0xa3d8 182#define AR_PHY_TX_PWRCTRL6_1 0xb270 183#define AR_PHY_CH1_TX_PWRCTRL11 0xb398 184 185/* 186 * AR7010 registers. 187 */ 188#define AR7010_GPIO_OE 0x52000 189#define AR7010_GPIO_IN 0x52004 190#define AR7010_GPIO_OUT 0x52008 191 192 193/* Bits for AR_AN_RF2G1_CH0. */ 194#define AR_AN_RF2G1_CH0_OB_M 0x03800000 195#define AR_AN_RF2G1_CH0_OB_S 23 196#define AR_AN_RF2G1_CH0_DB_M 0x1c000000 197#define AR_AN_RF2G1_CH0_DB_S 26 198 199/* Bits for AR_AN_RF5G1_CH0. */ 200#define AR_AN_RF5G1_CH0_OB5_M 0x00070000 201#define AR_AN_RF5G1_CH0_OB5_S 16 202#define AR_AN_RF5G1_CH0_DB5_M 0x00380000 203#define AR_AN_RF5G1_CH0_DB5_S 19 204 205/* Bits for AR_AN_RF2G1_CH1. */ 206#define AR_AN_RF2G1_CH1_OB_M 0x03800000 207#define AR_AN_RF2G1_CH1_OB_S 23 208#define AR_AN_RF2G1_CH1_DB_M 0x1c000000 209#define AR_AN_RF2G1_CH1_DB_S 26 210 211/* Bits for AR_AN_RF5G1_CH1. */ 212#define AR_AN_RF5G1_CH1_OB5_M 0x00070000 213#define AR_AN_RF5G1_CH1_OB5_S 16 214#define AR_AN_RF5G1_CH1_DB5_M 0x00380000 215#define AR_AN_RF5G1_CH1_DB5_S 19 216 217/* Bits for AR_AN_SYNTH9. */ 218#define AR_AN_SYNTH9_REFDIVA_M 0xf8000000 219#define AR_AN_SYNTH9_REFDIVA_S 27 220 221/* Bits for AR_AN_TOP1. */ 222#define AR_AN_TOP1_DACLPMODE 0x00040000 223 224/* Bits for AR_AN_TOP2. */ 225#define AR_AN_TOP2_XPABIAS_LVL_M 0xc0000000 226#define AR_AN_TOP2_XPABIAS_LVL_S 30 227#define AR_AN_TOP2_LOCALBIAS 0x00200000 228#define AR_AN_TOP2_PWDCLKIND 0x00400000 229 230/* Bits for AR_PHY_TEST. */ 231#define AR_PHY_TEST_RFSILENT_BB 0x00002000 232#define AR_PHY_TEST_AGC_CLR 0x10000000 233 234/* Bits for AR_PHY_TURBO. */ 235#define AR_PHY_FC_TURBO_MODE 0x00000001 236#define AR_PHY_FC_TURBO_SHORT 0x00000002 237#define AR_PHY_FC_DYN2040_EN 0x00000004 238#define AR_PHY_FC_DYN2040_PRI_ONLY 0x00000008 239#define AR_PHY_FC_DYN2040_PRI_CH 0x00000010 240#define AR_PHY_FC_DYN2040_EXT_CH 0x00000020 241#define AR_PHY_FC_HT_EN 0x00000040 242#define AR_PHY_FC_SHORT_GI_40 0x00000080 243#define AR_PHY_FC_WALSH 0x00000100 244#define AR_PHY_FC_SINGLE_HT_LTF1 0x00000200 245#define AR_PHY_FC_ENABLE_DAC_FIFO 0x00000800 246 247/* Bits for AR_PHY_TIMING3. */ 248#define AR_PHY_TIMING3_DSC_MAN_M 0xfffe0000 249#define AR_PHY_TIMING3_DSC_MAN_S 17 250#define AR_PHY_TIMING3_DSC_EXP_M 0x0001e000 251#define AR_PHY_TIMING3_DSC_EXP_S 13 252 253/* Bits for AR_PHY_CHIP_ID. */ 254#define AR_PHY_CHIP_ID_REV_0 0x00000080 255#define AR_PHY_CHIP_ID_REV_1 0x00000081 256#define AR_PHY_CHIP_ID_9160_REV_0 0x000000b0 257 258/* Bits for AR_PHY_ACTIVE. */ 259#define AR_PHY_ACTIVE_EN 0x00000001 260#define AR_PHY_ACTIVE_DIS 0x00000000 261 262/* Bits for AR_PHY_RF_CTL2. */ 263#define AR_PHY_TX_END_DATA_START_M 0x000000ff 264#define AR_PHY_TX_END_DATA_START_S 0 265#define AR_PHY_TX_END_PA_ON_M 0x0000ff00 266#define AR_PHY_TX_END_PA_ON_S 8 267 268/* Bits for AR_PHY_RF_CTL3. */ 269#define AR_PHY_TX_END_TO_A2_RX_ON_M 0x00ff0000 270#define AR_PHY_TX_END_TO_A2_RX_ON_S 16 271 272/* Bits for AR_PHY_ADC_CTL. */ 273#define AR_PHY_ADC_CTL_OFF_INBUFGAIN_M 0x00000003 274#define AR_PHY_ADC_CTL_OFF_INBUFGAIN_S 0 275#define AR_PHY_ADC_CTL_OFF_PWDDAC 0x00002000 276#define AR_PHY_ADC_CTL_OFF_PWDBANDGAP 0x00004000 277#define AR_PHY_ADC_CTL_OFF_PWDADC 0x00008000 278#define AR_PHY_ADC_CTL_ON_INBUFGAIN_M 0x00030000 279#define AR_PHY_ADC_CTL_ON_INBUFGAIN_S 16 280 281/* Bits for AR_PHY_ADC_SERIAL_CTL. */ 282#define AR_PHY_SEL_INTERNAL_ADDAC 0x00000000 283#define AR_PHY_SEL_EXTERNAL_RADIO 0x00000001 284 285/* Bits for AR_PHY_RF_CTL4. */ 286#define AR_PHY_RF_CTL4_TX_END_XPAB_OFF_M 0xff000000 287#define AR_PHY_RF_CTL4_TX_END_XPAB_OFF_S 24 288#define AR_PHY_RF_CTL4_TX_END_XPAA_OFF_M 0x00ff0000 289#define AR_PHY_RF_CTL4_TX_END_XPAA_OFF_S 16 290#define AR_PHY_RF_CTL4_FRAME_XPAB_ON_M 0x0000ff00 291#define AR_PHY_RF_CTL4_FRAME_XPAB_ON_S 8 292#define AR_PHY_RF_CTL4_FRAME_XPAA_ON_M 0x000000ff 293#define AR_PHY_RF_CTL4_FRAME_XPAA_ON_S 0 294 295/* Bits for AR_PHY_SETTLING. */ 296#define AR_PHY_SETTLING_SWITCH_M 0x00003f80 297#define AR_PHY_SETTLING_SWITCH_S 7 298 299/* Bits for AR_PHY_RXGAIN. */ 300#define AR_PHY_RXGAIN_TXRX_ATTEN_M 0x0003f000 301#define AR_PHY_RXGAIN_TXRX_ATTEN_S 12 302#define AR_PHY_RXGAIN_TXRX_RF_MAX_M 0x007c0000 303#define AR_PHY_RXGAIN_TXRX_RF_MAX_S 18 304#define AR9280_PHY_RXGAIN_TXRX_ATTEN_M 0x00003f80 305#define AR9280_PHY_RXGAIN_TXRX_ATTEN_S 7 306#define AR9280_PHY_RXGAIN_TXRX_MARGIN_M 0x001fc000 307#define AR9280_PHY_RXGAIN_TXRX_MARGIN_S 14 308 309/* Bits for AR_PHY_DESIRED_SZ. */ 310#define AR_PHY_DESIRED_SZ_ADC_M 0x000000ff 311#define AR_PHY_DESIRED_SZ_ADC_S 0 312#define AR_PHY_DESIRED_SZ_PGA_M 0x0000ff00 313#define AR_PHY_DESIRED_SZ_PGA_S 8 314#define AR_PHY_DESIRED_SZ_TOT_DES_M 0x0ff00000 315#define AR_PHY_DESIRED_SZ_TOT_DES_S 20 316 317/* Bits for AR_PHY_FIND_SIG. */ 318#define AR_PHY_FIND_SIG_FIRSTEP_M 0x0003f000 319#define AR_PHY_FIND_SIG_FIRSTEP_S 12 320#define AR_PHY_FIND_SIG_FIRPWR_M 0x03fc0000 321#define AR_PHY_FIND_SIG_FIRPWR_S 18 322 323/* Bits for AR_PHY_AGC_CTL1. */ 324#define AR_PHY_AGC_CTL1_COARSE_LOW_M 0x00007f80 325#define AR_PHY_AGC_CTL1_COARSE_LOW_S 7 326#define AR_PHY_AGC_CTL1_COARSE_HIGH_M 0x003f8000 327#define AR_PHY_AGC_CTL1_COARSE_HIGH_S 15 328 329/* Bits for AR_PHY_AGC_CONTROL. */ 330#define AR_PHY_AGC_CONTROL_CAL 0x00000001 331#define AR_PHY_AGC_CONTROL_NF 0x00000002 332#define AR_PHY_AGC_CONTROL_ENABLE_NF 0x00008000 333#define AR_PHY_AGC_CONTROL_FLTR_CAL 0x00010000 334#define AR_PHY_AGC_CONTROL_NO_UPDATE_NF 0x00020000 335 336/* Bits for AR_PHY_CCA. */ 337#define AR_PHY_MAXCCA_PWR_M 0x000001ff 338#define AR_PHY_MAXCCA_PWR_S 0 339#define AR_PHY_CCA_THRESH62_M 0x0007f000 340#define AR_PHY_CCA_THRESH62_S 12 341#define AR_PHY_MINCCA_PWR_M 0x0ff80000 342#define AR_PHY_MINCCA_PWR_S 19 343#define AR9280_PHY_CCA_THRESH62_M 0x000ff000 344#define AR9280_PHY_CCA_THRESH62_S 12 345#define AR9280_PHY_MINCCA_PWR_M 0x1ff00000 346#define AR9280_PHY_MINCCA_PWR_S 20 347 348/* Bits for AR_PHY_SFCORR_LOW. */ 349#define AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW 0x00000001 350#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_M 0x00003f00 351#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S 8 352#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_M 0x001fc000 353#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_S 14 354#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_M 0x0fe00000 355#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_S 21 356 357/* Bits for AR_PHY_SFCORR. */ 358#define AR_PHY_SFCORR_M2COUNT_THR_M 0x0000001f 359#define AR_PHY_SFCORR_M2COUNT_THR_S 0 360#define AR_PHY_SFCORR_M1_THRESH_M 0x00fe0000 361#define AR_PHY_SFCORR_M1_THRESH_S 17 362#define AR_PHY_SFCORR_M2_THRESH_M 0x7f000000 363#define AR_PHY_SFCORR_M2_THRESH_S 24 364 365/* Bits for AR_PHY_RX_DELAY. */ 366#define AR_PHY_RX_DELAY_DELAY_M 0x00003fff 367#define AR_PHY_RX_DELAY_DELAY_S 0 368 369/* Bits for AR_PHY_TIMING_CTRL4_0. */ 370#define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_M 0x0000001f 371#define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_S 0 372#define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_M 0x000007e0 373#define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_S 5 374#define AR_PHY_TIMING_CTRL4_IQCORR_ENABLE 0x00000800 375#define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_M 0x0000f000 376#define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_S 12 377#define AR_PHY_TIMING_CTRL4_DO_CAL 0x00010000 378#define AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK 0x10000000 379#define AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK 0x20000000 380#define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER 0x40000000 381#define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI 0x80000000 382 383/* Bits for AR_PHY_TIMING5. */ 384#define AR_PHY_TIMING5_CYCPWR_THR1_M 0x000000fe 385#define AR_PHY_TIMING5_CYCPWR_THR1_S 1 386 387/* Bits for AR_PHY_POWER_TX_RATE_MAX. */ 388#define AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE 0x00000040 389 390/* Bits for AR_PHY_FRAME_CTL. */ 391#define AR_PHY_FRAME_CTL_TX_CLIP_M 0x00000038 392#define AR_PHY_FRAME_CTL_TX_CLIP_S 3 393 394/* Bits for AR_PHY_TXPWRADJ. */ 395#define AR_PHY_TXPWRADJ_CCK_GAIN_DELTA_M 0x00000fc0 396#define AR_PHY_TXPWRADJ_CCK_GAIN_DELTA_S 6 397#define AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX_M 0x00fc0000 398#define AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX_S 18 399 400/* Bits for AR_PHY_RADAR_EXT. */ 401#define AR_PHY_RADAR_EXT_ENA 0x00004000 402 403/* Bits for AR_PHY_RADAR_0. */ 404#define AR_PHY_RADAR_0_ENA 0x00000001 405#define AR_PHY_RADAR_0_INBAND_M 0x0000003e 406#define AR_PHY_RADAR_0_INBAND_S 1 407#define AR_PHY_RADAR_0_PRSSI_M 0x00000fc0 408#define AR_PHY_RADAR_0_PRSSI_S 6 409#define AR_PHY_RADAR_0_HEIGHT_M 0x0003f000 410#define AR_PHY_RADAR_0_HEIGHT_S 12 411#define AR_PHY_RADAR_0_RRSSI_M 0x00fc0000 412#define AR_PHY_RADAR_0_RRSSI_S 18 413#define AR_PHY_RADAR_0_FIRPWR_M 0x7f000000 414#define AR_PHY_RADAR_0_FIRPWR_S 24 415#define AR_PHY_RADAR_0_FFT_ENA 0x80000000 416 417/* Bits for AR_PHY_RADAR_1. */ 418#define AR_PHY_RADAR_1_MAXLEN_M 0x000000ff 419#define AR_PHY_RADAR_1_MAXLEN_S 0 420#define AR_PHY_RADAR_1_RELSTEP_THRESH_M 0x00001f00 421#define AR_PHY_RADAR_1_RELSTEP_THRESH_S 8 422#define AR_PHY_RADAR_1_RELSTEP_CHECK 0x00002000 423#define AR_PHY_RADAR_1_MAX_RRSSI 0x00004000 424#define AR_PHY_RADAR_1_BLOCK_CHECK 0x00008000 425#define AR_PHY_RADAR_1_RELPWR_THRESH_M 0x003f0000 426#define AR_PHY_RADAR_1_RELPWR_THRESH_S 16 427#define AR_PHY_RADAR_1_USE_FIR128 0x00400000 428#define AR_PHY_RADAR_1_RELPWR_ENA 0x00800000 429 430/* Bits for AR_PHY_SIGMA_DELTA. */ 431#define AR_PHY_SIGMA_DELTA_ADC_SEL_M 0x00000003 432#define AR_PHY_SIGMA_DELTA_ADC_SEL_S 0 433#define AR_PHY_SIGMA_DELTA_FILT2_M 0x000000f8 434#define AR_PHY_SIGMA_DELTA_FILT2_S 3 435#define AR_PHY_SIGMA_DELTA_FILT1_M 0x00001f00 436#define AR_PHY_SIGMA_DELTA_FILT1_S 8 437#define AR_PHY_SIGMA_DELTA_ADC_CLIP_M 0x01ffe000 438#define AR_PHY_SIGMA_DELTA_ADC_CLIP_S 13 439 440/* Bits for AR_PHY_RESTART. */ 441#define AR_PHY_RESTART_DIV_GC_M 0x001c0000 442#define AR_PHY_RESTART_DIV_GC_S 18 443 444/* Bits for AR_PHY_RFBUS_REQ. */ 445#define AR_PHY_RFBUS_REQ_EN 0x00000001 446 447/* Bits for AR_PHY_TIMING11. */ 448#define AR_PHY_TIMING11_SPUR_DELTA_PHASE_M 0x000fffff 449#define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S 0 450#define AR_PHY_TIMING11_SPUR_FREQ_SD_M 0x3ff00000 451#define AR_PHY_TIMING11_SPUR_FREQ_SD_S 20 452#define AR_PHY_TIMING11_USE_SPUR_IN_AGC 0x40000000 453#define AR_PHY_TIMING11_USE_SPUR_IN_SELFCOR 0x80000000 454 455/* Bits for AR_PHY_NEW_ADC_DC_GAIN_CORR(). */ 456#define AR_PHY_NEW_ADC_GAIN_CORR_ENABLE 0x40000000 457#define AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE 0x80000000 458 459/* Bits for AR_PHY_EXT_CCA0. */ 460#define AR_PHY_EXT_CCA0_THRESH62_M 0x000000ff 461#define AR_PHY_EXT_CCA0_THRESH62_S 0 462 463/* Bits for AR_PHY_EXT_CCA. */ 464#define AR_PHY_EXT_MAXCCA_PWR_M 0x000001ff 465#define AR_PHY_EXT_MAXCCA_PWR_S 0 466#define AR_PHY_EXT_CCA_CYCPWR_THR1_M 0x0000fe00 467#define AR_PHY_EXT_CCA_CYCPWR_THR1_S 9 468#define AR_PHY_EXT_CCA_THRESH62_M 0x007f0000 469#define AR_PHY_EXT_CCA_THRESH62_S 16 470#define AR_PHY_EXT_MINCCA_PWR_M 0xff800000 471#define AR_PHY_EXT_MINCCA_PWR_S 23 472#define AR9280_PHY_EXT_MINCCA_PWR_M 0x01ff0000 473#define AR9280_PHY_EXT_MINCCA_PWR_S 16 474 475/* Bits for AR_PHY_SFCORR_EXT. */ 476#define AR_PHY_SFCORR_EXT_M1_THRESH_M 0x0000007f 477#define AR_PHY_SFCORR_EXT_M1_THRESH_S 0 478#define AR_PHY_SFCORR_EXT_M2_THRESH_M 0x00003f80 479#define AR_PHY_SFCORR_EXT_M2_THRESH_S 7 480#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_M 0x001fc000 481#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S 14 482#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_M 0x0fe00000 483#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S 21 484#define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_M 0xf0000000 485#define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S 28 486 487/* Bits for AR_PHY_HALFGI. */ 488#define AR_PHY_HALFGI_DSC_EXP_M 0x0000000f 489#define AR_PHY_HALFGI_DSC_EXP_S 0 490#define AR_PHY_HALFGI_DSC_MAN_M 0x0007fff0 491#define AR_PHY_HALFGI_DSC_MAN_S 4 492 493/* Bits for AR_PHY_CHAN_INFO_MEMORY. */ 494#define AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK 0x00000001 495 496/* Bits for AR_PHY_HEAVY_CLIP_FACTOR_RIFS. */ 497#define AR_PHY_RIFS_INIT_DELAY_M 0x03ff0000 498#define AR_PHY_RIFS_INIT_DELAY_S 16 499 500/* Bits for AR_PHY_CALMODE. */ 501#define AR_PHY_CALMODE_IQ 0x00000000 502#define AR_PHY_CALMODE_ADC_GAIN 0x00000001 503#define AR_PHY_CALMODE_ADC_DC_PER 0x00000002 504#define AR_PHY_CALMODE_ADC_DC_INIT 0x00000003 505 506/* Bits for AR_PHY_RFBUS_GRANT. */ 507#define AR_PHY_RFBUS_GRANT_EN 0x00000001 508 509/* Bits for AR_PHY_CHAN_INFO_GAIN_DIFF. */ 510#define AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT 320 511 512/* Bits for AR_PHY_MODE. */ 513#define AR_PHY_MODE_ASYNCFIFO 0x00000080 514#define AR_PHY_MODE_AR2133 0x00000008 515#define AR_PHY_MODE_AR5111 0x00000000 516#define AR_PHY_MODE_AR5112 0x00000008 517#define AR_PHY_MODE_DYNAMIC 0x00000004 518#define AR_PHY_MODE_RF2GHZ 0x00000002 519#define AR_PHY_MODE_RF5GHZ 0x00000000 520#define AR_PHY_MODE_CCK 0x00000001 521#define AR_PHY_MODE_OFDM 0x00000000 522#define AR_PHY_MODE_DYN_CCK_DISABLE 0x00000100 523 524/* Bits for AR_PHY_CCK_TX_CTRL. */ 525#define AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK_M 0x0000000c 526#define AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK_S 2 527#define AR_PHY_CCK_TX_CTRL_JAPAN 0x00000010 528 529/* Bits for AR_PHY_CCK_DETECT. */ 530#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_M 0x0000003f 531#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S 0 532#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_M 0x00001fc0 533#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_S 6 534#define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV 0x00002000 535 536/* Bits for AR_PHY_GAIN_2GHZ. */ 537#define AR_PHY_GAIN_2GHZ_XATTEN1_DB_M 0x0000003f 538#define AR_PHY_GAIN_2GHZ_XATTEN1_DB_S 0 539#define AR_PHY_GAIN_2GHZ_BSW_ATTEN_M 0x0000001f 540#define AR_PHY_GAIN_2GHZ_BSW_ATTEN_S 0 541#define AR_PHY_GAIN_2GHZ_XATTEN2_DB_M 0x00000fc0 542#define AR_PHY_GAIN_2GHZ_XATTEN2_DB_S 6 543#define AR_PHY_GAIN_2GHZ_BSW_MARGIN_M 0x00003c00 544#define AR_PHY_GAIN_2GHZ_BSW_MARGIN_S 10 545#define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN_M 0x0001f000 546#define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN_S 12 547#define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN_M 0x003e0000 548#define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN_S 17 549#define AR_PHY_GAIN_2GHZ_RXTX_MARGIN_M 0x00fc0000 550#define AR_PHY_GAIN_2GHZ_RXTX_MARGIN_S 18 551 552/* Bit for AR_PHY_CCK_RXCTRL4. */ 553#define AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT_M 0x01f80000 554#define AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT_S 19 555 556/* Bits for AR_PHY_DAG_CTRLCCK. */ 557#define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR 0x00000200 558#define AR_PHY_DAG_CTRLCCK_RSSI_THR_M 0x0001fc00 559#define AR_PHY_DAG_CTRLCCK_RSSI_THR_S 10 560 561/* Bits for AR_PHY_FORCE_CLKEN_CCK. */ 562#define AR_PHY_FORCE_CLKEN_CCK_MRC_MUX 0x00000040 563 564/* Bits for AR_PHY_TPCRG1. */ 565#define AR_PHY_TPCRG1_NUM_PD_GAIN_M 0x0000c000 566#define AR_PHY_TPCRG1_NUM_PD_GAIN_S 14 567#define AR_PHY_TPCRG1_PD_GAIN_1_M 0x00030000 568#define AR_PHY_TPCRG1_PD_GAIN_1_S 16 569#define AR_PHY_TPCRG1_PD_GAIN_2_M 0x000c0000 570#define AR_PHY_TPCRG1_PD_GAIN_2_S 18 571#define AR_PHY_TPCRG1_PD_GAIN_3_M 0x00300000 572#define AR_PHY_TPCRG1_PD_GAIN_3_S 20 573#define AR_PHY_TPCRG1_PD_CAL_ENABLE 0x00400000 574 575/* Bits for AR_PHY_TX_PWRCTRL4. */ 576#define AR_PHY_TX_PWRCTRL_PD_AVG_VALID 0x00000001 577#define AR_PHY_TX_PWRCTRL_PD_AVG_OUT_M 0x000001fe 578#define AR_PHY_TX_PWRCTRL_PD_AVG_OUT_S 1 579 580/* Bits for AR_PHY_TX_PWRCTRL6_[01]. */ 581#define AR_PHY_TX_PWRCTRL_ERR_EST_MODE_M 0x03000000 582#define AR_PHY_TX_PWRCTRL_ERR_EST_MODE_S 24 583 584/* Bits for AR_PHY_TX_PWRCTRL7. */ 585#define AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX_M 0x0007e000 586#define AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX_S 13 587#define AR_PHY_TX_PWRCTRL_INIT_TX_GAIN_M 0x01f80000 588#define AR_PHY_TX_PWRCTRL_INIT_TX_GAIN_S 19 589 590/* Bits for AR_PHY_TX_PWRCTRL9. */ 591#define AR_PHY_TX_DESIRED_SCALE_CCK_M 0x00007c00 592#define AR_PHY_TX_DESIRED_SCALE_CCK_S 10 /* XXX should be 9? */ 593#define AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL 0x80000000 594 595/* Bits for AR_PHY_TX_GAIN_TBL. */ 596#define AR_PHY_TX_GAIN_CLC_M 0x0000001e 597#define AR_PHY_TX_GAIN_CLC_S 1 598#define AR_PHY_TX_GAIN_M 0x0007f000 599#define AR_PHY_TX_GAIN_S 12 600 601/* Bits for AR_PHY_SPUR_REG. */ 602#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_M 0x0000007f 603#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0 604#define AR_SPUR_RSSI_THRESH 40 605#define AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI 0x00000100 606#define AR_PHY_SPUR_REG_MASK_RATE_SELECT 0x0001fe00 607#define AR_PHY_SPUR_REG_ENABLE_MASK_PPM 0x00020000 608#define AR_PHY_SPUR_REG_MASK_RATE_CNTL 0x03fc0000 609 610/* Bits for AR_PHY_ANALOG_SWAP. */ 611#define AR_PHY_SWAP_ALT_CHAIN 0x00000040 612 613/* Bits for AR_PHY_TPCRG5. */ 614#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP_M 0x0000000f 615#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP_S 0 616#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_M 0x000003f0 617#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_S 4 618#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_M 0x0000fc00 619#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_S 10 620#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_M 0x003f0000 621#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_S 16 622#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_M 0x0fc00000 623#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_S 22 624 625/* Bits for AR_PHY_CL_CAL_CTL. */ 626#define AR_PHY_PARALLEL_CAL_ENABLE 0x00000001 627#define AR_PHY_CL_CAL_ENABLE 0x00000002 628 629/* Bits for AR_PHY_CLC_TBL. */ 630#define AR_PHY_CLC_Q0_M 0x0000ffd0 631#define AR_PHY_CLC_Q0_S 5 632#define AR_PHY_CLC_I0_M 0x07ff0000 633#define AR_PHY_CLC_I0_S 16 634 635/* Bits for AR_PHY_XPA_CFG. */ 636#define AR_PHY_FORCE_XPA_CFG 0x000000001 637 638/* Bits for AR_PHY_CH[01]_TX_PWRCTRL11. */ 639#define AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP_M 0x0000fc00 640#define AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP_S 10 641#define AR_PHY_TX_PWRCTRL_OLPC_PWR_M 0x00ff0000 642#define AR_PHY_TX_PWRCTRL_OLPC_PWR_S 16 643 644/* Bits for AR_PHY_NEW_ADC_DC_GAIN_CORR. */ 645#define AR_PHY_NEW_ADC_DC_GAIN_QGAIN_M 0x0000003f 646#define AR_PHY_NEW_ADC_DC_GAIN_QGAIN_S 0 647#define AR_PHY_NEW_ADC_DC_GAIN_IGAIN_M 0x00000fc0 648#define AR_PHY_NEW_ADC_DC_GAIN_IGAIN_S 6 649#define AR_PHY_NEW_ADC_DC_GAIN_QDC_M 0x001ff000 650#define AR_PHY_NEW_ADC_DC_GAIN_QDC_S 12 651#define AR_PHY_NEW_ADC_DC_GAIN_IDC_M 0x3fe00000 652#define AR_PHY_NEW_ADC_DC_GAIN_IDC_S 21 653 654/* Bits for AR_PHY(0x37). */ 655#define AR5416_BMODE_SYNTH 0x00000002 656#define AR5416_AMODE_REFSEL_M 0x0000000c 657#define AR5416_AMODE_REFSEL_S 2 658 659 660#define AR5008_MAX_SCATTER 16 /* NB: not a hardware limit. */ 661 662/* 663 * Tx DMA descriptor. 664 */ 665struct ar_tx_desc { 666 uint32_t ds_link; 667 uint32_t ds_data; 668 uint32_t ds_ctl0; 669 uint32_t ds_ctl1; 670 uint32_t ds_ctl2; 671 uint32_t ds_ctl3; 672 uint32_t ds_ctl4; 673 uint32_t ds_ctl5; 674 uint32_t ds_ctl6; 675 uint32_t ds_ctl7; 676 uint32_t ds_ctl8; 677 uint32_t ds_ctl9; 678 uint32_t ds_ctl10; 679 uint32_t ds_ctl11; 680 uint32_t ds_status0; 681 uint32_t ds_status1; 682 uint32_t ds_tstamp; 683 uint32_t ds_ba_bitmap_lo; 684 uint32_t ds_ba_bitmap_hi; 685 uint32_t ds_evm0; 686 uint32_t ds_evm1; 687 uint32_t ds_evm2; 688 uint32_t ds_status8; 689 uint32_t ds_status9; 690 /* 691 * Padding to make Tx descriptors 128 bytes such that they will 692 * not cross a 4KB boundary. 693 */ 694 uint32_t pad[8]; 695} __packed __attribute__((aligned(4))); 696 697/* Bits for ds_ctl0. */ 698#define AR_TXC0_FRAME_LEN_M 0x00000fff 699#define AR_TXC0_FRAME_LEN_S 0 700#define AR_TXC0_VIRT_MORE_FRAG 0x00001000 701#define AR_TXC0_XMIT_POWER_M 0x003f0000 702#define AR_TXC0_XMIT_POWER_S 16 703#define AR_TXC0_RTS_ENABLE 0x00400000 704#define AR_TXC0_VEOL 0x00800000 705#define AR_TXC0_CLR_DEST_MASK 0x01000000 706#define AR_TXC0_INTR_REQ 0x20000000 707#define AR_TXC0_DEST_IDX_VALID 0x40000000 708#define AR_TXC0_CTS_ENABLE 0x80000000 709 710/* Bits for ds_ctl1. */ 711#define AR_TXC1_BUF_LEN_M 0x00000fff 712#define AR_TXC1_BUF_LEN_S 0 713#define AR_TXC1_MORE 0x00001000 714#define AR_TXC1_DEST_IDX_M 0x000fe000 715#define AR_TXC1_DEST_IDX_S 13 716#define AR_TXC1_FRAME_TYPE_M 0x00f00000 717#define AR_TXC1_FRAME_TYPE_S 20 718#define AR_FRAME_TYPE_NORMAL 0 719#define AR_FRAME_TYPE_ATIM 1 720#define AR_FRAME_TYPE_PSPOLL 2 721#define AR_FRAME_TYPE_BEACON 3 722#define AR_FRAME_TYPE_PROBE_RESP 4 723#define AR_TXC1_NO_ACK 0x01000000 724#define AR_TXC1_INSERT_TS 0x02000000 725#define AR_TXC1_EXT_ONLY 0x08000000 726#define AR_TXC1_EXT_AND_CTL 0x10000000 727#define AR_TXC1_MORE_AGGR 0x20000000 728#define AR_TXC1_IS_AGGR 0x40000000 729 730/* Bits for ds_ctl2. */ 731#define AR_TXC2_BURST_DUR_M 0x00007fff 732#define AR_TXC2_BURST_DUR_S 0 733#define AR_TXC2_DUR_UPDATE_ENA 0x00008000 734#define AR_TXC2_XMIT_DATA_TRIES0_M 0x000f0000 735#define AR_TXC2_XMIT_DATA_TRIES0_S 16 736#define AR_TXC2_XMIT_DATA_TRIES1_M 0x00f00000 737#define AR_TXC2_XMIT_DATA_TRIES1_S 20 738#define AR_TXC2_XMIT_DATA_TRIES2_M 0x0f000000 739#define AR_TXC2_XMIT_DATA_TRIES2_S 24 740#define AR_TXC2_XMIT_DATA_TRIES3_M 0xf0000000 741#define AR_TXC2_XMIT_DATA_TRIES3_S 28 742 743/* Bits for ds_ctl3. */ 744#define AR_TXC3_XMIT_RATE0_M 0x000000ff 745#define AR_TXC3_XMIT_RATE0_S 0 746#define AR_TXC3_XMIT_RATE1_M 0x0000ff00 747#define AR_TXC3_XMIT_RATE1_S 8 748#define AR_TXC3_XMIT_RATE2_M 0x00ff0000 749#define AR_TXC3_XMIT_RATE2_S 16 750#define AR_TXC3_XMIT_RATE3_M 0xff000000 751#define AR_TXC3_XMIT_RATE3_S 24 752 753/* Bits for ds_ctl4. */ 754#define AR_TXC4_PACKET_DUR0_M 0x00007fff 755#define AR_TXC4_PACKET_DUR0_S 0 756#define AR_TXC4_RTSCTS_QUAL0 0x00008000 757#define AR_TXC4_PACKET_DUR1_M 0x7fff0000 758#define AR_TXC4_PACKET_DUR1_S 16 759#define AR_TXC4_RTSCTS_QUAL1 0x80000000 760/* Shortcut. */ 761#define AR_TXC4_RTSCTS_QUAL01 \ 762 (AR_TXC4_RTSCTS_QUAL0 | AR_TXC4_RTSCTS_QUAL1) 763 764/* Bits for ds_ctl5. */ 765#define AR_TXC5_PACKET_DUR2_M 0x00007fff 766#define AR_TXC5_PACKET_DUR2_S 0 767#define AR_TXC5_RTSCTS_QUAL2 0x00008000 768#define AR_TXC5_PACKET_DUR3_M 0x7fff0000 769#define AR_TXC5_PACKET_DUR3_S 16 770#define AR_TXC5_RTSCTS_QUAL3 0x80000000 771/* Shortcut. */ 772#define AR_TXC5_RTSCTS_QUAL23 \ 773 (AR_TXC5_RTSCTS_QUAL2 | AR_TXC5_RTSCTS_QUAL3) 774 775/* Bits for ds_ctl6. */ 776#define AR_TXC6_AGGR_LEN_M 0x0000ffff 777#define AR_TXC6_AGGR_LEN_S 0 778#define AR_TXC6_PAD_DELIM_M 0x03fc0000 779#define AR_TXC6_PAD_DELIM_S 18 780#define AR_TXC6_ENCR_TYPE_M 0x0c000000 781#define AR_TXC6_ENCR_TYPE_S 26 782#define AR_ENCR_TYPE_CLEAR 0 783#define AR_ENCR_TYPE_WEP 1 784#define AR_ENCR_TYPE_AES 2 785#define AR_ENCR_TYPE_TKIP 3 786 787/* Bits for ds_ctl7. */ 788#define AR_TXC7_2040_0 0x00000001 789#define AR_TXC7_GI0 0x00000002 790#define AR_TXC7_CHAIN_SEL0_M 0x0000001c 791#define AR_TXC7_CHAIN_SEL0_S 2 792#define AR_TXC7_2040_1 0x00000020 793#define AR_TXC7_GI1 0x00000040 794#define AR_TXC7_CHAIN_SEL1_M 0x00000380 795#define AR_TXC7_CHAIN_SEL1_S 7 796#define AR_TXC7_2040_2 0x00000400 797#define AR_TXC7_GI2 0x00000800 798#define AR_TXC7_CHAIN_SEL2_M 0x00007000 799#define AR_TXC7_CHAIN_SEL2_S 12 800#define AR_TXC7_2040_3 0x00008000 801#define AR_TXC7_GI3 0x00010000 802#define AR_TXC7_CHAIN_SEL3_M 0x000e0000 803#define AR_TXC7_CHAIN_SEL3_S 17 804#define AR_TXC7_RTSCTS_RATE_M 0x0ff00000 805#define AR_TXC7_RTSCTS_RATE_S 20 806/* Shortcuts. */ 807#define AR_TXC7_2040_0123 \ 808 (AR_TXC7_2040_0 | AR_TXC7_2040_1 | AR_TXC7_2040_2 | AR_TXC7_2040_3) 809#define AR_TXC7_GI0123 \ 810 (AR_TXC7_GI0 | AR_TXC7_GI1 | AR_TXC7_GI2 | AR_TXC7_GI3) 811 812/* Bits for ds_status0. */ 813#define AR_TXS0_RSSI_ANT0(i) (((x) >> ((i) * 8)) & 0xff) 814#define AR_TXS0_BA_STATUS 0x40000000 815 816/* Bits for ds_status1. */ 817#define AR_TXS1_FRM_XMIT_OK 0x00000001 818#define AR_TXS1_EXCESSIVE_RETRIES 0x00000002 819#define AR_TXS1_FIFO_UNDERRUN 0x00000004 820#define AR_TXS1_FILTERED 0x00000008 821#define AR_TXS1_RTS_FAIL_CNT_M 0x000000f0 822#define AR_TXS1_RTS_FAIL_CNT_S 4 823#define AR_TXS1_DATA_FAIL_CNT_M 0x00000f00 824#define AR_TXS1_DATA_FAIL_CNT_S 8 825#define AR_TXS1_VIRT_RETRY_CNT_M 0x0000f000 826#define AR_TXS1_VIRT_RETRY_CNT_S 12 827#define AR_TXS1_TX_DELIM_UNDERRUN 0x00010000 828#define AR_TXS1_TX_DATA_UNDERRUN 0x00020000 829#define AR_TXS1_DESC_CFG_ERR 0x00040000 830#define AR_TXS1_TX_TIMER_EXPIRED 0x00080000 831/* Shortcut. */ 832#define AR_TXS1_UNDERRUN \ 833 (AR_TXS1_FIFO_UNDERRUN | \ 834 AR_TXS1_TX_DELIM_UNDERRUN | \ 835 AR_TXS1_TX_DATA_UNDERRUN) 836 837/* Bits for ds_status9. */ 838#define AR_TXS9_DONE 0x00000001 839#define AR_TXS9_SEQNUM_M 0x00001ffe 840#define AR_TXS9_SEQNUM_S 1 841#define AR_TXS9_TXOP_EXCEEDED 0x00020000 842#define AR_TXS9_FINAL_IDX_M 0x00600000 843#define AR_TXS9_FINAL_IDX_S 21 844#define AR_TXS9_POWER_MGMT 0x02000000 845 846/* 847 * Rx DMA descriptor. 848 */ 849struct ar_rx_desc { 850 uint32_t ds_link; 851 uint32_t ds_data; 852 uint32_t ds_ctl0; 853 uint32_t ds_ctl1; 854 uint32_t ds_status0; 855 uint32_t ds_status1; 856 uint32_t ds_status2; 857 uint32_t ds_status3; 858 uint32_t ds_status4; 859 uint32_t ds_status5; 860 uint32_t ds_status6; 861 uint32_t ds_status7; 862 uint32_t ds_status8; 863 /* 864 * Padding to make Rx descriptors 64 bytes such that they will 865 * not cross a 4KB boundary. 866 */ 867 uint32_t pad[3]; 868} __packed __attribute__((aligned(4))); 869 870/* Bits for ds_ctl1. */ 871#define AR_RXC1_BUF_LEN_M 0x00000fff 872#define AR_RXC1_BUF_LEN_S 0 873#define AR_RXC1_INTR_REQ 0x00002000 874 875/* Bits for ds_status0. */ 876#define AR_RXS0_RSSI_ANT00(x) (((x) >> 0) & 0xff) 877#define AR_RXS0_RSSI_ANT01(x) (((x) >> 8) & 0xff) 878#define AR_RXS0_RSSI_ANT02(x) (((x) >> 16) & 0xff) 879#define AR_RXS0_RATE_M 0xff000000 880#define AR_RXS0_RATE_S 24 881 882/* Bits for ds_status1. */ 883#define AR_RXS1_DATA_LEN_M 0x00000fff 884#define AR_RXS1_DATA_LEN_S 0 885#define AR_RXS1_MORE 0x00001000 886 887/* Bits for ds_status3. */ 888#define AR_RXS3_GI 0x00000001 889#define AR_RXS3_2040 0x00000002 890#define AR_RXS3_PARALLEL_40 0x00000004 891#define AR_RXS3_ANTENNA_M 0xffffff00 892#define AR_RXS3_ANTENNA_S 8 893#define AR_RXS3_RATE_M 0x000003fc 894#define AR_RXS3_RATE_S 2 895 896/* Bits for ds_status4. */ 897#define AR_RXS0_RSSI_ANT10(x) (((x) >> 0) & 0xff) 898#define AR_RXS0_RSSI_ANT11(x) (((x) >> 8) & 0xff) 899#define AR_RXS0_RSSI_ANT12(x) (((x) >> 16) & 0xff) 900#define AR_RXS4_RSSI_COMBINED_M 0xff000000 901#define AR_RXS4_RSSI_COMBINED_S 24 902 903/* Bits for ds_status8. */ 904#define AR_RXS8_DONE 0x00000001 905#define AR_RXS8_FRAME_OK 0x00000002 906#define AR_RXS8_CRC_ERR 0x00000004 907#define AR_RXS8_DECRYPT_CRC_ERR 0x00000008 908#define AR_RXS8_PHY_ERR 0x00000010 909#define AR_RXS8_MICHAEL_ERR 0x00000020 910#define AR_RXS8_PRE_DELIM_CRC_ERR 0x00000040 911#define AR_RXS8_PHY_ERR_CODE_M 0x0000ff00 912#define AR_RXS8_PHY_ERR_CODE_S 8 913#define AR_RXS8_KEY_IDX_VALID 0x00000100 914#define AR_RXS8_KEY_IDX_M 0x0000fe00 915#define AR_RXS8_KEY_IDX_S 9 916#define AR_RXS8_POST_DELIM_CRC_ERR 0x00040000 917#define AR_RXS8_DECRYPT_BUSY_ERR 0x40000000 918 919#define AR_MAX_PWR_RANGE_IN_HALF_DB 64 920#define AR9285_PD_GAIN_BOUNDARY_DEFAULT 58 921 922/* 923 * AR5008 family common ROM header. 924 */ 925#define AR_EEPROM_MAGIC_OFFSET 0x0000 926#if BYTE_ORDER == BIG_ENDIAN 927#define AR_EEPROM_MAGIC 0x5aa5 928#else 929#define AR_EEPROM_MAGIC 0xa55a 930#endif 931 932#define AR_NO_SPUR 0x8000 933#define AR_NUM_PDADC_VALUES 128 934 935struct ar_base_eep_header { 936 uint16_t length; 937 uint16_t checksum; 938 uint16_t version; 939#define AR_EEP_VER 0xe 940#define AR_EEP_VER_MINOR_MASK 0x0fff 941#define AR_EEP_MINOR_VER_2 2 942#define AR_EEP_MINOR_VER_3 3 943#define AR_EEP_MINOR_VER_7 7 944#define AR_EEP_MINOR_VER_9 9 945#define AR_EEP_MINOR_VER_10 10 946#define AR_EEP_MINOR_VER_16 16 947#define AR_EEP_MINOR_VER_17 17 948#define AR_EEP_MINOR_VER_19 19 949#define AR_EEP_MINOR_VER_20 20 950#define AR_EEP_MINOR_VER_21 21 951#define AR_EEP_MINOR_VER_22 22 952 953 uint8_t opCapFlags; 954#define AR_OPFLAGS_11A 0x01 955#define AR_OPFLAGS_11G 0x02 956/* NB: If set, 11n is _disabled_ in the corresponding mode: */ 957#define AR_OPFLAGS_11N_5G40 0x04 958#define AR_OPFLAGS_11N_2G40 0x08 959#define AR_OPFLAGS_11N_5G20 0x10 960#define AR_OPFLAGS_11N_2G20 0x20 961 962 uint8_t eepMisc; 963 uint16_t regDmn[2]; 964 uint8_t macAddr[6]; 965 uint8_t rxMask; 966 uint8_t txMask; 967 uint16_t rfSilent; 968#define AR_EEP_RFSILENT_ENABLED 0x0001 969#define AR_EEP_RFSILENT_GPIO_SEL_M 0x001c 970#define AR_EEP_RFSILENT_GPIO_SEL_S 2 971#define AR_EEP_RFSILENT_POLARITY 0x0002 972 973 uint16_t blueToothOptions; 974 uint16_t deviceCap; 975#define AR_EEP_DEVCAP_COMPRESS_DIS 0x0001 976#define AR_EEP_DEVCAP_AES_DIS 0x0002 977#define AR_EEP_DEVCAP_FASTFRAME_DIS 0x0004 978#define AR_EEP_DEVCAP_BURST_DIS 0x0008 979#define AR_EEP_DEVCAP_MAXQCU_M 0x01f0 980#define AR_EEP_DEVCAP_MAXQCU_S 4 981#define AR_EEP_DEVCAP_HEAVY_CLIP_EN 0x0200 982#define AR_EEP_DEVCAP_KC_ENTRIES_M 0xf000 983#define AR_EEP_DEVCAP_KC_ENTRIES_S 12 984 985 uint32_t binBuildNumber; 986 uint8_t deviceType; 987} __packed; 988 989#define AR_EEP_TXGAIN_ORIGINAL 0 990#define AR_EEP_TXGAIN_HIGH_POWER 1 991 992#define AR_EEPROM_MODAL_SPURS 5 993 994struct ar_spur_chan { 995 uint16_t spurChan; 996 uint8_t spurRangeLow; 997 uint8_t spurRangeHigh; 998} __packed; 999 1000struct ar_cal_data_per_freq_olpc { 1001 uint8_t pwrPdg[2][5]; 1002 uint8_t vpdPdg[2][5]; 1003 uint8_t pcdac[2][5]; 1004 uint8_t empty[2][5]; 1005} __packed; 1006 1007struct ar_cal_target_power_leg { 1008 uint8_t bChannel; 1009 uint8_t tPow2x[4]; 1010} __packed; 1011 1012struct ar_cal_target_power_ht { 1013 uint8_t bChannel; 1014 uint8_t tPow2x[8]; 1015} __packed; 1016 1017struct ar_cal_ctl_edges { 1018 uint8_t bChannel; 1019 uint8_t tPowerFlag; 1020#define AR_CAL_CTL_EDGES_POWER_M 0x3f 1021#define AR_CAL_CTL_EDGES_POWER_S 0 1022#define AR_CAL_CTL_EDGES_FLAG_M 0xc0 1023#define AR_CAL_CTL_EDGES_FLAG_S 6 1024} __packed; 1025