1/* $OpenBSD: sunxireg.h,v 1.1 2017/01/21 08:26:49 patrick Exp $ */ 2/* 3 * Copyright (c) 2013 Artturi Alm 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18#define SXIREAD1(sc, reg) \ 19 (bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, (reg))) 20#define SXIWRITE1(sc, reg, val) \ 21 bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 22#define SXISET1(sc, reg, bits) \ 23 SXIWRITE1((sc), (reg), SXIREAD1((sc), (reg)) | (bits)) 24#define SXICLR1(sc, reg, bits) \ 25 SXIWRITE1((sc), (reg), SXIREAD1((sc), (reg)) & ~(bits)) 26#define SXICMS1(sc, reg, mask, bits) \ 27 SXIWRITE1((sc), (reg), (SXIREAD1((sc), (reg)) & ~(mask)) | (bits)) 28 29#define SXIREAD4(sc, reg) \ 30 (bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))) 31#define SXIWRITE4(sc, reg, val) \ 32 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 33#define SXISET4(sc, reg, bits) \ 34 SXIWRITE4((sc), (reg), SXIREAD4((sc), (reg)) | (bits)) 35#define SXICLR4(sc, reg, bits) \ 36 SXIWRITE4((sc), (reg), SXIREAD4((sc), (reg)) & ~(bits)) 37#define SXICMS4(sc, reg, mask, bits) \ 38 SXIWRITE4((sc), (reg), (SXIREAD4((sc), (reg)) & ~(mask)) | (bits)) 39 40#define TIMER0_FREQUENCY (24000000) 41#define TIMER1_FREQUENCY (24000000) 42#define TIMER2_FREQUENCY (24000000) 43#define COUNTER_FREQUENCY (24000000) 44 45/* SRAM Controller / System Control */ 46#define SYSCTRL_ADDR 0x01c00000 47#define SYSCTRL_SIZE 0x1000 48 49#define DMAC_ADDR 0x01c02000 50#define DMAC_SIZE 0x1000 51#define DMAC_IRQ 27 52 53#define SDMMC0_ADDR 0x01c0f000 54#define SDMMCx_SIZE 0x1000 55#define SDMMC0_IRQ 32 56 57#define SATA_ADDR 0x01c18000 58#define SATA_SIZE 0x1000 59#define SATA_IRQ 56 60 61#define TIMER_ADDR 0x01c20c00 62#define TIMERx_SIZE 0x200 63#define TIMER0_IRQ 22 64#define TIMER1_IRQ 23 65#define TIMER2_IRQ 24 66#define STATTIMER_IRQ TIMER1_IRQ /* XXX */ 67 68#define WDOG_ADDR 0x01c20c90 69#define WDOG_SIZE 0x08 70#define WDOG_IRQ 24 71 72#define RTC_ADDR 0x01c20d00 73#define RTC_SIZE 0x20 74 75/* Clock Control Module/Unit */ 76#define CCMU_ADDR 0x01c20000 77#define CCMU_SIZE 0x400 78 79#define PIO_ADDR 0x01c20800 80#define PIOx_SIZE 0x400 81#define PIO_IRQ 28 82 83/* Secure ID */ 84#define SID_ADDR 0x01c23800 85#define SID_SIZE 0x400 86 87#define UARTx_SIZE 0x400 88#define UART0_ADDR 0x01c28000 89#define UART1_ADDR 0x01c28400 90#define UART2_ADDR 0x01c28800 91#define UART3_ADDR 0x01c28c00 92#define UART4_ADDR 0x01c29000 93#define UART5_ADDR 0x01c29400 94#define UART6_ADDR 0x01c29800 95#define UART7_ADDR 0x01c29c00 96#define UART0_IRQ 1 97#define UART1_IRQ 2 98#define UART2_IRQ 3 99#define UART3_IRQ 4 100#define UART4_IRQ 17 101#define UART5_IRQ 18 102#define UART6_IRQ 19 103#define UART7_IRQ 20 104 105#define USB0_ADDR 0x01c13000 /* usb otg */ 106#define USB1_ADDR 0x01c14000 /* first port up from pcb */ 107#define USB2_ADDR 0x01c1c000 /* 'top port' == above USB1 */ 108#define USBx_SIZE 0x1000 109#define USB0_IRQ 38 110#define USB1_IRQ 39 111#define USB2_IRQ 40 112 113/* Ethernet MAC Controller */ 114#define EMAC_ADDR 0x01c0b000 115#define EMAC_SIZE 0x1000 116#define EMAC_IRQ 55 117#define SXIESRAM_ADDR 0x00008000 /* combined area for EMAC fifos */ 118#define SXIESRAM_SIZE 0x4000 119 120/* Security System */ 121#define SS_ADDR 0x01c15000 122#define SS_SIZE 0x1000 123#define SS_IRQ 54 124 125/* GMAC */ 126#define GMAC_ADDR 0x01c50000 127#define GMAC_SIZE 0x10000 128#define GMAC_IRQ 85 129 130/* A1x / Cortex-A8 */ 131#define INTC_ADDR 0x01c20400 132#define INTC_SIZE 0x400 133 134/* A20 / Cortex-A7 */ 135#define GIC_ADDR 0x01c80000 /* = periphbase */ 136#define GIC_SIZE 0x8000 137#define CPUCONFG_ADDR 0x01c25c00 /* not in use */ 138#define CPUCONFG_SIZE 0x200 139#define CPUCNTRS_ADDR 0x01c25e00 /* used by sxitimer */ 140#define CPUCNTRS_SIZE 0x200 141