1/* $OpenBSD: imxanatopvar.h,v 1.2 2018/06/28 10:07:35 kettenis Exp $ */ 2/* 3 * Copyright (c) 2018 Patrick Wildt <patrick@blueri.se> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18enum imxanatop_clocks { 19 /* OSC */ 20 OSC, /* 24 MHz OSC */ 21 22 /* PLLs */ 23 ARM_PLL1, /* ARM core PLL */ 24 SYS_PLL2, /* System PLL: 528 MHz */ 25 USB1_PLL3, /* OTG USB PLL: 480 MHz */ 26 USB2_PLL, /* Host USB PLL: 480 MHz */ 27 AUD_PLL4, /* Audio PLL */ 28 VID_PLL5, /* Video PLL */ 29 ENET_PLL6, /* ENET PLL */ 30 MLB_PLL, /* MLB PLL */ 31 32 /* SYS_PLL2 PFDs */ 33 SYS_PLL2_PFD0, /* 352 MHz */ 34 SYS_PLL2_PFD1, /* 594 MHz */ 35 SYS_PLL2_PFD2, /* 396 MHz */ 36 37 /* USB1_PLL3 PFDs */ 38 USB1_PLL3_PFD0, /* 720 MHz */ 39 USB1_PLL3_PFD1, /* 540 MHz */ 40 USB1_PLL3_PFD2, /* 508.2 MHz */ 41 USB1_PLL3_PFD3, /* 454.7 MHz */ 42}; 43 44uint32_t imxanatop_decode_pll(enum imxanatop_clocks, uint32_t); 45uint32_t imxanatop_get_pll2_pfd(unsigned int); 46uint32_t imxanatop_get_pll3_pfd(unsigned int); 47