if_rl_cardbus.c revision 1.26 
1/*	$OpenBSD: if_rl_cardbus.c,v 1.26 2014/08/11 12:45:45 mpi Exp $ */
2/*	$NetBSD: if_rl_cardbus.c,v 1.3.8.3 2001/11/14 19:14:02 nathanw Exp $	*/
3
4/*
5 * Copyright (c) 2000 Masanori Kanaoka
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 *    notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 *    notice, this list of conditions and the following disclaimer in the
15 *    documentation and/or other materials provided with the distribution.
16 * 3. The name of the author may not be used to endorse or promote products
17 *    derived from this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
31/*
32 * if_rl_cardbus.c:
33 *	Cardbus specific routines for RealTek 8139 ethernet adapter.
34 *	Tested for
35 *		- elecom-Laneed	LD-10/100CBA (Accton MPX5030)
36 *		- MELCO		LPC3-TX-CB   (RealTek 8139)
37 */
38
39#include "bpfilter.h"
40
41#include <sys/param.h>
42#include <sys/systm.h>
43#include <sys/mbuf.h>
44#include <sys/socket.h>
45#include <sys/ioctl.h>
46#include <sys/errno.h>
47#include <sys/malloc.h>
48#include <sys/kernel.h>
49#include <sys/timeout.h>
50#include <sys/device.h>
51
52#include <net/if.h>
53#include <net/if_dl.h>
54#include <net/if_types.h>
55#include <net/if_media.h>
56
57#include <machine/endian.h>
58
59#if NBPFILTER > 0
60#include <net/bpf.h>
61#endif
62
63#include <netinet/in.h>
64#include <netinet/if_ether.h>
65
66#include <machine/bus.h>
67#include <machine/intr.h>
68
69#include <dev/mii/miivar.h>
70
71#include <dev/pci/pcivar.h>
72#include <dev/pci/pcireg.h>
73#include <dev/pci/pcidevs.h>
74
75#include <dev/cardbus/cardbusvar.h>
76
77/*
78 * Default to using PIO access for this driver. On SMP systems,
79 * there appear to be problems with memory mapped mode: it looks like
80 * doing too many memory mapped access back to back in rapid succession
81 * can hang the bus. I'm inclined to blame this on crummy design/construction
82 * on the part of RealTek. Memory mapped mode does appear to work on
83 * uniprocessor systems though.
84 */
85#define RL_USEIOSPACE
86
87#include <dev/ic/rtl81x9reg.h>
88
89/*
90 * Various supported device vendors/types and their names.
91 */
92const struct pci_matchid rl_cardbus_devices[] = {
93	{ PCI_VENDOR_ABOCOM, PCI_PRODUCT_ABOCOM_FE2000VX },
94	{ PCI_VENDOR_ACCTON, PCI_PRODUCT_ACCTON_5030 },
95	{ PCI_VENDOR_COREGA, PCI_PRODUCT_COREGA_2CB_TXD },
96	{ PCI_VENDOR_COREGA, PCI_PRODUCT_COREGA_CB_TXD },
97	{ PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DFE690TXD },
98	{ PCI_VENDOR_PLANEX, PCI_PRODUCT_PLANEX_FNW_3603_TX },
99	{ PCI_VENDOR_PLANEX, PCI_PRODUCT_PLANEX_FNW_3800_TX },
100	{ PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8138 },
101	{ PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8139 },
102};
103
104struct rl_cardbus_softc {
105	struct rl_softc sc_rl;	/* real rtk softc */
106
107	/* CardBus-specific goo. */
108	void *sc_ih;
109	cardbus_devfunc_t sc_ct;
110	pci_chipset_tag_t sc_pc;
111	pcitag_t sc_tag;
112	int sc_csr;
113	int sc_cben;
114	int sc_bar_reg;
115	pcireg_t sc_bar_val;
116	bus_size_t sc_mapsize;
117	int sc_intrline;
118};
119
120static int rl_cardbus_match(struct device *, void *, void *);
121static void rl_cardbus_attach(struct device *, struct device *, void *);
122static int rl_cardbus_detach(struct device *, int);
123void rl_cardbus_setup(struct rl_cardbus_softc *);
124
125struct cfattach rl_cardbus_ca = {
126	sizeof(struct rl_cardbus_softc), rl_cardbus_match, rl_cardbus_attach,
127	    rl_cardbus_detach
128};
129
130int
131rl_cardbus_match(struct device *parent, void *match, void *aux)
132{
133	return (cardbus_matchbyid((struct cardbus_attach_args *)aux,
134	    rl_cardbus_devices, nitems(rl_cardbus_devices)));
135}
136
137
138void
139rl_cardbus_attach(struct device *parent, struct device *self, void *aux)
140{
141	struct rl_cardbus_softc		*csc =
142	    (struct rl_cardbus_softc *)self;
143	struct rl_softc			*sc = &csc->sc_rl;
144	struct cardbus_attach_args	*ca = aux;
145	struct cardbus_softc		*psc =
146	    (struct cardbus_softc *)sc->sc_dev.dv_parent;
147	cardbus_chipset_tag_t		cc = psc->sc_cc;
148	cardbus_function_tag_t		cf = psc->sc_cf;
149	cardbus_devfunc_t		ct = ca->ca_ct;
150	bus_addr_t			adr;
151
152	sc->sc_dmat = ca->ca_dmat;
153	csc->sc_ct = ct;
154	csc->sc_tag = ca->ca_tag;
155	csc->sc_intrline = ca->ca_intrline;
156	csc->sc_pc = ca->ca_pc;
157
158	/*
159	 * Map control/status registers.
160	 */
161	csc->sc_csr = PCI_COMMAND_MASTER_ENABLE;
162#ifdef RL_USEIOSPACE
163	if (Cardbus_mapreg_map(ct, RL_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0,
164	    &sc->rl_btag, &sc->rl_bhandle, &adr, &csc->sc_mapsize) == 0) {
165		csc->sc_cben = CARDBUS_IO_ENABLE;
166		csc->sc_csr |= PCI_COMMAND_IO_ENABLE;
167		csc->sc_bar_reg = RL_PCI_LOIO;
168		csc->sc_bar_val = adr | PCI_MAPREG_TYPE_IO;
169	}
170#else
171	if (Cardbus_mapreg_map(ct, RL_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0,
172	    &sc->rl_btag, &sc->rl_bhandle, &adr, &csc->sc_mapsize) == 0) {
173		csc->sc_cben = CARDBUS_MEM_ENABLE;
174		csc->sc_csr |= PCI_COMMAND_MEM_ENABLE;
175		csc->sc_bar_reg = RL_PCI_LOMEM;
176		csc->sc_bar_val = adr | PCI_MAPREG_TYPE_MEM;
177	}
178#endif
179	else {
180		printf("%s: unable to map deviceregisters\n",
181			 sc->sc_dev.dv_xname);
182		return;
183	}
184
185	Cardbus_function_enable(ct);
186
187	rl_cardbus_setup(csc);
188
189	/*
190	 * Map and establish the interrupt.
191	 */
192	csc->sc_ih = cardbus_intr_establish(cc, cf, csc->sc_intrline, IPL_NET,
193	    rl_intr, sc, sc->sc_dev.dv_xname);
194	if (csc->sc_ih == NULL) {
195		printf(": couldn't establish interrupt\n");
196		Cardbus_function_disable(csc->sc_ct);
197		return;
198	}
199	printf(": irq %d", csc->sc_intrline);
200
201	sc->rl_type = RL_8139;
202
203	rl_attach(sc);
204}
205
206int
207rl_cardbus_detach(struct device *self, int flags)
208{
209	struct rl_cardbus_softc	*csc = (void *) self;
210	struct rl_softc		*sc = &csc->sc_rl;
211	struct cardbus_devfunc	*ct = csc->sc_ct;
212	int			rv;
213
214#ifdef DIAGNOSTIC
215	if (ct == NULL)
216		panic("%s: data structure lacks", sc->sc_dev.dv_xname);
217#endif
218	rv = rl_detach(sc);
219	if (rv)
220		return (rv);
221	/*
222	 * Unhook the interrupt handler.
223	 */
224	if (csc->sc_ih != NULL)
225		cardbus_intr_disestablish(ct->ct_cc, ct->ct_cf, csc->sc_ih);
226
227	/*
228	 * Release bus space and close window.
229	 */
230	if (csc->sc_bar_reg != 0)
231		Cardbus_mapreg_unmap(ct, csc->sc_bar_reg,
232			sc->rl_btag, sc->rl_bhandle, csc->sc_mapsize);
233
234	return (0);
235}
236
237void
238rl_cardbus_setup(struct rl_cardbus_softc *csc)
239{
240	struct rl_softc		*sc = &csc->sc_rl;
241	cardbus_devfunc_t	ct = csc->sc_ct;
242	cardbus_chipset_tag_t	cc = ct->ct_cc;
243	pci_chipset_tag_t	pc = csc->sc_pc;
244	pcireg_t		reg, command;
245	int			pmreg;
246
247	/*
248	 * Handle power management nonsense.
249	 */
250	if (pci_get_capability(pc, csc->sc_tag,
251	    PCI_CAP_PWRMGMT, &pmreg, 0)) {
252		command = pci_conf_read(pc, csc->sc_tag, pmreg + 4);
253		if (command & RL_PSTATE_MASK) {
254			pcireg_t		iobase, membase, irq;
255
256			/* Save important PCI config data. */
257			iobase = pci_conf_read(pc, csc->sc_tag,
258			    RL_PCI_LOIO);
259			membase = pci_conf_read(pc, csc->sc_tag,
260			    RL_PCI_LOMEM);
261			irq = pci_conf_read(pc, csc->sc_tag,
262			    PCI_PRODUCT_DELTA_8139);
263
264			/* Reset the power state. */
265			printf("%s: chip is in D%d power mode "
266			    "-- setting to D0\n", sc->sc_dev.dv_xname,
267			    command & RL_PSTATE_MASK);
268			command &= 0xFFFFFFFC;
269			pci_conf_write(pc, csc->sc_tag,
270			    pmreg + 4, command);
271
272			/* Restore PCI config data. */
273			pci_conf_write(pc, csc->sc_tag,
274			    RL_PCI_LOIO, iobase);
275			pci_conf_write(pc, csc->sc_tag,
276			    RL_PCI_LOMEM, membase);
277			pci_conf_write(pc, csc->sc_tag,
278			    PCI_PRODUCT_DELTA_8139, irq);
279		}
280	}
281
282	/* Make sure the right access type is on the CardBus bridge. */
283	(*ct->ct_cf->cardbus_ctrl)(cc, csc->sc_cben);
284	(*ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_BM_ENABLE);
285
286	/* Program the BAR */
287	pci_conf_write(pc, csc->sc_tag,
288		csc->sc_bar_reg, csc->sc_bar_val);
289
290	/* Enable the appropriate bits in the CARDBUS CSR. */
291	reg = pci_conf_read(pc, csc->sc_tag,
292	    PCI_COMMAND_STATUS_REG);
293	reg &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE);
294	reg |= csc->sc_csr;
295	pci_conf_write(pc, csc->sc_tag,
296	    PCI_COMMAND_STATUS_REG, reg);
297
298	/*
299	 * Make sure the latency timer is set to some reasonable
300	 * value.
301	 */
302	reg = pci_conf_read(pc, csc->sc_tag, PCI_BHLC_REG);
303	if (PCI_LATTIMER(reg) < 0x20) {
304		reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
305		reg |= (0x20 << PCI_LATTIMER_SHIFT);
306		pci_conf_write(pc, csc->sc_tag, PCI_BHLC_REG, reg);
307	}
308}
309
310