1/* $OpenBSD: if_rl_cardbus.c,v 1.33 2024/05/24 06:26:47 jsg Exp $ */ 2/* $NetBSD: if_rl_cardbus.c,v 1.3.8.3 2001/11/14 19:14:02 nathanw Exp $ */ 3 4/* 5 * Copyright (c) 2000 Masanori Kanaoka 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The name of the author may not be used to endorse or promote products 17 * derived from this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31/* 32 * if_rl_cardbus.c: 33 * Cardbus specific routines for Realtek 8139 ethernet adapter. 34 * Tested for 35 * - elecom-Laneed LD-10/100CBA (Accton MPX5030) 36 * - MELCO LPC3-TX-CB (Realtek 8139) 37 */ 38 39#include "bpfilter.h" 40 41#include <sys/param.h> 42#include <sys/systm.h> 43#include <sys/timeout.h> 44#include <sys/device.h> 45 46#include <net/if.h> 47#include <net/if_media.h> 48 49#include <netinet/in.h> 50#include <netinet/if_ether.h> 51 52#include <machine/bus.h> 53 54#include <dev/mii/miivar.h> 55 56#include <dev/pci/pcivar.h> 57#include <dev/pci/pcireg.h> 58#include <dev/pci/pcidevs.h> 59 60#include <dev/cardbus/cardbusvar.h> 61 62/* 63 * Default to using PIO access for this driver. On SMP systems, 64 * there appear to be problems with memory mapped mode: it looks like 65 * doing too many memory mapped access back to back in rapid succession 66 * can hang the bus. I'm inclined to blame this on crummy design/construction 67 * on the part of Realtek. Memory mapped mode does appear to work on 68 * uniprocessor systems though. 69 */ 70#define RL_USEIOSPACE 71 72#include <dev/ic/rtl81x9reg.h> 73 74/* 75 * Various supported device vendors/types and their names. 76 */ 77const struct pci_matchid rl_cardbus_devices[] = { 78 { PCI_VENDOR_ABOCOM, PCI_PRODUCT_ABOCOM_FE2000VX }, 79 { PCI_VENDOR_ACCTON, PCI_PRODUCT_ACCTON_5030 }, 80 { PCI_VENDOR_COREGA, PCI_PRODUCT_COREGA_2CB_TXD }, 81 { PCI_VENDOR_COREGA, PCI_PRODUCT_COREGA_CB_TXD }, 82 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DFE690TXD }, 83 { PCI_VENDOR_PLANEX, PCI_PRODUCT_PLANEX_FNW_3603_TX }, 84 { PCI_VENDOR_PLANEX, PCI_PRODUCT_PLANEX_FNW_3800_TX }, 85 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8138 }, 86 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8139 }, 87}; 88 89struct rl_cardbus_softc { 90 struct rl_softc sc_rl; /* real rtk softc */ 91 92 /* CardBus-specific goo. */ 93 cardbus_devfunc_t sc_ct; 94 pci_chipset_tag_t sc_pc; 95 pcitag_t sc_tag; 96 int sc_csr; 97 int sc_cben; 98 int sc_bar_reg; 99 pcireg_t sc_bar_val; 100 bus_size_t sc_mapsize; 101 int sc_intrline; 102}; 103 104static int rl_cardbus_match(struct device *, void *, void *); 105static void rl_cardbus_attach(struct device *, struct device *, void *); 106static int rl_cardbus_detach(struct device *, int); 107void rl_cardbus_setup(struct rl_cardbus_softc *); 108 109const struct cfattach rl_cardbus_ca = { 110 sizeof(struct rl_cardbus_softc), rl_cardbus_match, rl_cardbus_attach, 111 rl_cardbus_detach 112}; 113 114int 115rl_cardbus_match(struct device *parent, void *match, void *aux) 116{ 117 return (cardbus_matchbyid((struct cardbus_attach_args *)aux, 118 rl_cardbus_devices, nitems(rl_cardbus_devices))); 119} 120 121 122void 123rl_cardbus_attach(struct device *parent, struct device *self, void *aux) 124{ 125 struct rl_cardbus_softc *csc = 126 (struct rl_cardbus_softc *)self; 127 struct rl_softc *sc = &csc->sc_rl; 128 struct cardbus_attach_args *ca = aux; 129 struct cardbus_softc *psc = 130 (struct cardbus_softc *)sc->sc_dev.dv_parent; 131 cardbus_chipset_tag_t cc = psc->sc_cc; 132 cardbus_function_tag_t cf = psc->sc_cf; 133 cardbus_devfunc_t ct = ca->ca_ct; 134 bus_addr_t adr; 135 136 sc->sc_dmat = ca->ca_dmat; 137 csc->sc_ct = ct; 138 csc->sc_tag = ca->ca_tag; 139 csc->sc_intrline = ca->ca_intrline; 140 csc->sc_pc = ca->ca_pc; 141 142 /* 143 * Map control/status registers. 144 */ 145 csc->sc_csr = PCI_COMMAND_MASTER_ENABLE; 146#ifdef RL_USEIOSPACE 147 if (Cardbus_mapreg_map(ct, RL_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 148 &sc->rl_btag, &sc->rl_bhandle, &adr, &csc->sc_mapsize) == 0) { 149 csc->sc_cben = CARDBUS_IO_ENABLE; 150 csc->sc_csr |= PCI_COMMAND_IO_ENABLE; 151 csc->sc_bar_reg = RL_PCI_LOIO; 152 csc->sc_bar_val = adr | PCI_MAPREG_TYPE_IO; 153 } 154#else 155 if (Cardbus_mapreg_map(ct, RL_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0, 156 &sc->rl_btag, &sc->rl_bhandle, &adr, &csc->sc_mapsize) == 0) { 157 csc->sc_cben = CARDBUS_MEM_ENABLE; 158 csc->sc_csr |= PCI_COMMAND_MEM_ENABLE; 159 csc->sc_bar_reg = RL_PCI_LOMEM; 160 csc->sc_bar_val = adr | PCI_MAPREG_TYPE_MEM; 161 } 162#endif 163 else { 164 printf("%s: unable to map deviceregisters\n", 165 sc->sc_dev.dv_xname); 166 return; 167 } 168 169 Cardbus_function_enable(ct); 170 171 rl_cardbus_setup(csc); 172 173 /* 174 * Map and establish the interrupt. 175 */ 176 sc->sc_ih = cardbus_intr_establish(cc, cf, csc->sc_intrline, IPL_NET, 177 rl_intr, sc, sc->sc_dev.dv_xname); 178 if (sc->sc_ih == NULL) { 179 printf(": couldn't establish interrupt\n"); 180 Cardbus_function_disable(csc->sc_ct); 181 return; 182 } 183 printf(": irq %d", csc->sc_intrline); 184 185 sc->rl_type = RL_8139; 186 187 rl_attach(sc); 188} 189 190int 191rl_cardbus_detach(struct device *self, int flags) 192{ 193 struct rl_cardbus_softc *csc = (void *) self; 194 struct rl_softc *sc = &csc->sc_rl; 195 struct cardbus_devfunc *ct = csc->sc_ct; 196 int rv; 197 198#ifdef DIAGNOSTIC 199 if (ct == NULL) 200 panic("%s: data structure lacks", sc->sc_dev.dv_xname); 201#endif 202 rv = rl_detach(sc); 203 if (rv) 204 return (rv); 205 /* 206 * Unhook the interrupt handler. 207 */ 208 if (sc->sc_ih != NULL) 209 cardbus_intr_disestablish(ct->ct_cc, ct->ct_cf, sc->sc_ih); 210 211 /* 212 * Release bus space and close window. 213 */ 214 if (csc->sc_bar_reg != 0) 215 Cardbus_mapreg_unmap(ct, csc->sc_bar_reg, 216 sc->rl_btag, sc->rl_bhandle, csc->sc_mapsize); 217 218 return (0); 219} 220 221void 222rl_cardbus_setup(struct rl_cardbus_softc *csc) 223{ 224 struct rl_softc *sc = &csc->sc_rl; 225 cardbus_devfunc_t ct = csc->sc_ct; 226 cardbus_chipset_tag_t cc = ct->ct_cc; 227 pci_chipset_tag_t pc = csc->sc_pc; 228 pcireg_t reg, command; 229 int pmreg; 230 231 /* 232 * Handle power management nonsense. 233 */ 234 if (pci_get_capability(pc, csc->sc_tag, 235 PCI_CAP_PWRMGMT, &pmreg, 0)) { 236 command = pci_conf_read(pc, csc->sc_tag, pmreg + 4); 237 if (command & RL_PSTATE_MASK) { 238 pcireg_t iobase, membase, irq; 239 240 /* Save important PCI config data. */ 241 iobase = pci_conf_read(pc, csc->sc_tag, 242 RL_PCI_LOIO); 243 membase = pci_conf_read(pc, csc->sc_tag, 244 RL_PCI_LOMEM); 245 irq = pci_conf_read(pc, csc->sc_tag, 246 PCI_PRODUCT_DELTA_8139); 247 248 /* Reset the power state. */ 249 printf("%s: chip is in D%d power mode " 250 "-- setting to D0\n", sc->sc_dev.dv_xname, 251 command & RL_PSTATE_MASK); 252 command &= 0xFFFFFFFC; 253 pci_conf_write(pc, csc->sc_tag, 254 pmreg + 4, command); 255 256 /* Restore PCI config data. */ 257 pci_conf_write(pc, csc->sc_tag, 258 RL_PCI_LOIO, iobase); 259 pci_conf_write(pc, csc->sc_tag, 260 RL_PCI_LOMEM, membase); 261 pci_conf_write(pc, csc->sc_tag, 262 PCI_PRODUCT_DELTA_8139, irq); 263 } 264 } 265 266 /* Make sure the right access type is on the CardBus bridge. */ 267 (*ct->ct_cf->cardbus_ctrl)(cc, csc->sc_cben); 268 (*ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_BM_ENABLE); 269 270 /* Program the BAR */ 271 pci_conf_write(pc, csc->sc_tag, 272 csc->sc_bar_reg, csc->sc_bar_val); 273 274 /* Enable the appropriate bits in the CARDBUS CSR. */ 275 reg = pci_conf_read(pc, csc->sc_tag, 276 PCI_COMMAND_STATUS_REG); 277 reg &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE); 278 reg |= csc->sc_csr; 279 pci_conf_write(pc, csc->sc_tag, 280 PCI_COMMAND_STATUS_REG, reg); 281 282 /* 283 * Make sure the latency timer is set to some reasonable 284 * value. 285 */ 286 reg = pci_conf_read(pc, csc->sc_tag, PCI_BHLC_REG); 287 if (PCI_LATTIMER(reg) < 0x20) { 288 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 289 reg |= (0x20 << PCI_LATTIMER_SHIFT); 290 pci_conf_write(pc, csc->sc_tag, PCI_BHLC_REG, reg); 291 } 292} 293 294