1/* $OpenBSD: iommureg.h,v 1.20 2022/02/21 10:20:51 jsg Exp $ */ 2/* $NetBSD: iommureg.h,v 1.6 2001/07/20 00:07:13 eeh Exp $ */ 3 4/* 5 * Copyright (c) 1992, 1993 6 * The Regents of the University of California. All rights reserved. 7 * 8 * This software was developed by the Computer Systems Engineering group 9 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 10 * contributed to Berkeley. 11 * 12 * All advertising materials mentioning features or use of this software 13 * must display the following acknowledgement: 14 * This product includes software developed by the University of 15 * California, Lawrence Berkeley Laboratory. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions 19 * are met: 20 * 1. Redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer. 22 * 2. Redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution. 25 * 3. Neither the name of the University nor the names of its contributors 26 * may be used to endorse or promote products derived from this software 27 * without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 30 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 31 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 32 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 33 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 35 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 37 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 38 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 39 * SUCH DAMAGE. 40 * 41 * @(#)sbusreg.h 8.1 (Berkeley) 6/11/93 42 */ 43 44#ifndef _SPARC64_DEV_IOMMUREG_H_ 45#define _SPARC64_DEV_IOMMUREG_H_ 46 47/* 48 * UltraSPARC IOMMU registers, common to both the sbus and PCI 49 * controllers. 50 */ 51 52/* iommu registers */ 53struct iommureg { 54 volatile u_int64_t iommu_cr; /* IOMMU control register */ 55 volatile u_int64_t iommu_tsb; /* IOMMU TSB base register */ 56 volatile u_int64_t iommu_flush; /* IOMMU flush register */ 57 volatile u_int64_t iommu_ctxflush; 58 volatile u_int64_t iommu_reserved[28]; 59 volatile u_int64_t iommu_cache_flush; 60 volatile u_int64_t iommu_cache_invalidate; 61 volatile u_int64_t iommu_reserved2[30]; 62}; 63 64/* streaming buffer registers */ 65struct iommu_strbuf { 66 volatile u_int64_t strbuf_ctl; /* streaming buffer control reg */ 67 volatile u_int64_t strbuf_pgflush; /* streaming buffer page flush */ 68 volatile u_int64_t strbuf_flushsync;/* streaming buffer flush sync */ 69}; 70 71#define IOMMUREG(x) (offsetof(struct iommureg, x)) 72#define STRBUFREG(x) (offsetof(struct iommu_strbuf, x)) 73 74/* streaming buffer control register */ 75#define STRBUF_EN 0x000000000000000001LL 76#define STRBUF_D 0x000000000000000002LL 77 78/* control register bits */ 79#define IOMMUCR_TSB1K 0x000000000000000000LL /* Number of entries in IOTSB */ 80#define IOMMUCR_TSB2K 0x000000000000010000LL 81#define IOMMUCR_TSB4K 0x000000000000020000LL 82#define IOMMUCR_TSB8K 0x000000000000030000LL 83#define IOMMUCR_TSB16K 0x000000000000040000LL 84#define IOMMUCR_TSB32K 0x000000000000050000LL 85#define IOMMUCR_TSB64K 0x000000000000060000LL 86#define IOMMUCR_TSB128K 0x000000000000070000LL 87#define IOMMUCR_TSBMASK 0xfffffffffffff8ffffLL /* Mask for above */ 88#define IOMMUCR_8KPG 0x000000000000000000LL /* 8K iommu page size */ 89#define IOMMUCR_64KPG 0x000000000000000004LL /* 64K iommu page size */ 90#define IOMMUCR_DE 0x000000000000000002LL /* Diag enable */ 91#define IOMMUCR_EN 0x000000000000000001LL /* Enable IOMMU */ 92 93#define IOMMUCR_FIRE_PD 0x000000000000001000UL /* Process disable */ 94#define IOMMUCR_FIRE_SE 0x000000000000000400UL /* Snoop enable */ 95#define IOMMUCR_FIRE_CM_EN 0x000000000000000300UL /* Cache mode enable */ 96#define IOMMUCR_FIRE_BE 0x000000000000000002UL /* Bypass enable */ 97#define IOMMUCR_FIRE_TE 0x000000000000000001UL /* Translation enabled */ 98 99/* 100 * IOMMU stuff 101 */ 102#define IOTTE_V 0x8000000000000000LL /* Entry valid */ 103#define IOTTE_64K 0x2000000000000000LL /* 8K or 64K page? */ 104#define IOTTE_8K 0x0000000000000000LL 105#define IOTTE_STREAM 0x1000000000000000LL /* Is page streamable? */ 106#define IOTTE_LOCAL 0x0800000000000000LL /* Accesses to same bus segment? */ 107#define IOTTE_CONTEXT 0x07ff800000000000LL /* context number */ 108#define IOTTE_PAMASK 0x00007fffffffe000LL /* Let's assume this is correct (bits 42..13) */ 109#define IOTTE_C 0x0000000000000010LL /* Accesses to cacheable space */ 110#define IOTTE_W 0x0000000000000002LL /* Writeable */ 111#define IOTTE_SOFTWARE 0x0000000000001f80LL /* For software use (bits 12..7) */ 112 113 114/* 115 * On sun4u each bus controller has a separate IOMMU. The IOMMU has 116 * a TSB which must be page aligned and physically contiguous. Mappings 117 * can be of 8K IOMMU pages or 64K IOMMU pages. We use 8K for compatibility 118 * with the CPU's MMU. 119 * 120 * On sysio, psycho, and psycho+, IOMMU TSBs using 8K pages can map the 121 * following size segments: 122 * 123 * VA size VA base TSB size tsbsize 124 * -------- -------- --------- ------- 125 * 8MB ff800000 8K 0 126 * 16MB ff000000 16K 1 127 * 32MB fe000000 32K 2 128 * 64MB fc000000 64K 3 129 * 128MB f8000000 128K 4 130 * 256MB f0000000 256K 5 131 * 512MB e0000000 512K 6 132 * 1GB c0000000 1MB 7 133 * 134 * Unfortunately, sabres on UltraSPARC IIi and IIe processors does not use 135 * this scheme to determine the IOVA base address. Instead, bits 31-29 are 136 * used to check against the Target Address Space register in the IIi and 137 * the IOMMU is used if they hit. God knows what goes on in the IIe. 138 * 139 */ 140 141 142#define IOTSB_VEND 0xffffffffU 143#define IOTSB_VSTART(sz) (u_int)(IOTSB_VEND << ((sz)+10+PGSHIFT)) 144#define IOTSB_VSIZE(sz) (u_int)(1 << ((sz)+10+PGSHIFT)) 145 146#define MAKEIOTTE(pa,w,c,s) (((pa)&IOTTE_PAMASK)|((w)?IOTTE_W:0)|((c)?IOTTE_C:0)|((s)?IOTTE_STREAM:0)|(IOTTE_V|IOTTE_8K)) 147#define IOTSBSLOT(va,sz) ((u_int)(((vaddr_t)(va))-(is->is_dvmabase))>>PGSHIFT) 148 149/* 150 * interrupt map stuff. this belongs elsewhere. 151 */ 152 153#define INTMAP_V 0x080000000LL /* Interrupt valid (enabled) */ 154#define INTMAP_TID 0x07c000000LL /* UPA target ID mask */ 155#define INTMAP_IGN 0x0000007c0LL /* Interrupt group no (sbus only). */ 156#define INTMAP_IGN_SHIFT 6 157#define INTMAP_INO 0x00000003fLL /* Interrupt number */ 158#define INTMAP_INR (INTMAP_IGN|INTMAP_INO) 159#define INTMAP_SBUSSLOT 0x000000018LL /* SBus slot # */ 160#define INTMAP_PCIBUS 0x000000010LL /* PCI bus number (A or B) */ 161#define INTMAP_PCISLOT 0x00000000cLL /* PCI slot # */ 162#define INTMAP_PCIINT 0x000000003LL /* PCI interrupt #A,#B,#C,#D */ 163#define INTMAP_OBIO 0x000000020LL /* Onboard device */ 164#define INTMAP_LSHIFT 11 /* Encode level in vector */ 165#define INTLEVENCODE(x) (((x)&0x0f)<<INTMAP_LSHIFT) 166#define INTLEV(x) (((x)>>INTMAP_LSHIFT)&0x0f) 167#define INTVEC(x) ((x)&INTMAP_INR) 168#define INTSLOT(x) (((x)>>3)&0x7) 169#define INTPRI(x) ((x)&0x7) 170#define INTIGN(x) ((x)&INTMAP_IGN) 171#define INTINO(x) ((x)&INTMAP_INO) 172#define INTTID_SHIFT 26 173#define INTTID(x) (((x) & INTMAP_TID) >> INTTID_SHIFT) 174 175#define INTPCI_MAXOBINO 0x16 /* maximum OBIO INO value for PCI */ 176#define INTPCIOBINOX(x) ((x)&0x1f) /* OBIO ino index (for PCI machines) */ 177#define INTPCIINOX(x) (((x)&0x1c)>>2) /* PCI ino index */ 178 179#define INTCLR_IDLE 0 180 181#endif /* _SPARC64_DEV_IOMMUREG_H_ */ 182