1/* $OpenBSD: stfpcie.c,v 1.3 2023/11/27 13:42:19 jsg Exp $ */ 2/* 3 * Copyright (c) 2023 Mark Kettenis <kettenis@openbsd.org> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18#include <sys/param.h> 19#include <sys/systm.h> 20#include <sys/device.h> 21#include <sys/evcount.h> 22#include <sys/extent.h> 23#include <sys/malloc.h> 24 25#include <machine/intr.h> 26#include <machine/bus.h> 27#include <machine/fdt.h> 28 29#include <dev/pci/pcidevs.h> 30#include <dev/pci/pcireg.h> 31#include <dev/pci/pcivar.h> 32 33#include <dev/ofw/openfirm.h> 34#include <dev/ofw/ofw_clock.h> 35#include <dev/ofw/ofw_gpio.h> 36#include <dev/ofw/ofw_misc.h> 37#include <dev/ofw/ofw_pinctrl.h> 38#include <dev/ofw/ofw_power.h> 39#include <dev/ofw/fdt.h> 40 41/* 42 * This driver is based on preliminary device tree bindings and will 43 * almost certainly need changes once the official bindings land in 44 * mainline Linux. Support for these preliminary bindings will be 45 * dropped as soon as official bindings are available. 46 */ 47 48#define GEN_SETTINGS 0x80 49#define PORT_TYPE_RP (1 << 0) 50#define PCI_IDS_DW1 0x9c 51#define PCIE_PCI_IOV_DW0 0xb4 52#define PHY_FUNCTION_DIS (1 << 15) 53#define PCIE_BAR_WIN 0xfc 54#define PFETCH_MEMWIN_64BADDR (1 << 3) 55#define IMASK_LOCAL 0x180 56#define IMASK_INT_INTA (1 << 24) 57#define IMASK_INT_INTB (1 << 25) 58#define IMASK_INT_INTC (1 << 26) 59#define IMASK_INT_INTD (1 << 27) 60#define IMASK_INT_INTX (0xf << 24) 61#define IMASK_INT_MSI (1 << 28) 62#define ISTATUS_LOCAL 0x184 63#define PM_MSI_INT_INTA (1 << 24) 64#define PM_MSI_INT_INTB (1 << 25) 65#define PM_MSI_INT_INTC (1 << 26) 66#define PM_MSI_INT_INTD (1 << 27) 67#define PM_MSI_INT_INTX (0xf << 24) 68#define PM_MSI_INT_MSI (1 << 28) 69#define IMSI_ADDR 0x190 70#define ISTATUS_MSI 0x194 71#define PMSG_SUPPORT_RX 0x3f0 72#define PMSG_LTR_SUPPORT (1 << 2) 73#define ATR_AXI4_SLV0_SRCADDR_PARAM(n) (0x800 + (n) * 0x20) 74#define ATR_IMPL (1 << 0) 75#define ATR_SIZE_SHIFT 1 76#define ATR_AXI4_SLV0_SRC_ADDR(n) (0x804 + (n) * 0x20) 77#define ATR_AXI4_SLV0_TRSL_ADDR_LSB(n) (0x808 + (n) * 0x20) 78#define ATR_AXI4_SLV0_TRSL_ADDR_UDW(n) (0x80c + (n) * 0x20) 79#define ATR_AXI4_SLV0_TRSL_PARAM(n) (0x810 + (n) * 0x20) 80#define TRSL_ID_PCIE_RX_TX 0 81#define TRSL_ID_PCIE_CONFIG 1 82 83#define STG_PCIE0_BASE 0x048 84#define STG_PCIE1_BASE 0x1f8 85 86#define STG_ARFUN 0x078 87#define STG_ARFUN_AXI4_SLVL_MASK (0x7ffff << 8) 88#define STG_ARFUN_AXI4_SLVL_SHIFT 8 89#define STG_PHY_FUNC_SHIFT 9 90#define STG_AWFUN 0x07c 91#define STG_AWFUN_AXI4_SLVL_MASK (0x7ffff << 0) 92#define STG_AWFUN_AXI4_SLVL_SHIFT 0 93#define STG_AWFUN_CKREF_SRC_MASK (0x3 << 18) 94#define STG_AWFUN_CKREF_SRC_SHIFT 18 95#define STG_AWFUN_CLKREQ (1 << 22) 96#define STG_RP_NEP 0x0e8 97#define STG_K_RP_NEP (1 << 8) 98#define STG_LNKSTA 0x170 99#define STG_DATA_LINK_ACTIVE (1 << 5) 100 101#define HREAD4(sc, reg) \ 102 (bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))) 103#define HWRITE4(sc, reg, val) \ 104 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 105 106struct stfpcie_range { 107 uint32_t flags; 108 uint64_t pci_base; 109 uint64_t phys_base; 110 uint64_t size; 111}; 112 113struct stfpcie_intx { 114 int (*si_func)(void *); 115 void *si_arg; 116 int si_ipl; 117 int si_flags; 118 int si_pin; 119 struct evcount si_count; 120 char *si_name; 121 struct stfpcie_softc *si_sc; 122 TAILQ_ENTRY(stfpcie_intx) si_next; 123}; 124 125#define STFPCIE_NUM_MSI 32 126 127struct stfpcie_msi { 128 int (*sm_func)(void *); 129 void *sm_arg; 130 int sm_ipl; 131 int sm_flags; 132 int sm_vec; 133 struct evcount sm_count; 134 char *sm_name; 135}; 136 137struct stfpcie_softc { 138 struct device sc_dev; 139 bus_space_tag_t sc_iot; 140 bus_space_handle_t sc_ioh; 141 bus_space_handle_t sc_cfg_ioh; 142 bus_dma_tag_t sc_dmat; 143 144 int sc_node; 145 int sc_acells; 146 int sc_scells; 147 int sc_pacells; 148 int sc_pscells; 149 struct stfpcie_range *sc_ranges; 150 int sc_nranges; 151 152 struct bus_space sc_bus_iot; 153 struct bus_space sc_bus_memt; 154 155 struct machine_pci_chipset sc_pc; 156 struct extent *sc_busex; 157 struct extent *sc_memex; 158 struct extent *sc_pmemex; 159 struct extent *sc_ioex; 160 int sc_bus; 161 162 void *sc_ih; 163 struct interrupt_controller sc_ic; 164 TAILQ_HEAD(,stfpcie_intx) sc_intx[4]; 165 166 uint32_t sc_msi_addr; 167 struct stfpcie_msi sc_msi[STFPCIE_NUM_MSI]; 168}; 169 170struct stfpcie_intr_handle { 171 struct machine_intr_handle pih_ih; 172 struct stfpcie_softc *pih_sc; 173 struct stfpcie_msi *pih_sm; 174}; 175 176int stfpcie_match(struct device *, void *, void *); 177void stfpcie_attach(struct device *, struct device *, void *); 178 179const struct cfattach stfpcie_ca = { 180 sizeof (struct stfpcie_softc), stfpcie_match, stfpcie_attach 181}; 182 183struct cfdriver stfpcie_cd = { 184 NULL, "stfpcie", DV_DULL 185}; 186 187int 188stfpcie_match(struct device *parent, void *match, void *aux) 189{ 190 struct fdt_attach_args *faa = aux; 191 192 return OF_is_compatible(faa->fa_node, "starfive,jh7110-pcie"); 193} 194 195int stfpcie_intr(void *); 196void *stfpcie_intx_intr_establish(void *, int *, int, 197 struct cpu_info *, int (*)(void *), void *, char *); 198void stfpcie_intx_intr_disestablish(void *); 199void stfpcie_intx_intr_barrier(void *); 200 201void stfpcie_attach_hook(struct device *, struct device *, 202 struct pcibus_attach_args *); 203int stfpcie_bus_maxdevs(void *, int); 204pcitag_t stfpcie_make_tag(void *, int, int, int); 205void stfpcie_decompose_tag(void *, pcitag_t, int *, int *, int *); 206int stfpcie_conf_size(void *, pcitag_t); 207pcireg_t stfpcie_conf_read(void *, pcitag_t, int); 208void stfpcie_conf_write(void *, pcitag_t, int, pcireg_t); 209int stfpcie_probe_device_hook(void *, struct pci_attach_args *); 210 211int stfpcie_intr_map(struct pci_attach_args *, pci_intr_handle_t *); 212const char *stfpcie_intr_string(void *, pci_intr_handle_t); 213void *stfpcie_intr_establish(void *, pci_intr_handle_t, int, 214 struct cpu_info *, int (*)(void *), void *, char *); 215void stfpcie_intr_disestablish(void *, void *); 216 217int stfpcie_bs_iomap(bus_space_tag_t, bus_addr_t, bus_size_t, int, 218 bus_space_handle_t *); 219int stfpcie_bs_memmap(bus_space_tag_t, bus_addr_t, bus_size_t, int, 220 bus_space_handle_t *); 221 222struct interrupt_controller stfpcie_ic = { 223 .ic_barrier = intr_barrier 224}; 225 226void 227stfpcie_attach(struct device *parent, struct device *self, void *aux) 228{ 229 struct stfpcie_softc *sc = (struct stfpcie_softc *)self; 230 struct fdt_attach_args *faa = aux; 231 struct pcibus_attach_args pba; 232 struct regmap *rm; 233 uint32_t *ranges; 234 int i, j, nranges, rangeslen; 235 uint32_t bus_range[2]; 236 bus_addr_t cfg_base; 237 bus_size_t cfg_size; 238 bus_size_t stg_base; 239 uint32_t *perst_gpio; 240 int perst_gpiolen; 241 uint32_t reg, stg; 242 int idx, node, timo; 243 244 sc->sc_iot = faa->fa_iot; 245 246 idx = OF_getindex(faa->fa_node, "apb", "reg-names"); 247 /* XXX Preliminary bindings used a different name. */ 248 if (idx < 0) 249 idx = OF_getindex(faa->fa_node, "reg", "reg-names"); 250 if (idx < 0 || idx >= faa->fa_nreg || 251 bus_space_map(sc->sc_iot, faa->fa_reg[idx].addr, 252 faa->fa_reg[idx].size, 0, &sc->sc_ioh)) { 253 printf(": can't map registers\n"); 254 return; 255 } 256 257 idx = OF_getindex(faa->fa_node, "cfg", "reg-names"); 258 /* XXX Preliminary bindings used a different name. */ 259 if (idx < 0) 260 idx = OF_getindex(faa->fa_node, "config", "reg-names"); 261 if (idx < 0 || idx >= faa->fa_nreg || 262 bus_space_map(sc->sc_iot, faa->fa_reg[idx].addr, 263 faa->fa_reg[idx].size, 0, &sc->sc_cfg_ioh)) { 264 printf(": can't map registers\n"); 265 return; 266 } 267 cfg_base = faa->fa_reg[idx].addr; 268 cfg_size = faa->fa_reg[idx].size; 269 270 sc->sc_dmat = faa->fa_dmat; 271 sc->sc_node = faa->fa_node; 272 273 switch (cfg_base) { 274 case 0x940000000: 275 stg_base = STG_PCIE0_BASE; 276 break; 277 case 0x9c0000000: 278 stg_base = STG_PCIE1_BASE; 279 break; 280 default: 281 printf(": unknown controller at 0x%lx\n", cfg_base); 282 return; 283 } 284 285 /* 286 * XXX This was an array in the preliminary bindings; simplify 287 * when we drop support for those. 288 */ 289 if (OF_getpropintarray(sc->sc_node, "starfive,stg-syscon", &stg, 290 sizeof(stg)) < sizeof(stg)) { 291 printf(": failed to get starfive,stg-syscon\n"); 292 return; 293 } 294 295 rm = regmap_byphandle(stg); 296 if (rm == NULL) { 297 printf(": can't get regmap\n"); 298 return; 299 } 300 301 pinctrl_byname(sc->sc_node, "default"); 302 303 reg = regmap_read_4(rm, stg_base + STG_RP_NEP); 304 reg |= STG_K_RP_NEP; 305 regmap_write_4(rm, stg_base + STG_RP_NEP, reg); 306 307 reg = regmap_read_4(rm, stg_base + STG_AWFUN); 308 reg &= ~STG_AWFUN_CKREF_SRC_MASK; 309 reg |= (2 << STG_AWFUN_CKREF_SRC_SHIFT); 310 regmap_write_4(rm, stg_base + STG_AWFUN, reg); 311 312 reg = regmap_read_4(rm, stg_base + STG_AWFUN); 313 reg |= STG_AWFUN_CLKREQ; 314 regmap_write_4(rm, stg_base + STG_AWFUN, reg); 315 316 clock_enable_all(sc->sc_node); 317 reset_deassert_all(sc->sc_node); 318 319 sc->sc_acells = OF_getpropint(sc->sc_node, "#address-cells", 320 faa->fa_acells); 321 sc->sc_scells = OF_getpropint(sc->sc_node, "#size-cells", 322 faa->fa_scells); 323 sc->sc_pacells = faa->fa_acells; 324 sc->sc_pscells = faa->fa_scells; 325 326 rangeslen = OF_getproplen(sc->sc_node, "ranges"); 327 if (rangeslen <= 0 || (rangeslen % sizeof(uint32_t)) || 328 (rangeslen / sizeof(uint32_t)) % (sc->sc_acells + 329 sc->sc_pacells + sc->sc_scells)) { 330 printf(": invalid ranges property\n"); 331 return; 332 } 333 334 ranges = malloc(rangeslen, M_TEMP, M_WAITOK); 335 OF_getpropintarray(sc->sc_node, "ranges", ranges, 336 rangeslen); 337 338 nranges = (rangeslen / sizeof(uint32_t)) / 339 (sc->sc_acells + sc->sc_pacells + sc->sc_scells); 340 sc->sc_ranges = mallocarray(nranges, 341 sizeof(struct stfpcie_range), M_TEMP, M_WAITOK); 342 sc->sc_nranges = nranges; 343 344 for (i = 0, j = 0; i < sc->sc_nranges; i++) { 345 sc->sc_ranges[i].flags = ranges[j++]; 346 sc->sc_ranges[i].pci_base = ranges[j++]; 347 if (sc->sc_acells - 1 == 2) { 348 sc->sc_ranges[i].pci_base <<= 32; 349 sc->sc_ranges[i].pci_base |= ranges[j++]; 350 } 351 sc->sc_ranges[i].phys_base = ranges[j++]; 352 if (sc->sc_pacells == 2) { 353 sc->sc_ranges[i].phys_base <<= 32; 354 sc->sc_ranges[i].phys_base |= ranges[j++]; 355 } 356 sc->sc_ranges[i].size = ranges[j++]; 357 if (sc->sc_scells == 2) { 358 sc->sc_ranges[i].size <<= 32; 359 sc->sc_ranges[i].size |= ranges[j++]; 360 } 361 } 362 363 free(ranges, M_TEMP, rangeslen); 364 365 /* Mask and acknowledge all interrupts. */ 366 HWRITE4(sc, IMASK_LOCAL, 0); 367 HWRITE4(sc, ISTATUS_LOCAL, 0xffffffff); 368 369 sc->sc_ih = fdt_intr_establish(sc->sc_node, IPL_BIO | IPL_MPSAFE, 370 stfpcie_intr, sc, sc->sc_dev.dv_xname); 371 if (sc->sc_ih == NULL) { 372 printf(": can't establish interrupt\n"); 373 return; 374 } 375 376 printf("\n"); 377 378 perst_gpiolen = OF_getproplen(sc->sc_node, "perst-gpios"); 379 /* XXX Preliminary bindings used a different name. */ 380 if (perst_gpiolen <= 0) 381 perst_gpiolen = OF_getproplen(sc->sc_node, "reset-gpios"); 382 if (perst_gpiolen <= 0) 383 return; 384 385 /* Assert PERST#. */ 386 perst_gpio = malloc(perst_gpiolen, M_TEMP, M_WAITOK); 387 if (OF_getpropintarray(sc->sc_node, "perst-gpios", 388 perst_gpio, perst_gpiolen) != perst_gpiolen) { 389 OF_getpropintarray(sc->sc_node, "reset-gpios", 390 perst_gpio, perst_gpiolen); 391 } 392 gpio_controller_config_pin(perst_gpio, GPIO_CONFIG_OUTPUT); 393 gpio_controller_set_pin(perst_gpio, 1); 394 395 /* Disable additional functions. */ 396 for (i = 1; i < 4; i++) { 397 reg = regmap_read_4(rm, stg_base + STG_ARFUN); 398 reg &= ~STG_ARFUN_AXI4_SLVL_MASK; 399 reg |= (i << STG_PHY_FUNC_SHIFT) << STG_ARFUN_AXI4_SLVL_SHIFT; 400 regmap_write_4(rm, stg_base + STG_ARFUN, reg); 401 reg = regmap_read_4(rm, stg_base + STG_AWFUN); 402 reg &= ~STG_AWFUN_AXI4_SLVL_MASK; 403 reg |= (i << STG_PHY_FUNC_SHIFT) << STG_AWFUN_AXI4_SLVL_SHIFT; 404 regmap_write_4(rm, stg_base + STG_AWFUN, reg); 405 406 reg = HREAD4(sc, PCIE_PCI_IOV_DW0); 407 reg |= PHY_FUNCTION_DIS; 408 HWRITE4(sc, PCIE_PCI_IOV_DW0, reg); 409 } 410 reg = regmap_read_4(rm, stg_base + STG_ARFUN); 411 reg &= ~STG_ARFUN_AXI4_SLVL_MASK; 412 regmap_write_4(rm, stg_base + STG_ARFUN, reg); 413 reg = regmap_read_4(rm, stg_base + STG_AWFUN); 414 reg &= ~STG_AWFUN_AXI4_SLVL_MASK; 415 regmap_write_4(rm, stg_base + STG_AWFUN, reg); 416 417 /* Configure controller as root port. */ 418 reg = HREAD4(sc, GEN_SETTINGS); 419 reg |= PORT_TYPE_RP; 420 HWRITE4(sc, GEN_SETTINGS, reg); 421 422 /* Configure as PCI bridge. */ 423 HWRITE4(sc, PCI_IDS_DW1, 424 PCI_CLASS_BRIDGE << PCI_CLASS_SHIFT | 425 PCI_SUBCLASS_BRIDGE_PCI << PCI_SUBCLASS_SHIFT); 426 427 /* Enable prefetchable memory windows. */ 428 reg = HREAD4(sc, PCIE_BAR_WIN); 429 reg |= PFETCH_MEMWIN_64BADDR; 430 HWRITE4(sc, PCIE_BAR_WIN, reg); 431 432 /* Disable LTR message forwarding. */ 433 reg = HREAD4(sc, PMSG_SUPPORT_RX); 434 reg &= ~PMSG_LTR_SUPPORT; 435 HWRITE4(sc, PMSG_SUPPORT_RX, reg); 436 437 /* Configure config space address translation. */ 438 HWRITE4(sc, ATR_AXI4_SLV0_SRCADDR_PARAM(0), 439 cfg_base | ATR_IMPL | (flsl(cfg_size) - 1) << ATR_SIZE_SHIFT); 440 HWRITE4(sc, ATR_AXI4_SLV0_SRC_ADDR(0), cfg_base >> 32); 441 HWRITE4(sc, ATR_AXI4_SLV0_TRSL_ADDR_LSB(0), 0); 442 HWRITE4(sc, ATR_AXI4_SLV0_TRSL_ADDR_UDW(0), 0); 443 HWRITE4(sc, ATR_AXI4_SLV0_TRSL_PARAM(0), TRSL_ID_PCIE_CONFIG); 444 445 /* Configure mmio space address translation. */ 446 for (i = 0; i < sc->sc_nranges; i++) { 447 HWRITE4(sc, ATR_AXI4_SLV0_SRCADDR_PARAM(i + 1), 448 sc->sc_ranges[0].phys_base | ATR_IMPL | 449 (flsl(sc->sc_ranges[0].size) - 1) << ATR_SIZE_SHIFT); 450 HWRITE4(sc, ATR_AXI4_SLV0_SRC_ADDR(i + 1), 451 sc->sc_ranges[0].phys_base >> 32); 452 HWRITE4(sc, ATR_AXI4_SLV0_TRSL_ADDR_LSB(i + 1), 453 sc->sc_ranges[0].pci_base); 454 HWRITE4(sc, ATR_AXI4_SLV0_TRSL_ADDR_UDW(i + 1), 455 sc->sc_ranges[0].pci_base >> 32); 456 HWRITE4(sc, ATR_AXI4_SLV0_TRSL_PARAM(i + 1), 457 TRSL_ID_PCIE_RX_TX); 458 } 459 460 /* 461 * PERST# must remain asserted for at least 100us after the 462 * reference clock becomes stable. But also has to remain 463 * active at least 100ms after power up. Since we may have 464 * just powered on the device, play it safe and use 100ms. 465 */ 466 delay(100000); 467 468 /* Deassert PERST#. */ 469 gpio_controller_set_pin(perst_gpio, 0); 470 free(perst_gpio, M_TEMP, perst_gpiolen); 471 472 /* Wait for link to come up. */ 473 for (timo = 100; timo > 0; timo--) { 474 reg = regmap_read_4(rm, stg_base + STG_LNKSTA); 475 if (reg & STG_DATA_LINK_ACTIVE) 476 break; 477 delay(1000); 478 } 479 480 /* INTx handling. */ 481 node = OF_getnodebyname(sc->sc_node, "interrupt-controller"); 482 if (node) { 483 int pin; 484 485 for (pin = 0; pin < nitems(sc->sc_intx); pin++) 486 TAILQ_INIT(&sc->sc_intx[pin]); 487 sc->sc_ic.ic_node = node; 488 sc->sc_ic.ic_cookie = sc; 489 sc->sc_ic.ic_establish = stfpcie_intx_intr_establish; 490 sc->sc_ic.ic_disestablish = stfpcie_intx_intr_disestablish; 491 sc->sc_ic.ic_barrier = stfpcie_intx_intr_barrier; 492 fdt_intr_register(&sc->sc_ic); 493 } 494 495 /* MSI handling. */ 496 sc->sc_msi_addr = HREAD4(sc, IMSI_ADDR); 497 498 /* Unmask interrupts. */ 499 HWRITE4(sc, IMASK_LOCAL, IMASK_INT_MSI); 500 501 /* Create extents for our address spaces. */ 502 sc->sc_busex = extent_create("pcibus", 0, 255, 503 M_DEVBUF, NULL, 0, EX_WAITOK | EX_FILLED); 504 sc->sc_memex = extent_create("pcimem", 0, (u_long)-1, 505 M_DEVBUF, NULL, 0, EX_WAITOK | EX_FILLED); 506 sc->sc_pmemex = extent_create("pcipmem", 0, (u_long)-1, 507 M_DEVBUF, NULL, 0, EX_WAITOK | EX_FILLED); 508 sc->sc_ioex = extent_create("pciio", 0, 0xffffffff, 509 M_DEVBUF, NULL, 0, EX_WAITOK | EX_FILLED); 510 for (i = 0; i < sc->sc_nranges; i++) { 511 if ((sc->sc_ranges[i].flags & 0x03000000) == 0x01000000) { 512 extent_free(sc->sc_ioex, sc->sc_ranges[i].pci_base, 513 sc->sc_ranges[i].size, EX_WAITOK); 514 } 515 if ((sc->sc_ranges[i].flags & 0x03000000) == 0x02000000) { 516 extent_free(sc->sc_memex, sc->sc_ranges[i].pci_base, 517 sc->sc_ranges[i].size, EX_WAITOK); 518 } 519 if ((sc->sc_ranges[i].flags & 0x03000000) == 0x03000000) { 520 extent_free(sc->sc_pmemex, sc->sc_ranges[i].pci_base, 521 sc->sc_ranges[i].size, EX_WAITOK); 522 } 523 } 524 525 /* Set up bus range. */ 526 if (OF_getpropintarray(sc->sc_node, "bus-range", bus_range, 527 sizeof(bus_range)) != sizeof(bus_range) || 528 bus_range[0] >= 32 || bus_range[1] >= 32) { 529 bus_range[0] = 0; 530 bus_range[1] = 31; 531 } 532 sc->sc_bus = bus_range[0]; 533 extent_free(sc->sc_busex, bus_range[0], 534 bus_range[1] - bus_range[0] + 1, EX_WAITOK); 535 536 memcpy(&sc->sc_bus_iot, sc->sc_iot, sizeof(sc->sc_bus_iot)); 537 sc->sc_bus_iot.bus_private = sc; 538 sc->sc_bus_iot._space_map = stfpcie_bs_iomap; 539 memcpy(&sc->sc_bus_memt, sc->sc_iot, sizeof(sc->sc_bus_memt)); 540 sc->sc_bus_memt.bus_private = sc; 541 sc->sc_bus_memt._space_map = stfpcie_bs_memmap; 542 543 sc->sc_pc.pc_conf_v = sc; 544 sc->sc_pc.pc_attach_hook = stfpcie_attach_hook; 545 sc->sc_pc.pc_bus_maxdevs = stfpcie_bus_maxdevs; 546 sc->sc_pc.pc_make_tag = stfpcie_make_tag; 547 sc->sc_pc.pc_decompose_tag = stfpcie_decompose_tag; 548 sc->sc_pc.pc_conf_size = stfpcie_conf_size; 549 sc->sc_pc.pc_conf_read = stfpcie_conf_read; 550 sc->sc_pc.pc_conf_write = stfpcie_conf_write; 551 sc->sc_pc.pc_probe_device_hook = stfpcie_probe_device_hook; 552 553 sc->sc_pc.pc_intr_v = sc; 554 sc->sc_pc.pc_intr_map = stfpcie_intr_map; 555 sc->sc_pc.pc_intr_map_msi = _pci_intr_map_msi; 556 sc->sc_pc.pc_intr_map_msix = _pci_intr_map_msix; 557 sc->sc_pc.pc_intr_string = stfpcie_intr_string; 558 sc->sc_pc.pc_intr_establish = stfpcie_intr_establish; 559 sc->sc_pc.pc_intr_disestablish = stfpcie_intr_disestablish; 560 561 memset(&pba, 0, sizeof(pba)); 562 pba.pba_busname = "pci"; 563 pba.pba_iot = &sc->sc_bus_iot; 564 pba.pba_memt = &sc->sc_bus_memt; 565 pba.pba_dmat = sc->sc_dmat; 566 pba.pba_pc = &sc->sc_pc; 567 pba.pba_busex = sc->sc_busex; 568 pba.pba_memex = sc->sc_memex; 569 pba.pba_pmemex = sc->sc_pmemex; 570 pba.pba_ioex = sc->sc_ioex; 571 pba.pba_domain = pci_ndomains++; 572 pba.pba_bus = sc->sc_bus; 573#ifdef notyet 574 pba.pba_flags |= PCI_FLAGS_MSI_ENABLED; 575#endif 576 577 config_found(self, &pba, NULL); 578} 579 580void * 581stfpcie_intx_intr_establish(void *cookie, int *cell, int level, 582 struct cpu_info *ci, int (*func)(void *), void *arg, char *name) 583{ 584 struct stfpcie_softc *sc = (struct stfpcie_softc *)cookie; 585 struct stfpcie_intx *si; 586 int pin = cell[0] - 1; 587 uint32_t mask; 588 589 if (ci != NULL && !CPU_IS_PRIMARY(ci)) 590 return NULL; 591 592 if (pin < 0 || pin >= nitems(sc->sc_intx)) 593 return NULL; 594 595 /* Mask the interrupt. */ 596 mask = HREAD4(sc, IMASK_LOCAL); 597 mask &= ~(IMASK_INT_INTA << pin); 598 HWRITE4(sc, IMASK_LOCAL, mask); 599 intr_barrier(sc->sc_ih); 600 601 si = malloc(sizeof(*si), M_DEVBUF, M_WAITOK | M_ZERO); 602 si->si_func = func; 603 si->si_arg = arg; 604 si->si_ipl = level & IPL_IRQMASK; 605 si->si_flags = level & IPL_FLAGMASK; 606 si->si_pin = pin; 607 si->si_name = name; 608 if (name != NULL) 609 evcount_attach(&si->si_count, name, &si->si_pin); 610 si->si_sc = sc; 611 TAILQ_INSERT_TAIL(&sc->sc_intx[pin], si, si_next); 612 613 /* Unmask the interrupt. */ 614 mask = HREAD4(sc, IMASK_LOCAL); 615 mask |= (IMASK_INT_INTA << pin); 616 HWRITE4(sc, IMASK_LOCAL, mask); 617 618 return si; 619} 620 621void 622stfpcie_intx_intr_disestablish(void *cookie) 623{ 624 struct stfpcie_intx *si = cookie; 625 struct stfpcie_softc *sc = si->si_sc; 626 uint32_t mask; 627 628 /* Mask the interrupt. */ 629 mask = HREAD4(sc, IMASK_LOCAL); 630 mask &= ~(IMASK_INT_INTA << si->si_pin); 631 HWRITE4(sc, IMASK_LOCAL, mask); 632 intr_barrier(sc->sc_ih); 633 634 if (si->si_name) 635 evcount_detach(&si->si_count); 636 637 TAILQ_REMOVE(&sc->sc_intx[si->si_pin], si, si_next); 638 639 if (!TAILQ_EMPTY(&sc->sc_intx[si->si_pin])) { 640 /* Unmask the interrupt. */ 641 mask = HREAD4(sc, IMASK_LOCAL); 642 mask |= (IMASK_INT_INTA << si->si_pin); 643 HWRITE4(sc, IMASK_LOCAL, mask); 644 } 645 646 free(si, M_DEVBUF, sizeof(*si)); 647} 648 649void 650stfpcie_intx_intr_barrier(void *cookie) 651{ 652 struct stfpcie_intx *si = cookie; 653 struct stfpcie_softc *sc = si->si_sc; 654 655 intr_barrier(sc->sc_ih); 656} 657 658struct stfpcie_msi * 659stfpcie_msi_establish(struct stfpcie_softc *sc, int level, 660 int (*func)(void *), void *arg, char *name) 661{ 662 struct stfpcie_msi *sm; 663 int vec; 664 665 for (vec = 0; vec < STFPCIE_NUM_MSI; vec++) { 666 sm = &sc->sc_msi[vec]; 667 if (sm->sm_func == NULL) 668 break; 669 } 670 if (vec == STFPCIE_NUM_MSI) 671 return NULL; 672 673 sm->sm_func = func; 674 sm->sm_arg = arg; 675 sm->sm_ipl = level & IPL_IRQMASK; 676 sm->sm_flags = level & IPL_FLAGMASK; 677 sm->sm_vec = vec; 678 sm->sm_name = name; 679 if (name != NULL) 680 evcount_attach(&sm->sm_count, name, &sm->sm_vec); 681 682 return sm; 683 684} 685 686void 687stfpcie_msi_disestablish(struct stfpcie_softc *sc, struct stfpcie_msi *sm) 688{ 689 if (sm->sm_name) 690 evcount_detach(&sm->sm_count); 691 sm->sm_func = NULL; 692} 693 694void 695stfpcie_intx_intr(struct stfpcie_softc *sc, uint32_t status) 696{ 697 struct stfpcie_intx *si; 698 int pin, s; 699 700 for (pin = 0; pin < nitems(sc->sc_intx); pin++) { 701 if ((status & (PM_MSI_INT_INTA << pin)) == 0) 702 continue; 703 704 TAILQ_FOREACH(si, &sc->sc_intx[pin], si_next) { 705 if ((si->si_flags & IPL_MPSAFE) == 0) 706 KERNEL_LOCK(); 707 s = splraise(si->si_ipl); 708 if (si->si_func(si->si_arg)) 709 si->si_count.ec_count++; 710 splx(s); 711 if ((si->si_flags & IPL_MPSAFE) == 0) 712 KERNEL_UNLOCK(); 713 } 714 } 715} 716 717void 718stfpcie_msi_intr(struct stfpcie_softc *sc) 719{ 720 struct stfpcie_msi *sm; 721 uint32_t status; 722 int vec, s; 723 724 status = HREAD4(sc, ISTATUS_MSI); 725 if (status == 0) 726 return; 727 HWRITE4(sc, ISTATUS_MSI, status); 728 729 while (status) { 730 vec = ffs(status) - 1; 731 status &= ~(1U << vec); 732 733 sm = &sc->sc_msi[vec]; 734 if (sm->sm_func == NULL) 735 continue; 736 737 if ((sm->sm_flags & IPL_MPSAFE) == 0) 738 KERNEL_LOCK(); 739 s = splraise(sm->sm_ipl); 740 if (sm->sm_func(sm->sm_arg)) 741 sm->sm_count.ec_count++; 742 splx(s); 743 if ((sm->sm_flags & IPL_MPSAFE) == 0) 744 KERNEL_UNLOCK(); 745 } 746} 747 748int 749stfpcie_intr(void *arg) 750{ 751 struct stfpcie_softc *sc = arg; 752 uint32_t status; 753 754 status = HREAD4(sc, ISTATUS_LOCAL); 755 if (status == 0) 756 return 0; 757 758 if (status & PM_MSI_INT_INTX) 759 stfpcie_intx_intr(sc, status); 760 761 /* 762 * Ack INTx late as they are level-triggered. Ack MSI early 763 * as they are edge-triggered. 764 */ 765 HWRITE4(sc, ISTATUS_LOCAL, status); 766 767 if (status & PM_MSI_INT_MSI) 768 stfpcie_msi_intr(sc); 769 770 return 1; 771} 772 773void 774stfpcie_attach_hook(struct device *parent, struct device *self, 775 struct pcibus_attach_args *pba) 776{ 777} 778 779int 780stfpcie_bus_maxdevs(void *v, int bus) 781{ 782 struct stfpcie_softc *sc = v; 783 784 if (bus == sc->sc_bus || bus == sc->sc_bus + 1) 785 return 1; 786 return 32; 787} 788 789int 790stfpcie_find_node(int node, int bus, int device, int function) 791{ 792 uint32_t reg[5]; 793 uint32_t phys_hi; 794 int child; 795 796 phys_hi = ((bus << 16) | (device << 11) | (function << 8)); 797 798 for (child = OF_child(node); child; child = OF_peer(child)) { 799 if (OF_getpropintarray(child, "reg", 800 reg, sizeof(reg)) != sizeof(reg)) 801 continue; 802 803 if (reg[0] == phys_hi) 804 return child; 805 806 node = stfpcie_find_node(child, bus, device, function); 807 if (node) 808 return node; 809 } 810 811 return 0; 812} 813 814pcitag_t 815stfpcie_make_tag(void *v, int bus, int device, int function) 816{ 817 struct stfpcie_softc *sc = v; 818 int node; 819 820 node = stfpcie_find_node(sc->sc_node, bus, device, function); 821 return (((pcitag_t)node << 32) | 822 (bus << 20) | (device << 15) | (function << 12)); 823} 824 825void 826stfpcie_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 827{ 828 if (bp != NULL) 829 *bp = (tag >> 20) & 0xff; 830 if (dp != NULL) 831 *dp = (tag >> 15) & 0x1f; 832 if (fp != NULL) 833 *fp = (tag >> 12) & 0x7; 834} 835 836int 837stfpcie_conf_size(void *v, pcitag_t tag) 838{ 839 return PCIE_CONFIG_SPACE_SIZE; 840} 841 842pcireg_t 843stfpcie_conf_read(void *v, pcitag_t tag, int reg) 844{ 845 struct stfpcie_softc *sc = v; 846 847 tag = PCITAG_OFFSET(tag); 848 return bus_space_read_4(sc->sc_iot, sc->sc_cfg_ioh, tag | reg); 849} 850 851void 852stfpcie_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data) 853{ 854 struct stfpcie_softc *sc = v; 855 856 tag = PCITAG_OFFSET(tag); 857 bus_space_write_4(sc->sc_iot, sc->sc_cfg_ioh, tag | reg, data); 858} 859 860int 861stfpcie_probe_device_hook(void *v, struct pci_attach_args *pa) 862{ 863 struct stfpcie_softc *sc = v; 864 uint16_t rid; 865 866 rid = pci_requester_id(pa->pa_pc, pa->pa_tag); 867 pa->pa_dmat = iommu_device_map_pci(sc->sc_node, rid, pa->pa_dmat); 868 869 return 0; 870} 871 872int 873stfpcie_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 874{ 875 int pin = pa->pa_rawintrpin; 876 877 if (pin == 0 || pin > PCI_INTERRUPT_PIN_MAX) 878 return -1; 879 880 if (pa->pa_tag == 0) 881 return -1; 882 883 ihp->ih_pc = pa->pa_pc; 884 ihp->ih_tag = pa->pa_intrtag; 885 ihp->ih_intrpin = pa->pa_intrpin; 886 ihp->ih_type = PCI_INTX; 887 888 return 0; 889} 890 891const char * 892stfpcie_intr_string(void *v, pci_intr_handle_t ih) 893{ 894 switch (ih.ih_type) { 895 case PCI_MSI: 896 return "msi"; 897 case PCI_MSIX: 898 return "msix"; 899 } 900 901 return "intx"; 902} 903 904void * 905stfpcie_intr_establish(void *v, pci_intr_handle_t ih, int level, 906 struct cpu_info *ci, int (*func)(void *), void *arg, char *name) 907{ 908 struct stfpcie_softc *sc = v; 909 struct stfpcie_intr_handle *pih; 910 void *cookie; 911 912 KASSERT(ih.ih_type != PCI_NONE); 913 914 if (ih.ih_type != PCI_INTX) { 915 struct stfpcie_msi *sm; 916 uint64_t addr, data; 917 918 sm = stfpcie_msi_establish(sc, level, func, arg, name); 919 if (sm == NULL) 920 return NULL; 921 addr = sc->sc_msi_addr; 922 data = sm->sm_vec; 923 924 pih = malloc(sizeof(*pih), M_DEVBUF, M_WAITOK | M_ZERO); 925 pih->pih_ih.ih_ic = &stfpcie_ic; 926 pih->pih_sc = sc; 927 pih->pih_sm = sm; 928 929 if (ih.ih_type == PCI_MSIX) { 930 pci_msix_enable(ih.ih_pc, ih.ih_tag, 931 &sc->sc_bus_memt, ih.ih_intrpin, addr, data); 932 } else 933 pci_msi_enable(ih.ih_pc, ih.ih_tag, addr, data); 934 } else { 935 int bus, dev, fn; 936 uint32_t reg[4]; 937 938 stfpcie_decompose_tag(sc, ih.ih_tag, &bus, &dev, &fn); 939 940 reg[0] = bus << 16 | dev << 11 | fn << 8; 941 reg[1] = reg[2] = 0; 942 reg[3] = ih.ih_intrpin; 943 944 cookie = fdt_intr_establish_imap_cpu(sc->sc_node, reg, 945 sizeof(reg), level, ci, func, arg, name); 946 if (cookie == NULL) 947 return NULL; 948 949 pih = malloc(sizeof(*pih), M_DEVBUF, M_WAITOK | M_ZERO); 950 pih->pih_ih.ih_ic = &stfpcie_ic; 951 pih->pih_ih.ih_ih = cookie; 952 } 953 954 return pih; 955} 956 957void 958stfpcie_intr_disestablish(void *v, void *cookie) 959{ 960 struct stfpcie_intr_handle *pih = cookie; 961 962 if (pih->pih_sm) 963 stfpcie_msi_disestablish(pih->pih_sc, pih->pih_sm); 964 else 965 fdt_intr_disestablish(pih->pih_ih.ih_ih); 966 967 free(pih, M_DEVBUF, sizeof(*pih)); 968} 969 970int 971stfpcie_bs_iomap(bus_space_tag_t t, bus_addr_t addr, bus_size_t size, 972 int flags, bus_space_handle_t *bshp) 973{ 974 struct stfpcie_softc *sc = t->bus_private; 975 int i; 976 977 for (i = 0; i < sc->sc_nranges; i++) { 978 uint64_t pci_start = sc->sc_ranges[i].pci_base; 979 uint64_t pci_end = pci_start + sc->sc_ranges[i].size; 980 uint64_t phys_start = sc->sc_ranges[i].phys_base; 981 982 if ((sc->sc_ranges[i].flags & 0x03000000) == 0x01000000 && 983 addr >= pci_start && addr + size <= pci_end) { 984 return bus_space_map(sc->sc_iot, 985 addr - pci_start + phys_start, size, flags, bshp); 986 } 987 } 988 989 return ENXIO; 990} 991 992int 993stfpcie_bs_memmap(bus_space_tag_t t, bus_addr_t addr, bus_size_t size, 994 int flags, bus_space_handle_t *bshp) 995{ 996 struct stfpcie_softc *sc = t->bus_private; 997 int i; 998 999 for (i = 0; i < sc->sc_nranges; i++) { 1000 uint64_t pci_start = sc->sc_ranges[i].pci_base; 1001 uint64_t pci_end = pci_start + sc->sc_ranges[i].size; 1002 uint64_t phys_start = sc->sc_ranges[i].phys_base; 1003 1004 if ((sc->sc_ranges[i].flags & 0x02000000) == 0x02000000 && 1005 addr >= pci_start && addr + size <= pci_end) { 1006 return bus_space_map(sc->sc_iot, 1007 addr - pci_start + phys_start, size, flags, bshp); 1008 } 1009 } 1010 1011 return ENXIO; 1012} 1013