intr.h revision 1.46
1/* $OpenBSD: intr.h,v 1.46 2015/07/19 18:53:49 sf Exp $ */ 2/* $NetBSD: intr.h,v 1.5 1996/05/13 06:11:28 mycroft Exp $ */ 3 4/* 5 * Copyright (c) 1996 Charles M. Hannum. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Charles M. Hannum. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#ifndef _MACHINE_INTR_H_ 34#define _MACHINE_INTR_H_ 35 36#include <machine/intrdefs.h> 37 38#ifndef _LOCORE 39#include <sys/mutex.h> 40#include <machine/cpu.h> 41 42extern volatile u_int32_t lapic_tpr; /* Current interrupt priority level. */ 43 44extern int imask[]; /* Bitmasks telling what interrupts are blocked. */ 45extern int iunmask[]; /* Bitmasks telling what interrupts are accepted. */ 46 47#define IMASK(level) imask[IPL(level)] 48#define IUNMASK(level) iunmask[IPL(level)] 49 50extern void Xspllower(void); 51 52extern int splraise(int); 53extern int spllower(int); 54extern void splx(int); 55extern void softintr(int); 56 57/* 58 * compiler barrier: prevent reordering of instructions. 59 * XXX something similar will move to <sys/cdefs.h> 60 * or thereabouts. 61 * This prevents the compiler from reordering code around 62 * this "instruction", acting as a sequence point for code generation. 63 */ 64 65#define __splbarrier() __asm volatile("":::"memory") 66 67/* SPL asserts */ 68#ifdef DIAGNOSTIC 69/* 70 * Although this function is implemented in MI code, it must be in this MD 71 * header because we don't want this header to include MI includes. 72 */ 73void splassert_fail(int, int, const char *); 74extern int splassert_ctl; 75void splassert_check(int, const char *); 76#define splassert(__wantipl) do { \ 77 if (splassert_ctl > 0) { \ 78 splassert_check(__wantipl, __func__); \ 79 } \ 80} while (0) 81#define splsoftassert(wantipl) splassert(wantipl) 82#else 83#define splassert(wantipl) do { /* nada */ } while (0) 84#define splsoftassert(wantipl) do { /* nada */ } while (0) 85#endif 86 87/* 88 * Define the splraise and splx code in macros, so that the code can be 89 * reused in a profiling build in a way that does not cause recursion. 90 */ 91#define _SPLRAISE(ocpl, ncpl) \ 92 ocpl = lapic_tpr; \ 93 if (ncpl > ocpl) \ 94 lapic_tpr = ncpl 95 96 97#define _SPLX(ncpl) \ 98 lapic_tpr = ncpl; \ 99 if (curcpu()->ci_ipending & IUNMASK(ncpl)) \ 100 Xspllower() 101 102/* 103 * Hardware interrupt masks 104 */ 105#define splbio() splraise(IPL_BIO) 106#define splnet() splraise(IPL_NET) 107#define spltty() splraise(IPL_TTY) 108#define splaudio() splraise(IPL_AUDIO) 109#define splclock() splraise(IPL_CLOCK) 110#define splstatclock() splclock() 111#define splipi() splraise(IPL_IPI) 112 113/* 114 * Software interrupt masks 115 */ 116#define splsoftclock() splraise(IPL_SOFTCLOCK) 117#define splsoftnet() splraise(IPL_SOFTNET) 118#define splsofttty() splraise(IPL_SOFTTTY) 119 120/* 121 * Miscellaneous 122 */ 123#define splvm() splraise(IPL_VM) 124#define splhigh() splraise(IPL_HIGH) 125#define splsched() splraise(IPL_SCHED) 126#define spllock() splhigh() 127#define spl0() spllower(IPL_NONE) 128 129#include <machine/pic.h> 130 131struct cpu_info; 132 133#ifdef MULTIPROCESSOR 134void i386_send_ipi(struct cpu_info *, int); 135int i386_fast_ipi(struct cpu_info *, int); 136void i386_broadcast_ipi(int); 137void i386_ipi_handler(void); 138void i386_setperf_ipi(struct cpu_info *); 139 140extern void (*ipifunc[I386_NIPI])(struct cpu_info *); 141#endif 142 143#endif /* !_LOCORE */ 144 145/* 146 * Generic software interrupt support. 147 */ 148 149#define I386_SOFTINTR_SOFTCLOCK 0 150#define I386_SOFTINTR_SOFTNET 1 151#define I386_SOFTINTR_SOFTTTY 2 152#define I386_NSOFTINTR 3 153 154#ifndef _LOCORE 155#include <sys/queue.h> 156 157struct i386_soft_intrhand { 158 TAILQ_ENTRY(i386_soft_intrhand) 159 sih_q; 160 struct i386_soft_intr *sih_intrhead; 161 void (*sih_fn)(void *); 162 void *sih_arg; 163 int sih_pending; 164}; 165 166struct i386_soft_intr { 167 TAILQ_HEAD(, i386_soft_intrhand) 168 softintr_q; 169 int softintr_ssir; 170 struct mutex softintr_lock; 171}; 172 173void *softintr_establish(int, void (*)(void *), void *); 174void softintr_disestablish(void *); 175void softintr_init(void); 176void softintr_dispatch(int); 177 178#define softintr_schedule(arg) \ 179do { \ 180 struct i386_soft_intrhand *__sih = (arg); \ 181 struct i386_soft_intr *__si = __sih->sih_intrhead; \ 182 \ 183 mtx_enter(&__si->softintr_lock); \ 184 if (__sih->sih_pending == 0) { \ 185 TAILQ_INSERT_TAIL(&__si->softintr_q, __sih, sih_q); \ 186 __sih->sih_pending = 1; \ 187 softintr(__si->softintr_ssir); \ 188 } \ 189 mtx_leave(&__si->softintr_lock); \ 190} while (/*CONSTCOND*/ 0) 191#endif /* _LOCORE */ 192 193#endif /* !_MACHINE_INTR_H_ */ 194