11897Swollman/* $OpenBSD: psl.h,v 1.11 2021/03/11 11:16:57 jsg Exp $ */ 21897Swollman 31897Swollman/* 41897Swollman * Copyright (c) 1999-2004 Michael Shalayeff 51897Swollman * All rights reserved. 61897Swollman * 71897Swollman * Redistribution and use in source and binary forms, with or without 8100441Scharnier * modification, are permitted provided that the following conditions 91897Swollman * are met: 101897Swollman * 1. Redistributions of source code must retain the above copyright 111897Swollman * notice, this list of conditions and the following disclaimer. 12100441Scharnier * 2. Redistributions in binary form must reproduce the above copyright 131897Swollman * notice, this list of conditions and the following disclaimer in the 141897Swollman * documentation and/or other materials provided with the distribution. 151897Swollman * 16100441Scharnier * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 171897Swollman * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 181897Swollman * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 191897Swollman * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 20100441Scharnier * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 211897Swollman * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 221897Swollman * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 231897Swollman * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24100441Scharnier * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 251897Swollman * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 261897Swollman * THE POSSIBILITY OF SUCH DAMAGE. 271897Swollman */ 281897Swollman 2912798Swpaul#ifndef _MACHINE_PSL_H_ 30100441Scharnier#define _MACHINE_PSL_H_ 311897Swollman 32146833Sstefanf/* 3312798Swpaul * Reference: 341897Swollman * 1. PA-RISC 1.1 Architecture and Instruction Set Manual 3599979Salfred * Hewlett Packard, 3rd Edition, February 1994; Part Number 09740-90039 361897Swollman */ 37100441Scharnier 38100441Scharnier/* 39100441Scharnier * Processor Status Word Bit Positions (in PA-RISC bit order) 401897Swollman */ 418874Srgrimes#define PSL_Y_POS (0) 428874Srgrimes#define PSL_Z_POS (1) 431897Swollman#define PSL_SS_POS (3) /* Reserved, Software-defined */ 441897Swollman#define PSL_W_POS (4) 451897Swollman#define PSL_E_POS (5) 4612798Swpaul#define PSL_S_POS (6) 47149682Sstefanf#define PSL_T_POS (7) 481897Swollman#define PSL_H_POS (8) 491897Swollman#define PSL_L_POS (9) 50152398Sdwmalone#define PSL_N_POS (10) 5192921Simp#define PSL_X_POS (11) 5292921Simp#define PSL_B_POS (12) 5392921Simp#define PSL_C_POS (13) 54149695Sstefanf#define PSL_V_POS (14) 5592921Simp#define PSL_M_POS (15) 5692921Simp#define PSL_CB_POS (16) 57152398Sdwmalone#define PSL_O_POS (24) 58152398Sdwmalone#define PSL_G_POS (25) 59152398Sdwmalone#define PSL_F_POS (26) 60152398Sdwmalone#define PSL_R_POS (27) 611897Swollman#define PSL_Q_POS (28) 621897Swollman#define PSL_P_POS (29) 638874Srgrimes#define PSL_D_POS (30) 641897Swollman#define PSL_I_POS (31) 651897Swollman 66149695Sstefanf#define PSL_BITS "\020\001I\002D\003P\004Q\005R\006F\007G\010O" \ 671897Swollman "\021M\022V\023C\024B\025X\026N\027L\030H" \ 6812798Swpaul "\031T\032S\033E\034W\037Z\040Y" 6912798Swpaul 7012798Swpaul/* 7112798Swpaul * Processor Status Word Bit Values 721897Swollman */ 731897Swollman#define PSL_Y (1 << (31-PSL_Y_POS)) /* Data Debug Trap Disable */ 741897Swollman#define PSL_Z (1 << (31-PSL_Z_POS)) /* Instruction Debug Trap Disable */ 751897Swollman#define PSL_SS (1 << (31-PSL_SS_POS)) /* Reserved; Software Single-Step */ 761897Swollman#define PSL_W (1 << (31-PSL_W_POS)) /* 64bit address decode enable */ 771897Swollman#define PSL_E (1 << (31-PSL_E_POS)) /* Little Endian Memory Access Enable */ 781897Swollman#define PSL_S (1 << (31-PSL_S_POS)) /* Secure Interval Timer */ 791897Swollman#define PSL_T (1 << (31-PSL_T_POS)) /* Taken Branch Trap Enable */ 801897Swollman#define PSL_H (1 << (31-PSL_H_POS)) /* Higher-privilege Transfer Trap Enable */ 811897Swollman#define PSL_L (1 << (31-PSL_L_POS)) /* Lower-privilege Transfer Trap Enable */ 821897Swollman#define PSL_N (1 << (31-PSL_N_POS)) /* Nullify */ 831897Swollman#define PSL_X (1 << (31-PSL_X_POS)) /* Data Memory Break Disable */ 841897Swollman#define PSL_B (1 << (31-PSL_B_POS)) /* Taken Branch */ 851897Swollman#define PSL_C (1 << (31-PSL_C_POS)) /* Instruction Address Translation Enable */ 861897Swollman#define PSL_V (1 << (31-PSL_V_POS)) /* Divide Step Correction */ 871897Swollman#define PSL_M (1 << (31-PSL_M_POS)) /* High-priority Machine Check Mask */ 881897Swollman#define PSL_CB (1 << (31-PSL_CB_POS)) /* Carry/Borrow Bits */ 89149695Sstefanf#define PSL_O (1 << (31-PSL_O_POS)) /* Force strong ordering (2.0) */ 901897Swollman#define PSL_G (1 << (31-PSL_G_POS)) /* Debug Trap Enable */ 911897Swollman#define PSL_F (1 << (31-PSL_F_POS)) /* Performance Monitor Interrupt Unmask */ 921897Swollman#define PSL_R (1 << (31-PSL_R_POS)) /* Recover Counter Enable */ 931897Swollman#define PSL_Q (1 << (31-PSL_Q_POS)) /* Interrupt State Collection Enable */ 941897Swollman#define PSL_P (1 << (31-PSL_P_POS)) /* Protection Identifier Validation Enable */ 951897Swollman#define PSL_D (1 << (31-PSL_D_POS)) /* Data Address Translation Enable */ 9612798Swpaul#define PSL_I (1 << (31-PSL_I_POS)) /* External Interrupt, Power Failure 9712798Swpaul Interrupt, and Low-Priority Machine 9812798Swpaul Check Interrupt unmask */ 9912798Swpaul 1001897Swollman/* 10112798Swpaul * Frequently Used PSW Values 10212798Swpaul */ 10312798Swpaul#define RESET_PSL (PSL_R | PSL_Q | PSL_P | PSL_D | PSL_I) 10412798Swpaul 105149695Sstefanf#endif /* _MACHINE_PSL_H_ */ 10612798Swpaul