1/* $OpenBSD: osiop_gsc.c,v 1.13 2022/03/13 08:04:38 mpi Exp $ */ 2/* $NetBSD: osiop_gsc.c,v 1.6 2002/10/02 05:17:50 thorpej Exp $ */ 3 4/* 5 * Copyright (c) 2001 Matt Fredette. All rights reserved. 6 * Copyright (c) 2001 Izumi Tsutsui. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The name of the author may not be used to endorse or promote products 17 * derived from this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30/* 31 * Copyright (c) 1998 Michael Shalayeff 32 * All rights reserved. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 3. The name of the author may not be used to endorse or promote products 43 * derived from this software without specific prior written permission. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 46 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 47 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 48 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 49 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 50 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 51 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 52 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 53 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 54 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 55 */ 56 57#include <sys/param.h> 58#include <sys/systm.h> 59#include <sys/device.h> 60#include <sys/buf.h> 61#include <sys/malloc.h> 62 63#include <scsi/scsi_all.h> 64#include <scsi/scsiconf.h> 65 66#include <machine/cpu.h> 67#include <machine/intr.h> 68#include <machine/iomod.h> 69#include <machine/autoconf.h> 70#include <machine/bus.h> 71 72#include <dev/ic/osiopreg.h> 73#include <dev/ic/osiopvar.h> 74 75#include <hppa/dev/cpudevs.h> 76#include <hppa/gsc/gscbusvar.h> 77/* #include <hppa/hppa/machdep.h> */ 78 79#define OSIOP_GSC_RESET 0x0000 80#define OSIOP_GSC_OFFSET 0x0100 81 82int osiop_gsc_match(struct device *, void *, void *); 83void osiop_gsc_attach(struct device *, struct device *, void *); 84int osiop_gsc_intr(void *); 85 86const struct cfattach osiop_gsc_ca = { 87 sizeof(struct osiop_softc), osiop_gsc_match, osiop_gsc_attach 88}; 89 90int 91osiop_gsc_match(parent, match, aux) 92 struct device *parent; 93 void *match, *aux; 94{ 95 struct gsc_attach_args *ga = aux; 96 97 if (ga->ga_type.iodc_type != HPPA_TYPE_FIO || 98 ga->ga_type.iodc_sv_model != HPPA_FIO_GSCSI) 99 return 0; 100 101 return 1; 102} 103 104void 105osiop_gsc_attach(parent, self, aux) 106 struct device *parent, *self; 107 void *aux; 108{ 109 struct osiop_softc *sc = (void *)self; 110 struct gsc_attach_args *ga = aux; 111 bus_space_handle_t ioh; 112 113 sc->sc_bst = ga->ga_iot; 114 sc->sc_dmat = ga->ga_dmatag; 115 if (bus_space_map(sc->sc_bst, ga->ga_hpa, 116 OSIOP_GSC_OFFSET + OSIOP_NREGS, 0, &ioh)) 117 panic("osiop_gsc_attach: couldn't map I/O ports"); 118 if (bus_space_subregion(sc->sc_bst, ioh, 119 OSIOP_GSC_OFFSET, OSIOP_NREGS, &sc->sc_reg)) 120 panic("osiop_gsc_attach: couldn't get chip ports"); 121 122 sc->sc_clock_freq = ga->ga_ca.ca_pdc_iodc_read->filler2[14] / 1000000; 123 if (!sc->sc_clock_freq) 124 sc->sc_clock_freq = 50; 125 126 sc->sc_dcntl = OSIOP_DCNTL_EA; 127 /* XXX set burst mode to 8 words (32 bytes) */ 128 sc->sc_ctest7 = OSIOP_CTEST7_CDIS; 129 sc->sc_dmode = OSIOP_DMODE_BL8; /* | OSIOP_DMODE_FC2 */ 130 sc->sc_flags = 0; 131 sc->sc_id = 7; /* XXX */ 132 133 /* 134 * Reset the SCSI subsystem. 135 */ 136 bus_space_write_1(sc->sc_bst, ioh, OSIOP_GSC_RESET, 0); 137 DELAY(1000); 138 139 /* 140 * Call common attachment 141 */ 142#ifdef OSIOP_DEBUG 143 { 144 extern int osiop_debug; 145 osiop_debug = -1; 146 } 147#endif /* OSIOP_DEBUG */ 148 osiop_attach(sc); 149 150 (void)gsc_intr_establish((struct gsc_softc *)parent, 151 ga->ga_irq, IPL_BIO, osiop_gsc_intr, sc, sc->sc_dev.dv_xname); 152} 153 154/* 155 * interrupt handler 156 */ 157int 158osiop_gsc_intr(arg) 159 void *arg; 160{ 161 struct osiop_softc *sc = arg; 162 u_int8_t istat; 163 164 /* This is potentially nasty, since the IRQ is level triggered... */ 165 if (sc->sc_flags & OSIOP_INTSOFF) 166 return (0); 167 168 istat = osiop_read_1(sc, OSIOP_ISTAT); 169 170 if ((istat & (OSIOP_ISTAT_SIP | OSIOP_ISTAT_DIP)) == 0) 171 return (0); 172 173 /* Save interrupt details for the back-end interrupt handler */ 174 sc->sc_sstat0 = osiop_read_1(sc, OSIOP_SSTAT0); 175 sc->sc_istat = istat; 176 /* 177 * Per page 4-18 of the LSI 53C710 Technical Manual, 178 * "insert a delay equivalent to 12 BCLK periods between 179 * the reads [of DSTAT and SSTAT0] to ensure that the 180 * interrupts clear properly." 1 BCLK = 40ns. Pg. 6-10. 181 */ 182 DELAY(25); 183 sc->sc_dstat = osiop_read_1(sc, OSIOP_DSTAT); 184 185 /* Deal with the interrupt */ 186 osiop_intr(sc); 187 188#ifdef USELEDS 189 ledctl(PALED_DISK, 0, 0); 190#endif 191 192 return (1); 193} 194