bus_space_asm_armv7.S revision 1.1 
1/*	$OpenBSD: bus_space_asm_armv7.S,v 1.1 2013/05/09 20:41:47 patrick Exp $	*/
2/*	$NetBSD: bus_space_asm_armv7.S,v 1.3 2003/03/27 19:46:14 mycroft Exp $	*/
3
4/*
5 * Copyright (c) 1997 Causality Limited.
6 * Copyright (c) 1997 Mark Brinicombe.
7 * All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 *    notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 *    notice, this list of conditions and the following disclaimer in the
16 *    documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 *    must display the following acknowledgement:
19 *	This product includes software developed by Mark Brinicombe
20 *	for the NetBSD Project.
21 * 4. The name of the company nor the name of the author may be used to
22 *    endorse or promote products derived from this software without specific
23 *    prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
26 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
27 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
28 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * SUCH DAMAGE.
36 */
37
38#include <arm/asm.h>
39#include <arm/cpuconf.h>
40
41#define	DSB	.long	0xf57ff040
42#define	ISB	.long	0xf57ff060
43#define	WFI	.long	0xe320f003
44
45/*
46 * Generic bus_space functions.
47 */
48
49/*
50 * read single
51 */
52
53ENTRY(armv7_bs_r_1)
54	DSB
55	ldrb	r0, [r1, r2]
56	mov	pc, lr
57
58#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
59ENTRY(armv7_bs_r_2)
60	DSB
61	ldrh	r0, [r1, r2]
62	mov	pc, lr
63#endif
64
65ENTRY(armv7_bs_r_4)
66	DSB
67	ldr	r0, [r1, r2]
68	mov	pc, lr
69
70/*
71 * write single
72 */
73
74ENTRY(armv7_bs_w_1)
75	strb	r3, [r1, r2]
76	DSB
77	mov	pc, lr
78
79ENTRY(armv7_bs_w_2)
80	strh	r3, [r1, r2]
81	DSB
82	mov	pc, lr
83
84ENTRY(armv7_bs_w_4)
85	str	r3, [r1, r2]
86	DSB
87	mov	pc, lr
88
89/*
90 * read multiple
91 */
92
93ENTRY(armv7_bs_rm_1)
94	add	r0, r1, r2
95	mov	r1, r3
96	ldr	r2, [sp, #0]
97	teq	r2, #0
98	moveq	pc, lr
99
1001:	ldrb	r3, [r0]
101	strb	r3, [r1], #1
102	subs	r2, r2, #1
103	bne	1b
104	DSB
105
106	mov	pc, lr
107
108ENTRY(armv7_bs_rm_2)
109	add	r0, r1, r2
110	mov	r1, r3
111	ldr	r2, [sp, #0]
112	teq	r2, #0
113	moveq	pc, lr
114
1151:	ldrh	r3, [r0]
116	strh	r3, [r1], #2
117	subs	r2, r2, #1
118	bne	1b
119	DSB
120
121	mov	pc, lr
122
123ENTRY(armv7_bs_rm_4)
124	add	r0, r1, r2
125	mov	r1, r3
126	ldr	r2, [sp, #0]
127	teq	r2, #0
128	moveq	pc, lr
129
1301:	ldr	r3, [r0]
131	str	r3, [r1], #4
132	subs	r2, r2, #1
133	bne	1b
134	DSB
135
136	mov	pc, lr
137
138/*
139 * write multiple
140 */
141
142ENTRY(armv7_bs_wm_1)
143	add	r0, r1, r2
144	mov	r1, r3
145	ldr	r2, [sp, #0]
146	teq	r2, #0
147	moveq	pc, lr
148
1491:	ldrb	r3, [r1], #1
150	strb	r3, [r0]
151	subs	r2, r2, #1
152	bne	1b
153	DSB
154
155	mov	pc, lr
156
157ENTRY(armv7_bs_wm_2)
158	add	r0, r1, r2
159	mov	r1, r3
160	ldr	r2, [sp, #0]
161	teq	r2, #0
162	moveq	pc, lr
163
1641:	ldrh	r3, [r1], #2
165	strh	r3, [r0]
166	subs	r2, r2, #1
167	bne	1b
168	DSB
169
170	mov	pc, lr
171
172ENTRY(armv7_bs_wm_4)
173	add	r0, r1, r2
174	mov	r1, r3
175	ldr	r2, [sp, #0]
176	teq	r2, #0
177	moveq	pc, lr
178
1791:	ldr	r3, [r1], #4
180	str	r3, [r0]
181	subs	r2, r2, #1
182	bne	1b
183	DSB
184
185	mov	pc, lr
186
187/*
188 * read region
189 */
190
191ENTRY(armv7_bs_rr_1)
192	add	r0, r1, r2
193	mov	r1, r3
194	ldr	r2, [sp, #0]
195	teq	r2, #0
196	moveq	pc, lr
197
1981:	ldrb	r3, [r0], #1
199	strb	r3, [r1], #1
200	subs	r2, r2, #1
201	bne	1b
202	DSB
203
204	mov	pc, lr
205
206ENTRY(armv7_bs_rr_2)
207	add	r0, r1, r2
208	mov	r1, r3
209	ldr	r2, [sp, #0]
210	teq	r2, #0
211	moveq	pc, lr
212
2131:	ldrh	r3, [r0], #2
214	strh	r3, [r1], #2
215	subs	r2, r2, #1
216	bne	1b
217	DSB
218
219	mov	pc, lr
220
221ENTRY(armv7_bs_rr_4)
222	add	r0, r1, r2
223	mov	r1, r3
224	ldr	r2, [sp, #0]
225	teq	r2, #0
226	moveq	pc, lr
227
2281:	ldr	r3, [r0], #4
229	str	r3, [r1], #4
230	subs	r2, r2, #1
231	bne	1b
232
233	mov	pc, lr
234
235/*
236 * write region.
237 */
238
239ENTRY(armv7_bs_wr_1)
240	add	r0, r1, r2
241	mov	r1, r3
242	ldr	r2, [sp, #0]
243	teq	r2, #0
244	moveq	pc, lr
245
2461:	ldrb	r3, [r1], #1
247	strb	r3, [r0], #1
248	subs	r2, r2, #1
249	bne	1b
250	DSB
251
252	mov	pc, lr
253
254ENTRY(armv7_bs_wr_2)
255	add	r0, r1, r2
256	mov	r1, r3
257	ldr	r2, [sp, #0]
258	teq	r2, #0
259	moveq	pc, lr
260
2611:	ldrh	r3, [r1], #2
262	strh	r3, [r0], #2
263	subs	r2, r2, #1
264	bne	1b
265	DSB
266
267	mov	pc, lr
268
269ENTRY(armv7_bs_wr_4)
270	add	r0, r1, r2
271	mov	r1, r3
272	ldr	r2, [sp, #0]
273	teq	r2, #0
274	moveq	pc, lr
275
2761:	ldr	r3, [r1], #4
277	str	r3, [r0], #4
278	subs	r2, r2, #1
279	bne	1b
280	DSB
281
282	mov	pc, lr
283
284/*
285 * set region
286 */
287
288ENTRY(armv7_bs_sr_1)
289	add	r0, r1, r2
290	mov	r1, r3
291	ldr	r2, [sp, #0]
292	teq	r2, #0
293	moveq	pc, lr
294
2951:	strb	r1, [r0], #1
296	subs	r2, r2, #1
297	bne	1b
298	DSB
299
300	mov	pc, lr
301
302ENTRY(armv7_bs_sr_2)
303	add	r0, r1, r2
304	mov	r1, r3
305	ldr	r2, [sp, #0]
306	teq	r2, #0
307	moveq	pc, lr
308
3091:	strh	r1, [r0], #2
310	subs	r2, r2, #1
311	bne	1b
312	DSB
313
314	mov	pc, lr
315
316ENTRY(armv7_bs_sr_4)
317	add	r0, r1, r2
318	mov	r1, r3
319	ldr	r2, [sp, #0]
320	teq	r2, #0
321	moveq	pc, lr
322
3231:	str	r1, [r0], #4
324	subs	r2, r2, #1
325	bne	1b
326	DSB
327
328	mov	pc, lr
329
330/*
331 * copy region
332 */
333
334ENTRY(armv7_bs_c_2)
335	add	r0, r1, r2
336	ldr	r2, [sp, #0]
337	add	r1, r2, r3
338	ldr	r2, [sp, #4]
339	teq	r2, #0
340	moveq	pc, lr
341
342	cmp	r0, r1
343	blt	2f
344
3451:	ldrh	r3, [r0], #2
346	strh	r3, [r1], #2
347	subs	r2, r2, #1
348	bne	1b
349	DSB
350
351	mov	pc, lr
352
3532:	add	r0, r0, r2, lsl #1
354	add	r1, r1, r2, lsl #1
355	sub	r0, r0, #2
356	sub	r1, r1, #2
357
3583:	ldrh	r3, [r0], #-2
359	strh	r3, [r1], #-2
360	subs	r2, r2, #1
361	bne	3b
362	DSB
363
364	mov	pc, lr
365