1/* $OpenBSD: intrdefs.h,v 1.24 2024/05/26 13:37:31 kettenis Exp $ */ 2/* $NetBSD: intrdefs.h,v 1.2 2003/05/04 22:01:56 fvdl Exp $ */ 3 4#ifndef _AMD64_INTRDEFS_H 5#define _AMD64_INTRDEFS_H 6 7/* 8 * Interrupt priority levels. 9 * 10 * There are tty, network and disk drivers that use free() at interrupt 11 * time, so imp > (tty | net | bio). 12 * 13 * Since run queues may be manipulated by both the statclock and tty, 14 * network, and disk drivers, clock > imp. 15 * 16 * IPL_HIGH must block everything that can manipulate a run queue. 17 * 18 * The level numbers are picked to fit into APIC vector priorities. 19 * 20 */ 21#define IPL_NONE 0x0 /* nothing */ 22#define IPL_SOFTCLOCK 0x1 /* timeouts */ 23#define IPL_SOFTNET 0x2 /* protocol stacks */ 24#define IPL_BIO 0x3 /* block I/O */ 25#define IPL_NET 0x4 /* network */ 26#define IPL_SOFTTTY 0x8 /* delayed terminal handling */ 27#define IPL_TTY 0x9 /* terminal */ 28#define IPL_VM 0xa /* memory allocation */ 29#define IPL_AUDIO 0xb /* audio */ 30#define IPL_CLOCK 0xc /* clock */ 31#define IPL_SCHED IPL_CLOCK 32#define IPL_STATCLOCK IPL_CLOCK 33#define IPL_HIGH 0xd /* everything */ 34#define IPL_IPI 0xe /* inter-processor interrupts */ 35#define NIPL 16 36 37#define IPL_MPFLOOR IPL_TTY 38#define IPL_MPSAFE 0x100 39#define IPL_WAKEUP 0x200 40 41/* Interrupt sharing types. */ 42#define IST_NONE 0 /* none */ 43#define IST_PULSE 1 /* pulsed */ 44#define IST_EDGE 2 /* edge-triggered */ 45#define IST_LEVEL 3 /* level-triggered */ 46 47/* 48 * Local APIC masks. Must not conflict with SIR_* above, and must 49 * be >= NUM_LEGACY_IRQs. Note that LIR_IPI must be first. 50 */ 51#define LIR_IPI 63 52#define LIR_TIMER 62 53 54/* Soft interrupt masks. */ 55#define SIR_CLOCK 61 56#define SIR_NET 60 57#define SIR_TTY 59 58 59#define LIR_XEN 58 60#define LIR_HYPERV 57 61 62/* 63 * Maximum # of interrupt sources per CPU. 64 to fit in one word. 64 * ioapics can theoretically produce more, but it's not likely to 65 * happen. For multiple ioapics, things can be routed to different 66 * CPUs. 67 */ 68#define MAX_INTR_SOURCES 64 69#define NUM_LEGACY_IRQS 16 70 71/* 72 * Low and high boundaries between which interrupt gates will 73 * be allocated in the IDT. 74 */ 75#define IDT_INTR_LOW (0x20 + NUM_LEGACY_IRQS) 76#define IDT_INTR_HIGH 0xef 77 78#define X86_IPI_HALT 0x00000001 79#define X86_IPI_NOP 0x00000002 80#define X86_IPI_VMCLEAR_VMM 0x00000004 81#define X86_IPI_PCTR 0x00000010 82#define X86_IPI_MTRR 0x00000020 83#define X86_IPI_SETPERF 0x00000040 84#define X86_IPI_DDB 0x00000080 85#define X86_IPI_START_VMM 0x00000100 86#define X86_IPI_STOP_VMM 0x00000200 87#define X86_IPI_WBINVD 0x00000400 88 89#define X86_NIPI 12 90 91#define IREENT_MAGIC 0x18041969 92 93#endif /* _AMD64_INTRDEFS_H */ 94