1;; Scheduling description for UltraSPARC-III. 2;; Copyright (C) 2002 Free Software Foundation, Inc. 3;; 4;; This file is part of GNU CC. 5;; 6;; GNU CC is free software; you can redistribute it and/or modify 7;; it under the terms of the GNU General Public License as published by 8;; the Free Software Foundation; either version 2, or (at your option) 9;; any later version. 10;; 11;; GNU CC is distributed in the hope that it will be useful, 12;; but WITHOUT ANY WARRANTY; without even the implied warranty of 13;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14;; GNU General Public License for more details. 15;; 16;; You should have received a copy of the GNU General Public License 17;; along with GNU CC; see the file COPYING. If not, write to 18;; the Free Software Foundation, 59 Temple Place - Suite 330, 19;; Boston, MA 02111-1307, USA. 20 21;; UltraSPARC-III is a quad-issue processor. 22;; 23;; It is also a much simpler beast than Ultra-I/II, no silly 24;; slotting rules and both integer units are fully symmetric. 25;; It does still have single-issue instructions though. 26 27(define_automaton "ultrasparc3_0,ultrasparc3_1") 28 29(define_cpu_unit "us3_ms,us3_br,us3_fpm" "ultrasparc3_0") 30(define_cpu_unit "us3_a0,us3_a1,us3_slot0,\ 31 us3_slot1,us3_slot2,us3_slot3,us3_fpa" "ultrasparc3_1") 32(define_cpu_unit "us3_load_writeback" "ultrasparc3_1") 33 34(define_reservation "us3_slotany" "(us3_slot0 | us3_slot1 | us3_slot2 | us3_slot3)") 35(define_reservation "us3_single_issue" "us3_slot0 + us3_slot1 + us3_slot2 + us3_slot3") 36(define_reservation "us3_ax" "(us3_a0 | us3_a1)") 37 38(define_insn_reservation "us3_single" 1 39 (and (eq_attr "cpu" "ultrasparc3") 40 (eq_attr "type" "multi,flushw,iflush,trap")) 41 "us3_single_issue") 42 43(define_insn_reservation "us3_integer" 1 44 (and (eq_attr "cpu" "ultrasparc3") 45 (eq_attr "type" "ialu,shift,compare")) 46 "us3_ax + us3_slotany") 47 48(define_insn_reservation "us3_ialuX" 5 49 (and (eq_attr "cpu" "ultrasparc3") 50 (eq_attr "type" "ialu,shift,compare")) 51 "us3_single_issue*4, nothing") 52 53(define_insn_reservation "us3_cmove" 2 54 (and (eq_attr "cpu" "ultrasparc3") 55 (eq_attr "type" "cmove")) 56 "us3_ms + us3_br + us3_slotany, nothing") 57 58;; ??? Not entirely accurate. 59;; ??? It can run from 6 to 9 cycles. The first cycle the MS pipe 60;; ??? is needed, and the instruction group is broken right after 61;; ??? the imul. Then 'helper' instructions are generated to perform 62;; ??? each further stage of the multiplication, each such 'helper' is 63;; ??? single group. So, the reservation aspect is represented accurately 64;; ??? here, but the variable cycles are not. 65;; ??? Currently I have no idea how to determine the variability, but once 66;; ??? known we can simply add a define_bypass or similar to model it. 67(define_insn_reservation "us3_imul" 7 68 (and (eq_attr "cpu" "ultrasparc3") 69 (eq_attr "type" "imul")) 70 "us3_ms + us3_slotany, us3_single_issue*4, nothing*2") 71 72(define_insn_reservation "us3_idiv" 72 73 (and (eq_attr "cpu" "ultrasparc3") 74 (eq_attr "type" "idiv")) 75 "us3_ms + us3_slotany, us3_single_issue*69, nothing*2") 76 77;; UltraSPARC-III has a similar load delay as UltraSPARC-I/II except 78;; that all loads except 32-bit/64-bit unsigned loads take the extra 79;; delay for sign/zero extension. 80(define_insn_reservation "us3_2cycle_load" 2 81 (and (eq_attr "cpu" "ultrasparc3") 82 (and (eq_attr "type" "load,fpload") 83 (eq_attr "us3load_type" "2cycle"))) 84 "us3_ms + us3_slotany, us3_load_writeback") 85 86(define_insn_reservation "us3_load_delayed" 3 87 (and (eq_attr "cpu" "ultrasparc3") 88 (and (eq_attr "type" "load,sload") 89 (eq_attr "us3load_type" "3cycle"))) 90 "us3_ms + us3_slotany, nothing, us3_load_writeback") 91 92(define_insn_reservation "us3_store" 1 93 (and (eq_attr "cpu" "ultrasparc3") 94 (eq_attr "type" "store,fpstore")) 95 "us3_ms + us3_slotany") 96 97(define_insn_reservation "us3_branch" 1 98 (and (eq_attr "cpu" "ultrasparc3") 99 (eq_attr "type" "branch")) 100 "us3_br + us3_slotany") 101 102(define_insn_reservation "us3_call_jmpl" 1 103 (and (eq_attr "cpu" "ultrasparc3") 104 (eq_attr "type" "call,sibcall,call_no_delay_slot,uncond_branch")) 105 "us3_br + us3_ms + us3_slotany") 106 107(define_insn_reservation "us3_fmov" 3 108 (and (eq_attr "cpu" "ultrasparc3") 109 (eq_attr "type" "fpmove")) 110 "us3_fpa + us3_slotany, nothing*2") 111 112(define_insn_reservation "us3_fcmov" 3 113 (and (eq_attr "cpu" "ultrasparc3") 114 (eq_attr "type" "fpcmove")) 115 "us3_fpa + us3_br + us3_slotany, nothing*2") 116 117(define_insn_reservation "us3_fcrmov" 3 118 (and (eq_attr "cpu" "ultrasparc3") 119 (eq_attr "type" "fpcrmove")) 120 "us3_fpa + us3_ms + us3_slotany, nothing*2") 121 122(define_insn_reservation "us3_faddsub" 4 123 (and (eq_attr "cpu" "ultrasparc3") 124 (eq_attr "type" "fp")) 125 "us3_fpa + us3_slotany, nothing*3") 126 127(define_insn_reservation "us3_fpcmp" 5 128 (and (eq_attr "cpu" "ultrasparc3") 129 (eq_attr "type" "fpcmp")) 130 "us3_fpa + us3_slotany, nothing*4") 131 132(define_insn_reservation "us3_fmult" 4 133 (and (eq_attr "cpu" "ultrasparc3") 134 (eq_attr "type" "fpmul")) 135 "us3_fpm + us3_slotany, nothing*3") 136 137(define_insn_reservation "us3_fdivs" 17 138 (and (eq_attr "cpu" "ultrasparc3") 139 (eq_attr "type" "fpdivs")) 140 "(us3_fpm + us3_slotany), us3_fpm*14, nothing*2") 141 142(define_insn_reservation "us3_fsqrts" 20 143 (and (eq_attr "cpu" "ultrasparc3") 144 (eq_attr "type" "fpsqrts")) 145 "(us3_fpm + us3_slotany), us3_fpm*17, nothing*2") 146 147(define_insn_reservation "us3_fdivd" 20 148 (and (eq_attr "cpu" "ultrasparc3") 149 (eq_attr "type" "fpdivd")) 150 "(us3_fpm + us3_slotany), us3_fpm*17, nothing*2") 151 152(define_insn_reservation "us3_fsqrtd" 29 153 (and (eq_attr "cpu" "ultrasparc3") 154 (eq_attr "type" "fpsqrtd")) 155 "(us3_fpm + us3_slotany), us3_fpm*26, nothing*2") 156 157;; Any store may multi issue with the insn creating the source 158;; data as long as that creating insn is not an FPU div/sqrt. 159;; We need a special guard function because this bypass does 160;; not apply to the address inputs of the store. 161(define_bypass 0 "us3_integer,us3_faddsub,us3_fmov,us3_fcmov,us3_fmult" "us3_store" 162 "store_data_bypass_p") 163 164;; An integer branch may execute in the same cycle as the compare 165;; creating the condition codes. 166(define_bypass 0 "us3_integer" "us3_branch") 167 168;; If FMOVfcc is user of FPCMP, latency is only 1 cycle. 169(define_bypass 1 "us3_fpcmp" "us3_fcmov") 170