1/* Definitions of target machine for GNU compiler, for DEC Alpha. 2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 3 2000, 2001, 2002 Free Software Foundation, Inc. 4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) 5 6This file is part of GNU CC. 7 8GNU CC is free software; you can redistribute it and/or modify 9it under the terms of the GNU General Public License as published by 10the Free Software Foundation; either version 2, or (at your option) 11any later version. 12 13GNU CC is distributed in the hope that it will be useful, 14but WITHOUT ANY WARRANTY; without even the implied warranty of 15MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16GNU General Public License for more details. 17 18You should have received a copy of the GNU General Public License 19along with GNU CC; see the file COPYING. If not, write to 20the Free Software Foundation, 59 Temple Place - Suite 330, 21Boston, MA 02111-1307, USA. */ 22 23/* Target CPU builtins. */ 24#define TARGET_CPU_CPP_BUILTINS() \ 25 do \ 26 { \ 27 builtin_define ("__alpha"); \ 28 builtin_define ("__alpha__"); \ 29 builtin_assert ("cpu=alpha"); \ 30 builtin_assert ("machine=alpha"); \ 31 if (TARGET_CIX) \ 32 { \ 33 builtin_define ("__alpha_cix__"); \ 34 builtin_assert ("cpu=cix"); \ 35 } \ 36 if (TARGET_FIX) \ 37 { \ 38 builtin_define ("__alpha_fix__"); \ 39 builtin_assert ("cpu=fix"); \ 40 } \ 41 if (TARGET_BWX) \ 42 { \ 43 builtin_define ("__alpha_bwx__"); \ 44 builtin_assert ("cpu=bwx"); \ 45 } \ 46 if (TARGET_MAX) \ 47 { \ 48 builtin_define ("__alpha_max__"); \ 49 builtin_assert ("cpu=max"); \ 50 } \ 51 if (TARGET_CPU_EV6) \ 52 { \ 53 builtin_define ("__alpha_ev6__"); \ 54 builtin_assert ("cpu=ev6"); \ 55 } \ 56 else if (TARGET_CPU_EV5) \ 57 { \ 58 builtin_define ("__alpha_ev5__"); \ 59 builtin_assert ("cpu=ev5"); \ 60 } \ 61 else /* Presumably ev4. */ \ 62 { \ 63 builtin_define ("__alpha_ev4__"); \ 64 builtin_assert ("cpu=ev4"); \ 65 } \ 66 if (TARGET_IEEE || TARGET_IEEE_WITH_INEXACT) \ 67 builtin_define ("_IEEE_FP"); \ 68 if (TARGET_IEEE_WITH_INEXACT) \ 69 builtin_define ("_IEEE_FP_INEXACT"); \ 70 if (TARGET_LONG_DOUBLE_128) \ 71 builtin_define ("__LONG_DOUBLE_128__"); \ 72 \ 73 /* Macros dependent on the C dialect. */ \ 74 SUBTARGET_LANGUAGE_CPP_BUILTINS(); \ 75} while (0) 76 77#ifndef SUBTARGET_LANGUAGE_CPP_BUILTINS 78#define SUBTARGET_LANGUAGE_CPP_BUILTINS() \ 79 do \ 80 { \ 81 if (preprocessing_asm_p ()) \ 82 builtin_define_std ("LANGUAGE_ASSEMBLY"); \ 83 else if (c_language == clk_c) \ 84 builtin_define_std ("LANGUAGE_C"); \ 85 else if (c_language == clk_cplusplus) \ 86 { \ 87 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \ 88 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \ 89 } \ 90 if (flag_objc) \ 91 { \ 92 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \ 93 builtin_define ("__LANGUAGE_OBJECTIVE_C__"); \ 94 } \ 95 } \ 96 while (0) 97#endif 98 99#define CPP_SPEC "%(cpp_subtarget)" 100 101#ifndef CPP_SUBTARGET_SPEC 102#define CPP_SUBTARGET_SPEC "" 103#endif 104 105#define WORD_SWITCH_TAKES_ARG(STR) \ 106 (!strcmp (STR, "rpath") || DEFAULT_WORD_SWITCH_TAKES_ARG(STR)) 107 108/* Print subsidiary information on the compiler version in use. */ 109#define TARGET_VERSION 110 111/* Run-time compilation parameters selecting different hardware subsets. */ 112 113/* Which processor to schedule for. The cpu attribute defines a list that 114 mirrors this list, so changes to alpha.md must be made at the same time. */ 115 116enum processor_type 117 {PROCESSOR_EV4, /* 2106[46]{a,} */ 118 PROCESSOR_EV5, /* 21164{a,pc,} */ 119 PROCESSOR_EV6}; /* 21264 */ 120 121extern enum processor_type alpha_cpu; 122 123enum alpha_trap_precision 124{ 125 ALPHA_TP_PROG, /* No precision (default). */ 126 ALPHA_TP_FUNC, /* Trap contained within originating function. */ 127 ALPHA_TP_INSN /* Instruction accuracy and code is resumption safe. */ 128}; 129 130enum alpha_fp_rounding_mode 131{ 132 ALPHA_FPRM_NORM, /* Normal rounding mode. */ 133 ALPHA_FPRM_MINF, /* Round towards minus-infinity. */ 134 ALPHA_FPRM_CHOP, /* Chopped rounding mode (towards 0). */ 135 ALPHA_FPRM_DYN /* Dynamic rounding mode. */ 136}; 137 138enum alpha_fp_trap_mode 139{ 140 ALPHA_FPTM_N, /* Normal trap mode. */ 141 ALPHA_FPTM_U, /* Underflow traps enabled. */ 142 ALPHA_FPTM_SU, /* Software completion, w/underflow traps */ 143 ALPHA_FPTM_SUI /* Software completion, w/underflow & inexact traps */ 144}; 145 146extern int target_flags; 147 148extern enum alpha_trap_precision alpha_tp; 149extern enum alpha_fp_rounding_mode alpha_fprm; 150extern enum alpha_fp_trap_mode alpha_fptm; 151extern int alpha_tls_size; 152 153/* This means that floating-point support exists in the target implementation 154 of the Alpha architecture. This is usually the default. */ 155#define MASK_FP (1 << 0) 156#define TARGET_FP (target_flags & MASK_FP) 157 158/* This means that floating-point registers are allowed to be used. Note 159 that Alpha implementations without FP operations are required to 160 provide the FP registers. */ 161 162#define MASK_FPREGS (1 << 1) 163#define TARGET_FPREGS (target_flags & MASK_FPREGS) 164 165/* This means that gas is used to process the assembler file. */ 166 167#define MASK_GAS (1 << 2) 168#define TARGET_GAS (target_flags & MASK_GAS) 169 170/* This means that we should mark procedures as IEEE conformant. */ 171 172#define MASK_IEEE_CONFORMANT (1 << 3) 173#define TARGET_IEEE_CONFORMANT (target_flags & MASK_IEEE_CONFORMANT) 174 175/* This means we should be IEEE-compliant except for inexact. */ 176 177#define MASK_IEEE (1 << 4) 178#define TARGET_IEEE (target_flags & MASK_IEEE) 179 180/* This means we should be fully IEEE-compliant. */ 181 182#define MASK_IEEE_WITH_INEXACT (1 << 5) 183#define TARGET_IEEE_WITH_INEXACT (target_flags & MASK_IEEE_WITH_INEXACT) 184 185/* This means we must construct all constants rather than emitting 186 them as literal data. */ 187 188#define MASK_BUILD_CONSTANTS (1 << 6) 189#define TARGET_BUILD_CONSTANTS (target_flags & MASK_BUILD_CONSTANTS) 190 191/* This means we handle floating points in VAX F- (float) 192 or G- (double) Format. */ 193 194#define MASK_FLOAT_VAX (1 << 7) 195#define TARGET_FLOAT_VAX (target_flags & MASK_FLOAT_VAX) 196 197/* This means that the processor has byte and half word loads and stores 198 (the BWX extension). */ 199 200#define MASK_BWX (1 << 8) 201#define TARGET_BWX (target_flags & MASK_BWX) 202 203/* This means that the processor has the MAX extension. */ 204#define MASK_MAX (1 << 9) 205#define TARGET_MAX (target_flags & MASK_MAX) 206 207/* This means that the processor has the FIX extension. */ 208#define MASK_FIX (1 << 10) 209#define TARGET_FIX (target_flags & MASK_FIX) 210 211/* This means that the processor has the CIX extension. */ 212#define MASK_CIX (1 << 11) 213#define TARGET_CIX (target_flags & MASK_CIX) 214 215/* This means use !literal style explicit relocations. */ 216#define MASK_EXPLICIT_RELOCS (1 << 12) 217#define TARGET_EXPLICIT_RELOCS (target_flags & MASK_EXPLICIT_RELOCS) 218 219/* This means use 16-bit relocations to .sdata/.sbss. */ 220#define MASK_SMALL_DATA (1 << 13) 221#define TARGET_SMALL_DATA (target_flags & MASK_SMALL_DATA) 222 223/* This means emit thread pointer loads for kernel not user. */ 224#define MASK_TLS_KERNEL (1 << 14) 225#define TARGET_TLS_KERNEL (target_flags & MASK_TLS_KERNEL) 226 227/* This means use IEEE quad-format for long double. Assumes the 228 presence of the GEM support library routines. */ 229#define MASK_LONG_DOUBLE_128 (1 << 16) 230#define TARGET_LONG_DOUBLE_128 (target_flags & MASK_LONG_DOUBLE_128) 231 232/* This means that the processor is an EV5, EV56, or PCA56. 233 Unlike alpha_cpu this is not affected by -mtune= setting. */ 234#define MASK_CPU_EV5 (1 << 28) 235#define TARGET_CPU_EV5 (target_flags & MASK_CPU_EV5) 236 237/* Likewise for EV6. */ 238#define MASK_CPU_EV6 (1 << 29) 239#define TARGET_CPU_EV6 (target_flags & MASK_CPU_EV6) 240 241/* This means we support the .arch directive in the assembler. Only 242 defined in TARGET_CPU_DEFAULT. */ 243#define MASK_SUPPORT_ARCH (1 << 30) 244#define TARGET_SUPPORT_ARCH (target_flags & MASK_SUPPORT_ARCH) 245 246/* These are for target os support and cannot be changed at runtime. */ 247#define TARGET_ABI_WINDOWS_NT 0 248#define TARGET_ABI_OPEN_VMS 0 249#define TARGET_ABI_UNICOSMK 0 250#define TARGET_ABI_OSF (!TARGET_ABI_WINDOWS_NT \ 251 && !TARGET_ABI_OPEN_VMS \ 252 && !TARGET_ABI_UNICOSMK) 253 254#ifndef TARGET_AS_CAN_SUBTRACT_LABELS 255#define TARGET_AS_CAN_SUBTRACT_LABELS TARGET_GAS 256#endif 257#ifndef TARGET_AS_SLASH_BEFORE_SUFFIX 258#define TARGET_AS_SLASH_BEFORE_SUFFIX TARGET_GAS 259#endif 260#ifndef TARGET_CAN_FAULT_IN_PROLOGUE 261#define TARGET_CAN_FAULT_IN_PROLOGUE 0 262#endif 263#ifndef TARGET_HAS_XFLOATING_LIBS 264#define TARGET_HAS_XFLOATING_LIBS TARGET_LONG_DOUBLE_128 265#endif 266#ifndef TARGET_PROFILING_NEEDS_GP 267#define TARGET_PROFILING_NEEDS_GP 0 268#endif 269#ifndef TARGET_LD_BUGGY_LDGP 270#define TARGET_LD_BUGGY_LDGP 0 271#endif 272#ifndef TARGET_FIXUP_EV5_PREFETCH 273#define TARGET_FIXUP_EV5_PREFETCH 0 274#endif 275#ifndef HAVE_AS_TLS 276#define HAVE_AS_TLS 0 277#endif 278 279/* Macro to define tables used to set the flags. 280 This is a list in braces of pairs in braces, 281 each pair being { "NAME", VALUE } 282 where VALUE is the bits to set or minus the bits to clear. 283 An empty string NAME is used to identify the default VALUE. */ 284 285#define TARGET_SWITCHES \ 286 { {"no-soft-float", MASK_FP, N_("Use hardware fp")}, \ 287 {"soft-float", - MASK_FP, N_("Do not use hardware fp")}, \ 288 {"fp-regs", MASK_FPREGS, N_("Use fp registers")}, \ 289 {"no-fp-regs", - (MASK_FP|MASK_FPREGS), \ 290 N_("Do not use fp registers")}, \ 291 {"alpha-as", -MASK_GAS, N_("Do not assume GAS")}, \ 292 {"gas", MASK_GAS, N_("Assume GAS")}, \ 293 {"ieee-conformant", MASK_IEEE_CONFORMANT, \ 294 N_("Request IEEE-conformant math library routines (OSF/1)")}, \ 295 {"ieee", MASK_IEEE|MASK_IEEE_CONFORMANT, \ 296 N_("Emit IEEE-conformant code, without inexact exceptions")}, \ 297 {"no-ieee", - (MASK_IEEE|MASK_IEEE_WITH_INEXACT|MASK_IEEE_CONFORMANT), \ 298 N_("Emit non-IEEE-conformant code")}, \ 299 {"ieee-with-inexact", MASK_IEEE_WITH_INEXACT|MASK_IEEE_CONFORMANT, \ 300 N_("Emit IEEE-conformant code, with inexact exceptions")}, \ 301 {"build-constants", MASK_BUILD_CONSTANTS, \ 302 N_("Do not emit complex integer constants to read-only memory")}, \ 303 {"float-vax", MASK_FLOAT_VAX, N_("Use VAX fp")}, \ 304 {"float-ieee", -MASK_FLOAT_VAX, N_("Do not use VAX fp")}, \ 305 {"bwx", MASK_BWX, N_("Emit code for the byte/word ISA extension")}, \ 306 {"no-bwx", -MASK_BWX, ""}, \ 307 {"max", MASK_MAX, \ 308 N_("Emit code for the motion video ISA extension")}, \ 309 {"no-max", -MASK_MAX, ""}, \ 310 {"fix", MASK_FIX, \ 311 N_("Emit code for the fp move and sqrt ISA extension")}, \ 312 {"no-fix", -MASK_FIX, ""}, \ 313 {"cix", MASK_CIX, N_("Emit code for the counting ISA extension")}, \ 314 {"no-cix", -MASK_CIX, ""}, \ 315 {"explicit-relocs", MASK_EXPLICIT_RELOCS, \ 316 N_("Emit code using explicit relocation directives")}, \ 317 {"no-explicit-relocs", -MASK_EXPLICIT_RELOCS, ""}, \ 318 {"small-data", MASK_SMALL_DATA, \ 319 N_("Emit 16-bit relocations to the small data areas")}, \ 320 {"large-data", -MASK_SMALL_DATA, \ 321 N_("Emit 32-bit relocations to the small data areas")}, \ 322 {"tls-kernel", MASK_TLS_KERNEL, \ 323 N_("Emit rdval instead of rduniq for thread pointer")}, \ 324 {"long-double-128", MASK_LONG_DOUBLE_128, \ 325 N_("Use 128-bit long double")}, \ 326 {"long-double-64", -MASK_LONG_DOUBLE_128, \ 327 N_("Use 64-bit long double")}, \ 328 {"", TARGET_DEFAULT | TARGET_CPU_DEFAULT \ 329 | TARGET_DEFAULT_EXPLICIT_RELOCS, ""} } 330 331#define TARGET_DEFAULT MASK_FP|MASK_FPREGS 332 333#ifndef TARGET_CPU_DEFAULT 334#define TARGET_CPU_DEFAULT 0 335#endif 336 337#ifndef TARGET_DEFAULT_EXPLICIT_RELOCS 338#ifdef HAVE_AS_EXPLICIT_RELOCS 339#define TARGET_DEFAULT_EXPLICIT_RELOCS MASK_EXPLICIT_RELOCS 340#else 341#define TARGET_DEFAULT_EXPLICIT_RELOCS 0 342#endif 343#endif 344 345extern const char *alpha_cpu_string; /* For -mcpu= */ 346extern const char *alpha_tune_string; /* For -mtune= */ 347extern const char *alpha_fprm_string; /* For -mfp-rounding-mode=[n|m|c|d] */ 348extern const char *alpha_fptm_string; /* For -mfp-trap-mode=[n|u|su|sui] */ 349extern const char *alpha_tp_string; /* For -mtrap-precision=[p|f|i] */ 350extern const char *alpha_mlat_string; /* For -mmemory-latency= */ 351extern const char *alpha_tls_size_string; /* For -mtls-size= */ 352 353#define TARGET_OPTIONS \ 354{ \ 355 {"cpu=", &alpha_cpu_string, \ 356 N_("Use features of and schedule given CPU")}, \ 357 {"tune=", &alpha_tune_string, \ 358 N_("Schedule given CPU")}, \ 359 {"fp-rounding-mode=", &alpha_fprm_string, \ 360 N_("Control the generated fp rounding mode")}, \ 361 {"fp-trap-mode=", &alpha_fptm_string, \ 362 N_("Control the IEEE trap mode")}, \ 363 {"trap-precision=", &alpha_tp_string, \ 364 N_("Control the precision given to fp exceptions")}, \ 365 {"memory-latency=", &alpha_mlat_string, \ 366 N_("Tune expected memory latency")}, \ 367 {"tls-size=", &alpha_tls_size_string, \ 368 N_("Specify bit size of immediate TLS offsets")}, \ 369} 370 371/* This macro defines names of additional specifications to put in the 372 specs that can be used in various specifications like CC1_SPEC. Its 373 definition is an initializer with a subgrouping for each command option. 374 375 Each subgrouping contains a string constant, that defines the 376 specification name, and a string constant that used by the GNU CC driver 377 program. 378 379 Do not define this macro if it does not need to do anything. */ 380 381#ifndef SUBTARGET_EXTRA_SPECS 382#define SUBTARGET_EXTRA_SPECS 383#endif 384 385#define EXTRA_SPECS \ 386 { "cpp_subtarget", CPP_SUBTARGET_SPEC }, \ 387 SUBTARGET_EXTRA_SPECS 388 389 390/* Sometimes certain combinations of command options do not make sense 391 on a particular target machine. You can define a macro 392 `OVERRIDE_OPTIONS' to take account of this. This macro, if 393 defined, is executed once just after all the command options have 394 been parsed. 395 396 On the Alpha, it is used to translate target-option strings into 397 numeric values. */ 398 399#define OVERRIDE_OPTIONS override_options () 400 401 402/* Define this macro to change register usage conditional on target flags. 403 404 On the Alpha, we use this to disable the floating-point registers when 405 they don't exist. */ 406 407#define CONDITIONAL_REGISTER_USAGE \ 408{ \ 409 int i; \ 410 if (! TARGET_FPREGS) \ 411 for (i = 32; i < 63; i++) \ 412 fixed_regs[i] = call_used_regs[i] = 1; \ 413} 414 415 416/* Show we can debug even without a frame pointer. */ 417#define CAN_DEBUG_WITHOUT_FP 418 419/* target machine storage layout */ 420 421/* Define the size of `int'. The default is the same as the word size. */ 422#define INT_TYPE_SIZE 32 423 424/* Define the size of `long long'. The default is the twice the word size. */ 425#define LONG_LONG_TYPE_SIZE 64 426 427/* We're IEEE unless someone says to use VAX. */ 428#define TARGET_FLOAT_FORMAT \ 429 (TARGET_FLOAT_VAX ? VAX_FLOAT_FORMAT : IEEE_FLOAT_FORMAT) 430 431/* The two floating-point formats we support are S-floating, which is 432 4 bytes, and T-floating, which is 8 bytes. `float' is S and `double' 433 and `long double' are T. */ 434 435#define FLOAT_TYPE_SIZE 32 436#define DOUBLE_TYPE_SIZE 64 437#define LONG_DOUBLE_TYPE_SIZE (TARGET_LONG_DOUBLE_128 ? 128 : 64) 438 439/* Define this to set long double type size to use in libgcc2.c, which can 440 not depend on target_flags. */ 441#ifdef __LONG_DOUBLE_128__ 442#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128 443#else 444#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64 445#endif 446 447/* Work around target_flags dependency in ada/targtyps.c. */ 448#define WIDEST_HARDWARE_FP_SIZE 64 449 450#define WCHAR_TYPE "unsigned int" 451#define WCHAR_TYPE_SIZE 32 452 453/* Define this macro if it is advisable to hold scalars in registers 454 in a wider mode than that declared by the program. In such cases, 455 the value is constrained to be within the bounds of the declared 456 type, but kept valid in the wider mode. The signedness of the 457 extension may differ from that of the type. 458 459 For Alpha, we always store objects in a full register. 32-bit objects 460 are always sign-extended, but smaller objects retain their signedness. */ 461 462#define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ 463 if (GET_MODE_CLASS (MODE) == MODE_INT \ 464 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ 465 { \ 466 if ((MODE) == SImode) \ 467 (UNSIGNEDP) = 0; \ 468 (MODE) = DImode; \ 469 } 470 471/* Define this if function arguments should also be promoted using the above 472 procedure. */ 473 474#define PROMOTE_FUNCTION_ARGS 475 476/* Likewise, if the function return value is promoted. */ 477 478#define PROMOTE_FUNCTION_RETURN 479 480/* Define this if most significant bit is lowest numbered 481 in instructions that operate on numbered bit-fields. 482 483 There are no such instructions on the Alpha, but the documentation 484 is little endian. */ 485#define BITS_BIG_ENDIAN 0 486 487/* Define this if most significant byte of a word is the lowest numbered. 488 This is false on the Alpha. */ 489#define BYTES_BIG_ENDIAN 0 490 491/* Define this if most significant word of a multiword number is lowest 492 numbered. 493 494 For Alpha we can decide arbitrarily since there are no machine instructions 495 for them. Might as well be consistent with bytes. */ 496#define WORDS_BIG_ENDIAN 0 497 498/* Width of a word, in units (bytes). */ 499#define UNITS_PER_WORD 8 500 501/* Width in bits of a pointer. 502 See also the macro `Pmode' defined below. */ 503#define POINTER_SIZE 64 504 505/* Allocation boundary (in *bits*) for storing arguments in argument list. */ 506#define PARM_BOUNDARY 64 507 508/* Boundary (in *bits*) on which stack pointer should be aligned. */ 509#define STACK_BOUNDARY 128 510 511/* Allocation boundary (in *bits*) for the code of a function. */ 512#define FUNCTION_BOUNDARY 32 513 514/* Alignment of field after `int : 0' in a structure. */ 515#define EMPTY_FIELD_BOUNDARY 64 516 517/* Every structure's size must be a multiple of this. */ 518#define STRUCTURE_SIZE_BOUNDARY 8 519 520/* A bit-field declared as `int' forces `int' alignment for the struct. */ 521#define PCC_BITFIELD_TYPE_MATTERS 1 522 523/* No data type wants to be aligned rounder than this. */ 524#define BIGGEST_ALIGNMENT 128 525 526/* For atomic access to objects, must have at least 32-bit alignment 527 unless the machine has byte operations. */ 528#define MINIMUM_ATOMIC_ALIGNMENT ((unsigned int) (TARGET_BWX ? 8 : 32)) 529 530/* Align all constants and variables to at least a word boundary so 531 we can pick up pieces of them faster. */ 532/* ??? Only if block-move stuff knows about different source/destination 533 alignment. */ 534#if 0 535#define CONSTANT_ALIGNMENT(EXP, ALIGN) MAX ((ALIGN), BITS_PER_WORD) 536#define DATA_ALIGNMENT(EXP, ALIGN) MAX ((ALIGN), BITS_PER_WORD) 537#endif 538 539/* Set this nonzero if move instructions will actually fail to work 540 when given unaligned data. 541 542 Since we get an error message when we do one, call them invalid. */ 543 544#define STRICT_ALIGNMENT 1 545 546/* Set this nonzero if unaligned move instructions are extremely slow. 547 548 On the Alpha, they trap. */ 549 550#define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1 551 552/* Standard register usage. */ 553 554/* Number of actual hardware registers. 555 The hardware registers are assigned numbers for the compiler 556 from 0 to just below FIRST_PSEUDO_REGISTER. 557 All registers that the compiler knows about must be given numbers, 558 even those that are not normally considered general registers. 559 560 We define all 32 integer registers, even though $31 is always zero, 561 and all 32 floating-point registers, even though $f31 is also 562 always zero. We do not bother defining the FP status register and 563 there are no other registers. 564 565 Since $31 is always zero, we will use register number 31 as the 566 argument pointer. It will never appear in the generated code 567 because we will always be eliminating it in favor of the stack 568 pointer or hardware frame pointer. 569 570 Likewise, we use $f31 for the frame pointer, which will always 571 be eliminated in favor of the hardware frame pointer or the 572 stack pointer. */ 573 574#define FIRST_PSEUDO_REGISTER 64 575 576/* 1 for registers that have pervasive standard uses 577 and are not available for the register allocator. */ 578 579#define FIXED_REGISTERS \ 580 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 581 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, \ 582 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 583 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 } 584 585/* 1 for registers not available across function calls. 586 These must include the FIXED_REGISTERS and also any 587 registers that can be used without being saved. 588 The latter must include the registers where values are returned 589 and the register where structure-value addresses are passed. 590 Aside from that, you can include as many other registers as you like. */ 591#define CALL_USED_REGISTERS \ 592 {1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, \ 593 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, \ 594 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, \ 595 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 } 596 597/* List the order in which to allocate registers. Each register must be 598 listed once, even those in FIXED_REGISTERS. 599 600 We allocate in the following order: 601 $f10-$f15 (nonsaved floating-point register) 602 $f22-$f30 (likewise) 603 $f21-$f16 (likewise, but input args) 604 $f0 (nonsaved, but return value) 605 $f1 (nonsaved, but immediate before saved) 606 $f2-$f9 (saved floating-point registers) 607 $1-$8 (nonsaved integer registers) 608 $22-$25 (likewise) 609 $28 (likewise) 610 $0 (likewise, but return value) 611 $21-$16 (likewise, but input args) 612 $27 (procedure value in OSF, nonsaved in NT) 613 $9-$14 (saved integer registers) 614 $26 (return PC) 615 $15 (frame pointer) 616 $29 (global pointer) 617 $30, $31, $f31 (stack pointer and always zero/ap & fp) */ 618 619#define REG_ALLOC_ORDER \ 620 {42, 43, 44, 45, 46, 47, \ 621 54, 55, 56, 57, 58, 59, 60, 61, 62, \ 622 53, 52, 51, 50, 49, 48, \ 623 32, 33, \ 624 34, 35, 36, 37, 38, 39, 40, 41, \ 625 1, 2, 3, 4, 5, 6, 7, 8, \ 626 22, 23, 24, 25, \ 627 28, \ 628 0, \ 629 21, 20, 19, 18, 17, 16, \ 630 27, \ 631 9, 10, 11, 12, 13, 14, \ 632 26, \ 633 15, \ 634 29, \ 635 30, 31, 63 } 636 637/* Return number of consecutive hard regs needed starting at reg REGNO 638 to hold something of mode MODE. 639 This is ordinarily the length in words of a value of mode MODE 640 but can be less for certain modes in special long registers. */ 641 642#define HARD_REGNO_NREGS(REGNO, MODE) \ 643 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 644 645/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. 646 On Alpha, the integer registers can hold any mode. The floating-point 647 registers can hold 64-bit integers as well, but not smaller values. */ 648 649#define HARD_REGNO_MODE_OK(REGNO, MODE) \ 650 ((REGNO) >= 32 && (REGNO) <= 62 \ 651 ? (MODE) == SFmode || (MODE) == DFmode || (MODE) == DImode \ 652 || (MODE) == SCmode || (MODE) == DCmode \ 653 : 1) 654 655/* Value is 1 if MODE is a supported vector mode. */ 656 657#define VECTOR_MODE_SUPPORTED_P(MODE) \ 658 (TARGET_MAX \ 659 && ((MODE) == V8QImode || (MODE) == V4HImode || (MODE) == V2SImode)) 660 661/* A C expression that is nonzero if a value of mode 662 MODE1 is accessible in mode MODE2 without copying. 663 664 This asymmetric test is true when MODE1 could be put 665 in an FP register but MODE2 could not. */ 666 667#define MODES_TIEABLE_P(MODE1, MODE2) \ 668 (HARD_REGNO_MODE_OK (32, (MODE1)) \ 669 ? HARD_REGNO_MODE_OK (32, (MODE2)) \ 670 : 1) 671 672/* Specify the registers used for certain standard purposes. 673 The values of these macros are register numbers. */ 674 675/* Alpha pc isn't overloaded on a register that the compiler knows about. */ 676/* #define PC_REGNUM */ 677 678/* Register to use for pushing function arguments. */ 679#define STACK_POINTER_REGNUM 30 680 681/* Base register for access to local variables of the function. */ 682#define HARD_FRAME_POINTER_REGNUM 15 683 684/* Value should be nonzero if functions must have frame pointers. 685 Zero means the frame pointer need not be set up (and parms 686 may be accessed via the stack pointer) in functions that seem suitable. 687 This is computed in `reload', in reload1.c. */ 688#define FRAME_POINTER_REQUIRED 0 689 690/* Base register for access to arguments of the function. */ 691#define ARG_POINTER_REGNUM 31 692 693/* Base register for access to local variables of function. */ 694#define FRAME_POINTER_REGNUM 63 695 696/* Register in which static-chain is passed to a function. 697 698 For the Alpha, this is based on an example; the calling sequence 699 doesn't seem to specify this. */ 700#define STATIC_CHAIN_REGNUM 1 701 702/* The register number of the register used to address a table of 703 static data addresses in memory. */ 704#define PIC_OFFSET_TABLE_REGNUM 29 705 706/* Define this macro if the register defined by `PIC_OFFSET_TABLE_REGNUM' 707 is clobbered by calls. */ 708/* ??? It is and it isn't. It's required to be valid for a given 709 function when the function returns. It isn't clobbered by 710 current_file functions. Moreover, we do not expose the ldgp 711 until after reload, so we're probably safe. */ 712/* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */ 713 714/* Register in which address to store a structure value 715 arrives in the function. On the Alpha, the address is passed 716 as a hidden argument. */ 717#define STRUCT_VALUE 0 718 719/* Define the classes of registers for register constraints in the 720 machine description. Also define ranges of constants. 721 722 One of the classes must always be named ALL_REGS and include all hard regs. 723 If there is more than one class, another class must be named NO_REGS 724 and contain no registers. 725 726 The name GENERAL_REGS must be the name of a class (or an alias for 727 another name such as ALL_REGS). This is the class of registers 728 that is allowed by "g" or "r" in a register constraint. 729 Also, registers outside this class are allocated only when 730 instructions express preferences for them. 731 732 The classes must be numbered in nondecreasing order; that is, 733 a larger-numbered class must never be contained completely 734 in a smaller-numbered class. 735 736 For any two classes, it is very desirable that there be another 737 class that represents their union. */ 738 739enum reg_class { 740 NO_REGS, R0_REG, R24_REG, R25_REG, R27_REG, 741 GENERAL_REGS, FLOAT_REGS, ALL_REGS, 742 LIM_REG_CLASSES 743}; 744 745#define N_REG_CLASSES (int) LIM_REG_CLASSES 746 747/* Give names of register classes as strings for dump file. */ 748 749#define REG_CLASS_NAMES \ 750 {"NO_REGS", "R0_REG", "R24_REG", "R25_REG", "R27_REG", \ 751 "GENERAL_REGS", "FLOAT_REGS", "ALL_REGS" } 752 753/* Define which registers fit in which classes. 754 This is an initializer for a vector of HARD_REG_SET 755 of length N_REG_CLASSES. */ 756 757#define REG_CLASS_CONTENTS \ 758{ {0x00000000, 0x00000000}, /* NO_REGS */ \ 759 {0x00000001, 0x00000000}, /* R0_REG */ \ 760 {0x01000000, 0x00000000}, /* R24_REG */ \ 761 {0x02000000, 0x00000000}, /* R25_REG */ \ 762 {0x08000000, 0x00000000}, /* R27_REG */ \ 763 {0xffffffff, 0x80000000}, /* GENERAL_REGS */ \ 764 {0x00000000, 0x7fffffff}, /* FLOAT_REGS */ \ 765 {0xffffffff, 0xffffffff} } 766 767/* The same information, inverted: 768 Return the class number of the smallest class containing 769 reg number REGNO. This could be a conditional expression 770 or could index an array. */ 771 772#define REGNO_REG_CLASS(REGNO) \ 773 ((REGNO) == 0 ? R0_REG \ 774 : (REGNO) == 24 ? R24_REG \ 775 : (REGNO) == 25 ? R25_REG \ 776 : (REGNO) == 27 ? R27_REG \ 777 : (REGNO) >= 32 && (REGNO) <= 62 ? FLOAT_REGS \ 778 : GENERAL_REGS) 779 780/* The class value for index registers, and the one for base regs. */ 781#define INDEX_REG_CLASS NO_REGS 782#define BASE_REG_CLASS GENERAL_REGS 783 784/* Get reg_class from a letter such as appears in the machine description. */ 785 786#define REG_CLASS_FROM_LETTER(C) \ 787 ((C) == 'a' ? R24_REG \ 788 : (C) == 'b' ? R25_REG \ 789 : (C) == 'c' ? R27_REG \ 790 : (C) == 'f' ? FLOAT_REGS \ 791 : (C) == 'v' ? R0_REG \ 792 : NO_REGS) 793 794/* Define this macro to change register usage conditional on target flags. */ 795/* #define CONDITIONAL_REGISTER_USAGE */ 796 797/* The letters I, J, K, L, M, N, O, and P in a register constraint string 798 can be used to stand for particular ranges of immediate operands. 799 This macro defines what the ranges are. 800 C is the letter, and VALUE is a constant value. 801 Return 1 if VALUE is in the range specified by C. 802 803 For Alpha: 804 `I' is used for the range of constants most insns can contain. 805 `J' is the constant zero. 806 `K' is used for the constant in an LDA insn. 807 `L' is used for the constant in a LDAH insn. 808 `M' is used for the constants that can be AND'ed with using a ZAP insn. 809 `N' is used for complemented 8-bit constants. 810 `O' is used for negated 8-bit constants. 811 `P' is used for the constants 1, 2 and 3. */ 812 813#define CONST_OK_FOR_LETTER_P alpha_const_ok_for_letter_p 814 815/* Similar, but for floating or large integer constants, and defining letters 816 G and H. Here VALUE is the CONST_DOUBLE rtx itself. 817 818 For Alpha, `G' is the floating-point constant zero. `H' is a CONST_DOUBLE 819 that is the operand of a ZAP insn. */ 820 821#define CONST_DOUBLE_OK_FOR_LETTER_P alpha_const_double_ok_for_letter_p 822 823/* Optional extra constraints for this machine. 824 825 For the Alpha, `Q' means that this is a memory operand but not a 826 reference to an unaligned location. 827 828 `R' is a SYMBOL_REF that has SYMBOL_REF_FLAG set or is the current 829 function. 830 831 'S' is a 6-bit constant (valid for a shift insn). 832 833 'T' is a HIGH. 834 835 'U' is a symbolic operand. 836 837 'W' is a vector zero. */ 838 839#define EXTRA_CONSTRAINT alpha_extra_constraint 840 841/* Given an rtx X being reloaded into a reg required to be 842 in class CLASS, return the class of reg to actually use. 843 In general this is just CLASS; but on some machines 844 in some cases it is preferable to use a more restrictive class. */ 845 846#define PREFERRED_RELOAD_CLASS alpha_preferred_reload_class 847 848/* Loading and storing HImode or QImode values to and from memory 849 usually requires a scratch register. The exceptions are loading 850 QImode and HImode from an aligned address to a general register 851 unless byte instructions are permitted. 852 We also cannot load an unaligned address or a paradoxical SUBREG into an 853 FP register. */ 854 855#define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,IN) \ 856 secondary_reload_class((CLASS), (MODE), (IN), 1) 857 858#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,OUT) \ 859 secondary_reload_class((CLASS), (MODE), (OUT), 0) 860 861/* If we are copying between general and FP registers, we need a memory 862 location unless the FIX extension is available. */ 863 864#define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \ 865 (! TARGET_FIX && (((CLASS1) == FLOAT_REGS && (CLASS2) != FLOAT_REGS) \ 866 || ((CLASS2) == FLOAT_REGS && (CLASS1) != FLOAT_REGS))) 867 868/* Specify the mode to be used for memory when a secondary memory 869 location is needed. If MODE is floating-point, use it. Otherwise, 870 widen to a word like the default. This is needed because we always 871 store integers in FP registers in quadword format. This whole 872 area is very tricky! */ 873#define SECONDARY_MEMORY_NEEDED_MODE(MODE) \ 874 (GET_MODE_CLASS (MODE) == MODE_FLOAT ? (MODE) \ 875 : GET_MODE_SIZE (MODE) >= 4 ? (MODE) \ 876 : mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0)) 877 878/* Return the maximum number of consecutive registers 879 needed to represent mode MODE in a register of class CLASS. */ 880 881#define CLASS_MAX_NREGS(CLASS, MODE) \ 882 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 883 884/* Return the class of registers that cannot change mode from FROM to TO. */ 885 886#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 887 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ 888 ? reg_classes_intersect_p (FLOAT_REGS, CLASS) : 0) 889 890/* Define the cost of moving between registers of various classes. Moving 891 between FLOAT_REGS and anything else except float regs is expensive. 892 In fact, we make it quite expensive because we really don't want to 893 do these moves unless it is clearly worth it. Optimizations may 894 reduce the impact of not being able to allocate a pseudo to a 895 hard register. */ 896 897#define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ 898 (((CLASS1) == FLOAT_REGS) == ((CLASS2) == FLOAT_REGS) \ 899 ? 2 \ 900 : TARGET_FIX ? 3 : 4+2*alpha_memory_latency) 901 902/* A C expressions returning the cost of moving data of MODE from a register to 903 or from memory. 904 905 On the Alpha, bump this up a bit. */ 906 907extern int alpha_memory_latency; 908#define MEMORY_MOVE_COST(MODE,CLASS,IN) (2*alpha_memory_latency) 909 910/* Provide the cost of a branch. Exact meaning under development. */ 911#define BRANCH_COST 5 912 913/* Stack layout; function entry, exit and calling. */ 914 915/* Define this if pushing a word on the stack 916 makes the stack pointer a smaller address. */ 917#define STACK_GROWS_DOWNWARD 918 919/* Define this if the nominal address of the stack frame 920 is at the high-address end of the local variables; 921 that is, each additional local variable allocated 922 goes at a more negative offset in the frame. */ 923/* #define FRAME_GROWS_DOWNWARD */ 924 925/* Offset within stack frame to start allocating local variables at. 926 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 927 first local allocated. Otherwise, it is the offset to the BEGINNING 928 of the first local allocated. */ 929 930#define STARTING_FRAME_OFFSET 0 931 932/* If we generate an insn to push BYTES bytes, 933 this says how many the stack pointer really advances by. 934 On Alpha, don't define this because there are no push insns. */ 935/* #define PUSH_ROUNDING(BYTES) */ 936 937/* Define this to be nonzero if stack checking is built into the ABI. */ 938#define STACK_CHECK_BUILTIN 1 939 940/* Define this if the maximum size of all the outgoing args is to be 941 accumulated and pushed during the prologue. The amount can be 942 found in the variable current_function_outgoing_args_size. */ 943#define ACCUMULATE_OUTGOING_ARGS 1 944 945/* Offset of first parameter from the argument pointer register value. */ 946 947#define FIRST_PARM_OFFSET(FNDECL) 0 948 949/* Definitions for register eliminations. 950 951 We have two registers that can be eliminated on the Alpha. First, the 952 frame pointer register can often be eliminated in favor of the stack 953 pointer register. Secondly, the argument pointer register can always be 954 eliminated; it is replaced with either the stack or frame pointer. */ 955 956/* This is an array of structures. Each structure initializes one pair 957 of eliminable registers. The "from" register number is given first, 958 followed by "to". Eliminations of the same "from" register are listed 959 in order of preference. */ 960 961#define ELIMINABLE_REGS \ 962{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 963 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 964 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 965 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} 966 967/* Given FROM and TO register numbers, say whether this elimination is allowed. 968 Frame pointer elimination is automatically handled. 969 970 All eliminations are valid since the cases where FP can't be 971 eliminated are already handled. */ 972 973#define CAN_ELIMINATE(FROM, TO) 1 974 975/* Round up to a multiple of 16 bytes. */ 976#define ALPHA_ROUND(X) (((X) + 15) & ~ 15) 977 978/* Define the offset between two registers, one to be eliminated, and the other 979 its replacement, at the start of a routine. */ 980#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 981{ if ((FROM) == FRAME_POINTER_REGNUM) \ 982 (OFFSET) = (ALPHA_ROUND (current_function_outgoing_args_size) \ 983 + alpha_sa_size ()); \ 984 else if ((FROM) == ARG_POINTER_REGNUM) \ 985 (OFFSET) = (ALPHA_ROUND (current_function_outgoing_args_size) \ 986 + alpha_sa_size () \ 987 + (ALPHA_ROUND (get_frame_size () \ 988 + current_function_pretend_args_size) \ 989 - current_function_pretend_args_size)); \ 990 else \ 991 abort (); \ 992} 993 994/* Define this if stack space is still allocated for a parameter passed 995 in a register. */ 996/* #define REG_PARM_STACK_SPACE */ 997 998/* Value is the number of bytes of arguments automatically 999 popped when returning from a subroutine call. 1000 FUNDECL is the declaration node of the function (as a tree), 1001 FUNTYPE is the data type of the function (as a tree), 1002 or for a library call it is an identifier node for the subroutine name. 1003 SIZE is the number of bytes of arguments passed on the stack. */ 1004 1005#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 1006 1007/* Define how to find the value returned by a function. 1008 VALTYPE is the data type of the value (as a tree). 1009 If the precise function being called is known, FUNC is its FUNCTION_DECL; 1010 otherwise, FUNC is 0. 1011 1012 On Alpha the value is found in $0 for integer functions and 1013 $f0 for floating-point functions. */ 1014 1015#define FUNCTION_VALUE(VALTYPE, FUNC) \ 1016 gen_rtx_REG (((INTEGRAL_TYPE_P (VALTYPE) \ 1017 && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \ 1018 || POINTER_TYPE_P (VALTYPE)) \ 1019 ? word_mode : TYPE_MODE (VALTYPE), \ 1020 ((TARGET_FPREGS \ 1021 && (TREE_CODE (VALTYPE) == REAL_TYPE \ 1022 || TREE_CODE (VALTYPE) == COMPLEX_TYPE)) \ 1023 ? 32 : 0)) 1024 1025/* Define how to find the value returned by a library function 1026 assuming the value has mode MODE. */ 1027 1028#define LIBCALL_VALUE(MODE) \ 1029 gen_rtx_REG (MODE, \ 1030 (TARGET_FPREGS \ 1031 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \ 1032 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \ 1033 ? 32 : 0)) 1034 1035/* The definition of this macro implies that there are cases where 1036 a scalar value cannot be returned in registers. 1037 1038 For the Alpha, any structure or union type is returned in memory, as 1039 are integers whose size is larger than 64 bits. */ 1040 1041#define RETURN_IN_MEMORY(TYPE) \ 1042 (TYPE_MODE (TYPE) == BLKmode \ 1043 || TYPE_MODE (TYPE) == TFmode \ 1044 || TYPE_MODE (TYPE) == TCmode \ 1045 || (TREE_CODE (TYPE) == INTEGER_TYPE && TYPE_PRECISION (TYPE) > 64)) 1046 1047/* 1 if N is a possible register number for a function value 1048 as seen by the caller. */ 1049 1050#define FUNCTION_VALUE_REGNO_P(N) \ 1051 ((N) == 0 || (N) == 1 || (N) == 32 || (N) == 33) 1052 1053/* 1 if N is a possible register number for function argument passing. 1054 On Alpha, these are $16-$21 and $f16-$f21. */ 1055 1056#define FUNCTION_ARG_REGNO_P(N) \ 1057 (((N) >= 16 && (N) <= 21) || ((N) >= 16 + 32 && (N) <= 21 + 32)) 1058 1059/* Define a data type for recording info about an argument list 1060 during the scan of that argument list. This data type should 1061 hold all necessary information about the function itself 1062 and about the args processed so far, enough to enable macros 1063 such as FUNCTION_ARG to determine where the next arg should go. 1064 1065 On Alpha, this is a single integer, which is a number of words 1066 of arguments scanned so far. 1067 Thus 6 or more means all following args should go on the stack. */ 1068 1069#define CUMULATIVE_ARGS int 1070 1071/* Initialize a variable CUM of type CUMULATIVE_ARGS 1072 for a call to a function whose data type is FNTYPE. 1073 For a library call, FNTYPE is 0. */ 1074 1075#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) (CUM) = 0 1076 1077/* Define intermediate macro to compute the size (in registers) of an argument 1078 for the Alpha. */ 1079 1080#define ALPHA_ARG_SIZE(MODE, TYPE, NAMED) \ 1081 ((MODE) == TFmode || (MODE) == TCmode ? 1 \ 1082 : (((MODE) == BLKmode ? int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) \ 1083 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD) 1084 1085/* Update the data in CUM to advance over an argument 1086 of mode MODE and data type TYPE. 1087 (TYPE is null for libcalls where that information may not be available.) */ 1088 1089#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 1090 if (MUST_PASS_IN_STACK (MODE, TYPE)) \ 1091 (CUM) = 6; \ 1092 else \ 1093 (CUM) += ALPHA_ARG_SIZE (MODE, TYPE, NAMED) 1094 1095/* Determine where to put an argument to a function. 1096 Value is zero to push the argument on the stack, 1097 or a hard register in which to store the argument. 1098 1099 MODE is the argument's machine mode. 1100 TYPE is the data type of the argument (as a tree). 1101 This is null for libcalls where that information may 1102 not be available. 1103 CUM is a variable of type CUMULATIVE_ARGS which gives info about 1104 the preceding args and about the function being called. 1105 NAMED is nonzero if this argument is a named parameter 1106 (otherwise it is an extra parameter matching an ellipsis). 1107 1108 On Alpha the first 6 words of args are normally in registers 1109 and the rest are pushed. */ 1110 1111#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 1112 function_arg((CUM), (MODE), (TYPE), (NAMED)) 1113 1114/* A C expression that indicates when an argument must be passed by 1115 reference. If nonzero for an argument, a copy of that argument is 1116 made in memory and a pointer to the argument is passed instead of 1117 the argument itself. The pointer is passed in whatever way is 1118 appropriate for passing a pointer to that type. */ 1119 1120#define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \ 1121 ((MODE) == TFmode || (MODE) == TCmode) 1122 1123/* Specify the padding direction of arguments. 1124 1125 On the Alpha, we must pad upwards in order to be able to pass args in 1126 registers. */ 1127 1128#define FUNCTION_ARG_PADDING(MODE, TYPE) upward 1129 1130/* For an arg passed partly in registers and partly in memory, 1131 this is the number of registers used. 1132 For args passed entirely in registers or entirely in memory, zero. */ 1133 1134#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ 1135((CUM) < 6 && 6 < (CUM) + ALPHA_ARG_SIZE (MODE, TYPE, NAMED) \ 1136 ? 6 - (CUM) : 0) 1137 1138/* Perform any needed actions needed for a function that is receiving a 1139 variable number of arguments. 1140 1141 CUM is as above. 1142 1143 MODE and TYPE are the mode and type of the current parameter. 1144 1145 PRETEND_SIZE is a variable that should be set to the amount of stack 1146 that must be pushed by the prolog to pretend that our caller pushed 1147 it. 1148 1149 Normally, this macro will push all remaining incoming registers on the 1150 stack and set PRETEND_SIZE to the length of the registers pushed. 1151 1152 On the Alpha, we allocate space for all 12 arg registers, but only 1153 push those that are remaining. 1154 1155 However, if NO registers need to be saved, don't allocate any space. 1156 This is not only because we won't need the space, but because AP includes 1157 the current_pretend_args_size and we don't want to mess up any 1158 ap-relative addresses already made. 1159 1160 If we are not to use the floating-point registers, save the integer 1161 registers where we would put the floating-point registers. This is 1162 not the most efficient way to implement varargs with just one register 1163 class, but it isn't worth doing anything more efficient in this rare 1164 case. */ 1165 1166#define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \ 1167{ if ((CUM) < 6) \ 1168 { \ 1169 if (! (NO_RTL)) \ 1170 { \ 1171 rtx tmp; int set = get_varargs_alias_set (); \ 1172 tmp = gen_rtx_MEM (BLKmode, \ 1173 plus_constant (virtual_incoming_args_rtx, \ 1174 ((CUM) + 6)* UNITS_PER_WORD)); \ 1175 set_mem_alias_set (tmp, set); \ 1176 move_block_from_reg \ 1177 (16 + CUM, tmp, \ 1178 6 - (CUM), (6 - (CUM)) * UNITS_PER_WORD); \ 1179 \ 1180 tmp = gen_rtx_MEM (BLKmode, \ 1181 plus_constant (virtual_incoming_args_rtx, \ 1182 (CUM) * UNITS_PER_WORD)); \ 1183 set_mem_alias_set (tmp, set); \ 1184 move_block_from_reg \ 1185 (16 + (TARGET_FPREGS ? 32 : 0) + CUM, tmp, \ 1186 6 - (CUM), (6 - (CUM)) * UNITS_PER_WORD); \ 1187 } \ 1188 PRETEND_SIZE = 12 * UNITS_PER_WORD; \ 1189 } \ 1190} 1191 1192/* We do not allow indirect calls to be optimized into sibling calls, nor 1193 can we allow a call to a function in a different compilation unit to 1194 be optimized into a sibcall. */ 1195#define FUNCTION_OK_FOR_SIBCALL(DECL) \ 1196 (DECL \ 1197 && (! TREE_PUBLIC (DECL) \ 1198 || (TREE_ASM_WRITTEN (DECL) && (*targetm.binds_local_p) (DECL)))) 1199 1200/* Try to output insns to set TARGET equal to the constant C if it can be 1201 done in less than N insns. Do all computations in MODE. Returns the place 1202 where the output has been placed if it can be done and the insns have been 1203 emitted. If it would take more than N insns, zero is returned and no 1204 insns and emitted. */ 1205 1206/* Define the information needed to generate branch and scc insns. This is 1207 stored from the compare operation. Note that we can't use "rtx" here 1208 since it hasn't been defined! */ 1209 1210struct alpha_compare 1211{ 1212 struct rtx_def *op0, *op1; 1213 int fp_p; 1214}; 1215 1216extern struct alpha_compare alpha_compare; 1217 1218/* Make (or fake) .linkage entry for function call. 1219 IS_LOCAL is 0 if name is used in call, 1 if name is used in definition. */ 1220 1221/* This macro defines the start of an assembly comment. */ 1222 1223#define ASM_COMMENT_START " #" 1224 1225/* This macro produces the initial definition of a function. */ 1226 1227#define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL) \ 1228 alpha_start_function(FILE,NAME,DECL); 1229 1230/* This macro closes up a function definition for the assembler. */ 1231 1232#define ASM_DECLARE_FUNCTION_SIZE(FILE,NAME,DECL) \ 1233 alpha_end_function(FILE,NAME,DECL) 1234 1235/* Output any profiling code before the prologue. */ 1236 1237#define PROFILE_BEFORE_PROLOGUE 1 1238 1239/* Output assembler code to FILE to increment profiler label # LABELNO 1240 for profiling a function entry. Under OSF/1, profiling is enabled 1241 by simply passing -pg to the assembler and linker. */ 1242 1243#define FUNCTION_PROFILER(FILE, LABELNO) 1244 1245/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1246 the stack pointer does not matter. The value is tested only in 1247 functions that have frame pointers. 1248 No definition is equivalent to always zero. */ 1249 1250#define EXIT_IGNORE_STACK 1 1251 1252/* Define registers used by the epilogue and return instruction. */ 1253 1254#define EPILOGUE_USES(REGNO) ((REGNO) == 26) 1255 1256/* Output assembler code for a block containing the constant parts 1257 of a trampoline, leaving space for the variable parts. 1258 1259 The trampoline should set the static chain pointer to value placed 1260 into the trampoline and should branch to the specified routine. 1261 Note that $27 has been set to the address of the trampoline, so we can 1262 use it for addressability of the two data items. */ 1263 1264#define TRAMPOLINE_TEMPLATE(FILE) \ 1265do { \ 1266 fprintf (FILE, "\tldq $1,24($27)\n"); \ 1267 fprintf (FILE, "\tldq $27,16($27)\n"); \ 1268 fprintf (FILE, "\tjmp $31,($27),0\n"); \ 1269 fprintf (FILE, "\tnop\n"); \ 1270 fprintf (FILE, "\t.quad 0,0\n"); \ 1271} while (0) 1272 1273/* Section in which to place the trampoline. On Alpha, instructions 1274 may only be placed in a text segment. */ 1275 1276#define TRAMPOLINE_SECTION text_section 1277 1278/* Length in units of the trampoline for entering a nested function. */ 1279 1280#define TRAMPOLINE_SIZE 32 1281 1282/* The alignment of a trampoline, in bits. */ 1283 1284#define TRAMPOLINE_ALIGNMENT 64 1285 1286/* Emit RTL insns to initialize the variable parts of a trampoline. 1287 FNADDR is an RTX for the address of the function's pure code. 1288 CXT is an RTX for the static chain value for the function. */ 1289 1290#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ 1291 alpha_initialize_trampoline (TRAMP, FNADDR, CXT, 16, 24, 8) 1292 1293/* A C expression whose value is RTL representing the value of the return 1294 address for the frame COUNT steps up from the current frame. 1295 FRAMEADDR is the frame pointer of the COUNT frame, or the frame pointer of 1296 the COUNT-1 frame if RETURN_ADDR_IN_PREVIOUS_FRAME is defined. */ 1297 1298#define RETURN_ADDR_RTX alpha_return_addr 1299 1300/* Before the prologue, RA lives in $26. */ 1301#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, 26) 1302#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (26) 1303#define DWARF_ALT_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (64) 1304#define DWARF_ZERO_REG 31 1305 1306/* Describe how we implement __builtin_eh_return. */ 1307#define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 16 : INVALID_REGNUM) 1308#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 28) 1309#define EH_RETURN_HANDLER_RTX \ 1310 gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx, \ 1311 current_function_outgoing_args_size)) 1312 1313/* Addressing modes, and classification of registers for them. */ 1314 1315/* #define HAVE_POST_INCREMENT 0 */ 1316/* #define HAVE_POST_DECREMENT 0 */ 1317 1318/* #define HAVE_PRE_DECREMENT 0 */ 1319/* #define HAVE_PRE_INCREMENT 0 */ 1320 1321/* Macros to check register numbers against specific register classes. */ 1322 1323/* These assume that REGNO is a hard or pseudo reg number. 1324 They give nonzero only if REGNO is a hard reg of the suitable class 1325 or a pseudo reg currently allocated to a suitable hard reg. 1326 Since they use reg_renumber, they are safe only once reg_renumber 1327 has been allocated, which happens in local-alloc.c. */ 1328 1329#define REGNO_OK_FOR_INDEX_P(REGNO) 0 1330#define REGNO_OK_FOR_BASE_P(REGNO) \ 1331((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32 \ 1332 || (REGNO) == 63 || reg_renumber[REGNO] == 63) 1333 1334/* Maximum number of registers that can appear in a valid memory address. */ 1335#define MAX_REGS_PER_ADDRESS 1 1336 1337/* Recognize any constant value that is a valid address. For the Alpha, 1338 there are only constants none since we want to use LDA to load any 1339 symbolic addresses into registers. */ 1340 1341#define CONSTANT_ADDRESS_P(X) \ 1342 (GET_CODE (X) == CONST_INT \ 1343 && (unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000) 1344 1345/* Include all constant integers and constant doubles, but not 1346 floating-point, except for floating-point zero. */ 1347 1348#define LEGITIMATE_CONSTANT_P(X) \ 1349 (GET_MODE_CLASS (GET_MODE (X)) != MODE_FLOAT \ 1350 || (X) == CONST0_RTX (GET_MODE (X))) 1351 1352/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 1353 and check its validity for a certain class. 1354 We have two alternate definitions for each of them. 1355 The usual definition accepts all pseudo regs; the other rejects 1356 them unless they have been allocated suitable hard regs. 1357 The symbol REG_OK_STRICT causes the latter definition to be used. 1358 1359 Most source files want to accept pseudo regs in the hope that 1360 they will get allocated to the class that the insn wants them to be in. 1361 Source files for reload pass need to be strict. 1362 After reload, it makes no difference, since pseudo regs have 1363 been eliminated by then. */ 1364 1365/* Nonzero if X is a hard reg that can be used as an index 1366 or if it is a pseudo reg. */ 1367#define REG_OK_FOR_INDEX_P(X) 0 1368 1369/* Nonzero if X is a hard reg that can be used as a base reg 1370 or if it is a pseudo reg. */ 1371#define NONSTRICT_REG_OK_FOR_BASE_P(X) \ 1372 (REGNO (X) < 32 || REGNO (X) == 63 || REGNO (X) >= FIRST_PSEUDO_REGISTER) 1373 1374/* ??? Nonzero if X is the frame pointer, or some virtual register 1375 that may eliminate to the frame pointer. These will be allowed to 1376 have offsets greater than 32K. This is done because register 1377 elimination offsets will change the hi/lo split, and if we split 1378 before reload, we will require additional instructions. */ 1379#define NONSTRICT_REG_OK_FP_BASE_P(X) \ 1380 (REGNO (X) == 31 || REGNO (X) == 63 \ 1381 || (REGNO (X) >= FIRST_PSEUDO_REGISTER \ 1382 && REGNO (X) < LAST_VIRTUAL_REGISTER)) 1383 1384/* Nonzero if X is a hard reg that can be used as a base reg. */ 1385#define STRICT_REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) 1386 1387#ifdef REG_OK_STRICT 1388#define REG_OK_FOR_BASE_P(X) STRICT_REG_OK_FOR_BASE_P (X) 1389#else 1390#define REG_OK_FOR_BASE_P(X) NONSTRICT_REG_OK_FOR_BASE_P (X) 1391#endif 1392 1393/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a 1394 valid memory address for an instruction. */ 1395 1396#ifdef REG_OK_STRICT 1397#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \ 1398do { \ 1399 if (alpha_legitimate_address_p (MODE, X, 1)) \ 1400 goto WIN; \ 1401} while (0) 1402#else 1403#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \ 1404do { \ 1405 if (alpha_legitimate_address_p (MODE, X, 0)) \ 1406 goto WIN; \ 1407} while (0) 1408#endif 1409 1410/* Try machine-dependent ways of modifying an illegitimate address 1411 to be legitimate. If we find one, return the new, valid address. 1412 This macro is used in only one place: `memory_address' in explow.c. */ 1413 1414#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ 1415do { \ 1416 rtx new_x = alpha_legitimize_address (X, NULL_RTX, MODE); \ 1417 if (new_x) \ 1418 { \ 1419 X = new_x; \ 1420 goto WIN; \ 1421 } \ 1422} while (0) 1423 1424/* Try a machine-dependent way of reloading an illegitimate address 1425 operand. If we find one, push the reload and jump to WIN. This 1426 macro is used in only one place: `find_reloads_address' in reload.c. */ 1427 1428#define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_L,WIN) \ 1429do { \ 1430 rtx new_x = alpha_legitimize_reload_address (X, MODE, OPNUM, TYPE, IND_L); \ 1431 if (new_x) \ 1432 { \ 1433 X = new_x; \ 1434 goto WIN; \ 1435 } \ 1436} while (0) 1437 1438/* Go to LABEL if ADDR (a legitimate address expression) 1439 has an effect that depends on the machine mode it is used for. 1440 On the Alpha this is true only for the unaligned modes. We can 1441 simplify this test since we know that the address must be valid. */ 1442 1443#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ 1444{ if (GET_CODE (ADDR) == AND) goto LABEL; } 1445 1446/* Compute the cost of an address. For the Alpha, all valid addresses are 1447 the same cost. */ 1448 1449#define ADDRESS_COST(X) 0 1450 1451/* Machine-dependent reorg pass. */ 1452#define MACHINE_DEPENDENT_REORG(X) alpha_reorg(X) 1453 1454/* Specify the machine mode that this machine uses 1455 for the index in the tablejump instruction. */ 1456#define CASE_VECTOR_MODE SImode 1457 1458/* Define as C expression which evaluates to nonzero if the tablejump 1459 instruction expects the table to contain offsets from the address of the 1460 table. 1461 1462 Do not define this if the table should contain absolute addresses. 1463 On the Alpha, the table is really GP-relative, not relative to the PC 1464 of the table, but we pretend that it is PC-relative; this should be OK, 1465 but we should try to find some better way sometime. */ 1466#define CASE_VECTOR_PC_RELATIVE 1 1467 1468/* Define this as 1 if `char' should by default be signed; else as 0. */ 1469#define DEFAULT_SIGNED_CHAR 1 1470 1471/* This flag, if defined, says the same insns that convert to a signed fixnum 1472 also convert validly to an unsigned one. 1473 1474 We actually lie a bit here as overflow conditions are different. But 1475 they aren't being checked anyway. */ 1476 1477#define FIXUNS_TRUNC_LIKE_FIX_TRUNC 1478 1479/* Max number of bytes we can move to or from memory 1480 in one reasonably fast instruction. */ 1481 1482#define MOVE_MAX 8 1483 1484/* If a memory-to-memory move would take MOVE_RATIO or more simple 1485 move-instruction pairs, we will do a movstr or libcall instead. 1486 1487 Without byte/word accesses, we want no more than four instructions; 1488 with, several single byte accesses are better. */ 1489 1490#define MOVE_RATIO (TARGET_BWX ? 7 : 2) 1491 1492/* Largest number of bytes of an object that can be placed in a register. 1493 On the Alpha we have plenty of registers, so use TImode. */ 1494#define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode) 1495 1496/* Nonzero if access to memory by bytes is no faster than for words. 1497 Also nonzero if doing byte operations (specifically shifts) in registers 1498 is undesirable. 1499 1500 On the Alpha, we want to not use the byte operation and instead use 1501 masking operations to access fields; these will save instructions. */ 1502 1503#define SLOW_BYTE_ACCESS 1 1504 1505/* Define if operations between registers always perform the operation 1506 on the full register even if a narrower mode is specified. */ 1507#define WORD_REGISTER_OPERATIONS 1508 1509/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 1510 will either zero-extend or sign-extend. The value of this macro should 1511 be the code that says which one of the two operations is implicitly 1512 done, NIL if none. */ 1513#define LOAD_EXTEND_OP(MODE) ((MODE) == SImode ? SIGN_EXTEND : ZERO_EXTEND) 1514 1515/* Define if loading short immediate values into registers sign extends. */ 1516#define SHORT_IMMEDIATES_SIGN_EXTEND 1517 1518/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 1519 is done just by pretending it is already truncated. */ 1520#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 1521 1522/* We assume that the store-condition-codes instructions store 0 for false 1523 and some other value for true. This is the value stored for true. */ 1524 1525#define STORE_FLAG_VALUE 1 1526 1527/* Define the value returned by a floating-point comparison instruction. */ 1528 1529#define FLOAT_STORE_FLAG_VALUE(MODE) \ 1530 REAL_VALUE_ATOF ((TARGET_FLOAT_VAX ? "0.5" : "2.0"), (MODE)) 1531 1532/* Canonicalize a comparison from one we don't have to one we do have. */ 1533 1534#define CANONICALIZE_COMPARISON(CODE,OP0,OP1) \ 1535 do { \ 1536 if (((CODE) == GE || (CODE) == GT || (CODE) == GEU || (CODE) == GTU) \ 1537 && (GET_CODE (OP1) == REG || (OP1) == const0_rtx)) \ 1538 { \ 1539 rtx tem = (OP0); \ 1540 (OP0) = (OP1); \ 1541 (OP1) = tem; \ 1542 (CODE) = swap_condition (CODE); \ 1543 } \ 1544 if (((CODE) == LT || (CODE) == LTU) \ 1545 && GET_CODE (OP1) == CONST_INT && INTVAL (OP1) == 256) \ 1546 { \ 1547 (CODE) = (CODE) == LT ? LE : LEU; \ 1548 (OP1) = GEN_INT (255); \ 1549 } \ 1550 } while (0) 1551 1552/* Specify the machine mode that pointers have. 1553 After generation of rtl, the compiler makes no further distinction 1554 between pointers and any other objects of this machine mode. */ 1555#define Pmode DImode 1556 1557/* Mode of a function address in a call instruction (for indexing purposes). */ 1558 1559#define FUNCTION_MODE Pmode 1560 1561/* Define this if addresses of constant functions 1562 shouldn't be put through pseudo regs where they can be cse'd. 1563 Desirable on machines where ordinary constants are expensive 1564 but a CALL with constant address is cheap. 1565 1566 We define this on the Alpha so that gen_call and gen_call_value 1567 get to see the SYMBOL_REF (for the hint field of the jsr). It will 1568 then copy it into a register, thus actually letting the address be 1569 cse'ed. */ 1570 1571#define NO_FUNCTION_CSE 1572 1573/* Define this to be nonzero if shift instructions ignore all but the low-order 1574 few bits. */ 1575#define SHIFT_COUNT_TRUNCATED 1 1576 1577/* Compute the cost of computing a constant rtl expression RTX 1578 whose rtx-code is CODE. The body of this macro is a portion 1579 of a switch statement. If the code is computed here, 1580 return it with a return statement. Otherwise, break from the switch. 1581 1582 If this is an 8-bit constant, return zero since it can be used 1583 nearly anywhere with no cost. If it is a valid operand for an 1584 ADD or AND, likewise return 0 if we know it will be used in that 1585 context. Otherwise, return 2 since it might be used there later. 1586 All other constants take at least two insns. */ 1587 1588#define CONST_COSTS(RTX,CODE,OUTER_CODE) \ 1589 case CONST_INT: \ 1590 if (INTVAL (RTX) >= 0 && INTVAL (RTX) < 256) \ 1591 return 0; \ 1592 case CONST_DOUBLE: \ 1593 if ((RTX) == CONST0_RTX (GET_MODE (RTX))) \ 1594 return 0; \ 1595 else if (((OUTER_CODE) == PLUS && add_operand (RTX, VOIDmode)) \ 1596 || ((OUTER_CODE) == AND && and_operand (RTX, VOIDmode))) \ 1597 return 0; \ 1598 else if (add_operand (RTX, VOIDmode) || and_operand (RTX, VOIDmode)) \ 1599 return 2; \ 1600 else \ 1601 return COSTS_N_INSNS (2); \ 1602 case CONST: \ 1603 case SYMBOL_REF: \ 1604 case LABEL_REF: \ 1605 switch (alpha_cpu) \ 1606 { \ 1607 case PROCESSOR_EV4: \ 1608 return COSTS_N_INSNS (3); \ 1609 case PROCESSOR_EV5: \ 1610 case PROCESSOR_EV6: \ 1611 return COSTS_N_INSNS (2); \ 1612 default: abort(); \ 1613 } 1614 1615/* Provide the costs of a rtl expression. This is in the body of a 1616 switch on CODE. */ 1617 1618#define RTX_COSTS(X,CODE,OUTER_CODE) \ 1619 case PLUS: case MINUS: \ 1620 if (FLOAT_MODE_P (GET_MODE (X))) \ 1621 switch (alpha_cpu) \ 1622 { \ 1623 case PROCESSOR_EV4: \ 1624 return COSTS_N_INSNS (6); \ 1625 case PROCESSOR_EV5: \ 1626 case PROCESSOR_EV6: \ 1627 return COSTS_N_INSNS (4); \ 1628 default: abort(); \ 1629 } \ 1630 else if (GET_CODE (XEXP (X, 0)) == MULT \ 1631 && const48_operand (XEXP (XEXP (X, 0), 1), VOIDmode)) \ 1632 return (2 + rtx_cost (XEXP (XEXP (X, 0), 0), OUTER_CODE) \ 1633 + rtx_cost (XEXP (X, 1), OUTER_CODE)); \ 1634 break; \ 1635 case MULT: \ 1636 switch (alpha_cpu) \ 1637 { \ 1638 case PROCESSOR_EV4: \ 1639 if (FLOAT_MODE_P (GET_MODE (X))) \ 1640 return COSTS_N_INSNS (6); \ 1641 return COSTS_N_INSNS (23); \ 1642 case PROCESSOR_EV5: \ 1643 if (FLOAT_MODE_P (GET_MODE (X))) \ 1644 return COSTS_N_INSNS (4); \ 1645 else if (GET_MODE (X) == DImode) \ 1646 return COSTS_N_INSNS (12); \ 1647 else \ 1648 return COSTS_N_INSNS (8); \ 1649 case PROCESSOR_EV6: \ 1650 if (FLOAT_MODE_P (GET_MODE (X))) \ 1651 return COSTS_N_INSNS (4); \ 1652 else \ 1653 return COSTS_N_INSNS (7); \ 1654 default: abort(); \ 1655 } \ 1656 case ASHIFT: \ 1657 if (GET_CODE (XEXP (X, 1)) == CONST_INT \ 1658 && INTVAL (XEXP (X, 1)) <= 3) \ 1659 break; \ 1660 /* ... fall through ... */ \ 1661 case ASHIFTRT: case LSHIFTRT: \ 1662 switch (alpha_cpu) \ 1663 { \ 1664 case PROCESSOR_EV4: \ 1665 return COSTS_N_INSNS (2); \ 1666 case PROCESSOR_EV5: \ 1667 case PROCESSOR_EV6: \ 1668 return COSTS_N_INSNS (1); \ 1669 default: abort(); \ 1670 } \ 1671 case IF_THEN_ELSE: \ 1672 switch (alpha_cpu) \ 1673 { \ 1674 case PROCESSOR_EV4: \ 1675 case PROCESSOR_EV6: \ 1676 return COSTS_N_INSNS (2); \ 1677 case PROCESSOR_EV5: \ 1678 return COSTS_N_INSNS (1); \ 1679 default: abort(); \ 1680 } \ 1681 case DIV: case UDIV: case MOD: case UMOD: \ 1682 switch (alpha_cpu) \ 1683 { \ 1684 case PROCESSOR_EV4: \ 1685 if (GET_MODE (X) == SFmode) \ 1686 return COSTS_N_INSNS (34); \ 1687 else if (GET_MODE (X) == DFmode) \ 1688 return COSTS_N_INSNS (63); \ 1689 else \ 1690 return COSTS_N_INSNS (70); \ 1691 case PROCESSOR_EV5: \ 1692 if (GET_MODE (X) == SFmode) \ 1693 return COSTS_N_INSNS (15); \ 1694 else if (GET_MODE (X) == DFmode) \ 1695 return COSTS_N_INSNS (22); \ 1696 else \ 1697 return COSTS_N_INSNS (70); /* ??? */ \ 1698 case PROCESSOR_EV6: \ 1699 if (GET_MODE (X) == SFmode) \ 1700 return COSTS_N_INSNS (12); \ 1701 else if (GET_MODE (X) == DFmode) \ 1702 return COSTS_N_INSNS (15); \ 1703 else \ 1704 return COSTS_N_INSNS (70); /* ??? */ \ 1705 default: abort(); \ 1706 } \ 1707 case MEM: \ 1708 switch (alpha_cpu) \ 1709 { \ 1710 case PROCESSOR_EV4: \ 1711 case PROCESSOR_EV6: \ 1712 return COSTS_N_INSNS (3); \ 1713 case PROCESSOR_EV5: \ 1714 return COSTS_N_INSNS (2); \ 1715 default: abort(); \ 1716 } \ 1717 case NEG: case ABS: \ 1718 if (! FLOAT_MODE_P (GET_MODE (X))) \ 1719 break; \ 1720 /* ... fall through ... */ \ 1721 case FLOAT: case UNSIGNED_FLOAT: case FIX: case UNSIGNED_FIX: \ 1722 case FLOAT_EXTEND: case FLOAT_TRUNCATE: \ 1723 switch (alpha_cpu) \ 1724 { \ 1725 case PROCESSOR_EV4: \ 1726 return COSTS_N_INSNS (6); \ 1727 case PROCESSOR_EV5: \ 1728 case PROCESSOR_EV6: \ 1729 return COSTS_N_INSNS (4); \ 1730 default: abort(); \ 1731 } 1732 1733/* Control the assembler format that we output. */ 1734 1735/* Output to assembler file text saying following lines 1736 may contain character constants, extra white space, comments, etc. */ 1737#define ASM_APP_ON (TARGET_EXPLICIT_RELOCS ? "\t.set\tmacro\n" : "") 1738 1739/* Output to assembler file text saying following lines 1740 no longer contain unusual constructs. */ 1741#define ASM_APP_OFF (TARGET_EXPLICIT_RELOCS ? "\t.set\tnomacro\n" : "") 1742 1743#define TEXT_SECTION_ASM_OP "\t.text" 1744 1745/* Output before read-only data. */ 1746 1747#define READONLY_DATA_SECTION_ASM_OP "\t.rdata" 1748 1749/* Output before writable data. */ 1750 1751#define DATA_SECTION_ASM_OP "\t.data" 1752 1753/* How to refer to registers in assembler output. 1754 This sequence is indexed by compiler's hard-register-number (see above). */ 1755 1756#define REGISTER_NAMES \ 1757{"$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8", \ 1758 "$9", "$10", "$11", "$12", "$13", "$14", "$15", \ 1759 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \ 1760 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "AP", \ 1761 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", "$f8", \ 1762 "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \ 1763 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",\ 1764 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "FP"} 1765 1766/* Strip name encoding when emitting labels. */ 1767 1768#define ASM_OUTPUT_LABELREF(STREAM, NAME) \ 1769do { \ 1770 const char *name_ = NAME; \ 1771 if (*name_ == '@' || *name_ == '%') \ 1772 name_ += 2; \ 1773 if (*name_ == '*') \ 1774 name_++; \ 1775 else \ 1776 fputs (user_label_prefix, STREAM); \ 1777 fputs (name_, STREAM); \ 1778} while (0) 1779 1780/* Globalizing directive for a label. */ 1781#define GLOBAL_ASM_OP "\t.globl " 1782 1783/* The prefix to add to user-visible assembler symbols. */ 1784 1785#define USER_LABEL_PREFIX "" 1786 1787/* This is how to output an internal numbered label where 1788 PREFIX is the class of label and NUM is the number within the class. */ 1789 1790#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ 1791 fprintf (FILE, "$%s%d:\n", PREFIX, NUM) 1792 1793/* This is how to output a label for a jump table. Arguments are the same as 1794 for ASM_OUTPUT_INTERNAL_LABEL, except the insn for the jump table is 1795 passed. */ 1796 1797#define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,TABLEINSN) \ 1798{ ASM_OUTPUT_ALIGN (FILE, 2); ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); } 1799 1800/* This is how to store into the string LABEL 1801 the symbol_ref name of an internal numbered label where 1802 PREFIX is the class of label and NUM is the number within the class. 1803 This is suitable for output with `assemble_name'. */ 1804 1805#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ 1806 sprintf ((LABEL), "*$%s%ld", (PREFIX), (long)(NUM)) 1807 1808/* We use the default ASCII-output routine, except that we don't write more 1809 than 50 characters since the assembler doesn't support very long lines. */ 1810 1811#define ASM_OUTPUT_ASCII(MYFILE, MYSTRING, MYLENGTH) \ 1812 do { \ 1813 FILE *_hide_asm_out_file = (MYFILE); \ 1814 const unsigned char *_hide_p = (const unsigned char *) (MYSTRING); \ 1815 int _hide_thissize = (MYLENGTH); \ 1816 int _size_so_far = 0; \ 1817 { \ 1818 FILE *asm_out_file = _hide_asm_out_file; \ 1819 const unsigned char *p = _hide_p; \ 1820 int thissize = _hide_thissize; \ 1821 int i; \ 1822 fprintf (asm_out_file, "\t.ascii \""); \ 1823 \ 1824 for (i = 0; i < thissize; i++) \ 1825 { \ 1826 register int c = p[i]; \ 1827 \ 1828 if (_size_so_far ++ > 50 && i < thissize - 4) \ 1829 _size_so_far = 0, fprintf (asm_out_file, "\"\n\t.ascii \""); \ 1830 \ 1831 if (c == '\"' || c == '\\') \ 1832 putc ('\\', asm_out_file); \ 1833 if (c >= ' ' && c < 0177) \ 1834 putc (c, asm_out_file); \ 1835 else \ 1836 { \ 1837 fprintf (asm_out_file, "\\%o", c); \ 1838 /* After an octal-escape, if a digit follows, \ 1839 terminate one string constant and start another. \ 1840 The VAX assembler fails to stop reading the escape \ 1841 after three digits, so this is the only way we \ 1842 can get it to parse the data properly. */ \ 1843 if (i < thissize - 1 && ISDIGIT (p[i + 1])) \ 1844 _size_so_far = 0, fprintf (asm_out_file, "\"\n\t.ascii \""); \ 1845 } \ 1846 } \ 1847 fprintf (asm_out_file, "\"\n"); \ 1848 } \ 1849 } \ 1850 while (0) 1851 1852/* This is how to output an insn to push a register on the stack. 1853 It need not be very fast code. */ 1854 1855#define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ 1856 fprintf (FILE, "\tsubq $30,8,$30\n\tst%s $%s%d,0($30)\n", \ 1857 (REGNO) > 32 ? "t" : "q", (REGNO) > 32 ? "f" : "", \ 1858 (REGNO) & 31); 1859 1860/* This is how to output an insn to pop a register from the stack. 1861 It need not be very fast code. */ 1862 1863#define ASM_OUTPUT_REG_POP(FILE,REGNO) \ 1864 fprintf (FILE, "\tld%s $%s%d,0($30)\n\taddq $30,8,$30\n", \ 1865 (REGNO) > 32 ? "t" : "q", (REGNO) > 32 ? "f" : "", \ 1866 (REGNO) & 31); 1867 1868/* This is how to output an element of a case-vector that is absolute. 1869 (Alpha does not use such vectors, but we must define this macro anyway.) */ 1870 1871#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) abort () 1872 1873/* This is how to output an element of a case-vector that is relative. */ 1874 1875#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 1876 fprintf (FILE, "\t.%s $L%d\n", TARGET_ABI_WINDOWS_NT ? "long" : "gprel32", \ 1877 (VALUE)) 1878 1879/* This is how to output an assembler line 1880 that says to advance the location counter 1881 to a multiple of 2**LOG bytes. */ 1882 1883#define ASM_OUTPUT_ALIGN(FILE,LOG) \ 1884 if ((LOG) != 0) \ 1885 fprintf (FILE, "\t.align %d\n", LOG); 1886 1887/* This is how to advance the location counter by SIZE bytes. */ 1888 1889#define ASM_OUTPUT_SKIP(FILE,SIZE) \ 1890 fprintf (FILE, "\t.space %d\n", (SIZE)) 1891 1892/* This says how to output an assembler line 1893 to define a global common symbol. */ 1894 1895#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ 1896( fputs ("\t.comm ", (FILE)), \ 1897 assemble_name ((FILE), (NAME)), \ 1898 fprintf ((FILE), ",%d\n", (SIZE))) 1899 1900/* This says how to output an assembler line 1901 to define a local common symbol. */ 1902 1903#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE,ROUNDED) \ 1904( fputs ("\t.lcomm ", (FILE)), \ 1905 assemble_name ((FILE), (NAME)), \ 1906 fprintf ((FILE), ",%d\n", (SIZE))) 1907 1908/* Store in OUTPUT a string (made with alloca) containing 1909 an assembler-name for a local static variable named NAME. 1910 LABELNO is an integer which is different for each call. */ 1911 1912#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ 1913( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ 1914 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO))) 1915 1916 1917/* Print operand X (an rtx) in assembler syntax to file FILE. 1918 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. 1919 For `%' followed by punctuation, CODE is the punctuation and X is null. */ 1920 1921#define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) 1922 1923/* Determine which codes are valid without a following integer. These must 1924 not be alphabetic. 1925 1926 ~ Generates the name of the current function. 1927 1928 / Generates the instruction suffix. The TRAP_SUFFIX and ROUND_SUFFIX 1929 attributes are examined to determine what is appropriate. 1930 1931 , Generates single precision suffix for floating point 1932 instructions (s for IEEE, f for VAX) 1933 1934 - Generates double precision suffix for floating point 1935 instructions (t for IEEE, g for VAX) 1936 */ 1937 1938#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ 1939 ((CODE) == '/' || (CODE) == ',' || (CODE) == '-' || (CODE) == '~' \ 1940 || (CODE) == '#' || (CODE) == '*' || (CODE) == '&') 1941 1942/* Print a memory address as an operand to reference that memory location. */ 1943 1944#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ 1945 print_operand_address((FILE), (ADDR)) 1946 1947/* Define the codes that are matched by predicates in alpha.c. */ 1948 1949#define PREDICATE_CODES \ 1950 {"reg_or_0_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, \ 1951 CONST_VECTOR}}, \ 1952 {"reg_or_6bit_operand", {SUBREG, REG, CONST_INT}}, \ 1953 {"reg_or_8bit_operand", {SUBREG, REG, CONST_INT}}, \ 1954 {"reg_or_const_int_operand", {SUBREG, REG, CONST_INT}}, \ 1955 {"cint8_operand", {CONST_INT}}, \ 1956 {"reg_or_cint_operand", {SUBREG, REG, CONST_INT}}, \ 1957 {"add_operand", {SUBREG, REG, CONST_INT}}, \ 1958 {"sext_add_operand", {SUBREG, REG, CONST_INT}}, \ 1959 {"const48_operand", {CONST_INT}}, \ 1960 {"and_operand", {SUBREG, REG, CONST_INT}}, \ 1961 {"or_operand", {SUBREG, REG, CONST_INT}}, \ 1962 {"mode_mask_operand", {CONST_INT}}, \ 1963 {"mul8_operand", {CONST_INT}}, \ 1964 {"mode_width_operand", {CONST_INT}}, \ 1965 {"alpha_comparison_operator", {EQ, LE, LT, LEU, LTU}}, \ 1966 {"alpha_zero_comparison_operator", {EQ, NE, LE, LT, LEU, LTU}}, \ 1967 {"alpha_swapped_comparison_operator", {EQ, GE, GT, GEU, GTU}}, \ 1968 {"signed_comparison_operator", {EQ, NE, LE, LT, GE, GT}}, \ 1969 {"alpha_fp_comparison_operator", {EQ, LE, LT, UNORDERED}}, \ 1970 {"divmod_operator", {DIV, MOD, UDIV, UMOD}}, \ 1971 {"const0_operand", {CONST_INT, CONST_DOUBLE, CONST_VECTOR}}, \ 1972 {"current_file_function_operand", {SYMBOL_REF}}, \ 1973 {"direct_call_operand", {SYMBOL_REF}}, \ 1974 {"local_symbolic_operand", {SYMBOL_REF, CONST, LABEL_REF}}, \ 1975 {"small_symbolic_operand", {SYMBOL_REF, CONST}}, \ 1976 {"global_symbolic_operand", {SYMBOL_REF, CONST}}, \ 1977 {"dtp16_symbolic_operand", {CONST}}, \ 1978 {"dtp32_symbolic_operand", {CONST}}, \ 1979 {"gotdtp_symbolic_operand", {CONST}}, \ 1980 {"tp16_symbolic_operand", {CONST}}, \ 1981 {"tp32_symbolic_operand", {CONST}}, \ 1982 {"gottp_symbolic_operand", {CONST}}, \ 1983 {"call_operand", {REG, SYMBOL_REF}}, \ 1984 {"input_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE, \ 1985 CONST_VECTOR, SYMBOL_REF, CONST, LABEL_REF, HIGH}},\ 1986 {"some_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE, \ 1987 CONST_VECTOR, SYMBOL_REF, CONST, LABEL_REF, HIGH}}, \ 1988 {"some_ni_operand", {SUBREG, REG, MEM}}, \ 1989 {"aligned_memory_operand", {MEM}}, \ 1990 {"unaligned_memory_operand", {MEM}}, \ 1991 {"reg_or_unaligned_mem_operand", {SUBREG, REG, MEM}}, \ 1992 {"any_memory_operand", {MEM}}, \ 1993 {"hard_fp_register_operand", {SUBREG, REG}}, \ 1994 {"hard_int_register_operand", {SUBREG, REG}}, \ 1995 {"reg_not_elim_operand", {SUBREG, REG}}, \ 1996 {"reg_no_subreg_operand", {REG}}, \ 1997 {"addition_operation", {PLUS}}, \ 1998 {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \ 1999 {"some_small_symbolic_operand", {SET, PARALLEL, PREFETCH, UNSPEC, \ 2000 UNSPEC_VOLATILE}}, 2001 2002/* Define the `__builtin_va_list' type for the ABI. */ 2003#define BUILD_VA_LIST_TYPE(VALIST) \ 2004 (VALIST) = alpha_build_va_list () 2005 2006/* Implement `va_start' for varargs and stdarg. */ 2007#define EXPAND_BUILTIN_VA_START(valist, nextarg) \ 2008 alpha_va_start (valist, nextarg) 2009 2010/* Implement `va_arg'. */ 2011#define EXPAND_BUILTIN_VA_ARG(valist, type) \ 2012 alpha_va_arg (valist, type) 2013 2014/* Tell collect that the object format is ECOFF. */ 2015#define OBJECT_FORMAT_COFF 2016#define EXTENDED_COFF 2017 2018/* If we use NM, pass -g to it so it only lists globals. */ 2019#define NM_FLAGS "-pg" 2020 2021/* Definitions for debugging. */ 2022 2023#define SDB_DEBUGGING_INFO 1 /* generate info for mips-tfile */ 2024#define DBX_DEBUGGING_INFO 1 /* generate embedded stabs */ 2025#define MIPS_DEBUGGING_INFO 1 /* MIPS specific debugging info */ 2026 2027#ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */ 2028#define PREFERRED_DEBUGGING_TYPE SDB_DEBUG 2029#endif 2030 2031 2032/* Correct the offset of automatic variables and arguments. Note that 2033 the Alpha debug format wants all automatic variables and arguments 2034 to be in terms of two different offsets from the virtual frame pointer, 2035 which is the stack pointer before any adjustment in the function. 2036 The offset for the argument pointer is fixed for the native compiler, 2037 it is either zero (for the no arguments case) or large enough to hold 2038 all argument registers. 2039 The offset for the auto pointer is the fourth argument to the .frame 2040 directive (local_offset). 2041 To stay compatible with the native tools we use the same offsets 2042 from the virtual frame pointer and adjust the debugger arg/auto offsets 2043 accordingly. These debugger offsets are set up in output_prolog. */ 2044 2045extern long alpha_arg_offset; 2046extern long alpha_auto_offset; 2047#define DEBUGGER_AUTO_OFFSET(X) \ 2048 ((GET_CODE (X) == PLUS ? INTVAL (XEXP (X, 1)) : 0) + alpha_auto_offset) 2049#define DEBUGGER_ARG_OFFSET(OFFSET, X) (OFFSET + alpha_arg_offset) 2050 2051 2052#define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) \ 2053 alpha_output_lineno (STREAM, LINE) 2054 2055#define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \ 2056 alpha_output_filename (STREAM, NAME) 2057 2058/* mips-tfile.c limits us to strings of one page. We must underestimate this 2059 number, because the real length runs past this up to the next 2060 continuation point. This is really a dbxout.c bug. */ 2061#define DBX_CONTIN_LENGTH 3000 2062 2063/* By default, turn on GDB extensions. */ 2064#define DEFAULT_GDB_EXTENSIONS 1 2065 2066/* Stabs-in-ECOFF can't handle dbxout_function_end(). */ 2067#define NO_DBX_FUNCTION_END 1 2068 2069/* If we are smuggling stabs through the ALPHA ECOFF object 2070 format, put a comment in front of the .stab<x> operation so 2071 that the ALPHA assembler does not choke. The mips-tfile program 2072 will correctly put the stab into the object file. */ 2073 2074#define ASM_STABS_OP ((TARGET_GAS) ? "\t.stabs\t" : " #.stabs\t") 2075#define ASM_STABN_OP ((TARGET_GAS) ? "\t.stabn\t" : " #.stabn\t") 2076#define ASM_STABD_OP ((TARGET_GAS) ? "\t.stabd\t" : " #.stabd\t") 2077 2078/* Forward references to tags are allowed. */ 2079#define SDB_ALLOW_FORWARD_REFERENCES 2080 2081/* Unknown tags are also allowed. */ 2082#define SDB_ALLOW_UNKNOWN_REFERENCES 2083 2084#define PUT_SDB_DEF(a) \ 2085do { \ 2086 fprintf (asm_out_file, "\t%s.def\t", \ 2087 (TARGET_GAS) ? "" : "#"); \ 2088 ASM_OUTPUT_LABELREF (asm_out_file, a); \ 2089 fputc (';', asm_out_file); \ 2090} while (0) 2091 2092#define PUT_SDB_PLAIN_DEF(a) \ 2093do { \ 2094 fprintf (asm_out_file, "\t%s.def\t.%s;", \ 2095 (TARGET_GAS) ? "" : "#", (a)); \ 2096} while (0) 2097 2098#define PUT_SDB_TYPE(a) \ 2099do { \ 2100 fprintf (asm_out_file, "\t.type\t0x%x;", (a)); \ 2101} while (0) 2102 2103/* For block start and end, we create labels, so that 2104 later we can figure out where the correct offset is. 2105 The normal .ent/.end serve well enough for functions, 2106 so those are just commented out. */ 2107 2108extern int sdb_label_count; /* block start/end next label # */ 2109 2110#define PUT_SDB_BLOCK_START(LINE) \ 2111do { \ 2112 fprintf (asm_out_file, \ 2113 "$Lb%d:\n\t%s.begin\t$Lb%d\t%d\n", \ 2114 sdb_label_count, \ 2115 (TARGET_GAS) ? "" : "#", \ 2116 sdb_label_count, \ 2117 (LINE)); \ 2118 sdb_label_count++; \ 2119} while (0) 2120 2121#define PUT_SDB_BLOCK_END(LINE) \ 2122do { \ 2123 fprintf (asm_out_file, \ 2124 "$Le%d:\n\t%s.bend\t$Le%d\t%d\n", \ 2125 sdb_label_count, \ 2126 (TARGET_GAS) ? "" : "#", \ 2127 sdb_label_count, \ 2128 (LINE)); \ 2129 sdb_label_count++; \ 2130} while (0) 2131 2132#define PUT_SDB_FUNCTION_START(LINE) 2133 2134#define PUT_SDB_FUNCTION_END(LINE) 2135 2136#define PUT_SDB_EPILOGUE_END(NAME) ((void)(NAME)) 2137 2138/* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for 2139 mips-tdump.c to print them out. 2140 2141 These must match the corresponding definitions in gdb/mipsread.c. 2142 Unfortunately, gcc and gdb do not currently share any directories. */ 2143 2144#define CODE_MASK 0x8F300 2145#define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK) 2146#define MIPS_MARK_STAB(code) ((code)+CODE_MASK) 2147#define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK) 2148 2149/* Override some mips-tfile definitions. */ 2150 2151#define SHASH_SIZE 511 2152#define THASH_SIZE 55 2153 2154/* Align ecoff symbol tables to avoid OSF1/1.3 nm complaints. */ 2155 2156#define ALIGN_SYMTABLE_OFFSET(OFFSET) (((OFFSET) + 7) & ~7) 2157 2158/* The system headers under Alpha systems are generally C++-aware. */ 2159#define NO_IMPLICIT_EXTERN_C 2160 2161/* Generate calls to memcpy, etc., not bcopy, etc. */ 2162#define TARGET_MEM_FUNCTIONS 1 2163