1/* ppc-opc.c -- PowerPC opcode list 2 Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004 3 Free Software Foundation, Inc. 4 Written by Ian Lance Taylor, Cygnus Support 5 6 This file is part of GDB, GAS, and the GNU binutils. 7 8 GDB, GAS, and the GNU binutils are free software; you can redistribute 9 them and/or modify them under the terms of the GNU General Public 10 License as published by the Free Software Foundation; either version 11 2, or (at your option) any later version. 12 13 GDB, GAS, and the GNU binutils are distributed in the hope that they 14 will be useful, but WITHOUT ANY WARRANTY; without even the implied 15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See 16 the GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this file; see the file COPYING. If not, write to the Free 20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 21 02111-1307, USA. */ 22 23#include <stdio.h> 24#include "sysdep.h" 25#include "opcode/ppc.h" 26#include "opintl.h" 27 28/* This file holds the PowerPC opcode table. The opcode table 29 includes almost all of the extended instruction mnemonics. This 30 permits the disassembler to use them, and simplifies the assembler 31 logic, at the cost of increasing the table size. The table is 32 strictly constant data, so the compiler should be able to put it in 33 the .text section. 34 35 This file also holds the operand table. All knowledge about 36 inserting operands into instructions and vice-versa is kept in this 37 file. */ 38 39/* Local insertion and extraction functions. */ 40 41static unsigned long insert_bat (unsigned long, long, int, const char **); 42static long extract_bat (unsigned long, int, int *); 43static unsigned long insert_bba (unsigned long, long, int, const char **); 44static long extract_bba (unsigned long, int, int *); 45static unsigned long insert_bd (unsigned long, long, int, const char **); 46static long extract_bd (unsigned long, int, int *); 47static unsigned long insert_bdm (unsigned long, long, int, const char **); 48static long extract_bdm (unsigned long, int, int *); 49static unsigned long insert_bdp (unsigned long, long, int, const char **); 50static long extract_bdp (unsigned long, int, int *); 51static unsigned long insert_bo (unsigned long, long, int, const char **); 52static long extract_bo (unsigned long, int, int *); 53static unsigned long insert_boe (unsigned long, long, int, const char **); 54static long extract_boe (unsigned long, int, int *); 55static unsigned long insert_dq (unsigned long, long, int, const char **); 56static long extract_dq (unsigned long, int, int *); 57static unsigned long insert_ds (unsigned long, long, int, const char **); 58static long extract_ds (unsigned long, int, int *); 59static unsigned long insert_de (unsigned long, long, int, const char **); 60static long extract_de (unsigned long, int, int *); 61static unsigned long insert_des (unsigned long, long, int, const char **); 62static long extract_des (unsigned long, int, int *); 63static unsigned long insert_fxm (unsigned long, long, int, const char **); 64static long extract_fxm (unsigned long, int, int *); 65static unsigned long insert_li (unsigned long, long, int, const char **); 66static long extract_li (unsigned long, int, int *); 67static unsigned long insert_mbe (unsigned long, long, int, const char **); 68static long extract_mbe (unsigned long, int, int *); 69static unsigned long insert_mb6 (unsigned long, long, int, const char **); 70static long extract_mb6 (unsigned long, int, int *); 71static unsigned long insert_nb (unsigned long, long, int, const char **); 72static long extract_nb (unsigned long, int, int *); 73static unsigned long insert_nsi (unsigned long, long, int, const char **); 74static long extract_nsi (unsigned long, int, int *); 75static unsigned long insert_ral (unsigned long, long, int, const char **); 76static unsigned long insert_ram (unsigned long, long, int, const char **); 77static unsigned long insert_raq (unsigned long, long, int, const char **); 78static unsigned long insert_ras (unsigned long, long, int, const char **); 79static unsigned long insert_rbs (unsigned long, long, int, const char **); 80static long extract_rbs (unsigned long, int, int *); 81static unsigned long insert_rsq (unsigned long, long, int, const char **); 82static unsigned long insert_rtq (unsigned long, long, int, const char **); 83static unsigned long insert_sh6 (unsigned long, long, int, const char **); 84static long extract_sh6 (unsigned long, int, int *); 85static unsigned long insert_spr (unsigned long, long, int, const char **); 86static long extract_spr (unsigned long, int, int *); 87static unsigned long insert_tbr (unsigned long, long, int, const char **); 88static long extract_tbr (unsigned long, int, int *); 89static unsigned long insert_ev2 (unsigned long, long, int, const char **); 90static long extract_ev2 (unsigned long, int, int *); 91static unsigned long insert_ev4 (unsigned long, long, int, const char **); 92static long extract_ev4 (unsigned long, int, int *); 93static unsigned long insert_ev8 (unsigned long, long, int, const char **); 94static long extract_ev8 (unsigned long, int, int *); 95 96/* The operands table. 97 98 The fields are bits, shift, insert, extract, flags. 99 100 We used to put parens around the various additions, like the one 101 for BA just below. However, that caused trouble with feeble 102 compilers with a limit on depth of a parenthesized expression, like 103 (reportedly) the compiler in Microsoft Developer Studio 5. So we 104 omit the parens, since the macros are never used in a context where 105 the addition will be ambiguous. */ 106 107const struct powerpc_operand powerpc_operands[] = 108{ 109 /* The zero index is used to indicate the end of the list of 110 operands. */ 111#define UNUSED 0 112 { 0, 0, 0, 0, 0 }, 113 114 /* The BA field in an XL form instruction. */ 115#define BA UNUSED + 1 116#define BA_MASK (0x1f << 16) 117 { 5, 16, 0, 0, PPC_OPERAND_CR }, 118 119 /* The BA field in an XL form instruction when it must be the same 120 as the BT field in the same instruction. */ 121#define BAT BA + 1 122 { 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE }, 123 124 /* The BB field in an XL form instruction. */ 125#define BB BAT + 1 126#define BB_MASK (0x1f << 11) 127 { 5, 11, 0, 0, PPC_OPERAND_CR }, 128 129 /* The BB field in an XL form instruction when it must be the same 130 as the BA field in the same instruction. */ 131#define BBA BB + 1 132 { 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE }, 133 134 /* The BD field in a B form instruction. The lower two bits are 135 forced to zero. */ 136#define BD BBA + 1 137 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, 138 139 /* The BD field in a B form instruction when absolute addressing is 140 used. */ 141#define BDA BD + 1 142 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, 143 144 /* The BD field in a B form instruction when the - modifier is used. 145 This sets the y bit of the BO field appropriately. */ 146#define BDM BDA + 1 147 { 16, 0, insert_bdm, extract_bdm, 148 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, 149 150 /* The BD field in a B form instruction when the - modifier is used 151 and absolute address is used. */ 152#define BDMA BDM + 1 153 { 16, 0, insert_bdm, extract_bdm, 154 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, 155 156 /* The BD field in a B form instruction when the + modifier is used. 157 This sets the y bit of the BO field appropriately. */ 158#define BDP BDMA + 1 159 { 16, 0, insert_bdp, extract_bdp, 160 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, 161 162 /* The BD field in a B form instruction when the + modifier is used 163 and absolute addressing is used. */ 164#define BDPA BDP + 1 165 { 16, 0, insert_bdp, extract_bdp, 166 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, 167 168 /* The BF field in an X or XL form instruction. */ 169#define BF BDPA + 1 170 { 3, 23, 0, 0, PPC_OPERAND_CR }, 171 172 /* An optional BF field. This is used for comparison instructions, 173 in which an omitted BF field is taken as zero. */ 174#define OBF BF + 1 175 { 3, 23, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL }, 176 177 /* The BFA field in an X or XL form instruction. */ 178#define BFA OBF + 1 179 { 3, 18, 0, 0, PPC_OPERAND_CR }, 180 181 /* The BI field in a B form or XL form instruction. */ 182#define BI BFA + 1 183#define BI_MASK (0x1f << 16) 184 { 5, 16, 0, 0, PPC_OPERAND_CR }, 185 186 /* The BO field in a B form instruction. Certain values are 187 illegal. */ 188#define BO BI + 1 189#define BO_MASK (0x1f << 21) 190 { 5, 21, insert_bo, extract_bo, 0 }, 191 192 /* The BO field in a B form instruction when the + or - modifier is 193 used. This is like the BO field, but it must be even. */ 194#define BOE BO + 1 195 { 5, 21, insert_boe, extract_boe, 0 }, 196 197 /* The BT field in an X or XL form instruction. */ 198#define BT BOE + 1 199 { 5, 21, 0, 0, PPC_OPERAND_CR }, 200 201 /* The condition register number portion of the BI field in a B form 202 or XL form instruction. This is used for the extended 203 conditional branch mnemonics, which set the lower two bits of the 204 BI field. This field is optional. */ 205#define CR BT + 1 206 { 3, 18, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL }, 207 208 /* The CRB field in an X form instruction. */ 209#define CRB CR + 1 210 { 5, 6, 0, 0, 0 }, 211 212 /* The CRFD field in an X form instruction. */ 213#define CRFD CRB + 1 214 { 3, 23, 0, 0, PPC_OPERAND_CR }, 215 216 /* The CRFS field in an X form instruction. */ 217#define CRFS CRFD + 1 218 { 3, 0, 0, 0, PPC_OPERAND_CR }, 219 220 /* The CT field in an X form instruction. */ 221#define CT CRFS + 1 222 { 5, 21, 0, 0, PPC_OPERAND_OPTIONAL }, 223 224 /* The D field in a D form instruction. This is a displacement off 225 a register, and implies that the next operand is a register in 226 parentheses. */ 227#define D CT + 1 228 { 16, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, 229 230 /* The DE field in a DE form instruction. This is like D, but is 12 231 bits only. */ 232#define DE D + 1 233 { 14, 0, insert_de, extract_de, PPC_OPERAND_PARENS }, 234 235 /* The DES field in a DES form instruction. This is like DS, but is 14 236 bits only (12 stored.) */ 237#define DES DE + 1 238 { 14, 0, insert_des, extract_des, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, 239 240 /* The DQ field in a DQ form instruction. This is like D, but the 241 lower four bits are forced to zero. */ 242#define DQ DES + 1 243 { 16, 0, insert_dq, extract_dq, 244 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ }, 245 246 /* The DS field in a DS form instruction. This is like D, but the 247 lower two bits are forced to zero. */ 248#define DS DQ + 1 249 { 16, 0, insert_ds, extract_ds, 250 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS }, 251 252 /* The E field in a wrteei instruction. */ 253#define E DS + 1 254 { 1, 15, 0, 0, 0 }, 255 256 /* The FL1 field in a POWER SC form instruction. */ 257#define FL1 E + 1 258 { 4, 12, 0, 0, 0 }, 259 260 /* The FL2 field in a POWER SC form instruction. */ 261#define FL2 FL1 + 1 262 { 3, 2, 0, 0, 0 }, 263 264 /* The FLM field in an XFL form instruction. */ 265#define FLM FL2 + 1 266 { 8, 17, 0, 0, 0 }, 267 268 /* The FRA field in an X or A form instruction. */ 269#define FRA FLM + 1 270#define FRA_MASK (0x1f << 16) 271 { 5, 16, 0, 0, PPC_OPERAND_FPR }, 272 273 /* The FRB field in an X or A form instruction. */ 274#define FRB FRA + 1 275#define FRB_MASK (0x1f << 11) 276 { 5, 11, 0, 0, PPC_OPERAND_FPR }, 277 278 /* The FRC field in an A form instruction. */ 279#define FRC FRB + 1 280#define FRC_MASK (0x1f << 6) 281 { 5, 6, 0, 0, PPC_OPERAND_FPR }, 282 283 /* The FRS field in an X form instruction or the FRT field in a D, X 284 or A form instruction. */ 285#define FRS FRC + 1 286#define FRT FRS 287 { 5, 21, 0, 0, PPC_OPERAND_FPR }, 288 289 /* The FXM field in an XFX instruction. */ 290#define FXM FRS + 1 291#define FXM_MASK (0xff << 12) 292 { 8, 12, insert_fxm, extract_fxm, 0 }, 293 294 /* Power4 version for mfcr. */ 295#define FXM4 FXM + 1 296 { 8, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL }, 297 298 /* The L field in a D or X form instruction. */ 299#define L FXM4 + 1 300 { 1, 21, 0, 0, PPC_OPERAND_OPTIONAL }, 301 302 /* The LEV field in a POWER SC form instruction. */ 303#define LEV L + 1 304 { 7, 5, 0, 0, 0 }, 305 306 /* The LI field in an I form instruction. The lower two bits are 307 forced to zero. */ 308#define LI LEV + 1 309 { 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, 310 311 /* The LI field in an I form instruction when used as an absolute 312 address. */ 313#define LIA LI + 1 314 { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, 315 316 /* The LS field in an X (sync) form instruction. */ 317#define LS LIA + 1 318 { 2, 21, 0, 0, PPC_OPERAND_OPTIONAL }, 319 320 /* The MB field in an M form instruction. */ 321#define MB LS + 1 322#define MB_MASK (0x1f << 6) 323 { 5, 6, 0, 0, 0 }, 324 325 /* The ME field in an M form instruction. */ 326#define ME MB + 1 327#define ME_MASK (0x1f << 1) 328 { 5, 1, 0, 0, 0 }, 329 330 /* The MB and ME fields in an M form instruction expressed a single 331 operand which is a bitmask indicating which bits to select. This 332 is a two operand form using PPC_OPERAND_NEXT. See the 333 description in opcode/ppc.h for what this means. */ 334#define MBE ME + 1 335 { 5, 6, 0, 0, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT }, 336 { 32, 0, insert_mbe, extract_mbe, 0 }, 337 338 /* The MB or ME field in an MD or MDS form instruction. The high 339 bit is wrapped to the low end. */ 340#define MB6 MBE + 2 341#define ME6 MB6 342#define MB6_MASK (0x3f << 5) 343 { 6, 5, insert_mb6, extract_mb6, 0 }, 344 345 /* The MO field in an mbar instruction. */ 346#define MO MB6 + 1 347 { 5, 21, 0, 0, PPC_OPERAND_OPTIONAL }, 348 349 /* The NB field in an X form instruction. The value 32 is stored as 350 0. */ 351#define NB MO + 1 352 { 6, 11, insert_nb, extract_nb, 0 }, 353 354 /* The NSI field in a D form instruction. This is the same as the 355 SI field, only negated. */ 356#define NSI NB + 1 357 { 16, 0, insert_nsi, extract_nsi, 358 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED }, 359 360 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */ 361#define RA NSI + 1 362#define RA_MASK (0x1f << 16) 363 { 5, 16, 0, 0, PPC_OPERAND_GPR }, 364 365 /* As above, but 0 in the RA field means zero, not r0. */ 366#define RA0 RA + 1 367 { 5, 16, 0, 0, PPC_OPERAND_GPR_0 }, 368 369 /* The RA field in the DQ form lq instruction, which has special 370 value restrictions. */ 371#define RAQ RA0 + 1 372 { 5, 16, insert_raq, 0, PPC_OPERAND_GPR_0 }, 373 374 /* The RA field in a D or X form instruction which is an updating 375 load, which means that the RA field may not be zero and may not 376 equal the RT field. */ 377#define RAL RAQ + 1 378 { 5, 16, insert_ral, 0, PPC_OPERAND_GPR_0 }, 379 380 /* The RA field in an lmw instruction, which has special value 381 restrictions. */ 382#define RAM RAL + 1 383 { 5, 16, insert_ram, 0, PPC_OPERAND_GPR_0 }, 384 385 /* The RA field in a D or X form instruction which is an updating 386 store or an updating floating point load, which means that the RA 387 field may not be zero. */ 388#define RAS RAM + 1 389 { 5, 16, insert_ras, 0, PPC_OPERAND_GPR_0 }, 390 391 /* The RA field of the tlbwe instruction, which is optional. */ 392#define RAOPT RAS + 1 393 { 5, 16, 0, 0, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL }, 394 395 /* The RB field in an X, XO, M, or MDS form instruction. */ 396#define RB RAOPT + 1 397#define RB_MASK (0x1f << 11) 398 { 5, 11, 0, 0, PPC_OPERAND_GPR }, 399 400 /* The RB field in an X form instruction when it must be the same as 401 the RS field in the instruction. This is used for extended 402 mnemonics like mr. */ 403#define RBS RB + 1 404 { 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE }, 405 406 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form 407 instruction or the RT field in a D, DS, X, XFX or XO form 408 instruction. */ 409#define RS RBS + 1 410#define RT RS 411#define RT_MASK (0x1f << 21) 412 { 5, 21, 0, 0, PPC_OPERAND_GPR }, 413 414 /* The RS field of the DS form stq instruction, which has special 415 value restrictions. */ 416#define RSQ RS + 1 417 { 5, 21, insert_rsq, 0, PPC_OPERAND_GPR_0 }, 418 419 /* The RT field of the DQ form lq instruction, which has special 420 value restrictions. */ 421#define RTQ RSQ + 1 422 { 5, 21, insert_rtq, 0, PPC_OPERAND_GPR_0 }, 423 424 /* The RS field of the tlbwe instruction, which is optional. */ 425#define RSO RTQ + 1 426 { 5, 21, 0, 0, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL }, 427 428 /* The SH field in an X or M form instruction. */ 429#define SH RSO + 1 430#define SH_MASK (0x1f << 11) 431 { 5, 11, 0, 0, 0 }, 432 433 /* The SH field in an MD form instruction. This is split. */ 434#define SH6 SH + 1 435#define SH6_MASK ((0x1f << 11) | (1 << 1)) 436 { 6, 1, insert_sh6, extract_sh6, 0 }, 437 438 /* The SH field of the tlbwe instruction, which is optional. */ 439#define SHO SH6 + 1 440 { 5, 11,0, 0, PPC_OPERAND_OPTIONAL }, 441 442 /* The SI field in a D form instruction. */ 443#define SI SHO + 1 444 { 16, 0, 0, 0, PPC_OPERAND_SIGNED }, 445 446 /* The SI field in a D form instruction when we accept a wide range 447 of positive values. */ 448#define SISIGNOPT SI + 1 449 { 16, 0, 0, 0, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, 450 451 /* The SPR field in an XFX form instruction. This is flipped--the 452 lower 5 bits are stored in the upper 5 and vice- versa. */ 453#define SPR SISIGNOPT + 1 454#define PMR SPR 455#define SPR_MASK (0x3ff << 11) 456 { 10, 11, insert_spr, extract_spr, 0 }, 457 458 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */ 459#define SPRBAT SPR + 1 460#define SPRBAT_MASK (0x3 << 17) 461 { 2, 17, 0, 0, 0 }, 462 463 /* The SPRG register number in an XFX form m[ft]sprg instruction. */ 464#define SPRG SPRBAT + 1 465#define SPRG_MASK (0x3 << 16) 466 { 2, 16, 0, 0, 0 }, 467 468 /* The SR field in an X form instruction. */ 469#define SR SPRG + 1 470 { 4, 16, 0, 0, 0 }, 471 472 /* The STRM field in an X AltiVec form instruction. */ 473#define STRM SR + 1 474#define STRM_MASK (0x3 << 21) 475 { 2, 21, 0, 0, 0 }, 476 477 /* The SV field in a POWER SC form instruction. */ 478#define SV STRM + 1 479 { 14, 2, 0, 0, 0 }, 480 481 /* The TBR field in an XFX form instruction. This is like the SPR 482 field, but it is optional. */ 483#define TBR SV + 1 484 { 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL }, 485 486 /* The TO field in a D or X form instruction. */ 487#define TO TBR + 1 488#define TO_MASK (0x1f << 21) 489 { 5, 21, 0, 0, 0 }, 490 491 /* The U field in an X form instruction. */ 492#define U TO + 1 493 { 4, 12, 0, 0, 0 }, 494 495 /* The UI field in a D form instruction. */ 496#define UI U + 1 497 { 16, 0, 0, 0, 0 }, 498 499 /* The VA field in a VA, VX or VXR form instruction. */ 500#define VA UI + 1 501#define VA_MASK (0x1f << 16) 502 { 5, 16, 0, 0, PPC_OPERAND_VR }, 503 504 /* The VB field in a VA, VX or VXR form instruction. */ 505#define VB VA + 1 506#define VB_MASK (0x1f << 11) 507 { 5, 11, 0, 0, PPC_OPERAND_VR }, 508 509 /* The VC field in a VA form instruction. */ 510#define VC VB + 1 511#define VC_MASK (0x1f << 6) 512 { 5, 6, 0, 0, PPC_OPERAND_VR }, 513 514 /* The VD or VS field in a VA, VX, VXR or X form instruction. */ 515#define VD VC + 1 516#define VS VD 517#define VD_MASK (0x1f << 21) 518 { 5, 21, 0, 0, PPC_OPERAND_VR }, 519 520 /* The SIMM field in a VX form instruction. */ 521#define SIMM VD + 1 522 { 5, 16, 0, 0, PPC_OPERAND_SIGNED}, 523 524 /* The UIMM field in a VX form instruction. */ 525#define UIMM SIMM + 1 526 { 5, 16, 0, 0, 0 }, 527 528 /* The SHB field in a VA form instruction. */ 529#define SHB UIMM + 1 530 { 4, 6, 0, 0, 0 }, 531 532 /* The other UIMM field in a EVX form instruction. */ 533#define EVUIMM SHB + 1 534 { 5, 11, 0, 0, 0 }, 535 536 /* The other UIMM field in a half word EVX form instruction. */ 537#define EVUIMM_2 EVUIMM + 1 538 { 32, 11, insert_ev2, extract_ev2, PPC_OPERAND_PARENS }, 539 540 /* The other UIMM field in a word EVX form instruction. */ 541#define EVUIMM_4 EVUIMM_2 + 1 542 { 32, 11, insert_ev4, extract_ev4, PPC_OPERAND_PARENS }, 543 544 /* The other UIMM field in a double EVX form instruction. */ 545#define EVUIMM_8 EVUIMM_4 + 1 546 { 32, 11, insert_ev8, extract_ev8, PPC_OPERAND_PARENS }, 547 548 /* The WS field. */ 549#define WS EVUIMM_8 + 1 550#define WS_MASK (0x7 << 11) 551 { 3, 11, 0, 0, 0 }, 552 553 /* The L field in an mtmsrd instruction */ 554#define MTMSRD_L WS + 1 555 { 1, 16, 0, 0, PPC_OPERAND_OPTIONAL }, 556 557}; 558 559/* The functions used to insert and extract complicated operands. */ 560 561/* The BA field in an XL form instruction when it must be the same as 562 the BT field in the same instruction. This operand is marked FAKE. 563 The insertion function just copies the BT field into the BA field, 564 and the extraction function just checks that the fields are the 565 same. */ 566 567static unsigned long 568insert_bat (unsigned long insn, 569 long value ATTRIBUTE_UNUSED, 570 int dialect ATTRIBUTE_UNUSED, 571 const char **errmsg ATTRIBUTE_UNUSED) 572{ 573 return insn | (((insn >> 21) & 0x1f) << 16); 574} 575 576static long 577extract_bat (unsigned long insn, 578 int dialect ATTRIBUTE_UNUSED, 579 int *invalid) 580{ 581 if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f)) 582 *invalid = 1; 583 return 0; 584} 585 586/* The BB field in an XL form instruction when it must be the same as 587 the BA field in the same instruction. This operand is marked FAKE. 588 The insertion function just copies the BA field into the BB field, 589 and the extraction function just checks that the fields are the 590 same. */ 591 592static unsigned long 593insert_bba (unsigned long insn, 594 long value ATTRIBUTE_UNUSED, 595 int dialect ATTRIBUTE_UNUSED, 596 const char **errmsg ATTRIBUTE_UNUSED) 597{ 598 return insn | (((insn >> 16) & 0x1f) << 11); 599} 600 601static long 602extract_bba (unsigned long insn, 603 int dialect ATTRIBUTE_UNUSED, 604 int *invalid) 605{ 606 if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f)) 607 *invalid = 1; 608 return 0; 609} 610 611/* The BD field in a B form instruction. The lower two bits are 612 forced to zero. */ 613 614static unsigned long 615insert_bd (unsigned long insn, 616 long value, 617 int dialect ATTRIBUTE_UNUSED, 618 const char **errmsg ATTRIBUTE_UNUSED) 619{ 620 return insn | (value & 0xfffc); 621} 622 623static long 624extract_bd (unsigned long insn, 625 int dialect ATTRIBUTE_UNUSED, 626 int *invalid ATTRIBUTE_UNUSED) 627{ 628 return ((insn & 0xfffc) ^ 0x8000) - 0x8000; 629} 630 631/* The BD field in a B form instruction when the - modifier is used. 632 This modifier means that the branch is not expected to be taken. 633 For chips built to versions of the architecture prior to version 2 634 (ie. not Power4 compatible), we set the y bit of the BO field to 1 635 if the offset is negative. When extracting, we require that the y 636 bit be 1 and that the offset be positive, since if the y bit is 0 637 we just want to print the normal form of the instruction. 638 Power4 compatible targets use two bits, "a", and "t", instead of 639 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable, 640 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001 641 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000 642 for branch on CTR. We only handle the taken/not-taken hint here. */ 643 644static unsigned long 645insert_bdm (unsigned long insn, 646 long value, 647 int dialect, 648 const char **errmsg ATTRIBUTE_UNUSED) 649{ 650 if ((dialect & PPC_OPCODE_POWER4) == 0) 651 { 652 if ((value & 0x8000) != 0) 653 insn |= 1 << 21; 654 } 655 else 656 { 657 if ((insn & (0x14 << 21)) == (0x04 << 21)) 658 insn |= 0x02 << 21; 659 else if ((insn & (0x14 << 21)) == (0x10 << 21)) 660 insn |= 0x08 << 21; 661 } 662 return insn | (value & 0xfffc); 663} 664 665static long 666extract_bdm (unsigned long insn, 667 int dialect, 668 int *invalid) 669{ 670 if ((dialect & PPC_OPCODE_POWER4) == 0) 671 { 672 if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0)) 673 *invalid = 1; 674 } 675 else 676 { 677 if ((insn & (0x17 << 21)) != (0x06 << 21) 678 && (insn & (0x1d << 21)) != (0x18 << 21)) 679 *invalid = 1; 680 } 681 682 return ((insn & 0xfffc) ^ 0x8000) - 0x8000; 683} 684 685/* The BD field in a B form instruction when the + modifier is used. 686 This is like BDM, above, except that the branch is expected to be 687 taken. */ 688 689static unsigned long 690insert_bdp (unsigned long insn, 691 long value, 692 int dialect, 693 const char **errmsg ATTRIBUTE_UNUSED) 694{ 695 if ((dialect & PPC_OPCODE_POWER4) == 0) 696 { 697 if ((value & 0x8000) == 0) 698 insn |= 1 << 21; 699 } 700 else 701 { 702 if ((insn & (0x14 << 21)) == (0x04 << 21)) 703 insn |= 0x03 << 21; 704 else if ((insn & (0x14 << 21)) == (0x10 << 21)) 705 insn |= 0x09 << 21; 706 } 707 return insn | (value & 0xfffc); 708} 709 710static long 711extract_bdp (unsigned long insn, 712 int dialect, 713 int *invalid) 714{ 715 if ((dialect & PPC_OPCODE_POWER4) == 0) 716 { 717 if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0)) 718 *invalid = 1; 719 } 720 else 721 { 722 if ((insn & (0x17 << 21)) != (0x07 << 21) 723 && (insn & (0x1d << 21)) != (0x19 << 21)) 724 *invalid = 1; 725 } 726 727 return ((insn & 0xfffc) ^ 0x8000) - 0x8000; 728} 729 730/* Check for legal values of a BO field. */ 731 732static int 733valid_bo (long value, int dialect) 734{ 735 if ((dialect & PPC_OPCODE_POWER4) == 0) 736 { 737 /* Certain encodings have bits that are required to be zero. 738 These are (z must be zero, y may be anything): 739 001zy 740 011zy 741 1z00y 742 1z01y 743 1z1zz 744 */ 745 switch (value & 0x14) 746 { 747 default: 748 case 0: 749 return 1; 750 case 0x4: 751 return (value & 0x2) == 0; 752 case 0x10: 753 return (value & 0x8) == 0; 754 case 0x14: 755 return value == 0x14; 756 } 757 } 758 else 759 { 760 /* Certain encodings have bits that are required to be zero. 761 These are (z must be zero, a & t may be anything): 762 0000z 763 0001z 764 0100z 765 0101z 766 001at 767 011at 768 1a00t 769 1a01t 770 1z1zz 771 */ 772 if ((value & 0x14) == 0) 773 return (value & 0x1) == 0; 774 else if ((value & 0x14) == 0x14) 775 return value == 0x14; 776 else 777 return 1; 778 } 779} 780 781/* The BO field in a B form instruction. Warn about attempts to set 782 the field to an illegal value. */ 783 784static unsigned long 785insert_bo (unsigned long insn, 786 long value, 787 int dialect, 788 const char **errmsg) 789{ 790 if (!valid_bo (value, dialect)) 791 *errmsg = _("invalid conditional option"); 792 return insn | ((value & 0x1f) << 21); 793} 794 795static long 796extract_bo (unsigned long insn, 797 int dialect, 798 int *invalid) 799{ 800 long value; 801 802 value = (insn >> 21) & 0x1f; 803 if (!valid_bo (value, dialect)) 804 *invalid = 1; 805 return value; 806} 807 808/* The BO field in a B form instruction when the + or - modifier is 809 used. This is like the BO field, but it must be even. When 810 extracting it, we force it to be even. */ 811 812static unsigned long 813insert_boe (unsigned long insn, 814 long value, 815 int dialect, 816 const char **errmsg) 817{ 818 if (!valid_bo (value, dialect)) 819 *errmsg = _("invalid conditional option"); 820 else if ((value & 1) != 0) 821 *errmsg = _("attempt to set y bit when using + or - modifier"); 822 823 return insn | ((value & 0x1f) << 21); 824} 825 826static long 827extract_boe (unsigned long insn, 828 int dialect, 829 int *invalid) 830{ 831 long value; 832 833 value = (insn >> 21) & 0x1f; 834 if (!valid_bo (value, dialect)) 835 *invalid = 1; 836 return value & 0x1e; 837} 838 839/* The DQ field in a DQ form instruction. This is like D, but the 840 lower four bits are forced to zero. */ 841 842static unsigned long 843insert_dq (unsigned long insn, 844 long value, 845 int dialect ATTRIBUTE_UNUSED, 846 const char **errmsg) 847{ 848 if ((value & 0xf) != 0) 849 *errmsg = _("offset not a multiple of 16"); 850 return insn | (value & 0xfff0); 851} 852 853static long 854extract_dq (unsigned long insn, 855 int dialect ATTRIBUTE_UNUSED, 856 int *invalid ATTRIBUTE_UNUSED) 857{ 858 return ((insn & 0xfff0) ^ 0x8000) - 0x8000; 859} 860 861static unsigned long 862insert_ev2 (unsigned long insn, 863 long value, 864 int dialect ATTRIBUTE_UNUSED, 865 const char **errmsg) 866{ 867 if ((value & 1) != 0) 868 *errmsg = _("offset not a multiple of 2"); 869 if ((value > 62) != 0) 870 *errmsg = _("offset greater than 62"); 871 return insn | ((value & 0x3e) << 10); 872} 873 874static long 875extract_ev2 (unsigned long insn, 876 int dialect ATTRIBUTE_UNUSED, 877 int *invalid ATTRIBUTE_UNUSED) 878{ 879 return (insn >> 10) & 0x3e; 880} 881 882static unsigned long 883insert_ev4 (unsigned long insn, 884 long value, 885 int dialect ATTRIBUTE_UNUSED, 886 const char **errmsg) 887{ 888 if ((value & 3) != 0) 889 *errmsg = _("offset not a multiple of 4"); 890 if ((value > 124) != 0) 891 *errmsg = _("offset greater than 124"); 892 return insn | ((value & 0x7c) << 9); 893} 894 895static long 896extract_ev4 (unsigned long insn, 897 int dialect ATTRIBUTE_UNUSED, 898 int *invalid ATTRIBUTE_UNUSED) 899{ 900 return (insn >> 9) & 0x7c; 901} 902 903static unsigned long 904insert_ev8 (unsigned long insn, 905 long value, 906 int dialect ATTRIBUTE_UNUSED, 907 const char **errmsg) 908{ 909 if ((value & 7) != 0) 910 *errmsg = _("offset not a multiple of 8"); 911 if ((value > 248) != 0) 912 *errmsg = _("offset greater than 248"); 913 return insn | ((value & 0xf8) << 8); 914} 915 916static long 917extract_ev8 (unsigned long insn, 918 int dialect ATTRIBUTE_UNUSED, 919 int *invalid ATTRIBUTE_UNUSED) 920{ 921 return (insn >> 8) & 0xf8; 922} 923 924/* The DS field in a DS form instruction. This is like D, but the 925 lower two bits are forced to zero. */ 926 927static unsigned long 928insert_ds (unsigned long insn, 929 long value, 930 int dialect ATTRIBUTE_UNUSED, 931 const char **errmsg) 932{ 933 if ((value & 3) != 0) 934 *errmsg = _("offset not a multiple of 4"); 935 return insn | (value & 0xfffc); 936} 937 938static long 939extract_ds (unsigned long insn, 940 int dialect ATTRIBUTE_UNUSED, 941 int *invalid ATTRIBUTE_UNUSED) 942{ 943 return ((insn & 0xfffc) ^ 0x8000) - 0x8000; 944} 945 946/* The DE field in a DE form instruction. */ 947 948static unsigned long 949insert_de (unsigned long insn, 950 long value, 951 int dialect ATTRIBUTE_UNUSED, 952 const char **errmsg) 953{ 954 if (value > 2047 || value < -2048) 955 *errmsg = _("offset not between -2048 and 2047"); 956 return insn | ((value << 4) & 0xfff0); 957} 958 959static long 960extract_de (unsigned long insn, 961 int dialect ATTRIBUTE_UNUSED, 962 int *invalid ATTRIBUTE_UNUSED) 963{ 964 return (insn & 0xfff0) >> 4; 965} 966 967/* The DES field in a DES form instruction. */ 968 969static unsigned long 970insert_des (unsigned long insn, 971 long value, 972 int dialect ATTRIBUTE_UNUSED, 973 const char **errmsg) 974{ 975 if (value > 8191 || value < -8192) 976 *errmsg = _("offset not between -8192 and 8191"); 977 else if ((value & 3) != 0) 978 *errmsg = _("offset not a multiple of 4"); 979 return insn | ((value << 2) & 0xfff0); 980} 981 982static long 983extract_des (unsigned long insn, 984 int dialect ATTRIBUTE_UNUSED, 985 int *invalid ATTRIBUTE_UNUSED) 986{ 987 return (((insn >> 2) & 0x3ffc) ^ 0x2000) - 0x2000; 988} 989 990/* FXM mask in mfcr and mtcrf instructions. */ 991 992static unsigned long 993insert_fxm (unsigned long insn, 994 long value, 995 int dialect, 996 const char **errmsg) 997{ 998 /* If the optional field on mfcr is missing that means we want to use 999 the old form of the instruction that moves the whole cr. In that 1000 case we'll have VALUE zero. There doesn't seem to be a way to 1001 distinguish this from the case where someone writes mfcr %r3,0. */ 1002 if (value == 0) 1003 ; 1004 1005 /* If only one bit of the FXM field is set, we can use the new form 1006 of the instruction, which is faster. Unlike the Power4 branch hint 1007 encoding, this is not backward compatible. */ 1008 else if ((dialect & PPC_OPCODE_POWER4) != 0 && (value & -value) == value) 1009 insn |= 1 << 20; 1010 1011 /* Any other value on mfcr is an error. */ 1012 else if ((insn & (0x3ff << 1)) == 19 << 1) 1013 { 1014 *errmsg = _("ignoring invalid mfcr mask"); 1015 value = 0; 1016 } 1017 1018 return insn | ((value & 0xff) << 12); 1019} 1020 1021static long 1022extract_fxm (unsigned long insn, 1023 int dialect, 1024 int *invalid) 1025{ 1026 long mask = (insn >> 12) & 0xff; 1027 1028 /* Is this a Power4 insn? */ 1029 if ((insn & (1 << 20)) != 0) 1030 { 1031 if ((dialect & PPC_OPCODE_POWER4) == 0) 1032 *invalid = 1; 1033 else 1034 { 1035 /* Exactly one bit of MASK should be set. */ 1036 if (mask == 0 || (mask & -mask) != mask) 1037 *invalid = 1; 1038 } 1039 } 1040 1041 /* Check that non-power4 form of mfcr has a zero MASK. */ 1042 else if ((insn & (0x3ff << 1)) == 19 << 1) 1043 { 1044 if (mask != 0) 1045 *invalid = 1; 1046 } 1047 1048 return mask; 1049} 1050 1051/* The LI field in an I form instruction. The lower two bits are 1052 forced to zero. */ 1053 1054static unsigned long 1055insert_li (unsigned long insn, 1056 long value, 1057 int dialect ATTRIBUTE_UNUSED, 1058 const char **errmsg) 1059{ 1060 if ((value & 3) != 0) 1061 *errmsg = _("ignoring least significant bits in branch offset"); 1062 return insn | (value & 0x3fffffc); 1063} 1064 1065static long 1066extract_li (unsigned long insn, 1067 int dialect ATTRIBUTE_UNUSED, 1068 int *invalid ATTRIBUTE_UNUSED) 1069{ 1070 return ((insn & 0x3fffffc) ^ 0x2000000) - 0x2000000; 1071} 1072 1073/* The MB and ME fields in an M form instruction expressed as a single 1074 operand which is itself a bitmask. The extraction function always 1075 marks it as invalid, since we never want to recognize an 1076 instruction which uses a field of this type. */ 1077 1078static unsigned long 1079insert_mbe (unsigned long insn, 1080 long value, 1081 int dialect ATTRIBUTE_UNUSED, 1082 const char **errmsg) 1083{ 1084 unsigned long uval, mask; 1085 int mb, me, mx, count, last; 1086 1087 uval = value; 1088 1089 if (uval == 0) 1090 { 1091 *errmsg = _("illegal bitmask"); 1092 return insn; 1093 } 1094 1095 mb = 0; 1096 me = 32; 1097 if ((uval & 1) != 0) 1098 last = 1; 1099 else 1100 last = 0; 1101 count = 0; 1102 1103 /* mb: location of last 0->1 transition */ 1104 /* me: location of last 1->0 transition */ 1105 /* count: # transitions */ 1106 1107 for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1) 1108 { 1109 if ((uval & mask) && !last) 1110 { 1111 ++count; 1112 mb = mx; 1113 last = 1; 1114 } 1115 else if (!(uval & mask) && last) 1116 { 1117 ++count; 1118 me = mx; 1119 last = 0; 1120 } 1121 } 1122 if (me == 0) 1123 me = 32; 1124 1125 if (count != 2 && (count != 0 || ! last)) 1126 *errmsg = _("illegal bitmask"); 1127 1128 return insn | (mb << 6) | ((me - 1) << 1); 1129} 1130 1131static long 1132extract_mbe (unsigned long insn, 1133 int dialect ATTRIBUTE_UNUSED, 1134 int *invalid) 1135{ 1136 long ret; 1137 int mb, me; 1138 int i; 1139 1140 *invalid = 1; 1141 1142 mb = (insn >> 6) & 0x1f; 1143 me = (insn >> 1) & 0x1f; 1144 if (mb < me + 1) 1145 { 1146 ret = 0; 1147 for (i = mb; i <= me; i++) 1148 ret |= 1L << (31 - i); 1149 } 1150 else if (mb == me + 1) 1151 ret = ~0; 1152 else /* (mb > me + 1) */ 1153 { 1154 ret = ~0; 1155 for (i = me + 1; i < mb; i++) 1156 ret &= ~(1L << (31 - i)); 1157 } 1158 return ret; 1159} 1160 1161/* The MB or ME field in an MD or MDS form instruction. The high bit 1162 is wrapped to the low end. */ 1163 1164static unsigned long 1165insert_mb6 (unsigned long insn, 1166 long value, 1167 int dialect ATTRIBUTE_UNUSED, 1168 const char **errmsg ATTRIBUTE_UNUSED) 1169{ 1170 return insn | ((value & 0x1f) << 6) | (value & 0x20); 1171} 1172 1173static long 1174extract_mb6 (unsigned long insn, 1175 int dialect ATTRIBUTE_UNUSED, 1176 int *invalid ATTRIBUTE_UNUSED) 1177{ 1178 return ((insn >> 6) & 0x1f) | (insn & 0x20); 1179} 1180 1181/* The NB field in an X form instruction. The value 32 is stored as 1182 0. */ 1183 1184static unsigned long 1185insert_nb (unsigned long insn, 1186 long value, 1187 int dialect ATTRIBUTE_UNUSED, 1188 const char **errmsg) 1189{ 1190 if (value < 0 || value > 32) 1191 *errmsg = _("value out of range"); 1192 if (value == 32) 1193 value = 0; 1194 return insn | ((value & 0x1f) << 11); 1195} 1196 1197static long 1198extract_nb (unsigned long insn, 1199 int dialect ATTRIBUTE_UNUSED, 1200 int *invalid ATTRIBUTE_UNUSED) 1201{ 1202 long ret; 1203 1204 ret = (insn >> 11) & 0x1f; 1205 if (ret == 0) 1206 ret = 32; 1207 return ret; 1208} 1209 1210/* The NSI field in a D form instruction. This is the same as the SI 1211 field, only negated. The extraction function always marks it as 1212 invalid, since we never want to recognize an instruction which uses 1213 a field of this type. */ 1214 1215static unsigned long 1216insert_nsi (unsigned long insn, 1217 long value, 1218 int dialect ATTRIBUTE_UNUSED, 1219 const char **errmsg ATTRIBUTE_UNUSED) 1220{ 1221 return insn | (-value & 0xffff); 1222} 1223 1224static long 1225extract_nsi (unsigned long insn, 1226 int dialect ATTRIBUTE_UNUSED, 1227 int *invalid) 1228{ 1229 *invalid = 1; 1230 return -(((insn & 0xffff) ^ 0x8000) - 0x8000); 1231} 1232 1233/* The RA field in a D or X form instruction which is an updating 1234 load, which means that the RA field may not be zero and may not 1235 equal the RT field. */ 1236 1237static unsigned long 1238insert_ral (unsigned long insn, 1239 long value, 1240 int dialect ATTRIBUTE_UNUSED, 1241 const char **errmsg) 1242{ 1243 if (value == 0 1244 || (unsigned long) value == ((insn >> 21) & 0x1f)) 1245 *errmsg = "invalid register operand when updating"; 1246 return insn | ((value & 0x1f) << 16); 1247} 1248 1249/* The RA field in an lmw instruction, which has special value 1250 restrictions. */ 1251 1252static unsigned long 1253insert_ram (unsigned long insn, 1254 long value, 1255 int dialect ATTRIBUTE_UNUSED, 1256 const char **errmsg) 1257{ 1258 if ((unsigned long) value >= ((insn >> 21) & 0x1f)) 1259 *errmsg = _("index register in load range"); 1260 return insn | ((value & 0x1f) << 16); 1261} 1262 1263/* The RA field in the DQ form lq instruction, which has special 1264 value restrictions. */ 1265 1266static unsigned long 1267insert_raq (unsigned long insn, 1268 long value, 1269 int dialect ATTRIBUTE_UNUSED, 1270 const char **errmsg) 1271{ 1272 long rtvalue = (insn & RT_MASK) >> 21; 1273 1274 if (value == rtvalue) 1275 *errmsg = _("source and target register operands must be different"); 1276 return insn | ((value & 0x1f) << 16); 1277} 1278 1279/* The RA field in a D or X form instruction which is an updating 1280 store or an updating floating point load, which means that the RA 1281 field may not be zero. */ 1282 1283static unsigned long 1284insert_ras (unsigned long insn, 1285 long value, 1286 int dialect ATTRIBUTE_UNUSED, 1287 const char **errmsg) 1288{ 1289 if (value == 0) 1290 *errmsg = _("invalid register operand when updating"); 1291 return insn | ((value & 0x1f) << 16); 1292} 1293 1294/* The RB field in an X form instruction when it must be the same as 1295 the RS field in the instruction. This is used for extended 1296 mnemonics like mr. This operand is marked FAKE. The insertion 1297 function just copies the BT field into the BA field, and the 1298 extraction function just checks that the fields are the same. */ 1299 1300static unsigned long 1301insert_rbs (unsigned long insn, 1302 long value ATTRIBUTE_UNUSED, 1303 int dialect ATTRIBUTE_UNUSED, 1304 const char **errmsg ATTRIBUTE_UNUSED) 1305{ 1306 return insn | (((insn >> 21) & 0x1f) << 11); 1307} 1308 1309static long 1310extract_rbs (unsigned long insn, 1311 int dialect ATTRIBUTE_UNUSED, 1312 int *invalid) 1313{ 1314 if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f)) 1315 *invalid = 1; 1316 return 0; 1317} 1318 1319/* The RT field of the DQ form lq instruction, which has special 1320 value restrictions. */ 1321 1322static unsigned long 1323insert_rtq (unsigned long insn, 1324 long value, 1325 int dialect ATTRIBUTE_UNUSED, 1326 const char **errmsg) 1327{ 1328 if ((value & 1) != 0) 1329 *errmsg = _("target register operand must be even"); 1330 return insn | ((value & 0x1f) << 21); 1331} 1332 1333/* The RS field of the DS form stq instruction, which has special 1334 value restrictions. */ 1335 1336static unsigned long 1337insert_rsq (unsigned long insn, 1338 long value ATTRIBUTE_UNUSED, 1339 int dialect ATTRIBUTE_UNUSED, 1340 const char **errmsg) 1341{ 1342 if ((value & 1) != 0) 1343 *errmsg = _("source register operand must be even"); 1344 return insn | ((value & 0x1f) << 21); 1345} 1346 1347/* The SH field in an MD form instruction. This is split. */ 1348 1349static unsigned long 1350insert_sh6 (unsigned long insn, 1351 long value, 1352 int dialect ATTRIBUTE_UNUSED, 1353 const char **errmsg ATTRIBUTE_UNUSED) 1354{ 1355 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4); 1356} 1357 1358static long 1359extract_sh6 (unsigned long insn, 1360 int dialect ATTRIBUTE_UNUSED, 1361 int *invalid ATTRIBUTE_UNUSED) 1362{ 1363 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20); 1364} 1365 1366/* The SPR field in an XFX form instruction. This is flipped--the 1367 lower 5 bits are stored in the upper 5 and vice- versa. */ 1368 1369static unsigned long 1370insert_spr (unsigned long insn, 1371 long value, 1372 int dialect ATTRIBUTE_UNUSED, 1373 const char **errmsg ATTRIBUTE_UNUSED) 1374{ 1375 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6); 1376} 1377 1378static long 1379extract_spr (unsigned long insn, 1380 int dialect ATTRIBUTE_UNUSED, 1381 int *invalid ATTRIBUTE_UNUSED) 1382{ 1383 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); 1384} 1385 1386/* The TBR field in an XFX instruction. This is just like SPR, but it 1387 is optional. When TBR is omitted, it must be inserted as 268 (the 1388 magic number of the TB register). These functions treat 0 1389 (indicating an omitted optional operand) as 268. This means that 1390 ``mftb 4,0'' is not handled correctly. This does not matter very 1391 much, since the architecture manual does not define mftb as 1392 accepting any values other than 268 or 269. */ 1393 1394#define TB (268) 1395 1396static unsigned long 1397insert_tbr (unsigned long insn, 1398 long value, 1399 int dialect ATTRIBUTE_UNUSED, 1400 const char **errmsg ATTRIBUTE_UNUSED) 1401{ 1402 if (value == 0) 1403 value = TB; 1404 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6); 1405} 1406 1407static long 1408extract_tbr (unsigned long insn, 1409 int dialect ATTRIBUTE_UNUSED, 1410 int *invalid ATTRIBUTE_UNUSED) 1411{ 1412 long ret; 1413 1414 ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); 1415 if (ret == TB) 1416 ret = 0; 1417 return ret; 1418} 1419 1420/* Macros used to form opcodes. */ 1421 1422/* The main opcode. */ 1423#define OP(x) ((((unsigned long)(x)) & 0x3f) << 26) 1424#define OP_MASK OP (0x3f) 1425 1426/* The main opcode combined with a trap code in the TO field of a D 1427 form instruction. Used for extended mnemonics for the trap 1428 instructions. */ 1429#define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21)) 1430#define OPTO_MASK (OP_MASK | TO_MASK) 1431 1432/* The main opcode combined with a comparison size bit in the L field 1433 of a D form or X form instruction. Used for extended mnemonics for 1434 the comparison instructions. */ 1435#define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21)) 1436#define OPL_MASK OPL (0x3f,1) 1437 1438/* An A form instruction. */ 1439#define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1)) 1440#define A_MASK A (0x3f, 0x1f, 1) 1441 1442/* An A_MASK with the FRB field fixed. */ 1443#define AFRB_MASK (A_MASK | FRB_MASK) 1444 1445/* An A_MASK with the FRC field fixed. */ 1446#define AFRC_MASK (A_MASK | FRC_MASK) 1447 1448/* An A_MASK with the FRA and FRC fields fixed. */ 1449#define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK) 1450 1451/* A B form instruction. */ 1452#define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1)) 1453#define B_MASK B (0x3f, 1, 1) 1454 1455/* A B form instruction setting the BO field. */ 1456#define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21)) 1457#define BBO_MASK BBO (0x3f, 0x1f, 1, 1) 1458 1459/* A BBO_MASK with the y bit of the BO field removed. This permits 1460 matching a conditional branch regardless of the setting of the y 1461 bit. Similarly for the 'at' bits used for power4 branch hints. */ 1462#define Y_MASK (((unsigned long) 1) << 21) 1463#define AT1_MASK (((unsigned long) 3) << 21) 1464#define AT2_MASK (((unsigned long) 9) << 21) 1465#define BBOY_MASK (BBO_MASK &~ Y_MASK) 1466#define BBOAT_MASK (BBO_MASK &~ AT1_MASK) 1467 1468/* A B form instruction setting the BO field and the condition bits of 1469 the BI field. */ 1470#define BBOCB(op, bo, cb, aa, lk) \ 1471 (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16)) 1472#define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1) 1473 1474/* A BBOCB_MASK with the y bit of the BO field removed. */ 1475#define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK) 1476#define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK) 1477#define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK) 1478 1479/* A BBOYCB_MASK in which the BI field is fixed. */ 1480#define BBOYBI_MASK (BBOYCB_MASK | BI_MASK) 1481#define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK) 1482 1483/* An Context form instruction. */ 1484#define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7)) 1485#define CTX_MASK CTX(0x3f, 0x7) 1486 1487/* An User Context form instruction. */ 1488#define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f)) 1489#define UCTX_MASK UCTX(0x3f, 0x1f) 1490 1491/* The main opcode mask with the RA field clear. */ 1492#define DRA_MASK (OP_MASK | RA_MASK) 1493 1494/* A DS form instruction. */ 1495#define DSO(op, xop) (OP (op) | ((xop) & 0x3)) 1496#define DS_MASK DSO (0x3f, 3) 1497 1498/* A DE form instruction. */ 1499#define DEO(op, xop) (OP (op) | ((xop) & 0xf)) 1500#define DE_MASK DEO (0x3e, 0xf) 1501 1502/* An EVSEL form instruction. */ 1503#define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3) 1504#define EVSEL_MASK EVSEL(0x3f, 0xff) 1505 1506/* An M form instruction. */ 1507#define M(op, rc) (OP (op) | ((rc) & 1)) 1508#define M_MASK M (0x3f, 1) 1509 1510/* An M form instruction with the ME field specified. */ 1511#define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1)) 1512 1513/* An M_MASK with the MB and ME fields fixed. */ 1514#define MMBME_MASK (M_MASK | MB_MASK | ME_MASK) 1515 1516/* An M_MASK with the SH and ME fields fixed. */ 1517#define MSHME_MASK (M_MASK | SH_MASK | ME_MASK) 1518 1519/* An MD form instruction. */ 1520#define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1)) 1521#define MD_MASK MD (0x3f, 0x7, 1) 1522 1523/* An MD_MASK with the MB field fixed. */ 1524#define MDMB_MASK (MD_MASK | MB6_MASK) 1525 1526/* An MD_MASK with the SH field fixed. */ 1527#define MDSH_MASK (MD_MASK | SH6_MASK) 1528 1529/* An MDS form instruction. */ 1530#define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1)) 1531#define MDS_MASK MDS (0x3f, 0xf, 1) 1532 1533/* An MDS_MASK with the MB field fixed. */ 1534#define MDSMB_MASK (MDS_MASK | MB6_MASK) 1535 1536/* An SC form instruction. */ 1537#define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1)) 1538#define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1) 1539 1540/* An VX form instruction. */ 1541#define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff)) 1542 1543/* The mask for an VX form instruction. */ 1544#define VX_MASK VX(0x3f, 0x7ff) 1545 1546/* An VA form instruction. */ 1547#define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f)) 1548 1549/* The mask for an VA form instruction. */ 1550#define VXA_MASK VXA(0x3f, 0x3f) 1551 1552/* An VXR form instruction. */ 1553#define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff)) 1554 1555/* The mask for a VXR form instruction. */ 1556#define VXR_MASK VXR(0x3f, 0x3ff, 1) 1557 1558/* An X form instruction. */ 1559#define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1)) 1560 1561/* An X form instruction with the RC bit specified. */ 1562#define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1)) 1563 1564/* The mask for an X form instruction. */ 1565#define X_MASK XRC (0x3f, 0x3ff, 1) 1566 1567/* An X_MASK with the RA field fixed. */ 1568#define XRA_MASK (X_MASK | RA_MASK) 1569 1570/* An X_MASK with the RB field fixed. */ 1571#define XRB_MASK (X_MASK | RB_MASK) 1572 1573/* An X_MASK with the RT field fixed. */ 1574#define XRT_MASK (X_MASK | RT_MASK) 1575 1576/* An X_MASK with the RA and RB fields fixed. */ 1577#define XRARB_MASK (X_MASK | RA_MASK | RB_MASK) 1578 1579/* An XRARB_MASK, but with the L bit clear. */ 1580#define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16)) 1581 1582/* An X_MASK with the RT and RA fields fixed. */ 1583#define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK) 1584 1585/* An XRTRA_MASK, but with L bit clear. */ 1586#define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21)) 1587 1588/* An X form instruction with the L bit specified. */ 1589#define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21)) 1590 1591/* An X form comparison instruction. */ 1592#define XCMPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21)) 1593 1594/* The mask for an X form comparison instruction. */ 1595#define XCMP_MASK (X_MASK | (((unsigned long)1) << 22)) 1596 1597/* The mask for an X form comparison instruction with the L field 1598 fixed. */ 1599#define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21)) 1600 1601/* An X form trap instruction with the TO field specified. */ 1602#define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21)) 1603#define XTO_MASK (X_MASK | TO_MASK) 1604 1605/* An X form tlb instruction with the SH field specified. */ 1606#define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11)) 1607#define XTLB_MASK (X_MASK | SH_MASK) 1608 1609/* An X form sync instruction. */ 1610#define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21)) 1611 1612/* An X form sync instruction with everything filled in except the LS field. */ 1613#define XSYNC_MASK (0xff9fffff) 1614 1615/* An X form AltiVec dss instruction. */ 1616#define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25)) 1617#define XDSS_MASK XDSS(0x3f, 0x3ff, 1) 1618 1619/* An XFL form instruction. */ 1620#define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1)) 1621#define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16)) 1622 1623/* An X form isel instruction. */ 1624#define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1)) 1625#define XISEL_MASK XISEL(0x3f, 0x1f) 1626 1627/* An XL form instruction with the LK field set to 0. */ 1628#define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1)) 1629 1630/* An XL form instruction which uses the LK field. */ 1631#define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1)) 1632 1633/* The mask for an XL form instruction. */ 1634#define XL_MASK XLLK (0x3f, 0x3ff, 1) 1635 1636/* An XL form instruction which explicitly sets the BO field. */ 1637#define XLO(op, bo, xop, lk) \ 1638 (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21)) 1639#define XLO_MASK (XL_MASK | BO_MASK) 1640 1641/* An XL form instruction which explicitly sets the y bit of the BO 1642 field. */ 1643#define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21)) 1644#define XLYLK_MASK (XL_MASK | Y_MASK) 1645 1646/* An XL form instruction which sets the BO field and the condition 1647 bits of the BI field. */ 1648#define XLOCB(op, bo, cb, xop, lk) \ 1649 (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16)) 1650#define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1) 1651 1652/* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */ 1653#define XLBB_MASK (XL_MASK | BB_MASK) 1654#define XLYBB_MASK (XLYLK_MASK | BB_MASK) 1655#define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK) 1656 1657/* An XL_MASK with the BO and BB fields fixed. */ 1658#define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK) 1659 1660/* An XL_MASK with the BO, BI and BB fields fixed. */ 1661#define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK) 1662 1663/* An XO form instruction. */ 1664#define XO(op, xop, oe, rc) \ 1665 (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1)) 1666#define XO_MASK XO (0x3f, 0x1ff, 1, 1) 1667 1668/* An XO_MASK with the RB field fixed. */ 1669#define XORB_MASK (XO_MASK | RB_MASK) 1670 1671/* An XS form instruction. */ 1672#define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1)) 1673#define XS_MASK XS (0x3f, 0x1ff, 1) 1674 1675/* A mask for the FXM version of an XFX form instruction. */ 1676#define XFXFXM_MASK (X_MASK | (1 << 11)) 1677 1678/* An XFX form instruction with the FXM field filled in. */ 1679#define XFXM(op, xop, fxm) \ 1680 (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12)) 1681 1682/* An XFX form instruction with the SPR field filled in. */ 1683#define XSPR(op, xop, spr) \ 1684 (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6)) 1685#define XSPR_MASK (X_MASK | SPR_MASK) 1686 1687/* An XFX form instruction with the SPR field filled in except for the 1688 SPRBAT field. */ 1689#define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK) 1690 1691/* An XFX form instruction with the SPR field filled in except for the 1692 SPRG field. */ 1693#define XSPRG_MASK (XSPR_MASK &~ SPRG_MASK) 1694 1695/* An X form instruction with everything filled in except the E field. */ 1696#define XE_MASK (0xffff7fff) 1697 1698/* An X form user context instruction. */ 1699#define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f)) 1700#define XUC_MASK XUC(0x3f, 0x1f) 1701 1702/* The BO encodings used in extended conditional branch mnemonics. */ 1703#define BODNZF (0x0) 1704#define BODNZFP (0x1) 1705#define BODZF (0x2) 1706#define BODZFP (0x3) 1707#define BODNZT (0x8) 1708#define BODNZTP (0x9) 1709#define BODZT (0xa) 1710#define BODZTP (0xb) 1711 1712#define BOF (0x4) 1713#define BOFP (0x5) 1714#define BOFM4 (0x6) 1715#define BOFP4 (0x7) 1716#define BOT (0xc) 1717#define BOTP (0xd) 1718#define BOTM4 (0xe) 1719#define BOTP4 (0xf) 1720 1721#define BODNZ (0x10) 1722#define BODNZP (0x11) 1723#define BODZ (0x12) 1724#define BODZP (0x13) 1725#define BODNZM4 (0x18) 1726#define BODNZP4 (0x19) 1727#define BODZM4 (0x1a) 1728#define BODZP4 (0x1b) 1729 1730#define BOU (0x14) 1731 1732/* The BI condition bit encodings used in extended conditional branch 1733 mnemonics. */ 1734#define CBLT (0) 1735#define CBGT (1) 1736#define CBEQ (2) 1737#define CBSO (3) 1738 1739/* The TO encodings used in extended trap mnemonics. */ 1740#define TOLGT (0x1) 1741#define TOLLT (0x2) 1742#define TOEQ (0x4) 1743#define TOLGE (0x5) 1744#define TOLNL (0x5) 1745#define TOLLE (0x6) 1746#define TOLNG (0x6) 1747#define TOGT (0x8) 1748#define TOGE (0xc) 1749#define TONL (0xc) 1750#define TOLT (0x10) 1751#define TOLE (0x14) 1752#define TONG (0x14) 1753#define TONE (0x18) 1754#define TOU (0x1f) 1755 1756/* Smaller names for the flags so each entry in the opcodes table will 1757 fit on a single line. */ 1758#undef PPC 1759#define PPC PPC_OPCODE_PPC 1760#define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON 1761#define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM 1762#define POWER4 PPC_OPCODE_POWER4 1763#define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC 1764#define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC 1765#define PPC403 PPC_OPCODE_403 1766#define PPC405 PPC403 1767#define PPC440 PPC_OPCODE_440 1768#define PPC750 PPC 1769#define PPC860 PPC 1770#define PPCVEC PPC_OPCODE_ALTIVEC 1771#define POWER PPC_OPCODE_POWER 1772#define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2 1773#define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 1774#define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_32 1775#define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON 1776#define COM32 PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_32 1777#define M601 PPC_OPCODE_POWER | PPC_OPCODE_601 1778#define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON 1779#define MFDEC1 PPC_OPCODE_POWER 1780#define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE 1781#define BOOKE PPC_OPCODE_BOOKE 1782#define BOOKE64 PPC_OPCODE_BOOKE64 1783#define CLASSIC PPC_OPCODE_CLASSIC 1784#define PPCSPE PPC_OPCODE_SPE 1785#define PPCISEL PPC_OPCODE_ISEL 1786#define PPCEFS PPC_OPCODE_EFS 1787#define PPCBRLK PPC_OPCODE_BRLOCK 1788#define PPCPMR PPC_OPCODE_PMR 1789#define PPCCHLK PPC_OPCODE_CACHELCK 1790#define PPCCHLK64 PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64 1791#define PPCRFMCI PPC_OPCODE_RFMCI 1792 1793/* The opcode table. 1794 1795 The format of the opcode table is: 1796 1797 NAME OPCODE MASK FLAGS { OPERANDS } 1798 1799 NAME is the name of the instruction. 1800 OPCODE is the instruction opcode. 1801 MASK is the opcode mask; this is used to tell the disassembler 1802 which bits in the actual opcode must match OPCODE. 1803 FLAGS are flags indicated what processors support the instruction. 1804 OPERANDS is the list of operands. 1805 1806 The disassembler reads the table in order and prints the first 1807 instruction which matches, so this table is sorted to put more 1808 specific instructions before more general instructions. It is also 1809 sorted by major opcode. */ 1810 1811const struct powerpc_opcode powerpc_opcodes[] = { 1812{ "attn", X(0,256), X_MASK, POWER4, { 0 } }, 1813{ "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, { RA, SI } }, 1814{ "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, { RA, SI } }, 1815{ "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, { RA, SI } }, 1816{ "tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, { RA, SI } }, 1817{ "tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, { RA, SI } }, 1818{ "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, { RA, SI } }, 1819{ "tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, { RA, SI } }, 1820{ "tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, { RA, SI } }, 1821{ "tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, { RA, SI } }, 1822{ "tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, { RA, SI } }, 1823{ "tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, { RA, SI } }, 1824{ "tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, { RA, SI } }, 1825{ "tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, { RA, SI } }, 1826{ "tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, { RA, SI } }, 1827{ "tdi", OP(2), OP_MASK, PPC64, { TO, RA, SI } }, 1828 1829{ "twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, { RA, SI } }, 1830{ "tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, { RA, SI } }, 1831{ "twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, { RA, SI } }, 1832{ "tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, { RA, SI } }, 1833{ "tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, { RA, SI } }, 1834{ "teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, { RA, SI } }, 1835{ "twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, { RA, SI } }, 1836{ "tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, { RA, SI } }, 1837{ "twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, { RA, SI } }, 1838{ "tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, { RA, SI } }, 1839{ "twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, { RA, SI } }, 1840{ "tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, { RA, SI } }, 1841{ "twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, { RA, SI } }, 1842{ "tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, { RA, SI } }, 1843{ "twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, { RA, SI } }, 1844{ "tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, { RA, SI } }, 1845{ "twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, { RA, SI } }, 1846{ "tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, { RA, SI } }, 1847{ "twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, { RA, SI } }, 1848{ "tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, { RA, SI } }, 1849{ "twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, { RA, SI } }, 1850{ "tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, { RA, SI } }, 1851{ "twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, { RA, SI } }, 1852{ "tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, { RA, SI } }, 1853{ "twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, { RA, SI } }, 1854{ "tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, { RA, SI } }, 1855{ "twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, { RA, SI } }, 1856{ "tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, { RA, SI } }, 1857{ "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } }, 1858{ "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } }, 1859 1860{ "macchw", XO(4,172,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1861{ "macchw.", XO(4,172,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1862{ "macchwo", XO(4,172,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1863{ "macchwo.", XO(4,172,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1864{ "macchws", XO(4,236,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1865{ "macchws.", XO(4,236,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1866{ "macchwso", XO(4,236,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1867{ "macchwso.", XO(4,236,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1868{ "macchwsu", XO(4,204,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1869{ "macchwsu.", XO(4,204,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1870{ "macchwsuo", XO(4,204,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1871{ "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1872{ "macchwu", XO(4,140,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1873{ "macchwu.", XO(4,140,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1874{ "macchwuo", XO(4,140,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1875{ "macchwuo.", XO(4,140,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1876{ "machhw", XO(4,44,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1877{ "machhw.", XO(4,44,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1878{ "machhwo", XO(4,44,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1879{ "machhwo.", XO(4,44,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1880{ "machhws", XO(4,108,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1881{ "machhws.", XO(4,108,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1882{ "machhwso", XO(4,108,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1883{ "machhwso.", XO(4,108,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1884{ "machhwsu", XO(4,76,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1885{ "machhwsu.", XO(4,76,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1886{ "machhwsuo", XO(4,76,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1887{ "machhwsuo.", XO(4,76,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1888{ "machhwu", XO(4,12,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1889{ "machhwu.", XO(4,12,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1890{ "machhwuo", XO(4,12,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1891{ "machhwuo.", XO(4,12,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1892{ "maclhw", XO(4,428,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1893{ "maclhw.", XO(4,428,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1894{ "maclhwo", XO(4,428,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1895{ "maclhwo.", XO(4,428,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1896{ "maclhws", XO(4,492,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1897{ "maclhws.", XO(4,492,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1898{ "maclhwso", XO(4,492,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1899{ "maclhwso.", XO(4,492,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1900{ "maclhwsu", XO(4,460,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1901{ "maclhwsu.", XO(4,460,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1902{ "maclhwsuo", XO(4,460,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1903{ "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1904{ "maclhwu", XO(4,396,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1905{ "maclhwu.", XO(4,396,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1906{ "maclhwuo", XO(4,396,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1907{ "maclhwuo.", XO(4,396,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1908{ "mulchw", XRC(4,168,0), X_MASK, PPC405|PPC440, { RT, RA, RB } }, 1909{ "mulchw.", XRC(4,168,1), X_MASK, PPC405|PPC440, { RT, RA, RB } }, 1910{ "mulchwu", XRC(4,136,0), X_MASK, PPC405|PPC440, { RT, RA, RB } }, 1911{ "mulchwu.", XRC(4,136,1), X_MASK, PPC405|PPC440, { RT, RA, RB } }, 1912{ "mulhhw", XRC(4,40,0), X_MASK, PPC405|PPC440, { RT, RA, RB } }, 1913{ "mulhhw.", XRC(4,40,1), X_MASK, PPC405|PPC440, { RT, RA, RB } }, 1914{ "mulhhwu", XRC(4,8,0), X_MASK, PPC405|PPC440, { RT, RA, RB } }, 1915{ "mulhhwu.", XRC(4,8,1), X_MASK, PPC405|PPC440, { RT, RA, RB } }, 1916{ "mullhw", XRC(4,424,0), X_MASK, PPC405|PPC440, { RT, RA, RB } }, 1917{ "mullhw.", XRC(4,424,1), X_MASK, PPC405|PPC440, { RT, RA, RB } }, 1918{ "mullhwu", XRC(4,392,0), X_MASK, PPC405|PPC440, { RT, RA, RB } }, 1919{ "mullhwu.", XRC(4,392,1), X_MASK, PPC405|PPC440, { RT, RA, RB } }, 1920{ "nmacchw", XO(4,174,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1921{ "nmacchw.", XO(4,174,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1922{ "nmacchwo", XO(4,174,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1923{ "nmacchwo.", XO(4,174,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1924{ "nmacchws", XO(4,238,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1925{ "nmacchws.", XO(4,238,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1926{ "nmacchwso", XO(4,238,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1927{ "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1928{ "nmachhw", XO(4,46,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1929{ "nmachhw.", XO(4,46,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1930{ "nmachhwo", XO(4,46,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1931{ "nmachhwo.", XO(4,46,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1932{ "nmachhws", XO(4,110,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1933{ "nmachhws.", XO(4,110,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1934{ "nmachhwso", XO(4,110,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1935{ "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1936{ "nmaclhw", XO(4,430,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1937{ "nmaclhw.", XO(4,430,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1938{ "nmaclhwo", XO(4,430,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1939{ "nmaclhwo.", XO(4,430,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1940{ "nmaclhws", XO(4,494,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1941{ "nmaclhws.", XO(4,494,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1942{ "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1943{ "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1944{ "mfvscr", VX(4, 1540), VX_MASK, PPCVEC, { VD } }, 1945{ "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VB } }, 1946{ "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } }, 1947{ "vaddfp", VX(4, 10), VX_MASK, PPCVEC, { VD, VA, VB } }, 1948{ "vaddsbs", VX(4, 768), VX_MASK, PPCVEC, { VD, VA, VB } }, 1949{ "vaddshs", VX(4, 832), VX_MASK, PPCVEC, { VD, VA, VB } }, 1950{ "vaddsws", VX(4, 896), VX_MASK, PPCVEC, { VD, VA, VB } }, 1951{ "vaddubm", VX(4, 0), VX_MASK, PPCVEC, { VD, VA, VB } }, 1952{ "vaddubs", VX(4, 512), VX_MASK, PPCVEC, { VD, VA, VB } }, 1953{ "vadduhm", VX(4, 64), VX_MASK, PPCVEC, { VD, VA, VB } }, 1954{ "vadduhs", VX(4, 576), VX_MASK, PPCVEC, { VD, VA, VB } }, 1955{ "vadduwm", VX(4, 128), VX_MASK, PPCVEC, { VD, VA, VB } }, 1956{ "vadduws", VX(4, 640), VX_MASK, PPCVEC, { VD, VA, VB } }, 1957{ "vand", VX(4, 1028), VX_MASK, PPCVEC, { VD, VA, VB } }, 1958{ "vandc", VX(4, 1092), VX_MASK, PPCVEC, { VD, VA, VB } }, 1959{ "vavgsb", VX(4, 1282), VX_MASK, PPCVEC, { VD, VA, VB } }, 1960{ "vavgsh", VX(4, 1346), VX_MASK, PPCVEC, { VD, VA, VB } }, 1961{ "vavgsw", VX(4, 1410), VX_MASK, PPCVEC, { VD, VA, VB } }, 1962{ "vavgub", VX(4, 1026), VX_MASK, PPCVEC, { VD, VA, VB } }, 1963{ "vavguh", VX(4, 1090), VX_MASK, PPCVEC, { VD, VA, VB } }, 1964{ "vavguw", VX(4, 1154), VX_MASK, PPCVEC, { VD, VA, VB } }, 1965{ "vcfsx", VX(4, 842), VX_MASK, PPCVEC, { VD, VB, UIMM } }, 1966{ "vcfux", VX(4, 778), VX_MASK, PPCVEC, { VD, VB, UIMM } }, 1967{ "vcmpbfp", VXR(4, 966, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, 1968{ "vcmpbfp.", VXR(4, 966, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, 1969{ "vcmpeqfp", VXR(4, 198, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, 1970{ "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, 1971{ "vcmpequb", VXR(4, 6, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, 1972{ "vcmpequb.", VXR(4, 6, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, 1973{ "vcmpequh", VXR(4, 70, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, 1974{ "vcmpequh.", VXR(4, 70, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, 1975{ "vcmpequw", VXR(4, 134, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, 1976{ "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, 1977{ "vcmpgefp", VXR(4, 454, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, 1978{ "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, 1979{ "vcmpgtfp", VXR(4, 710, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, 1980{ "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, 1981{ "vcmpgtsb", VXR(4, 774, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, 1982{ "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, 1983{ "vcmpgtsh", VXR(4, 838, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, 1984{ "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, 1985{ "vcmpgtsw", VXR(4, 902, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, 1986{ "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, 1987{ "vcmpgtub", VXR(4, 518, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, 1988{ "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, 1989{ "vcmpgtuh", VXR(4, 582, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, 1990{ "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, 1991{ "vcmpgtuw", VXR(4, 646, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, 1992{ "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, 1993{ "vctsxs", VX(4, 970), VX_MASK, PPCVEC, { VD, VB, UIMM } }, 1994{ "vctuxs", VX(4, 906), VX_MASK, PPCVEC, { VD, VB, UIMM } }, 1995{ "vexptefp", VX(4, 394), VX_MASK, PPCVEC, { VD, VB } }, 1996{ "vlogefp", VX(4, 458), VX_MASK, PPCVEC, { VD, VB } }, 1997{ "vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, { VD, VA, VC, VB } }, 1998{ "vmaxfp", VX(4, 1034), VX_MASK, PPCVEC, { VD, VA, VB } }, 1999{ "vmaxsb", VX(4, 258), VX_MASK, PPCVEC, { VD, VA, VB } }, 2000{ "vmaxsh", VX(4, 322), VX_MASK, PPCVEC, { VD, VA, VB } }, 2001{ "vmaxsw", VX(4, 386), VX_MASK, PPCVEC, { VD, VA, VB } }, 2002{ "vmaxub", VX(4, 2), VX_MASK, PPCVEC, { VD, VA, VB } }, 2003{ "vmaxuh", VX(4, 66), VX_MASK, PPCVEC, { VD, VA, VB } }, 2004{ "vmaxuw", VX(4, 130), VX_MASK, PPCVEC, { VD, VA, VB } }, 2005{ "vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, 2006{ "vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, 2007{ "vminfp", VX(4, 1098), VX_MASK, PPCVEC, { VD, VA, VB } }, 2008{ "vminsb", VX(4, 770), VX_MASK, PPCVEC, { VD, VA, VB } }, 2009{ "vminsh", VX(4, 834), VX_MASK, PPCVEC, { VD, VA, VB } }, 2010{ "vminsw", VX(4, 898), VX_MASK, PPCVEC, { VD, VA, VB } }, 2011{ "vminub", VX(4, 514), VX_MASK, PPCVEC, { VD, VA, VB } }, 2012{ "vminuh", VX(4, 578), VX_MASK, PPCVEC, { VD, VA, VB } }, 2013{ "vminuw", VX(4, 642), VX_MASK, PPCVEC, { VD, VA, VB } }, 2014{ "vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, 2015{ "vmrghb", VX(4, 12), VX_MASK, PPCVEC, { VD, VA, VB } }, 2016{ "vmrghh", VX(4, 76), VX_MASK, PPCVEC, { VD, VA, VB } }, 2017{ "vmrghw", VX(4, 140), VX_MASK, PPCVEC, { VD, VA, VB } }, 2018{ "vmrglb", VX(4, 268), VX_MASK, PPCVEC, { VD, VA, VB } }, 2019{ "vmrglh", VX(4, 332), VX_MASK, PPCVEC, { VD, VA, VB } }, 2020{ "vmrglw", VX(4, 396), VX_MASK, PPCVEC, { VD, VA, VB } }, 2021{ "vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, 2022{ "vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, 2023{ "vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, 2024{ "vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, 2025{ "vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, 2026{ "vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, 2027{ "vmulesb", VX(4, 776), VX_MASK, PPCVEC, { VD, VA, VB } }, 2028{ "vmulesh", VX(4, 840), VX_MASK, PPCVEC, { VD, VA, VB } }, 2029{ "vmuleub", VX(4, 520), VX_MASK, PPCVEC, { VD, VA, VB } }, 2030{ "vmuleuh", VX(4, 584), VX_MASK, PPCVEC, { VD, VA, VB } }, 2031{ "vmulosb", VX(4, 264), VX_MASK, PPCVEC, { VD, VA, VB } }, 2032{ "vmulosh", VX(4, 328), VX_MASK, PPCVEC, { VD, VA, VB } }, 2033{ "vmuloub", VX(4, 8), VX_MASK, PPCVEC, { VD, VA, VB } }, 2034{ "vmulouh", VX(4, 72), VX_MASK, PPCVEC, { VD, VA, VB } }, 2035{ "vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, { VD, VA, VC, VB } }, 2036{ "vnor", VX(4, 1284), VX_MASK, PPCVEC, { VD, VA, VB } }, 2037{ "vor", VX(4, 1156), VX_MASK, PPCVEC, { VD, VA, VB } }, 2038{ "vperm", VXA(4, 43), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, 2039{ "vpkpx", VX(4, 782), VX_MASK, PPCVEC, { VD, VA, VB } }, 2040{ "vpkshss", VX(4, 398), VX_MASK, PPCVEC, { VD, VA, VB } }, 2041{ "vpkshus", VX(4, 270), VX_MASK, PPCVEC, { VD, VA, VB } }, 2042{ "vpkswss", VX(4, 462), VX_MASK, PPCVEC, { VD, VA, VB } }, 2043{ "vpkswus", VX(4, 334), VX_MASK, PPCVEC, { VD, VA, VB } }, 2044{ "vpkuhum", VX(4, 14), VX_MASK, PPCVEC, { VD, VA, VB } }, 2045{ "vpkuhus", VX(4, 142), VX_MASK, PPCVEC, { VD, VA, VB } }, 2046{ "vpkuwum", VX(4, 78), VX_MASK, PPCVEC, { VD, VA, VB } }, 2047{ "vpkuwus", VX(4, 206), VX_MASK, PPCVEC, { VD, VA, VB } }, 2048{ "vrefp", VX(4, 266), VX_MASK, PPCVEC, { VD, VB } }, 2049{ "vrfim", VX(4, 714), VX_MASK, PPCVEC, { VD, VB } }, 2050{ "vrfin", VX(4, 522), VX_MASK, PPCVEC, { VD, VB } }, 2051{ "vrfip", VX(4, 650), VX_MASK, PPCVEC, { VD, VB } }, 2052{ "vrfiz", VX(4, 586), VX_MASK, PPCVEC, { VD, VB } }, 2053{ "vrlb", VX(4, 4), VX_MASK, PPCVEC, { VD, VA, VB } }, 2054{ "vrlh", VX(4, 68), VX_MASK, PPCVEC, { VD, VA, VB } }, 2055{ "vrlw", VX(4, 132), VX_MASK, PPCVEC, { VD, VA, VB } }, 2056{ "vrsqrtefp", VX(4, 330), VX_MASK, PPCVEC, { VD, VB } }, 2057{ "vsel", VXA(4, 42), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, 2058{ "vsl", VX(4, 452), VX_MASK, PPCVEC, { VD, VA, VB } }, 2059{ "vslb", VX(4, 260), VX_MASK, PPCVEC, { VD, VA, VB } }, 2060{ "vsldoi", VXA(4, 44), VXA_MASK, PPCVEC, { VD, VA, VB, SHB } }, 2061{ "vslh", VX(4, 324), VX_MASK, PPCVEC, { VD, VA, VB } }, 2062{ "vslo", VX(4, 1036), VX_MASK, PPCVEC, { VD, VA, VB } }, 2063{ "vslw", VX(4, 388), VX_MASK, PPCVEC, { VD, VA, VB } }, 2064{ "vspltb", VX(4, 524), VX_MASK, PPCVEC, { VD, VB, UIMM } }, 2065{ "vsplth", VX(4, 588), VX_MASK, PPCVEC, { VD, VB, UIMM } }, 2066{ "vspltisb", VX(4, 780), VX_MASK, PPCVEC, { VD, SIMM } }, 2067{ "vspltish", VX(4, 844), VX_MASK, PPCVEC, { VD, SIMM } }, 2068{ "vspltisw", VX(4, 908), VX_MASK, PPCVEC, { VD, SIMM } }, 2069{ "vspltw", VX(4, 652), VX_MASK, PPCVEC, { VD, VB, UIMM } }, 2070{ "vsr", VX(4, 708), VX_MASK, PPCVEC, { VD, VA, VB } }, 2071{ "vsrab", VX(4, 772), VX_MASK, PPCVEC, { VD, VA, VB } }, 2072{ "vsrah", VX(4, 836), VX_MASK, PPCVEC, { VD, VA, VB } }, 2073{ "vsraw", VX(4, 900), VX_MASK, PPCVEC, { VD, VA, VB } }, 2074{ "vsrb", VX(4, 516), VX_MASK, PPCVEC, { VD, VA, VB } }, 2075{ "vsrh", VX(4, 580), VX_MASK, PPCVEC, { VD, VA, VB } }, 2076{ "vsro", VX(4, 1100), VX_MASK, PPCVEC, { VD, VA, VB } }, 2077{ "vsrw", VX(4, 644), VX_MASK, PPCVEC, { VD, VA, VB } }, 2078{ "vsubcuw", VX(4, 1408), VX_MASK, PPCVEC, { VD, VA, VB } }, 2079{ "vsubfp", VX(4, 74), VX_MASK, PPCVEC, { VD, VA, VB } }, 2080{ "vsubsbs", VX(4, 1792), VX_MASK, PPCVEC, { VD, VA, VB } }, 2081{ "vsubshs", VX(4, 1856), VX_MASK, PPCVEC, { VD, VA, VB } }, 2082{ "vsubsws", VX(4, 1920), VX_MASK, PPCVEC, { VD, VA, VB } }, 2083{ "vsububm", VX(4, 1024), VX_MASK, PPCVEC, { VD, VA, VB } }, 2084{ "vsububs", VX(4, 1536), VX_MASK, PPCVEC, { VD, VA, VB } }, 2085{ "vsubuhm", VX(4, 1088), VX_MASK, PPCVEC, { VD, VA, VB } }, 2086{ "vsubuhs", VX(4, 1600), VX_MASK, PPCVEC, { VD, VA, VB } }, 2087{ "vsubuwm", VX(4, 1152), VX_MASK, PPCVEC, { VD, VA, VB } }, 2088{ "vsubuws", VX(4, 1664), VX_MASK, PPCVEC, { VD, VA, VB } }, 2089{ "vsumsws", VX(4, 1928), VX_MASK, PPCVEC, { VD, VA, VB } }, 2090{ "vsum2sws", VX(4, 1672), VX_MASK, PPCVEC, { VD, VA, VB } }, 2091{ "vsum4sbs", VX(4, 1800), VX_MASK, PPCVEC, { VD, VA, VB } }, 2092{ "vsum4shs", VX(4, 1608), VX_MASK, PPCVEC, { VD, VA, VB } }, 2093{ "vsum4ubs", VX(4, 1544), VX_MASK, PPCVEC, { VD, VA, VB } }, 2094{ "vupkhpx", VX(4, 846), VX_MASK, PPCVEC, { VD, VB } }, 2095{ "vupkhsb", VX(4, 526), VX_MASK, PPCVEC, { VD, VB } }, 2096{ "vupkhsh", VX(4, 590), VX_MASK, PPCVEC, { VD, VB } }, 2097{ "vupklpx", VX(4, 974), VX_MASK, PPCVEC, { VD, VB } }, 2098{ "vupklsb", VX(4, 654), VX_MASK, PPCVEC, { VD, VB } }, 2099{ "vupklsh", VX(4, 718), VX_MASK, PPCVEC, { VD, VB } }, 2100{ "vxor", VX(4, 1220), VX_MASK, PPCVEC, { VD, VA, VB } }, 2101 2102{ "evaddw", VX(4, 512), VX_MASK, PPCSPE, { RS, RA, RB } }, 2103{ "evaddiw", VX(4, 514), VX_MASK, PPCSPE, { RS, RB, UIMM } }, 2104{ "evsubfw", VX(4, 516), VX_MASK, PPCSPE, { RS, RA, RB } }, 2105{ "evsubw", VX(4, 516), VX_MASK, PPCSPE, { RS, RB, RA } }, 2106{ "evsubifw", VX(4, 518), VX_MASK, PPCSPE, { RS, UIMM, RB } }, 2107{ "evsubiw", VX(4, 518), VX_MASK, PPCSPE, { RS, RB, UIMM } }, 2108{ "evabs", VX(4, 520), VX_MASK, PPCSPE, { RS, RA } }, 2109{ "evneg", VX(4, 521), VX_MASK, PPCSPE, { RS, RA } }, 2110{ "evextsb", VX(4, 522), VX_MASK, PPCSPE, { RS, RA } }, 2111{ "evextsh", VX(4, 523), VX_MASK, PPCSPE, { RS, RA } }, 2112{ "evrndw", VX(4, 524), VX_MASK, PPCSPE, { RS, RA } }, 2113{ "evcntlzw", VX(4, 525), VX_MASK, PPCSPE, { RS, RA } }, 2114{ "evcntlsw", VX(4, 526), VX_MASK, PPCSPE, { RS, RA } }, 2115 2116{ "brinc", VX(4, 527), VX_MASK, PPCSPE, { RS, RA, RB } }, 2117 2118{ "evand", VX(4, 529), VX_MASK, PPCSPE, { RS, RA, RB } }, 2119{ "evandc", VX(4, 530), VX_MASK, PPCSPE, { RS, RA, RB } }, 2120{ "evmr", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, BBA } }, 2121{ "evor", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, RB } }, 2122{ "evorc", VX(4, 539), VX_MASK, PPCSPE, { RS, RA, RB } }, 2123{ "evxor", VX(4, 534), VX_MASK, PPCSPE, { RS, RA, RB } }, 2124{ "eveqv", VX(4, 537), VX_MASK, PPCSPE, { RS, RA, RB } }, 2125{ "evnand", VX(4, 542), VX_MASK, PPCSPE, { RS, RA, RB } }, 2126{ "evnot", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, BBA } }, 2127{ "evnor", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, RB } }, 2128 2129{ "evrlw", VX(4, 552), VX_MASK, PPCSPE, { RS, RA, RB } }, 2130{ "evrlwi", VX(4, 554), VX_MASK, PPCSPE, { RS, RA, EVUIMM } }, 2131{ "evslw", VX(4, 548), VX_MASK, PPCSPE, { RS, RA, RB } }, 2132{ "evslwi", VX(4, 550), VX_MASK, PPCSPE, { RS, RA, EVUIMM } }, 2133{ "evsrws", VX(4, 545), VX_MASK, PPCSPE, { RS, RA, RB } }, 2134{ "evsrwu", VX(4, 544), VX_MASK, PPCSPE, { RS, RA, RB } }, 2135{ "evsrwis", VX(4, 547), VX_MASK, PPCSPE, { RS, RA, EVUIMM } }, 2136{ "evsrwiu", VX(4, 546), VX_MASK, PPCSPE, { RS, RA, EVUIMM } }, 2137{ "evsplati", VX(4, 553), VX_MASK, PPCSPE, { RS, SIMM } }, 2138{ "evsplatfi", VX(4, 555), VX_MASK, PPCSPE, { RS, SIMM } }, 2139{ "evmergehi", VX(4, 556), VX_MASK, PPCSPE, { RS, RA, RB } }, 2140{ "evmergelo", VX(4, 557), VX_MASK, PPCSPE, { RS, RA, RB } }, 2141{ "evmergehilo",VX(4,558), VX_MASK, PPCSPE, { RS, RA, RB } }, 2142{ "evmergelohi",VX(4,559), VX_MASK, PPCSPE, { RS, RA, RB } }, 2143 2144{ "evcmpgts", VX(4, 561), VX_MASK, PPCSPE, { CRFD, RA, RB } }, 2145{ "evcmpgtu", VX(4, 560), VX_MASK, PPCSPE, { CRFD, RA, RB } }, 2146{ "evcmplts", VX(4, 563), VX_MASK, PPCSPE, { CRFD, RA, RB } }, 2147{ "evcmpltu", VX(4, 562), VX_MASK, PPCSPE, { CRFD, RA, RB } }, 2148{ "evcmpeq", VX(4, 564), VX_MASK, PPCSPE, { CRFD, RA, RB } }, 2149{ "evsel", EVSEL(4,79),EVSEL_MASK, PPCSPE, { RS, RA, RB, CRFS } }, 2150 2151{ "evldd", VX(4, 769), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } }, 2152{ "evlddx", VX(4, 768), VX_MASK, PPCSPE, { RS, RA, RB } }, 2153{ "evldw", VX(4, 771), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } }, 2154{ "evldwx", VX(4, 770), VX_MASK, PPCSPE, { RS, RA, RB } }, 2155{ "evldh", VX(4, 773), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } }, 2156{ "evldhx", VX(4, 772), VX_MASK, PPCSPE, { RS, RA, RB } }, 2157{ "evlwhe", VX(4, 785), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, 2158{ "evlwhex", VX(4, 784), VX_MASK, PPCSPE, { RS, RA, RB } }, 2159{ "evlwhou", VX(4, 789), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, 2160{ "evlwhoux", VX(4, 788), VX_MASK, PPCSPE, { RS, RA, RB } }, 2161{ "evlwhos", VX(4, 791), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, 2162{ "evlwhosx", VX(4, 790), VX_MASK, PPCSPE, { RS, RA, RB } }, 2163{ "evlwwsplat",VX(4, 793), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, 2164{ "evlwwsplatx",VX(4, 792), VX_MASK, PPCSPE, { RS, RA, RB } }, 2165{ "evlwhsplat",VX(4, 797), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, 2166{ "evlwhsplatx",VX(4, 796), VX_MASK, PPCSPE, { RS, RA, RB } }, 2167{ "evlhhesplat",VX(4, 777), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } }, 2168{ "evlhhesplatx",VX(4, 776), VX_MASK, PPCSPE, { RS, RA, RB } }, 2169{ "evlhhousplat",VX(4, 781), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } }, 2170{ "evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, { RS, RA, RB } }, 2171{ "evlhhossplat",VX(4, 783), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } }, 2172{ "evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, { RS, RA, RB } }, 2173 2174{ "evstdd", VX(4, 801), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } }, 2175{ "evstddx", VX(4, 800), VX_MASK, PPCSPE, { RS, RA, RB } }, 2176{ "evstdw", VX(4, 803), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } }, 2177{ "evstdwx", VX(4, 802), VX_MASK, PPCSPE, { RS, RA, RB } }, 2178{ "evstdh", VX(4, 805), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } }, 2179{ "evstdhx", VX(4, 804), VX_MASK, PPCSPE, { RS, RA, RB } }, 2180{ "evstwwe", VX(4, 825), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, 2181{ "evstwwex", VX(4, 824), VX_MASK, PPCSPE, { RS, RA, RB } }, 2182{ "evstwwo", VX(4, 829), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, 2183{ "evstwwox", VX(4, 828), VX_MASK, PPCSPE, { RS, RA, RB } }, 2184{ "evstwhe", VX(4, 817), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, 2185{ "evstwhex", VX(4, 816), VX_MASK, PPCSPE, { RS, RA, RB } }, 2186{ "evstwho", VX(4, 821), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, 2187{ "evstwhox", VX(4, 820), VX_MASK, PPCSPE, { RS, RA, RB } }, 2188 2189{ "evfsabs", VX(4, 644), VX_MASK, PPCSPE, { RS, RA } }, 2190{ "evfsnabs", VX(4, 645), VX_MASK, PPCSPE, { RS, RA } }, 2191{ "evfsneg", VX(4, 646), VX_MASK, PPCSPE, { RS, RA } }, 2192{ "evfsadd", VX(4, 640), VX_MASK, PPCSPE, { RS, RA, RB } }, 2193{ "evfssub", VX(4, 641), VX_MASK, PPCSPE, { RS, RA, RB } }, 2194{ "evfsmul", VX(4, 648), VX_MASK, PPCSPE, { RS, RA, RB } }, 2195{ "evfsdiv", VX(4, 649), VX_MASK, PPCSPE, { RS, RA, RB } }, 2196{ "evfscmpgt", VX(4, 652), VX_MASK, PPCSPE, { CRFD, RA, RB } }, 2197{ "evfscmplt", VX(4, 653), VX_MASK, PPCSPE, { CRFD, RA, RB } }, 2198{ "evfscmpeq", VX(4, 654), VX_MASK, PPCSPE, { CRFD, RA, RB } }, 2199{ "evfststgt", VX(4, 668), VX_MASK, PPCSPE, { CRFD, RA, RB } }, 2200{ "evfststlt", VX(4, 669), VX_MASK, PPCSPE, { CRFD, RA, RB } }, 2201{ "evfststeq", VX(4, 670), VX_MASK, PPCSPE, { CRFD, RA, RB } }, 2202{ "evfscfui", VX(4, 656), VX_MASK, PPCSPE, { RS, RB } }, 2203{ "evfsctuiz", VX(4, 664), VX_MASK, PPCSPE, { RS, RB } }, 2204{ "evfscfsi", VX(4, 657), VX_MASK, PPCSPE, { RS, RB } }, 2205{ "evfscfuf", VX(4, 658), VX_MASK, PPCSPE, { RS, RB } }, 2206{ "evfscfsf", VX(4, 659), VX_MASK, PPCSPE, { RS, RB } }, 2207{ "evfsctui", VX(4, 660), VX_MASK, PPCSPE, { RS, RB } }, 2208{ "evfsctsi", VX(4, 661), VX_MASK, PPCSPE, { RS, RB } }, 2209{ "evfsctsiz", VX(4, 666), VX_MASK, PPCSPE, { RS, RB } }, 2210{ "evfsctuf", VX(4, 662), VX_MASK, PPCSPE, { RS, RB } }, 2211{ "evfsctsf", VX(4, 663), VX_MASK, PPCSPE, { RS, RB } }, 2212 2213{ "efsabs", VX(4, 708), VX_MASK, PPCEFS, { RS, RA } }, 2214{ "efsnabs", VX(4, 709), VX_MASK, PPCEFS, { RS, RA } }, 2215{ "efsneg", VX(4, 710), VX_MASK, PPCEFS, { RS, RA } }, 2216{ "efsadd", VX(4, 704), VX_MASK, PPCEFS, { RS, RA, RB } }, 2217{ "efssub", VX(4, 705), VX_MASK, PPCEFS, { RS, RA, RB } }, 2218{ "efsmul", VX(4, 712), VX_MASK, PPCEFS, { RS, RA, RB } }, 2219{ "efsdiv", VX(4, 713), VX_MASK, PPCEFS, { RS, RA, RB } }, 2220{ "efscmpgt", VX(4, 716), VX_MASK, PPCEFS, { CRFD, RA, RB } }, 2221{ "efscmplt", VX(4, 717), VX_MASK, PPCEFS, { CRFD, RA, RB } }, 2222{ "efscmpeq", VX(4, 718), VX_MASK, PPCEFS, { CRFD, RA, RB } }, 2223{ "efststgt", VX(4, 732), VX_MASK, PPCEFS, { CRFD, RA, RB } }, 2224{ "efststlt", VX(4, 733), VX_MASK, PPCEFS, { CRFD, RA, RB } }, 2225{ "efststeq", VX(4, 734), VX_MASK, PPCEFS, { CRFD, RA, RB } }, 2226{ "efscfui", VX(4, 720), VX_MASK, PPCEFS, { RS, RB } }, 2227{ "efsctuiz", VX(4, 728), VX_MASK, PPCEFS, { RS, RB } }, 2228{ "efscfsi", VX(4, 721), VX_MASK, PPCEFS, { RS, RB } }, 2229{ "efscfuf", VX(4, 722), VX_MASK, PPCEFS, { RS, RB } }, 2230{ "efscfsf", VX(4, 723), VX_MASK, PPCEFS, { RS, RB } }, 2231{ "efsctui", VX(4, 724), VX_MASK, PPCEFS, { RS, RB } }, 2232{ "efsctsi", VX(4, 725), VX_MASK, PPCEFS, { RS, RB } }, 2233{ "efsctsiz", VX(4, 730), VX_MASK, PPCEFS, { RS, RB } }, 2234{ "efsctuf", VX(4, 726), VX_MASK, PPCEFS, { RS, RB } }, 2235{ "efsctsf", VX(4, 727), VX_MASK, PPCEFS, { RS, RB } }, 2236 2237{ "evmhossf", VX(4, 1031), VX_MASK, PPCSPE, { RS, RA, RB } }, 2238{ "evmhossfa", VX(4, 1063), VX_MASK, PPCSPE, { RS, RA, RB } }, 2239{ "evmhosmf", VX(4, 1039), VX_MASK, PPCSPE, { RS, RA, RB } }, 2240{ "evmhosmfa", VX(4, 1071), VX_MASK, PPCSPE, { RS, RA, RB } }, 2241{ "evmhosmi", VX(4, 1037), VX_MASK, PPCSPE, { RS, RA, RB } }, 2242{ "evmhosmia", VX(4, 1069), VX_MASK, PPCSPE, { RS, RA, RB } }, 2243{ "evmhoumi", VX(4, 1036), VX_MASK, PPCSPE, { RS, RA, RB } }, 2244{ "evmhoumia", VX(4, 1068), VX_MASK, PPCSPE, { RS, RA, RB } }, 2245{ "evmhessf", VX(4, 1027), VX_MASK, PPCSPE, { RS, RA, RB } }, 2246{ "evmhessfa", VX(4, 1059), VX_MASK, PPCSPE, { RS, RA, RB } }, 2247{ "evmhesmf", VX(4, 1035), VX_MASK, PPCSPE, { RS, RA, RB } }, 2248{ "evmhesmfa", VX(4, 1067), VX_MASK, PPCSPE, { RS, RA, RB } }, 2249{ "evmhesmi", VX(4, 1033), VX_MASK, PPCSPE, { RS, RA, RB } }, 2250{ "evmhesmia", VX(4, 1065), VX_MASK, PPCSPE, { RS, RA, RB } }, 2251{ "evmheumi", VX(4, 1032), VX_MASK, PPCSPE, { RS, RA, RB } }, 2252{ "evmheumia", VX(4, 1064), VX_MASK, PPCSPE, { RS, RA, RB } }, 2253 2254{ "evmhossfaaw",VX(4, 1287), VX_MASK, PPCSPE, { RS, RA, RB } }, 2255{ "evmhossiaaw",VX(4, 1285), VX_MASK, PPCSPE, { RS, RA, RB } }, 2256{ "evmhosmfaaw",VX(4, 1295), VX_MASK, PPCSPE, { RS, RA, RB } }, 2257{ "evmhosmiaaw",VX(4, 1293), VX_MASK, PPCSPE, { RS, RA, RB } }, 2258{ "evmhousiaaw",VX(4, 1284), VX_MASK, PPCSPE, { RS, RA, RB } }, 2259{ "evmhoumiaaw",VX(4, 1292), VX_MASK, PPCSPE, { RS, RA, RB } }, 2260{ "evmhessfaaw",VX(4, 1283), VX_MASK, PPCSPE, { RS, RA, RB } }, 2261{ "evmhessiaaw",VX(4, 1281), VX_MASK, PPCSPE, { RS, RA, RB } }, 2262{ "evmhesmfaaw",VX(4, 1291), VX_MASK, PPCSPE, { RS, RA, RB } }, 2263{ "evmhesmiaaw",VX(4, 1289), VX_MASK, PPCSPE, { RS, RA, RB } }, 2264{ "evmheusiaaw",VX(4, 1280), VX_MASK, PPCSPE, { RS, RA, RB } }, 2265{ "evmheumiaaw",VX(4, 1288), VX_MASK, PPCSPE, { RS, RA, RB } }, 2266 2267{ "evmhossfanw",VX(4, 1415), VX_MASK, PPCSPE, { RS, RA, RB } }, 2268{ "evmhossianw",VX(4, 1413), VX_MASK, PPCSPE, { RS, RA, RB } }, 2269{ "evmhosmfanw",VX(4, 1423), VX_MASK, PPCSPE, { RS, RA, RB } }, 2270{ "evmhosmianw",VX(4, 1421), VX_MASK, PPCSPE, { RS, RA, RB } }, 2271{ "evmhousianw",VX(4, 1412), VX_MASK, PPCSPE, { RS, RA, RB } }, 2272{ "evmhoumianw",VX(4, 1420), VX_MASK, PPCSPE, { RS, RA, RB } }, 2273{ "evmhessfanw",VX(4, 1411), VX_MASK, PPCSPE, { RS, RA, RB } }, 2274{ "evmhessianw",VX(4, 1409), VX_MASK, PPCSPE, { RS, RA, RB } }, 2275{ "evmhesmfanw",VX(4, 1419), VX_MASK, PPCSPE, { RS, RA, RB } }, 2276{ "evmhesmianw",VX(4, 1417), VX_MASK, PPCSPE, { RS, RA, RB } }, 2277{ "evmheusianw",VX(4, 1408), VX_MASK, PPCSPE, { RS, RA, RB } }, 2278{ "evmheumianw",VX(4, 1416), VX_MASK, PPCSPE, { RS, RA, RB } }, 2279 2280{ "evmhogsmfaa",VX(4, 1327), VX_MASK, PPCSPE, { RS, RA, RB } }, 2281{ "evmhogsmiaa",VX(4, 1325), VX_MASK, PPCSPE, { RS, RA, RB } }, 2282{ "evmhogumiaa",VX(4, 1324), VX_MASK, PPCSPE, { RS, RA, RB } }, 2283{ "evmhegsmfaa",VX(4, 1323), VX_MASK, PPCSPE, { RS, RA, RB } }, 2284{ "evmhegsmiaa",VX(4, 1321), VX_MASK, PPCSPE, { RS, RA, RB } }, 2285{ "evmhegumiaa",VX(4, 1320), VX_MASK, PPCSPE, { RS, RA, RB } }, 2286 2287{ "evmhogsmfan",VX(4, 1455), VX_MASK, PPCSPE, { RS, RA, RB } }, 2288{ "evmhogsmian",VX(4, 1453), VX_MASK, PPCSPE, { RS, RA, RB } }, 2289{ "evmhogumian",VX(4, 1452), VX_MASK, PPCSPE, { RS, RA, RB } }, 2290{ "evmhegsmfan",VX(4, 1451), VX_MASK, PPCSPE, { RS, RA, RB } }, 2291{ "evmhegsmian",VX(4, 1449), VX_MASK, PPCSPE, { RS, RA, RB } }, 2292{ "evmhegumian",VX(4, 1448), VX_MASK, PPCSPE, { RS, RA, RB } }, 2293 2294{ "evmwhssf", VX(4, 1095), VX_MASK, PPCSPE, { RS, RA, RB } }, 2295{ "evmwhssfa", VX(4, 1127), VX_MASK, PPCSPE, { RS, RA, RB } }, 2296{ "evmwhsmf", VX(4, 1103), VX_MASK, PPCSPE, { RS, RA, RB } }, 2297{ "evmwhsmfa", VX(4, 1135), VX_MASK, PPCSPE, { RS, RA, RB } }, 2298{ "evmwhsmi", VX(4, 1101), VX_MASK, PPCSPE, { RS, RA, RB } }, 2299{ "evmwhsmia", VX(4, 1133), VX_MASK, PPCSPE, { RS, RA, RB } }, 2300{ "evmwhumi", VX(4, 1100), VX_MASK, PPCSPE, { RS, RA, RB } }, 2301{ "evmwhumia", VX(4, 1132), VX_MASK, PPCSPE, { RS, RA, RB } }, 2302 2303{ "evmwlumi", VX(4, 1096), VX_MASK, PPCSPE, { RS, RA, RB } }, 2304{ "evmwlumia", VX(4, 1128), VX_MASK, PPCSPE, { RS, RA, RB } }, 2305 2306{ "evmwlssiaaw",VX(4, 1345), VX_MASK, PPCSPE, { RS, RA, RB } }, 2307{ "evmwlsmiaaw",VX(4, 1353), VX_MASK, PPCSPE, { RS, RA, RB } }, 2308{ "evmwlusiaaw",VX(4, 1344), VX_MASK, PPCSPE, { RS, RA, RB } }, 2309{ "evmwlumiaaw",VX(4, 1352), VX_MASK, PPCSPE, { RS, RA, RB } }, 2310 2311{ "evmwlssianw",VX(4, 1473), VX_MASK, PPCSPE, { RS, RA, RB } }, 2312{ "evmwlsmianw",VX(4, 1481), VX_MASK, PPCSPE, { RS, RA, RB } }, 2313{ "evmwlusianw",VX(4, 1472), VX_MASK, PPCSPE, { RS, RA, RB } }, 2314{ "evmwlumianw",VX(4, 1480), VX_MASK, PPCSPE, { RS, RA, RB } }, 2315 2316{ "evmwssf", VX(4, 1107), VX_MASK, PPCSPE, { RS, RA, RB } }, 2317{ "evmwssfa", VX(4, 1139), VX_MASK, PPCSPE, { RS, RA, RB } }, 2318{ "evmwsmf", VX(4, 1115), VX_MASK, PPCSPE, { RS, RA, RB } }, 2319{ "evmwsmfa", VX(4, 1147), VX_MASK, PPCSPE, { RS, RA, RB } }, 2320{ "evmwsmi", VX(4, 1113), VX_MASK, PPCSPE, { RS, RA, RB } }, 2321{ "evmwsmia", VX(4, 1145), VX_MASK, PPCSPE, { RS, RA, RB } }, 2322{ "evmwumi", VX(4, 1112), VX_MASK, PPCSPE, { RS, RA, RB } }, 2323{ "evmwumia", VX(4, 1144), VX_MASK, PPCSPE, { RS, RA, RB } }, 2324 2325{ "evmwssfaa", VX(4, 1363), VX_MASK, PPCSPE, { RS, RA, RB } }, 2326{ "evmwsmfaa", VX(4, 1371), VX_MASK, PPCSPE, { RS, RA, RB } }, 2327{ "evmwsmiaa", VX(4, 1369), VX_MASK, PPCSPE, { RS, RA, RB } }, 2328{ "evmwumiaa", VX(4, 1368), VX_MASK, PPCSPE, { RS, RA, RB } }, 2329 2330{ "evmwssfan", VX(4, 1491), VX_MASK, PPCSPE, { RS, RA, RB } }, 2331{ "evmwsmfan", VX(4, 1499), VX_MASK, PPCSPE, { RS, RA, RB } }, 2332{ "evmwsmian", VX(4, 1497), VX_MASK, PPCSPE, { RS, RA, RB } }, 2333{ "evmwumian", VX(4, 1496), VX_MASK, PPCSPE, { RS, RA, RB } }, 2334 2335{ "evaddssiaaw",VX(4, 1217), VX_MASK, PPCSPE, { RS, RA } }, 2336{ "evaddsmiaaw",VX(4, 1225), VX_MASK, PPCSPE, { RS, RA } }, 2337{ "evaddusiaaw",VX(4, 1216), VX_MASK, PPCSPE, { RS, RA } }, 2338{ "evaddumiaaw",VX(4, 1224), VX_MASK, PPCSPE, { RS, RA } }, 2339 2340{ "evsubfssiaaw",VX(4, 1219), VX_MASK, PPCSPE, { RS, RA } }, 2341{ "evsubfsmiaaw",VX(4, 1227), VX_MASK, PPCSPE, { RS, RA } }, 2342{ "evsubfusiaaw",VX(4, 1218), VX_MASK, PPCSPE, { RS, RA } }, 2343{ "evsubfumiaaw",VX(4, 1226), VX_MASK, PPCSPE, { RS, RA } }, 2344 2345{ "evmra", VX(4, 1220), VX_MASK, PPCSPE, { RS, RA } }, 2346 2347{ "evdivws", VX(4, 1222), VX_MASK, PPCSPE, { RS, RA, RB } }, 2348{ "evdivwu", VX(4, 1223), VX_MASK, PPCSPE, { RS, RA, RB } }, 2349 2350{ "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } }, 2351{ "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } }, 2352 2353{ "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } }, 2354{ "sfi", OP(8), OP_MASK, PWRCOM, { RT, RA, SI } }, 2355 2356{ "dozi", OP(9), OP_MASK, M601, { RT, RA, SI } }, 2357 2358{ "bce", B(9,0,0), B_MASK, BOOKE64, { BO, BI, BD } }, 2359{ "bcel", B(9,0,1), B_MASK, BOOKE64, { BO, BI, BD } }, 2360{ "bcea", B(9,1,0), B_MASK, BOOKE64, { BO, BI, BDA } }, 2361{ "bcela", B(9,1,1), B_MASK, BOOKE64, { BO, BI, BDA } }, 2362 2363{ "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } }, 2364{ "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } }, 2365{ "cmpli", OP(10), OP_MASK, PPC, { BF, L, RA, UI } }, 2366{ "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI } }, 2367 2368{ "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } }, 2369{ "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI } }, 2370{ "cmpi", OP(11), OP_MASK, PPC, { BF, L, RA, SI } }, 2371{ "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI } }, 2372 2373{ "addic", OP(12), OP_MASK, PPCCOM, { RT, RA, SI } }, 2374{ "ai", OP(12), OP_MASK, PWRCOM, { RT, RA, SI } }, 2375{ "subic", OP(12), OP_MASK, PPCCOM, { RT, RA, NSI } }, 2376 2377{ "addic.", OP(13), OP_MASK, PPCCOM, { RT, RA, SI } }, 2378{ "ai.", OP(13), OP_MASK, PWRCOM, { RT, RA, SI } }, 2379{ "subic.", OP(13), OP_MASK, PPCCOM, { RT, RA, NSI } }, 2380 2381{ "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } }, 2382{ "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI } }, 2383{ "addi", OP(14), OP_MASK, PPCCOM, { RT, RA0, SI } }, 2384{ "cal", OP(14), OP_MASK, PWRCOM, { RT, D, RA0 } }, 2385{ "subi", OP(14), OP_MASK, PPCCOM, { RT, RA0, NSI } }, 2386{ "la", OP(14), OP_MASK, PPCCOM, { RT, D, RA0 } }, 2387 2388{ "lis", OP(15), DRA_MASK, PPCCOM, { RT, SISIGNOPT } }, 2389{ "liu", OP(15), DRA_MASK, PWRCOM, { RT, SISIGNOPT } }, 2390{ "addis", OP(15), OP_MASK, PPCCOM, { RT,RA0,SISIGNOPT } }, 2391{ "cau", OP(15), OP_MASK, PWRCOM, { RT,RA0,SISIGNOPT } }, 2392{ "subis", OP(15), OP_MASK, PPCCOM, { RT, RA0, NSI } }, 2393 2394{ "bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } }, 2395{ "bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } }, 2396{ "bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BD } }, 2397{ "bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, { BD } }, 2398{ "bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } }, 2399{ "bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } }, 2400{ "bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BD } }, 2401{ "bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, { BD } }, 2402{ "bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } }, 2403{ "bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } }, 2404{ "bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDA } }, 2405{ "bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, { BDA } }, 2406{ "bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } }, 2407{ "bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } }, 2408{ "bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDA } }, 2409{ "bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, { BDA } }, 2410{ "bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } }, 2411{ "bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } }, 2412{ "bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, { BD } }, 2413{ "bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } }, 2414{ "bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } }, 2415{ "bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, { BD } }, 2416{ "bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } }, 2417{ "bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } }, 2418{ "bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, { BDA } }, 2419{ "bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } }, 2420{ "bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } }, 2421{ "bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, { BDA } }, 2422{ "blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2423{ "blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2424{ "blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } }, 2425{ "bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2426{ "bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2427{ "bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } }, 2428{ "blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2429{ "blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2430{ "blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, 2431{ "bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2432{ "bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2433{ "bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, 2434{ "bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2435{ "bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2436{ "bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } }, 2437{ "bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2438{ "bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2439{ "bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } }, 2440{ "bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2441{ "bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2442{ "bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, 2443{ "bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2444{ "bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2445{ "bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, 2446{ "beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2447{ "beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2448{ "beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } }, 2449{ "beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2450{ "beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2451{ "beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } }, 2452{ "beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2453{ "beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2454{ "beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } }, 2455{ "beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2456{ "beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2457{ "beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } }, 2458{ "bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2459{ "bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2460{ "bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } }, 2461{ "bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2462{ "bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2463{ "bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } }, 2464{ "bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2465{ "bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2466{ "bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } }, 2467{ "bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2468{ "bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2469{ "bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } }, 2470{ "bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2471{ "bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2472{ "bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } }, 2473{ "bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2474{ "bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2475{ "bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } }, 2476{ "buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2477{ "buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2478{ "buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } }, 2479{ "bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2480{ "bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2481{ "bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } }, 2482{ "bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2483{ "bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2484{ "bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } }, 2485{ "bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2486{ "bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2487{ "bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } }, 2488{ "bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2489{ "bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2490{ "bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, 2491{ "bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2492{ "bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2493{ "bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, 2494{ "bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2495{ "bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2496{ "bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } }, 2497{ "bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2498{ "bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2499{ "bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } }, 2500{ "bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2501{ "bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2502{ "bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, 2503{ "bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2504{ "bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2505{ "bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, 2506{ "ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2507{ "ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2508{ "ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } }, 2509{ "blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2510{ "blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2511{ "blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } }, 2512{ "blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2513{ "blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2514{ "blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, 2515{ "blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2516{ "blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2517{ "blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, 2518{ "bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2519{ "bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2520{ "bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } }, 2521{ "bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2522{ "bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2523{ "bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } }, 2524{ "bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2525{ "bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2526{ "bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, 2527{ "bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2528{ "bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2529{ "bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, 2530{ "bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2531{ "bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2532{ "bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } }, 2533{ "bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2534{ "bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2535{ "bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } }, 2536{ "bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2537{ "bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2538{ "bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } }, 2539{ "bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2540{ "bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2541{ "bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } }, 2542{ "bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2543{ "bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2544{ "bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } }, 2545{ "bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2546{ "bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2547{ "bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } }, 2548{ "bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2549{ "bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2550{ "bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } }, 2551{ "bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2552{ "bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2553{ "bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } }, 2554{ "bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2555{ "bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2556{ "bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } }, 2557{ "bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2558{ "bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2559{ "bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } }, 2560{ "bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2561{ "bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2562{ "bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } }, 2563{ "bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2564{ "bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2565{ "bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } }, 2566{ "bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } }, 2567{ "bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } }, 2568{ "bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } }, 2569{ "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } }, 2570{ "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } }, 2571{ "bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } }, 2572{ "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } }, 2573{ "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } }, 2574{ "bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } }, 2575{ "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } }, 2576{ "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } }, 2577{ "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } }, 2578{ "bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } }, 2579{ "bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } }, 2580{ "bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } }, 2581{ "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } }, 2582{ "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } }, 2583{ "bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } }, 2584{ "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } }, 2585{ "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } }, 2586{ "bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } }, 2587{ "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } }, 2588{ "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } }, 2589{ "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } }, 2590{ "bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } }, 2591{ "bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } }, 2592{ "bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BD } }, 2593{ "bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, { BI, BD } }, 2594{ "btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } }, 2595{ "btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } }, 2596{ "btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BD } }, 2597{ "bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, { BI, BD } }, 2598{ "bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } }, 2599{ "bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } }, 2600{ "bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } }, 2601{ "bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } }, 2602{ "btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } }, 2603{ "btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } }, 2604{ "btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } }, 2605{ "bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } }, 2606{ "bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } }, 2607{ "bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } }, 2608{ "bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BD } }, 2609{ "bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, { BI, BD } }, 2610{ "bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } }, 2611{ "bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } }, 2612{ "bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BD } }, 2613{ "bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, { BI, BD } }, 2614{ "bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } }, 2615{ "bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } }, 2616{ "bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } }, 2617{ "bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } }, 2618{ "bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } }, 2619{ "bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } }, 2620{ "bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } }, 2621{ "bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } }, 2622{ "bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } }, 2623{ "bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } }, 2624{ "bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } }, 2625{ "bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } }, 2626{ "bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } }, 2627{ "bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } }, 2628{ "bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } }, 2629{ "bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } }, 2630{ "bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } }, 2631{ "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } }, 2632{ "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } }, 2633{ "bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } }, 2634{ "bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } }, 2635{ "bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } }, 2636{ "bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } }, 2637{ "bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } }, 2638{ "bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } }, 2639{ "bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } }, 2640{ "bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } }, 2641{ "bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } }, 2642{ "bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } }, 2643{ "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } }, 2644{ "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } }, 2645{ "bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } }, 2646{ "bc-", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDM } }, 2647{ "bc+", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDP } }, 2648{ "bc", B(16,0,0), B_MASK, COM, { BO, BI, BD } }, 2649{ "bcl-", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDM } }, 2650{ "bcl+", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDP } }, 2651{ "bcl", B(16,0,1), B_MASK, COM, { BO, BI, BD } }, 2652{ "bca-", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDMA } }, 2653{ "bca+", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDPA } }, 2654{ "bca", B(16,1,0), B_MASK, COM, { BO, BI, BDA } }, 2655{ "bcla-", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDMA } }, 2656{ "bcla+", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDPA } }, 2657{ "bcla", B(16,1,1), B_MASK, COM, { BO, BI, BDA } }, 2658 2659{ "sc", SC(17,1,0), 0xffffffff, PPC, { 0 } }, 2660{ "svc", SC(17,0,0), SC_MASK, POWER, { LEV, FL1, FL2 } }, 2661{ "svcl", SC(17,0,1), SC_MASK, POWER, { LEV, FL1, FL2 } }, 2662{ "svca", SC(17,1,0), SC_MASK, PWRCOM, { SV } }, 2663{ "svcla", SC(17,1,1), SC_MASK, POWER, { SV } }, 2664 2665{ "b", B(18,0,0), B_MASK, COM, { LI } }, 2666{ "bl", B(18,0,1), B_MASK, COM, { LI } }, 2667{ "ba", B(18,1,0), B_MASK, COM, { LIA } }, 2668{ "bla", B(18,1,1), B_MASK, COM, { LIA } }, 2669 2670{ "mcrf", XL(19,0), XLBB_MASK|(3 << 21)|(3 << 16), COM, { BF, BFA } }, 2671 2672{ "blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } }, 2673{ "br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, { 0 } }, 2674{ "blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } }, 2675{ "brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, { 0 } }, 2676{ "bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } }, 2677{ "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } }, 2678{ "bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } }, 2679{ "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } }, 2680{ "bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } }, 2681{ "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } }, 2682{ "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } }, 2683{ "bdnzlrl-",XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } }, 2684{ "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } }, 2685{ "bdnzlrl+",XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } }, 2686{ "bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } }, 2687{ "bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } }, 2688{ "bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } }, 2689{ "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } }, 2690{ "bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } }, 2691{ "bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } }, 2692{ "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } }, 2693{ "bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } }, 2694{ "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } }, 2695{ "bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } }, 2696{ "bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 2697{ "bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2698{ "bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 2699{ "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2700{ "bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 2701{ "bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, 2702{ "bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 2703{ "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2704{ "bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 2705{ "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2706{ "bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 2707{ "bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, 2708{ "bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 2709{ "bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2710{ "bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 2711{ "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2712{ "bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 2713{ "bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, 2714{ "bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 2715{ "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2716{ "bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 2717{ "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2718{ "bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 2719{ "bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, 2720{ "beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 2721{ "beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2722{ "beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 2723{ "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2724{ "beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 2725{ "beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, 2726{ "beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 2727{ "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2728{ "beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 2729{ "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2730{ "beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 2731{ "beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, 2732{ "bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 2733{ "bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2734{ "bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 2735{ "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2736{ "bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 2737{ "bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, 2738{ "bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 2739{ "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2740{ "bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 2741{ "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2742{ "bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 2743{ "bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, 2744{ "bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 2745{ "bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2746{ "bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 2747{ "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2748{ "bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 2749{ "bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 2750{ "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2751{ "bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 2752{ "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2753{ "bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 2754{ "bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 2755{ "bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2756{ "bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 2757{ "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2758{ "bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 2759{ "bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, 2760{ "bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 2761{ "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2762{ "bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 2763{ "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2764{ "bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 2765{ "bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, 2766{ "bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 2767{ "bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2768{ "bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 2769{ "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2770{ "bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 2771{ "bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, 2772{ "bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 2773{ "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2774{ "bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 2775{ "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2776{ "bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 2777{ "bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, 2778{ "blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 2779{ "blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2780{ "blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 2781{ "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2782{ "blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 2783{ "bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, 2784{ "blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 2785{ "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2786{ "blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 2787{ "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2788{ "blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 2789{ "blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, 2790{ "bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 2791{ "bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2792{ "bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 2793{ "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2794{ "bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 2795{ "bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, 2796{ "bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 2797{ "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2798{ "bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 2799{ "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2800{ "bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 2801{ "bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, 2802{ "bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 2803{ "bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2804{ "bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 2805{ "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2806{ "bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 2807{ "bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, 2808{ "bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 2809{ "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2810{ "bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 2811{ "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2812{ "bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 2813{ "bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, 2814{ "bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 2815{ "bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2816{ "bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 2817{ "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2818{ "bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 2819{ "bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, 2820{ "bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 2821{ "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2822{ "bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 2823{ "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2824{ "bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 2825{ "bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, 2826{ "bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 2827{ "bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2828{ "bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 2829{ "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2830{ "bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 2831{ "bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 2832{ "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2833{ "bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 2834{ "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2835{ "bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 2836{ "btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, { BI } }, 2837{ "btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, 2838{ "btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4, { BI } }, 2839{ "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, 2840{ "btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4, { BI } }, 2841{ "bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, { BI } }, 2842{ "btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, { BI } }, 2843{ "btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, 2844{ "btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4, { BI } }, 2845{ "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, 2846{ "btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4, { BI } }, 2847{ "bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, { BI } }, 2848{ "bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, { BI } }, 2849{ "bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, 2850{ "bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4, { BI } }, 2851{ "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, 2852{ "bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4, { BI } }, 2853{ "bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, { BI } }, 2854{ "bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, { BI } }, 2855{ "bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, 2856{ "bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4, { BI } }, 2857{ "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, 2858{ "bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4, { BI } }, 2859{ "bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, { BI } }, 2860{ "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, { BI } }, 2861{ "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, 2862{ "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, 2863{ "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, { BI } }, 2864{ "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, 2865{ "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, 2866{ "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, { BI } }, 2867{ "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, 2868{ "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, 2869{ "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, { BI } }, 2870{ "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, 2871{ "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, 2872{ "bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, { BI } }, 2873{ "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, 2874{ "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, 2875{ "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, { BI } }, 2876{ "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, 2877{ "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, 2878{ "bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, { BI } }, 2879{ "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, 2880{ "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, 2881{ "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, { BI } }, 2882{ "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, 2883{ "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, 2884{ "bclr", XLLK(19,16,0), XLYBB_MASK, PPCCOM, { BO, BI } }, 2885{ "bclrl", XLLK(19,16,1), XLYBB_MASK, PPCCOM, { BO, BI } }, 2886{ "bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } }, 2887{ "bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } }, 2888{ "bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } }, 2889{ "bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } }, 2890{ "bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, { BO, BI } }, 2891{ "bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, { BO, BI } }, 2892{ "bclre", XLLK(19,17,0), XLBB_MASK, BOOKE64, { BO, BI } }, 2893{ "bclrel", XLLK(19,17,1), XLBB_MASK, BOOKE64, { BO, BI } }, 2894 2895{ "rfid", XL(19,18), 0xffffffff, PPC64, { 0 } }, 2896 2897{ "crnot", XL(19,33), XL_MASK, PPCCOM, { BT, BA, BBA } }, 2898{ "crnor", XL(19,33), XL_MASK, COM, { BT, BA, BB } }, 2899{ "rfmci", X(19,38), 0xffffffff, PPCRFMCI, { 0 } }, 2900 2901{ "rfi", XL(19,50), 0xffffffff, COM, { 0 } }, 2902{ "rfci", XL(19,51), 0xffffffff, PPC403 | BOOKE, { 0 } }, 2903 2904{ "rfsvc", XL(19,82), 0xffffffff, POWER, { 0 } }, 2905 2906{ "crandc", XL(19,129), XL_MASK, COM, { BT, BA, BB } }, 2907 2908{ "isync", XL(19,150), 0xffffffff, PPCCOM, { 0 } }, 2909{ "ics", XL(19,150), 0xffffffff, PWRCOM, { 0 } }, 2910 2911{ "crclr", XL(19,193), XL_MASK, PPCCOM, { BT, BAT, BBA } }, 2912{ "crxor", XL(19,193), XL_MASK, COM, { BT, BA, BB } }, 2913 2914{ "crnand", XL(19,225), XL_MASK, COM, { BT, BA, BB } }, 2915 2916{ "crand", XL(19,257), XL_MASK, COM, { BT, BA, BB } }, 2917 2918{ "crset", XL(19,289), XL_MASK, PPCCOM, { BT, BAT, BBA } }, 2919{ "creqv", XL(19,289), XL_MASK, COM, { BT, BA, BB } }, 2920 2921{ "crorc", XL(19,417), XL_MASK, COM, { BT, BA, BB } }, 2922 2923{ "crmove", XL(19,449), XL_MASK, PPCCOM, { BT, BA, BBA } }, 2924{ "cror", XL(19,449), XL_MASK, COM, { BT, BA, BB } }, 2925 2926{ "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, { 0 } }, 2927{ "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, { 0 } }, 2928{ "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 2929{ "bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2930{ "bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 2931{ "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2932{ "bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 2933{ "bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 2934{ "bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2935{ "bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 2936{ "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2937{ "bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 2938{ "bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 2939{ "bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2940{ "bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 2941{ "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2942{ "bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 2943{ "bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 2944{ "bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2945{ "bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 2946{ "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2947{ "bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 2948{ "beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 2949{ "beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2950{ "beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 2951{ "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2952{ "beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 2953{ "beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 2954{ "beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2955{ "beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 2956{ "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2957{ "beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 2958{ "bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 2959{ "bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2960{ "bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 2961{ "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2962{ "bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 2963{ "bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 2964{ "bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2965{ "bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 2966{ "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2967{ "bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 2968{ "bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 2969{ "bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2970{ "bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 2971{ "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2972{ "bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 2973{ "bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 2974{ "bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2975{ "bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 2976{ "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2977{ "bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 2978{ "bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 2979{ "bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2980{ "bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 2981{ "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2982{ "bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 2983{ "bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 2984{ "bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2985{ "bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 2986{ "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2987{ "bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 2988{ "bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 2989{ "bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2990{ "bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 2991{ "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2992{ "bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 2993{ "bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 2994{ "bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2995{ "bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 2996{ "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2997{ "bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 2998{ "blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 2999{ "blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3000{ "blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 3001{ "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3002{ "blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 3003{ "blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 3004{ "blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3005{ "blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 3006{ "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3007{ "blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 3008{ "bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 3009{ "bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3010{ "bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 3011{ "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3012{ "bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 3013{ "bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 3014{ "bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3015{ "bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 3016{ "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3017{ "bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 3018{ "bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 3019{ "bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3020{ "bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 3021{ "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3022{ "bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 3023{ "bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 3024{ "bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3025{ "bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 3026{ "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3027{ "bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 3028{ "bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 3029{ "bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3030{ "bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 3031{ "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3032{ "bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 3033{ "bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 3034{ "bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3035{ "bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 3036{ "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3037{ "bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 3038{ "bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 3039{ "bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3040{ "bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 3041{ "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3042{ "bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 3043{ "bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 3044{ "bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3045{ "bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 3046{ "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3047{ "bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 3048{ "btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, { BI } }, 3049{ "btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, NOPOWER4, { BI } }, 3050{ "btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, { BI } }, 3051{ "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4, { BI } }, 3052{ "btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, { BI } }, 3053{ "btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, { BI } }, 3054{ "btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, NOPOWER4, { BI } }, 3055{ "btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, { BI } }, 3056{ "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4, { BI } }, 3057{ "btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, { BI } }, 3058{ "bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, { BI } }, 3059{ "bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, NOPOWER4, { BI } }, 3060{ "bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, { BI } }, 3061{ "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, { BI } }, 3062{ "bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, { BI } }, 3063{ "bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, { BI } }, 3064{ "bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, NOPOWER4, { BI } }, 3065{ "bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, { BI } }, 3066{ "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, { BI } }, 3067{ "bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, { BI } }, 3068{ "bcctr", XLLK(19,528,0), XLYBB_MASK, PPCCOM, { BO, BI } }, 3069{ "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } }, 3070{ "bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } }, 3071{ "bcctrl", XLLK(19,528,1), XLYBB_MASK, PPCCOM, { BO, BI } }, 3072{ "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } }, 3073{ "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } }, 3074{ "bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, { BO, BI } }, 3075{ "bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, { BO, BI } }, 3076{ "bcctre", XLLK(19,529,0), XLYBB_MASK, BOOKE64, { BO, BI } }, 3077{ "bcctrel", XLLK(19,529,1), XLYBB_MASK, BOOKE64, { BO, BI } }, 3078 3079{ "rlwimi", M(20,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } }, 3080{ "rlimi", M(20,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } }, 3081 3082{ "rlwimi.", M(20,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } }, 3083{ "rlimi.", M(20,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } }, 3084 3085{ "rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, { RA, RS, SH } }, 3086{ "clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, { RA, RS, MB } }, 3087{ "rlwinm", M(21,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } }, 3088{ "rlinm", M(21,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } }, 3089{ "rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, { RA,RS,SH } }, 3090{ "clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, { RA, RS, MB } }, 3091{ "rlwinm.", M(21,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } }, 3092{ "rlinm.", M(21,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } }, 3093 3094{ "rlmi", M(22,0), M_MASK, M601, { RA,RS,RB,MBE,ME } }, 3095{ "rlmi.", M(22,1), M_MASK, M601, { RA,RS,RB,MBE,ME } }, 3096 3097{ "be", B(22,0,0), B_MASK, BOOKE64, { LI } }, 3098{ "bel", B(22,0,1), B_MASK, BOOKE64, { LI } }, 3099{ "bea", B(22,1,0), B_MASK, BOOKE64, { LIA } }, 3100{ "bela", B(22,1,1), B_MASK, BOOKE64, { LIA } }, 3101 3102{ "rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, { RA, RS, RB } }, 3103{ "rlwnm", M(23,0), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } }, 3104{ "rlnm", M(23,0), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } }, 3105{ "rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, { RA, RS, RB } }, 3106{ "rlwnm.", M(23,1), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } }, 3107{ "rlnm.", M(23,1), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } }, 3108 3109{ "nop", OP(24), 0xffffffff, PPCCOM, { 0 } }, 3110{ "ori", OP(24), OP_MASK, PPCCOM, { RA, RS, UI } }, 3111{ "oril", OP(24), OP_MASK, PWRCOM, { RA, RS, UI } }, 3112 3113{ "oris", OP(25), OP_MASK, PPCCOM, { RA, RS, UI } }, 3114{ "oriu", OP(25), OP_MASK, PWRCOM, { RA, RS, UI } }, 3115 3116{ "xori", OP(26), OP_MASK, PPCCOM, { RA, RS, UI } }, 3117{ "xoril", OP(26), OP_MASK, PWRCOM, { RA, RS, UI } }, 3118 3119{ "xoris", OP(27), OP_MASK, PPCCOM, { RA, RS, UI } }, 3120{ "xoriu", OP(27), OP_MASK, PWRCOM, { RA, RS, UI } }, 3121 3122{ "andi.", OP(28), OP_MASK, PPCCOM, { RA, RS, UI } }, 3123{ "andil.", OP(28), OP_MASK, PWRCOM, { RA, RS, UI } }, 3124 3125{ "andis.", OP(29), OP_MASK, PPCCOM, { RA, RS, UI } }, 3126{ "andiu.", OP(29), OP_MASK, PWRCOM, { RA, RS, UI } }, 3127 3128{ "rotldi", MD(30,0,0), MDMB_MASK, PPC64, { RA, RS, SH6 } }, 3129{ "clrldi", MD(30,0,0), MDSH_MASK, PPC64, { RA, RS, MB6 } }, 3130{ "rldicl", MD(30,0,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, 3131{ "rotldi.", MD(30,0,1), MDMB_MASK, PPC64, { RA, RS, SH6 } }, 3132{ "clrldi.", MD(30,0,1), MDSH_MASK, PPC64, { RA, RS, MB6 } }, 3133{ "rldicl.", MD(30,0,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, 3134 3135{ "rldicr", MD(30,1,0), MD_MASK, PPC64, { RA, RS, SH6, ME6 } }, 3136{ "rldicr.", MD(30,1,1), MD_MASK, PPC64, { RA, RS, SH6, ME6 } }, 3137 3138{ "rldic", MD(30,2,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, 3139{ "rldic.", MD(30,2,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, 3140 3141{ "rldimi", MD(30,3,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, 3142{ "rldimi.", MD(30,3,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, 3143 3144{ "rotld", MDS(30,8,0), MDSMB_MASK, PPC64, { RA, RS, RB } }, 3145{ "rldcl", MDS(30,8,0), MDS_MASK, PPC64, { RA, RS, RB, MB6 } }, 3146{ "rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, { RA, RS, RB } }, 3147{ "rldcl.", MDS(30,8,1), MDS_MASK, PPC64, { RA, RS, RB, MB6 } }, 3148 3149{ "rldcr", MDS(30,9,0), MDS_MASK, PPC64, { RA, RS, RB, ME6 } }, 3150{ "rldcr.", MDS(30,9,1), MDS_MASK, PPC64, { RA, RS, RB, ME6 } }, 3151 3152{ "cmpw", XCMPL(31,0,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } }, 3153{ "cmpd", XCMPL(31,0,1), XCMPL_MASK, PPC64, { OBF, RA, RB } }, 3154{ "cmp", X(31,0), XCMP_MASK, PPC, { BF, L, RA, RB } }, 3155{ "cmp", X(31,0), XCMPL_MASK, PWRCOM, { BF, RA, RB } }, 3156 3157{ "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, { RA, RB } }, 3158{ "tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, { RA, RB } }, 3159{ "twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, { RA, RB } }, 3160{ "tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, { RA, RB } }, 3161{ "tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, { RA, RB } }, 3162{ "teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, { RA, RB } }, 3163{ "twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, { RA, RB } }, 3164{ "tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, { RA, RB } }, 3165{ "twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, { RA, RB } }, 3166{ "tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, { RA, RB } }, 3167{ "twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, { RA, RB } }, 3168{ "tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, { RA, RB } }, 3169{ "twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, { RA, RB } }, 3170{ "tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, { RA, RB } }, 3171{ "twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, { RA, RB } }, 3172{ "tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, { RA, RB } }, 3173{ "twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, { RA, RB } }, 3174{ "tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, { RA, RB } }, 3175{ "twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, { RA, RB } }, 3176{ "tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, { RA, RB } }, 3177{ "twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, { RA, RB } }, 3178{ "tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, { RA, RB } }, 3179{ "twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, { RA, RB } }, 3180{ "tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, { RA, RB } }, 3181{ "twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, { RA, RB } }, 3182{ "tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, { RA, RB } }, 3183{ "twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, { RA, RB } }, 3184{ "tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, { RA, RB } }, 3185{ "trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, { 0 } }, 3186{ "tw", X(31,4), X_MASK, PPCCOM, { TO, RA, RB } }, 3187{ "t", X(31,4), X_MASK, PWRCOM, { TO, RA, RB } }, 3188 3189{ "subfc", XO(31,8,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, 3190{ "sf", XO(31,8,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, 3191{ "subc", XO(31,8,0,0), XO_MASK, PPC, { RT, RB, RA } }, 3192{ "subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, 3193{ "sf.", XO(31,8,0,1), XO_MASK, PWRCOM, { RT, RA, RB } }, 3194{ "subc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RB, RA } }, 3195{ "subfco", XO(31,8,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, 3196{ "sfo", XO(31,8,1,0), XO_MASK, PWRCOM, { RT, RA, RB } }, 3197{ "subco", XO(31,8,1,0), XO_MASK, PPC, { RT, RB, RA } }, 3198{ "subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, 3199{ "sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, 3200{ "subco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RB, RA } }, 3201 3202{ "mulhdu", XO(31,9,0,0), XO_MASK, PPC64, { RT, RA, RB } }, 3203{ "mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, { RT, RA, RB } }, 3204 3205{ "addc", XO(31,10,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, 3206{ "a", XO(31,10,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, 3207{ "addc.", XO(31,10,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, 3208{ "a.", XO(31,10,0,1), XO_MASK, PWRCOM, { RT, RA, RB } }, 3209{ "addco", XO(31,10,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, 3210{ "ao", XO(31,10,1,0), XO_MASK, PWRCOM, { RT, RA, RB } }, 3211{ "addco.", XO(31,10,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, 3212{ "ao.", XO(31,10,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, 3213 3214{ "mulhwu", XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB } }, 3215{ "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB } }, 3216 3217{ "isellt", X(31,15), X_MASK, PPCISEL, { RT, RA, RB } }, 3218{ "iselgt", X(31,47), X_MASK, PPCISEL, { RT, RA, RB } }, 3219{ "iseleq", X(31,79), X_MASK, PPCISEL, { RT, RA, RB } }, 3220{ "isel", XISEL(31,15), XISEL_MASK, PPCISEL, { RT, RA, RB, CRB } }, 3221 3222{ "mfcr", X(31,19), XRARB_MASK, NOPOWER4, { RT } }, 3223{ "mfcr", X(31,19), XFXFXM_MASK, POWER4, { RT, FXM4 } }, 3224 3225{ "lwarx", X(31,20), X_MASK, PPC, { RT, RA0, RB } }, 3226 3227{ "ldx", X(31,21), X_MASK, PPC64, { RT, RA0, RB } }, 3228 3229{ "icbt", X(31,22), X_MASK, BOOKE, { CT, RA, RB } }, 3230{ "icbt", X(31,262), XRT_MASK, PPC403, { RA, RB } }, 3231 3232{ "lwzx", X(31,23), X_MASK, PPCCOM, { RT, RA0, RB } }, 3233{ "lx", X(31,23), X_MASK, PWRCOM, { RT, RA, RB } }, 3234 3235{ "slw", XRC(31,24,0), X_MASK, PPCCOM, { RA, RS, RB } }, 3236{ "sl", XRC(31,24,0), X_MASK, PWRCOM, { RA, RS, RB } }, 3237{ "slw.", XRC(31,24,1), X_MASK, PPCCOM, { RA, RS, RB } }, 3238{ "sl.", XRC(31,24,1), X_MASK, PWRCOM, { RA, RS, RB } }, 3239 3240{ "cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, { RA, RS } }, 3241{ "cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, { RA, RS } }, 3242{ "cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, { RA, RS } }, 3243{ "cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, { RA, RS } }, 3244 3245{ "sld", XRC(31,27,0), X_MASK, PPC64, { RA, RS, RB } }, 3246{ "sld.", XRC(31,27,1), X_MASK, PPC64, { RA, RS, RB } }, 3247 3248{ "and", XRC(31,28,0), X_MASK, COM, { RA, RS, RB } }, 3249{ "and.", XRC(31,28,1), X_MASK, COM, { RA, RS, RB } }, 3250 3251{ "maskg", XRC(31,29,0), X_MASK, M601, { RA, RS, RB } }, 3252{ "maskg.", XRC(31,29,1), X_MASK, M601, { RA, RS, RB } }, 3253 3254{ "icbte", X(31,30), X_MASK, BOOKE64, { CT, RA, RB } }, 3255 3256{ "lwzxe", X(31,31), X_MASK, BOOKE64, { RT, RA0, RB } }, 3257 3258{ "cmplw", XCMPL(31,32,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } }, 3259{ "cmpld", XCMPL(31,32,1), XCMPL_MASK, PPC64, { OBF, RA, RB } }, 3260{ "cmpl", X(31,32), XCMP_MASK, PPC, { BF, L, RA, RB } }, 3261{ "cmpl", X(31,32), XCMPL_MASK, PWRCOM, { BF, RA, RB } }, 3262 3263{ "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } }, 3264{ "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } }, 3265{ "subf.", XO(31,40,0,1), XO_MASK, PPC, { RT, RA, RB } }, 3266{ "sub.", XO(31,40,0,1), XO_MASK, PPC, { RT, RB, RA } }, 3267{ "subfo", XO(31,40,1,0), XO_MASK, PPC, { RT, RA, RB } }, 3268{ "subo", XO(31,40,1,0), XO_MASK, PPC, { RT, RB, RA } }, 3269{ "subfo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RA, RB } }, 3270{ "subo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RB, RA } }, 3271 3272{ "ldux", X(31,53), X_MASK, PPC64, { RT, RAL, RB } }, 3273 3274{ "dcbst", X(31,54), XRT_MASK, PPC, { RA, RB } }, 3275 3276{ "lwzux", X(31,55), X_MASK, PPCCOM, { RT, RAL, RB } }, 3277{ "lux", X(31,55), X_MASK, PWRCOM, { RT, RA, RB } }, 3278 3279{ "dcbste", X(31,62), XRT_MASK, BOOKE64, { RA, RB } }, 3280 3281{ "lwzuxe", X(31,63), X_MASK, BOOKE64, { RT, RAL, RB } }, 3282 3283{ "cntlzd", XRC(31,58,0), XRB_MASK, PPC64, { RA, RS } }, 3284{ "cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, { RA, RS } }, 3285 3286{ "andc", XRC(31,60,0), X_MASK, COM, { RA, RS, RB } }, 3287{ "andc.", XRC(31,60,1), X_MASK, COM, { RA, RS, RB } }, 3288 3289{ "tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, { RA, RB } }, 3290{ "tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, { RA, RB } }, 3291{ "tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, { RA, RB } }, 3292{ "tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, { RA, RB } }, 3293{ "tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, { RA, RB } }, 3294{ "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, { RA, RB } }, 3295{ "tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, { RA, RB } }, 3296{ "tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, { RA, RB } }, 3297{ "tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, { RA, RB } }, 3298{ "tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, { RA, RB } }, 3299{ "tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, { RA, RB } }, 3300{ "tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, { RA, RB } }, 3301{ "tdng", XTO(31,68,TONG), XTO_MASK, PPC64, { RA, RB } }, 3302{ "tdne", XTO(31,68,TONE), XTO_MASK, PPC64, { RA, RB } }, 3303{ "td", X(31,68), X_MASK, PPC64, { TO, RA, RB } }, 3304 3305{ "mulhd", XO(31,73,0,0), XO_MASK, PPC64, { RT, RA, RB } }, 3306{ "mulhd.", XO(31,73,0,1), XO_MASK, PPC64, { RT, RA, RB } }, 3307 3308{ "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } }, 3309{ "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } }, 3310 3311{ "dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440, { RA, RS, RB } }, 3312{ "dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440, { RA, RS, RB } }, 3313 3314{ "mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, { SR, RS } }, 3315 3316{ "mfmsr", X(31,83), XRARB_MASK, COM, { RT } }, 3317 3318{ "ldarx", X(31,84), X_MASK, PPC64, { RT, RA0, RB } }, 3319 3320{ "dcbf", X(31,86), XRT_MASK, PPC, { RA, RB } }, 3321 3322{ "lbzx", X(31,87), X_MASK, COM, { RT, RA0, RB } }, 3323 3324{ "dcbfe", X(31,94), XRT_MASK, BOOKE64, { RA, RB } }, 3325 3326{ "lbzxe", X(31,95), X_MASK, BOOKE64, { RT, RA0, RB } }, 3327 3328{ "neg", XO(31,104,0,0), XORB_MASK, COM, { RT, RA } }, 3329{ "neg.", XO(31,104,0,1), XORB_MASK, COM, { RT, RA } }, 3330{ "nego", XO(31,104,1,0), XORB_MASK, COM, { RT, RA } }, 3331{ "nego.", XO(31,104,1,1), XORB_MASK, COM, { RT, RA } }, 3332 3333{ "mul", XO(31,107,0,0), XO_MASK, M601, { RT, RA, RB } }, 3334{ "mul.", XO(31,107,0,1), XO_MASK, M601, { RT, RA, RB } }, 3335{ "mulo", XO(31,107,1,0), XO_MASK, M601, { RT, RA, RB } }, 3336{ "mulo.", XO(31,107,1,1), XO_MASK, M601, { RT, RA, RB } }, 3337 3338{ "mtsrdin", X(31,114), XRA_MASK, PPC64, { RS, RB } }, 3339 3340{ "clf", X(31,118), XTO_MASK, POWER, { RA, RB } }, 3341 3342{ "lbzux", X(31,119), X_MASK, COM, { RT, RAL, RB } }, 3343 3344{ "not", XRC(31,124,0), X_MASK, COM, { RA, RS, RBS } }, 3345{ "nor", XRC(31,124,0), X_MASK, COM, { RA, RS, RB } }, 3346{ "not.", XRC(31,124,1), X_MASK, COM, { RA, RS, RBS } }, 3347{ "nor.", XRC(31,124,1), X_MASK, COM, { RA, RS, RB } }, 3348 3349{ "lwarxe", X(31,126), X_MASK, BOOKE64, { RT, RA0, RB } }, 3350 3351{ "lbzuxe", X(31,127), X_MASK, BOOKE64, { RT, RAL, RB } }, 3352 3353{ "wrtee", X(31,131), XRARB_MASK, PPC403 | BOOKE, { RS } }, 3354 3355{ "dcbtstls",X(31,134), X_MASK, PPCCHLK, { CT, RA, RB }}, 3356 3357{ "subfe", XO(31,136,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, 3358{ "sfe", XO(31,136,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, 3359{ "subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, 3360{ "sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, { RT, RA, RB } }, 3361{ "subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, 3362{ "sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, { RT, RA, RB } }, 3363{ "subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, 3364{ "sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, 3365 3366{ "adde", XO(31,138,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, 3367{ "ae", XO(31,138,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, 3368{ "adde.", XO(31,138,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, 3369{ "ae.", XO(31,138,0,1), XO_MASK, PWRCOM, { RT, RA, RB } }, 3370{ "addeo", XO(31,138,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, 3371{ "aeo", XO(31,138,1,0), XO_MASK, PWRCOM, { RT, RA, RB } }, 3372{ "addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, 3373{ "aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, 3374 3375{ "dcbtstlse",X(31,142),X_MASK, PPCCHLK64, { CT, RA, RB }}, 3376 3377{ "mtcr", XFXM(31,144,0xff), XRARB_MASK, COM, { RS }}, 3378{ "mtcrf", X(31,144), XFXFXM_MASK, COM, { FXM, RS } }, 3379 3380{ "mtmsr", X(31,146), XRARB_MASK, COM, { RS } }, 3381 3382{ "stdx", X(31,149), X_MASK, PPC64, { RS, RA0, RB } }, 3383 3384{ "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA0, RB } }, 3385 3386{ "stwx", X(31,151), X_MASK, PPCCOM, { RS, RA0, RB } }, 3387{ "stx", X(31,151), X_MASK, PWRCOM, { RS, RA, RB } }, 3388 3389{ "stwcxe.", XRC(31,158,1), X_MASK, BOOKE64, { RS, RA0, RB } }, 3390 3391{ "stwxe", X(31,159), X_MASK, BOOKE64, { RS, RA0, RB } }, 3392 3393{ "slq", XRC(31,152,0), X_MASK, M601, { RA, RS, RB } }, 3394{ "slq.", XRC(31,152,1), X_MASK, M601, { RA, RS, RB } }, 3395 3396{ "sle", XRC(31,153,0), X_MASK, M601, { RA, RS, RB } }, 3397{ "sle.", XRC(31,153,1), X_MASK, M601, { RA, RS, RB } }, 3398 3399{ "wrteei", X(31,163), XE_MASK, PPC403 | BOOKE, { E } }, 3400 3401{ "dcbtls", X(31,166), X_MASK, PPCCHLK, { CT, RA, RB }}, 3402{ "dcbtlse", X(31,174), X_MASK, PPCCHLK64, { CT, RA, RB }}, 3403 3404{ "mtmsrd", X(31,178), XRLARB_MASK, PPC64, { RS, MTMSRD_L } }, 3405 3406{ "stdux", X(31,181), X_MASK, PPC64, { RS, RAS, RB } }, 3407 3408{ "stwux", X(31,183), X_MASK, PPCCOM, { RS, RAS, RB } }, 3409{ "stux", X(31,183), X_MASK, PWRCOM, { RS, RA0, RB } }, 3410 3411{ "sliq", XRC(31,184,0), X_MASK, M601, { RA, RS, SH } }, 3412{ "sliq.", XRC(31,184,1), X_MASK, M601, { RA, RS, SH } }, 3413 3414{ "stwuxe", X(31,191), X_MASK, BOOKE64, { RS, RAS, RB } }, 3415 3416{ "subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, { RT, RA } }, 3417{ "sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, { RT, RA } }, 3418{ "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, { RT, RA } }, 3419{ "sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, { RT, RA } }, 3420{ "subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, { RT, RA } }, 3421{ "sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, { RT, RA } }, 3422{ "subfzeo.",XO(31,200,1,1), XORB_MASK, PPCCOM, { RT, RA } }, 3423{ "sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, { RT, RA } }, 3424 3425{ "addze", XO(31,202,0,0), XORB_MASK, PPCCOM, { RT, RA } }, 3426{ "aze", XO(31,202,0,0), XORB_MASK, PWRCOM, { RT, RA } }, 3427{ "addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, { RT, RA } }, 3428{ "aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, { RT, RA } }, 3429{ "addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, { RT, RA } }, 3430{ "azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, { RT, RA } }, 3431{ "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, { RT, RA } }, 3432{ "azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, { RT, RA } }, 3433 3434{ "mtsr", X(31,210), XRB_MASK|(1<<20), COM32, { SR, RS } }, 3435 3436{ "stdcx.", XRC(31,214,1), X_MASK, PPC64, { RS, RA0, RB } }, 3437 3438{ "stbx", X(31,215), X_MASK, COM, { RS, RA0, RB } }, 3439 3440{ "sllq", XRC(31,216,0), X_MASK, M601, { RA, RS, RB } }, 3441{ "sllq.", XRC(31,216,1), X_MASK, M601, { RA, RS, RB } }, 3442 3443{ "sleq", XRC(31,217,0), X_MASK, M601, { RA, RS, RB } }, 3444{ "sleq.", XRC(31,217,1), X_MASK, M601, { RA, RS, RB } }, 3445 3446{ "stbxe", X(31,223), X_MASK, BOOKE64, { RS, RA0, RB } }, 3447 3448{ "icblc", X(31,230), X_MASK, PPCCHLK, { CT, RA, RB }}, 3449 3450{ "subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, { RT, RA } }, 3451{ "sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, { RT, RA } }, 3452{ "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, { RT, RA } }, 3453{ "sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, { RT, RA } }, 3454{ "subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, { RT, RA } }, 3455{ "sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, { RT, RA } }, 3456{ "subfmeo.",XO(31,232,1,1), XORB_MASK, PPCCOM, { RT, RA } }, 3457{ "sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, { RT, RA } }, 3458 3459{ "mulld", XO(31,233,0,0), XO_MASK, PPC64, { RT, RA, RB } }, 3460{ "mulld.", XO(31,233,0,1), XO_MASK, PPC64, { RT, RA, RB } }, 3461{ "mulldo", XO(31,233,1,0), XO_MASK, PPC64, { RT, RA, RB } }, 3462{ "mulldo.", XO(31,233,1,1), XO_MASK, PPC64, { RT, RA, RB } }, 3463 3464{ "addme", XO(31,234,0,0), XORB_MASK, PPCCOM, { RT, RA } }, 3465{ "ame", XO(31,234,0,0), XORB_MASK, PWRCOM, { RT, RA } }, 3466{ "addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, { RT, RA } }, 3467{ "ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, { RT, RA } }, 3468{ "addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, { RT, RA } }, 3469{ "ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, { RT, RA } }, 3470{ "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, { RT, RA } }, 3471{ "ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, { RT, RA } }, 3472 3473{ "mullw", XO(31,235,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, 3474{ "muls", XO(31,235,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, 3475{ "mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, 3476{ "muls.", XO(31,235,0,1), XO_MASK, PWRCOM, { RT, RA, RB } }, 3477{ "mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, 3478{ "mulso", XO(31,235,1,0), XO_MASK, PWRCOM, { RT, RA, RB } }, 3479{ "mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, 3480{ "mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, 3481 3482{ "icblce", X(31,238), X_MASK, PPCCHLK64, { CT, RA, RB }}, 3483{ "mtsrin", X(31,242), XRA_MASK, PPC32, { RS, RB } }, 3484{ "mtsri", X(31,242), XRA_MASK, POWER32, { RS, RB } }, 3485 3486{ "dcbtst", X(31,246), X_MASK, PPC, { CT, RA, RB } }, 3487 3488{ "stbux", X(31,247), X_MASK, COM, { RS, RAS, RB } }, 3489 3490{ "slliq", XRC(31,248,0), X_MASK, M601, { RA, RS, SH } }, 3491{ "slliq.", XRC(31,248,1), X_MASK, M601, { RA, RS, SH } }, 3492 3493{ "dcbtste", X(31,253), X_MASK, BOOKE64, { CT, RA, RB } }, 3494 3495{ "stbuxe", X(31,255), X_MASK, BOOKE64, { RS, RAS, RB } }, 3496 3497{ "mfdcrx", X(31,259), X_MASK, BOOKE, { RS, RA } }, 3498 3499{ "doz", XO(31,264,0,0), XO_MASK, M601, { RT, RA, RB } }, 3500{ "doz.", XO(31,264,0,1), XO_MASK, M601, { RT, RA, RB } }, 3501{ "dozo", XO(31,264,1,0), XO_MASK, M601, { RT, RA, RB } }, 3502{ "dozo.", XO(31,264,1,1), XO_MASK, M601, { RT, RA, RB } }, 3503 3504{ "add", XO(31,266,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, 3505{ "cax", XO(31,266,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, 3506{ "add.", XO(31,266,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, 3507{ "cax.", XO(31,266,0,1), XO_MASK, PWRCOM, { RT, RA, RB } }, 3508{ "addo", XO(31,266,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, 3509{ "caxo", XO(31,266,1,0), XO_MASK, PWRCOM, { RT, RA, RB } }, 3510{ "addo.", XO(31,266,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, 3511{ "caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, 3512 3513{ "tlbiel", X(31,274), XRTRA_MASK, POWER4, { RB } }, 3514 3515{ "mfapidi", X(31,275), X_MASK, BOOKE, { RT, RA } }, 3516 3517{ "lscbx", XRC(31,277,0), X_MASK, M601, { RT, RA, RB } }, 3518{ "lscbx.", XRC(31,277,1), X_MASK, M601, { RT, RA, RB } }, 3519 3520{ "dcbt", X(31,278), X_MASK, PPC, { CT, RA, RB } }, 3521 3522{ "lhzx", X(31,279), X_MASK, COM, { RT, RA0, RB } }, 3523 3524{ "eqv", XRC(31,284,0), X_MASK, COM, { RA, RS, RB } }, 3525{ "eqv.", XRC(31,284,1), X_MASK, COM, { RA, RS, RB } }, 3526 3527{ "dcbte", X(31,286), X_MASK, BOOKE64, { CT, RA, RB } }, 3528 3529{ "lhzxe", X(31,287), X_MASK, BOOKE64, { RT, RA0, RB } }, 3530 3531{ "tlbie", X(31,306), XRTLRA_MASK, PPC, { RB, L } }, 3532{ "tlbi", X(31,306), XRT_MASK, POWER, { RA0, RB } }, 3533 3534{ "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } }, 3535 3536{ "lhzux", X(31,311), X_MASK, COM, { RT, RAL, RB } }, 3537 3538{ "xor", XRC(31,316,0), X_MASK, COM, { RA, RS, RB } }, 3539{ "xor.", XRC(31,316,1), X_MASK, COM, { RA, RS, RB } }, 3540 3541{ "lhzuxe", X(31,319), X_MASK, BOOKE64, { RT, RAL, RB } }, 3542 3543{ "mfexisr", XSPR(31,323,64), XSPR_MASK, PPC403, { RT } }, 3544{ "mfexier", XSPR(31,323,66), XSPR_MASK, PPC403, { RT } }, 3545{ "mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, { RT } }, 3546{ "mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, { RT } }, 3547{ "mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, { RT } }, 3548{ "mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, { RT } }, 3549{ "mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, { RT } }, 3550{ "mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, { RT } }, 3551{ "mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, { RT } }, 3552{ "mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, { RT } }, 3553{ "mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, { RT } }, 3554{ "mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, { RT } }, 3555{ "mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, { RT } }, 3556{ "mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, { RT } }, 3557{ "mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, { RT } }, 3558{ "mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, { RT } }, 3559{ "mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, { RT } }, 3560{ "mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, { RT } }, 3561{ "mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, { RT } }, 3562{ "mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, { RT } }, 3563{ "mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, { RT } }, 3564{ "mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, { RT } }, 3565{ "mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, { RT } }, 3566{ "mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, { RT } }, 3567{ "mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, { RT } }, 3568{ "mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, { RT } }, 3569{ "mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, { RT } }, 3570{ "mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, { RT } }, 3571{ "mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, { RT } }, 3572{ "mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, { RT } }, 3573{ "mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, { RT } }, 3574{ "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, { RT } }, 3575{ "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, { RT } }, 3576{ "mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, { RT } }, 3577{ "mfdcr", X(31,323), X_MASK, PPC403 | BOOKE, { RT, SPR } }, 3578 3579{ "div", XO(31,331,0,0), XO_MASK, M601, { RT, RA, RB } }, 3580{ "div.", XO(31,331,0,1), XO_MASK, M601, { RT, RA, RB } }, 3581{ "divo", XO(31,331,1,0), XO_MASK, M601, { RT, RA, RB } }, 3582{ "divo.", XO(31,331,1,1), XO_MASK, M601, { RT, RA, RB } }, 3583 3584{ "mfpmr", X(31,334), X_MASK, PPCPMR, { RT, PMR }}, 3585 3586{ "mfmq", XSPR(31,339,0), XSPR_MASK, M601, { RT } }, 3587{ "mfxer", XSPR(31,339,1), XSPR_MASK, COM, { RT } }, 3588{ "mfrtcu", XSPR(31,339,4), XSPR_MASK, COM, { RT } }, 3589{ "mfrtcl", XSPR(31,339,5), XSPR_MASK, COM, { RT } }, 3590{ "mfdec", XSPR(31,339,6), XSPR_MASK, MFDEC1, { RT } }, 3591{ "mfdec", XSPR(31,339,22), XSPR_MASK, MFDEC2, { RT } }, 3592{ "mflr", XSPR(31,339,8), XSPR_MASK, COM, { RT } }, 3593{ "mfctr", XSPR(31,339,9), XSPR_MASK, COM, { RT } }, 3594{ "mftid", XSPR(31,339,17), XSPR_MASK, POWER, { RT } }, 3595{ "mfdsisr", XSPR(31,339,18), XSPR_MASK, COM, { RT } }, 3596{ "mfdar", XSPR(31,339,19), XSPR_MASK, COM, { RT } }, 3597{ "mfsdr0", XSPR(31,339,24), XSPR_MASK, POWER, { RT } }, 3598{ "mfsdr1", XSPR(31,339,25), XSPR_MASK, COM, { RT } }, 3599{ "mfsrr0", XSPR(31,339,26), XSPR_MASK, COM, { RT } }, 3600{ "mfsrr1", XSPR(31,339,27), XSPR_MASK, COM, { RT } }, 3601{ "mfpid", XSPR(31,339,48), XSPR_MASK, BOOKE, { RT } }, 3602{ "mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, { RT } }, 3603{ "mfcsrr0", XSPR(31,339,58), XSPR_MASK, BOOKE, { RT } }, 3604{ "mfcsrr1", XSPR(31,339,59), XSPR_MASK, BOOKE, { RT } }, 3605{ "mfdear", XSPR(31,339,61), XSPR_MASK, BOOKE, { RT } }, 3606{ "mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, { RT } }, 3607{ "mfesr", XSPR(31,339,62), XSPR_MASK, BOOKE, { RT } }, 3608{ "mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, { RT } }, 3609{ "mfivpr", XSPR(31,339,63), XSPR_MASK, BOOKE, { RT } }, 3610{ "mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, { RT } }, 3611{ "mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, { RT } }, 3612{ "mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, { RT } }, 3613{ "mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, { RT } }, 3614{ "mficr", XSPR(31,339,148), XSPR_MASK, PPC860, { RT } }, 3615{ "mfder", XSPR(31,339,149), XSPR_MASK, PPC860, { RT } }, 3616{ "mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, { RT } }, 3617{ "mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, { RT } }, 3618{ "mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, { RT } }, 3619{ "mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, { RT } }, 3620{ "mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, { RT } }, 3621{ "mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, { RT } }, 3622{ "mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, { RT } }, 3623{ "mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, { RT } }, 3624{ "mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, { RT } }, 3625{ "mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, { RT } }, 3626{ "mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, { RT } }, 3627{ "mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, { RT } }, 3628{ "mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405, { RT } }, 3629{ "mfsprg4", XSPR(31,339,260), XSPR_MASK, BOOKE, { RT } }, 3630{ "mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405, { RT } }, 3631{ "mfsprg5", XSPR(31,339,261), XSPR_MASK, BOOKE, { RT } }, 3632{ "mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405, { RT } }, 3633{ "mfsprg6", XSPR(31,339,262), XSPR_MASK, BOOKE, { RT } }, 3634{ "mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405, { RT } }, 3635{ "mfsprg7", XSPR(31,339,263), XSPR_MASK, BOOKE, { RT } }, 3636{ "mftb", X(31,371), X_MASK, CLASSIC, { RT, TBR } }, 3637{ "mftb", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } }, 3638{ "mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, { RT } }, 3639{ "mftbl", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } }, 3640{ "mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, { RT } }, 3641{ "mftbu", XSPR(31,339,269), XSPR_MASK, BOOKE, { RT } }, 3642{ "mfsprg", XSPR(31,339,272), XSPRG_MASK, PPC, { RT, SPRG } }, 3643{ "mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, { RT } }, 3644{ "mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, { RT } }, 3645{ "mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, { RT } }, 3646{ "mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, { RT } }, 3647{ "mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, { RT } }, 3648{ "mfear", XSPR(31,339,282), XSPR_MASK, PPC, { RT } }, 3649{ "mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, { RT } }, 3650{ "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, { RT } }, 3651{ "mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, { RT } }, 3652{ "mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, { RT } }, 3653{ "mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, { RT } }, 3654{ "mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, { RT } }, 3655{ "mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, { RT } }, 3656{ "mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, { RT } }, 3657{ "mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, { RT } }, 3658{ "mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, { RT } }, 3659{ "mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, { RT } }, 3660{ "mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, { RT } }, 3661{ "mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, { RT } }, 3662{ "mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, { RT } }, 3663{ "mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, { RT } }, 3664{ "mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, { RT } }, 3665{ "mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, { RT } }, 3666{ "mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, { RT } }, 3667{ "mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, { RT } }, 3668{ "mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, { RT } }, 3669{ "mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, { RT } }, 3670{ "mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, { RT } }, 3671{ "mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, { RT } }, 3672{ "mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, { RT } }, 3673{ "mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, { RT } }, 3674{ "mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, { RT } }, 3675{ "mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, { RT } }, 3676{ "mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, { RT } }, 3677{ "mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, { RT } }, 3678{ "mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, { RT } }, 3679{ "mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, { RT } }, 3680{ "mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, { RT } }, 3681{ "mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, { RT } }, 3682{ "mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, { RT } }, 3683{ "mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, { RT } }, 3684{ "mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, { RT } }, 3685{ "mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, { RT } }, 3686{ "mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, { RT } }, 3687{ "mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, { RT } }, 3688{ "mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, { RT } }, 3689{ "mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, { RT } }, 3690{ "mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, { RT } }, 3691{ "mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, { RT } }, 3692{ "mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, { RT } }, 3693{ "mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, { RT } }, 3694{ "mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, { RT } }, 3695{ "mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, { RT } }, 3696{ "mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, { RT } }, 3697{ "mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE, { RT } }, 3698{ "mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE, { RT } }, 3699{ "mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, { RT } }, 3700{ "mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, { RT } }, 3701{ "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, 3702{ "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, 3703{ "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, 3704{ "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, 3705{ "mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, { RT } }, 3706{ "mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, { RT } }, 3707{ "mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, { RT } }, 3708{ "mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, { RT } }, 3709{ "mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, { RT } }, 3710{ "mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, { RT } }, 3711{ "mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, { RT } }, 3712{ "mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, { RT } }, 3713{ "mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, { RT } }, 3714{ "mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, { RT } }, 3715{ "mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, { RT } }, 3716{ "mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, { RT } }, 3717{ "mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, { RT } }, 3718{ "mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, { RT } }, 3719{ "mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, { RT } }, 3720{ "mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, { RT } }, 3721{ "mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, { RT } }, 3722{ "mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, { RT } }, 3723{ "mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, { RT } }, 3724{ "mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, { RT } }, 3725{ "mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, { RT } }, 3726{ "mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, { RT } }, 3727{ "mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, { RT } }, 3728{ "mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, { RT } }, 3729{ "mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, { RT } }, 3730{ "mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, { RT } }, 3731{ "mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, { RT } }, 3732{ "mfmi_dbram0",XSPR(31,339,817), XSPR_MASK, PPC860, { RT } }, 3733{ "mfmi_dbram1",XSPR(31,339,818), XSPR_MASK, PPC860, { RT } }, 3734{ "mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, { RT } }, 3735{ "mfmd_dbram0",XSPR(31,339,825), XSPR_MASK, PPC860, { RT } }, 3736{ "mfmd_dbram1",XSPR(31,339,826), XSPR_MASK, PPC860, { RT } }, 3737{ "mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, { RT } }, 3738{ "mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, { RT } }, 3739{ "mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, { RT } }, 3740{ "mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, { RT } }, 3741{ "mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, { RT } }, 3742{ "mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, { RT } }, 3743{ "mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, { RT } }, 3744{ "mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, { RT } }, 3745{ "mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405, { RT } }, 3746{ "mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, { RT } }, 3747{ "mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, { RT } }, 3748{ "mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, { RT } }, 3749{ "mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, { RT } }, 3750{ "mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, { RT } }, 3751{ "mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, { RT } }, 3752{ "mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, { RT } }, 3753{ "mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, { RT } }, 3754{ "mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, { RT } }, 3755{ "mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, { RT } }, 3756{ "mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, { RT } }, 3757{ "mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403, { RT } }, 3758{ "mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, { RT } }, 3759{ "mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, { RT } }, 3760{ "mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, { RT } }, 3761{ "mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, { RT } }, 3762{ "mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, { RT } }, 3763{ "mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, { RT } }, 3764{ "mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, { RT } }, 3765{ "mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, { RT } }, 3766{ "mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, { RT } }, 3767{ "mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, { RT } }, 3768{ "mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, { RT } }, 3769{ "mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, { RT } }, 3770{ "mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, { RT } }, 3771{ "mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, { RT } }, 3772{ "mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, { RT } }, 3773{ "mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, { RT } }, 3774{ "mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, { RT } }, 3775{ "mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, { RT } }, 3776{ "mfspr", X(31,339), X_MASK, COM, { RT, SPR } }, 3777 3778{ "lwax", X(31,341), X_MASK, PPC64, { RT, RA0, RB } }, 3779 3780{ "dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } }, 3781{ "dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } }, 3782 3783{ "lhax", X(31,343), X_MASK, COM, { RT, RA0, RB } }, 3784 3785{ "lhaxe", X(31,351), X_MASK, BOOKE64, { RT, RA0, RB } }, 3786 3787{ "dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } }, 3788{ "dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } }, 3789 3790{ "dccci", X(31,454), XRT_MASK, PPC403|PPC440, { RA, RB } }, 3791 3792{ "abs", XO(31,360,0,0), XORB_MASK, M601, { RT, RA } }, 3793{ "abs.", XO(31,360,0,1), XORB_MASK, M601, { RT, RA } }, 3794{ "abso", XO(31,360,1,0), XORB_MASK, M601, { RT, RA } }, 3795{ "abso.", XO(31,360,1,1), XORB_MASK, M601, { RT, RA } }, 3796 3797{ "divs", XO(31,363,0,0), XO_MASK, M601, { RT, RA, RB } }, 3798{ "divs.", XO(31,363,0,1), XO_MASK, M601, { RT, RA, RB } }, 3799{ "divso", XO(31,363,1,0), XO_MASK, M601, { RT, RA, RB } }, 3800{ "divso.", XO(31,363,1,1), XO_MASK, M601, { RT, RA, RB } }, 3801 3802{ "tlbia", X(31,370), 0xffffffff, PPC, { 0 } }, 3803 3804{ "lwaux", X(31,373), X_MASK, PPC64, { RT, RAL, RB } }, 3805 3806{ "lhaux", X(31,375), X_MASK, COM, { RT, RAL, RB } }, 3807 3808{ "lhauxe", X(31,383), X_MASK, BOOKE64, { RT, RAL, RB } }, 3809 3810{ "mtdcrx", X(31,387), X_MASK, BOOKE, { RA, RS } }, 3811 3812{ "dcblc", X(31,390), X_MASK, PPCCHLK, { CT, RA, RB }}, 3813 3814{ "subfe64", XO(31,392,0,0), XO_MASK, BOOKE64, { RT, RA, RB } }, 3815{ "subfe64o",XO(31,392,1,0), XO_MASK, BOOKE64, { RT, RA, RB } }, 3816 3817{ "adde64", XO(31,394,0,0), XO_MASK, BOOKE64, { RT, RA, RB } }, 3818{ "adde64o", XO(31,394,1,0), XO_MASK, BOOKE64, { RT, RA, RB } }, 3819 3820{ "dcblce", X(31,398), X_MASK, PPCCHLK64, { CT, RA, RB }}, 3821 3822{ "slbmte", X(31,402), XRA_MASK, PPC64, { RS, RB } }, 3823 3824{ "sthx", X(31,407), X_MASK, COM, { RS, RA0, RB } }, 3825 3826{ "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } }, 3827 3828{ "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB } }, 3829 3830{ "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB } }, 3831 3832{ "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB } }, 3833 3834{ "orc", XRC(31,412,0), X_MASK, COM, { RA, RS, RB } }, 3835{ "orc.", XRC(31,412,1), X_MASK, COM, { RA, RS, RB } }, 3836 3837{ "sradi", XS(31,413,0), XS_MASK, PPC64, { RA, RS, SH6 } }, 3838{ "sradi.", XS(31,413,1), XS_MASK, PPC64, { RA, RS, SH6 } }, 3839 3840{ "sthxe", X(31,415), X_MASK, BOOKE64, { RS, RA0, RB } }, 3841 3842{ "slbie", X(31,434), XRTRA_MASK, PPC64, { RB } }, 3843 3844{ "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } }, 3845 3846{ "sthux", X(31,439), X_MASK, COM, { RS, RAS, RB } }, 3847 3848{ "sthuxe", X(31,447), X_MASK, BOOKE64, { RS, RAS, RB } }, 3849 3850{ "mr", XRC(31,444,0), X_MASK, COM, { RA, RS, RBS } }, 3851{ "or", XRC(31,444,0), X_MASK, COM, { RA, RS, RB } }, 3852{ "mr.", XRC(31,444,1), X_MASK, COM, { RA, RS, RBS } }, 3853{ "or.", XRC(31,444,1), X_MASK, COM, { RA, RS, RB } }, 3854 3855{ "mtexisr", XSPR(31,451,64), XSPR_MASK, PPC403, { RS } }, 3856{ "mtexier", XSPR(31,451,66), XSPR_MASK, PPC403, { RS } }, 3857{ "mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, { RS } }, 3858{ "mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, { RS } }, 3859{ "mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, { RS } }, 3860{ "mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, { RS } }, 3861{ "mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, { RS } }, 3862{ "mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, { RS } }, 3863{ "mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, { RS } }, 3864{ "mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, { RS } }, 3865{ "mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, { RS } }, 3866{ "mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, { RS } }, 3867{ "mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, { RS } }, 3868{ "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, { RS } }, 3869{ "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, { RS } }, 3870{ "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, { RS } }, 3871{ "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, { RS } }, 3872{ "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, { RS } }, 3873{ "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, { RS } }, 3874{ "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, { RS } }, 3875{ "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, { RS } }, 3876{ "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, { RS } }, 3877{ "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, { RS } }, 3878{ "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, { RS } }, 3879{ "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, { RS } }, 3880{ "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, { RS } }, 3881{ "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, { RS } }, 3882{ "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, { RS } }, 3883{ "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, { RS } }, 3884{ "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, { RS } }, 3885{ "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, { RS } }, 3886{ "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, { RS } }, 3887{ "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, { RS } }, 3888{ "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, { RS } }, 3889{ "mtdcr", X(31,451), X_MASK, PPC403 | BOOKE, { SPR, RS } }, 3890 3891{ "subfze64",XO(31,456,0,0), XORB_MASK, BOOKE64, { RT, RA } }, 3892{ "subfze64o",XO(31,456,1,0), XORB_MASK, BOOKE64, { RT, RA } }, 3893 3894{ "divdu", XO(31,457,0,0), XO_MASK, PPC64, { RT, RA, RB } }, 3895{ "divdu.", XO(31,457,0,1), XO_MASK, PPC64, { RT, RA, RB } }, 3896{ "divduo", XO(31,457,1,0), XO_MASK, PPC64, { RT, RA, RB } }, 3897{ "divduo.", XO(31,457,1,1), XO_MASK, PPC64, { RT, RA, RB } }, 3898 3899{ "addze64", XO(31,458,0,0), XORB_MASK, BOOKE64, { RT, RA } }, 3900{ "addze64o",XO(31,458,1,0), XORB_MASK, BOOKE64, { RT, RA } }, 3901 3902{ "divwu", XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB } }, 3903{ "divwu.", XO(31,459,0,1), XO_MASK, PPC, { RT, RA, RB } }, 3904{ "divwuo", XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB } }, 3905{ "divwuo.", XO(31,459,1,1), XO_MASK, PPC, { RT, RA, RB } }, 3906 3907{ "mtmq", XSPR(31,467,0), XSPR_MASK, M601, { RS } }, 3908{ "mtxer", XSPR(31,467,1), XSPR_MASK, COM, { RS } }, 3909{ "mtlr", XSPR(31,467,8), XSPR_MASK, COM, { RS } }, 3910{ "mtctr", XSPR(31,467,9), XSPR_MASK, COM, { RS } }, 3911{ "mttid", XSPR(31,467,17), XSPR_MASK, POWER, { RS } }, 3912{ "mtdsisr", XSPR(31,467,18), XSPR_MASK, COM, { RS } }, 3913{ "mtdar", XSPR(31,467,19), XSPR_MASK, COM, { RS } }, 3914{ "mtrtcu", XSPR(31,467,20), XSPR_MASK, COM, { RS } }, 3915{ "mtrtcl", XSPR(31,467,21), XSPR_MASK, COM, { RS } }, 3916{ "mtdec", XSPR(31,467,22), XSPR_MASK, COM, { RS } }, 3917{ "mtsdr0", XSPR(31,467,24), XSPR_MASK, POWER, { RS } }, 3918{ "mtsdr1", XSPR(31,467,25), XSPR_MASK, COM, { RS } }, 3919{ "mtsrr0", XSPR(31,467,26), XSPR_MASK, COM, { RS } }, 3920{ "mtsrr1", XSPR(31,467,27), XSPR_MASK, COM, { RS } }, 3921{ "mtpid", XSPR(31,467,48), XSPR_MASK, BOOKE, { RS } }, 3922{ "mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, { RS } }, 3923{ "mtdecar", XSPR(31,467,54), XSPR_MASK, BOOKE, { RS } }, 3924{ "mtcsrr0", XSPR(31,467,58), XSPR_MASK, BOOKE, { RS } }, 3925{ "mtcsrr1", XSPR(31,467,59), XSPR_MASK, BOOKE, { RS } }, 3926{ "mtdear", XSPR(31,467,61), XSPR_MASK, BOOKE, { RS } }, 3927{ "mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, { RS } }, 3928{ "mtesr", XSPR(31,467,62), XSPR_MASK, BOOKE, { RS } }, 3929{ "mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, { RS } }, 3930{ "mtivpr", XSPR(31,467,63), XSPR_MASK, BOOKE, { RS } }, 3931{ "mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, { RS } }, 3932{ "mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, { RS } }, 3933{ "mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, { RS } }, 3934{ "mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, { RS } }, 3935{ "mticr", XSPR(31,467,148), XSPR_MASK, PPC860, { RS } }, 3936{ "mtder", XSPR(31,467,149), XSPR_MASK, PPC860, { RS } }, 3937{ "mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, { RS } }, 3938{ "mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, { RS } }, 3939{ "mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, { RS } }, 3940{ "mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, { RS } }, 3941{ "mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, { RS } }, 3942{ "mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, { RS } }, 3943{ "mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, { RS } }, 3944{ "mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, { RS } }, 3945{ "mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, { RS } }, 3946{ "mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, { RS } }, 3947{ "mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, { RS } }, 3948{ "mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, { RS } }, 3949{ "mtsprg", XSPR(31,467,272), XSPRG_MASK,PPC, { SPRG, RS } }, 3950{ "mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, { RS } }, 3951{ "mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, { RS } }, 3952{ "mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, { RS } }, 3953{ "mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, { RS } }, 3954{ "mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405 | BOOKE, { RS } }, 3955{ "mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405 | BOOKE, { RS } }, 3956{ "mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405 | BOOKE, { RS } }, 3957{ "mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405 | BOOKE, { RS } }, 3958{ "mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, { RS } }, 3959{ "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS } }, 3960{ "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } }, 3961{ "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, { RS } }, 3962{ "mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, { RS } }, 3963{ "mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, { RS } }, 3964{ "mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, { RS } }, 3965{ "mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, { RS } }, 3966{ "mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, { RS } }, 3967{ "mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, { RS } }, 3968{ "mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, { RS } }, 3969{ "mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, { RS } }, 3970{ "mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, { RS } }, 3971{ "mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, { RS } }, 3972{ "mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, { RS } }, 3973{ "mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, { RS } }, 3974{ "mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, { RS } }, 3975{ "mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, { RS } }, 3976{ "mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, { RS } }, 3977{ "mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, { RS } }, 3978{ "mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, { RS } }, 3979{ "mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, { RS } }, 3980{ "mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, { RS } }, 3981{ "mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, { RS } }, 3982{ "mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, { RS } }, 3983{ "mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, { RS } }, 3984{ "mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, { RS } }, 3985{ "mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, { RS } }, 3986{ "mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, { RS } }, 3987{ "mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, { RS } }, 3988{ "mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, { RS } }, 3989{ "mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, { RS } }, 3990{ "mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, { RS } }, 3991{ "mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, { RS } }, 3992{ "mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, { RS } }, 3993{ "mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, { RS } }, 3994{ "mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, { RS } }, 3995{ "mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, { RS } }, 3996{ "mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, { RS } }, 3997{ "mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, { RS } }, 3998{ "mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, { RS } }, 3999{ "mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, { RS } }, 4000{ "mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, { RS } }, 4001{ "mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, { RS } }, 4002{ "mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, { RS } }, 4003{ "mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, { RS } }, 4004{ "mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, { RS } }, 4005{ "mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, { RS } }, 4006{ "mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, { RS } }, 4007{ "mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, { RS } }, 4008{ "mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE, { RS } }, 4009{ "mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE, { RS } }, 4010{ "mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, { RS } }, 4011{ "mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, { RS } }, 4012{ "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, 4013{ "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, 4014{ "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, 4015{ "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, 4016{ "mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, { RS } }, 4017{ "mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, { RS } }, 4018{ "mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, { RS } }, 4019{ "mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, { RS } }, 4020{ "mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, { RS } }, 4021{ "mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, { RS } }, 4022{ "mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, { RS } }, 4023{ "mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, { RS } }, 4024{ "mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, { RS } }, 4025{ "mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, { RS } }, 4026{ "mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, { RS } }, 4027{ "mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405, { RS } }, 4028{ "mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, { RS } }, 4029{ "mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, { RS } }, 4030{ "mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, { RS } }, 4031{ "mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, { RS } }, 4032{ "mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, { RS } }, 4033{ "mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, { RS } }, 4034{ "mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, { RS } }, 4035{ "mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, { RS } }, 4036{ "mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, { RS } }, 4037{ "mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, { RS } }, 4038{ "mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, { RS } }, 4039{ "mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, { RS } }, 4040{ "mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, { RS } }, 4041{ "mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, { RS } }, 4042{ "mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, { RS } }, 4043{ "mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, { RS } }, 4044{ "mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, { RS } }, 4045{ "mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, { RS } }, 4046{ "mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, { RS } }, 4047{ "mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, { RS } }, 4048{ "mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, { RS } }, 4049{ "mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, { RS } }, 4050{ "mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, { RS } }, 4051{ "mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, { RS } }, 4052{ "mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, { RS } }, 4053{ "mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, { RS } }, 4054{ "mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, { RS } }, 4055{ "mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, { RS } }, 4056{ "mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, { RS } }, 4057{ "mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, { RS } }, 4058{ "mtspr", X(31,467), X_MASK, COM, { SPR, RS } }, 4059 4060{ "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } }, 4061 4062{ "nand", XRC(31,476,0), X_MASK, COM, { RA, RS, RB } }, 4063{ "nand.", XRC(31,476,1), X_MASK, COM, { RA, RS, RB } }, 4064 4065{ "dcbie", X(31,478), XRT_MASK, BOOKE64, { RA, RB } }, 4066 4067{ "dcread", X(31,486), X_MASK, PPC403|PPC440, { RT, RA, RB }}, 4068 4069{ "mtpmr", X(31,462), X_MASK, PPCPMR, { PMR, RS }}, 4070 4071{ "icbtls", X(31,486), X_MASK, PPCCHLK, { CT, RA, RB }}, 4072 4073{ "nabs", XO(31,488,0,0), XORB_MASK, M601, { RT, RA } }, 4074{ "subfme64",XO(31,488,0,0), XORB_MASK, BOOKE64, { RT, RA } }, 4075{ "nabs.", XO(31,488,0,1), XORB_MASK, M601, { RT, RA } }, 4076{ "nabso", XO(31,488,1,0), XORB_MASK, M601, { RT, RA } }, 4077{ "subfme64o",XO(31,488,1,0), XORB_MASK, BOOKE64, { RT, RA } }, 4078{ "nabso.", XO(31,488,1,1), XORB_MASK, M601, { RT, RA } }, 4079 4080{ "divd", XO(31,489,0,0), XO_MASK, PPC64, { RT, RA, RB } }, 4081{ "divd.", XO(31,489,0,1), XO_MASK, PPC64, { RT, RA, RB } }, 4082{ "divdo", XO(31,489,1,0), XO_MASK, PPC64, { RT, RA, RB } }, 4083{ "divdo.", XO(31,489,1,1), XO_MASK, PPC64, { RT, RA, RB } }, 4084 4085{ "addme64", XO(31,490,0,0), XORB_MASK, BOOKE64, { RT, RA } }, 4086{ "addme64o",XO(31,490,1,0), XORB_MASK, BOOKE64, { RT, RA } }, 4087 4088{ "divw", XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB } }, 4089{ "divw.", XO(31,491,0,1), XO_MASK, PPC, { RT, RA, RB } }, 4090{ "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } }, 4091{ "divwo.", XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB } }, 4092 4093{ "icbtlse", X(31,494), X_MASK, PPCCHLK64, { CT, RA, RB }}, 4094 4095{ "slbia", X(31,498), 0xffffffff, PPC64, { 0 } }, 4096 4097{ "cli", X(31,502), XRB_MASK, POWER, { RT, RA } }, 4098 4099{ "stdcxe.", XRC(31,511,1), X_MASK, BOOKE64, { RS, RA, RB } }, 4100 4101{ "mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, { BF } }, 4102 4103{ "bblels", X(31,518), X_MASK, PPCBRLK, { 0 }}, 4104{ "mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE64, { BF } }, 4105 4106{ "clcs", X(31,531), XRB_MASK, M601, { RT, RA } }, 4107 4108{ "lswx", X(31,533), X_MASK, PPCCOM, { RT, RA0, RB } }, 4109{ "lsx", X(31,533), X_MASK, PWRCOM, { RT, RA, RB } }, 4110 4111{ "lwbrx", X(31,534), X_MASK, PPCCOM, { RT, RA0, RB } }, 4112{ "lbrx", X(31,534), X_MASK, PWRCOM, { RT, RA, RB } }, 4113 4114{ "lfsx", X(31,535), X_MASK, COM, { FRT, RA0, RB } }, 4115 4116{ "srw", XRC(31,536,0), X_MASK, PPCCOM, { RA, RS, RB } }, 4117{ "sr", XRC(31,536,0), X_MASK, PWRCOM, { RA, RS, RB } }, 4118{ "srw.", XRC(31,536,1), X_MASK, PPCCOM, { RA, RS, RB } }, 4119{ "sr.", XRC(31,536,1), X_MASK, PWRCOM, { RA, RS, RB } }, 4120 4121{ "rrib", XRC(31,537,0), X_MASK, M601, { RA, RS, RB } }, 4122{ "rrib.", XRC(31,537,1), X_MASK, M601, { RA, RS, RB } }, 4123 4124{ "srd", XRC(31,539,0), X_MASK, PPC64, { RA, RS, RB } }, 4125{ "srd.", XRC(31,539,1), X_MASK, PPC64, { RA, RS, RB } }, 4126 4127{ "maskir", XRC(31,541,0), X_MASK, M601, { RA, RS, RB } }, 4128{ "maskir.", XRC(31,541,1), X_MASK, M601, { RA, RS, RB } }, 4129 4130{ "lwbrxe", X(31,542), X_MASK, BOOKE64, { RT, RA0, RB } }, 4131 4132{ "lfsxe", X(31,543), X_MASK, BOOKE64, { FRT, RA0, RB } }, 4133 4134{ "bbelr", X(31,550), X_MASK, PPCBRLK, { 0 }}, 4135 4136{ "tlbsync", X(31,566), 0xffffffff, PPC, { 0 } }, 4137 4138{ "lfsux", X(31,567), X_MASK, COM, { FRT, RAS, RB } }, 4139 4140{ "lfsuxe", X(31,575), X_MASK, BOOKE64, { FRT, RAS, RB } }, 4141 4142{ "mfsr", X(31,595), XRB_MASK|(1<<20), COM32, { RT, SR } }, 4143 4144{ "lswi", X(31,597), X_MASK, PPCCOM, { RT, RA0, NB } }, 4145{ "lsi", X(31,597), X_MASK, PWRCOM, { RT, RA0, NB } }, 4146 4147{ "lwsync", XSYNC(31,598,1), 0xffffffff, PPC, { 0 } }, 4148{ "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, { 0 } }, 4149{ "msync", X(31,598), 0xffffffff, BOOKE, { 0 } }, 4150{ "sync", X(31,598), XSYNC_MASK, PPCCOM, { LS } }, 4151{ "dcs", X(31,598), 0xffffffff, PWRCOM, { 0 } }, 4152 4153{ "lfdx", X(31,599), X_MASK, COM, { FRT, RA0, RB } }, 4154 4155{ "lfdxe", X(31,607), X_MASK, BOOKE64, { FRT, RA0, RB } }, 4156 4157{ "mfsri", X(31,627), X_MASK, PWRCOM, { RT, RA, RB } }, 4158 4159{ "dclst", X(31,630), XRB_MASK, PWRCOM, { RS, RA } }, 4160 4161{ "lfdux", X(31,631), X_MASK, COM, { FRT, RAS, RB } }, 4162 4163{ "lfduxe", X(31,639), X_MASK, BOOKE64, { FRT, RAS, RB } }, 4164 4165{ "mfsrin", X(31,659), XRA_MASK, PPC32, { RT, RB } }, 4166 4167{ "stswx", X(31,661), X_MASK, PPCCOM, { RS, RA0, RB } }, 4168{ "stsx", X(31,661), X_MASK, PWRCOM, { RS, RA0, RB } }, 4169 4170{ "stwbrx", X(31,662), X_MASK, PPCCOM, { RS, RA0, RB } }, 4171{ "stbrx", X(31,662), X_MASK, PWRCOM, { RS, RA0, RB } }, 4172 4173{ "stfsx", X(31,663), X_MASK, COM, { FRS, RA0, RB } }, 4174 4175{ "srq", XRC(31,664,0), X_MASK, M601, { RA, RS, RB } }, 4176{ "srq.", XRC(31,664,1), X_MASK, M601, { RA, RS, RB } }, 4177 4178{ "sre", XRC(31,665,0), X_MASK, M601, { RA, RS, RB } }, 4179{ "sre.", XRC(31,665,1), X_MASK, M601, { RA, RS, RB } }, 4180 4181{ "stwbrxe", X(31,670), X_MASK, BOOKE64, { RS, RA0, RB } }, 4182 4183{ "stfsxe", X(31,671), X_MASK, BOOKE64, { FRS, RA0, RB } }, 4184 4185{ "stfsux", X(31,695), X_MASK, COM, { FRS, RAS, RB } }, 4186 4187{ "sriq", XRC(31,696,0), X_MASK, M601, { RA, RS, SH } }, 4188{ "sriq.", XRC(31,696,1), X_MASK, M601, { RA, RS, SH } }, 4189 4190{ "stfsuxe", X(31,703), X_MASK, BOOKE64, { FRS, RAS, RB } }, 4191 4192{ "stswi", X(31,725), X_MASK, PPCCOM, { RS, RA0, NB } }, 4193{ "stsi", X(31,725), X_MASK, PWRCOM, { RS, RA0, NB } }, 4194 4195{ "stfdx", X(31,727), X_MASK, COM, { FRS, RA0, RB } }, 4196 4197{ "srlq", XRC(31,728,0), X_MASK, M601, { RA, RS, RB } }, 4198{ "srlq.", XRC(31,728,1), X_MASK, M601, { RA, RS, RB } }, 4199 4200{ "sreq", XRC(31,729,0), X_MASK, M601, { RA, RS, RB } }, 4201{ "sreq.", XRC(31,729,1), X_MASK, M601, { RA, RS, RB } }, 4202 4203{ "stfdxe", X(31,735), X_MASK, BOOKE64, { FRS, RA0, RB } }, 4204 4205{ "dcba", X(31,758), XRT_MASK, PPC405 | BOOKE, { RA, RB } }, 4206 4207{ "stfdux", X(31,759), X_MASK, COM, { FRS, RAS, RB } }, 4208 4209{ "srliq", XRC(31,760,0), X_MASK, M601, { RA, RS, SH } }, 4210{ "srliq.", XRC(31,760,1), X_MASK, M601, { RA, RS, SH } }, 4211 4212{ "dcbae", X(31,766), XRT_MASK, BOOKE64, { RA, RB } }, 4213 4214{ "stfduxe", X(31,767), X_MASK, BOOKE64, { FRS, RAS, RB } }, 4215 4216{ "tlbivax", X(31,786), XRT_MASK, BOOKE, { RA, RB } }, 4217{ "tlbivaxe",X(31,787), XRT_MASK, BOOKE64, { RA, RB } }, 4218 4219{ "lhbrx", X(31,790), X_MASK, COM, { RT, RA0, RB } }, 4220 4221{ "sraw", XRC(31,792,0), X_MASK, PPCCOM, { RA, RS, RB } }, 4222{ "sra", XRC(31,792,0), X_MASK, PWRCOM, { RA, RS, RB } }, 4223{ "sraw.", XRC(31,792,1), X_MASK, PPCCOM, { RA, RS, RB } }, 4224{ "sra.", XRC(31,792,1), X_MASK, PWRCOM, { RA, RS, RB } }, 4225 4226{ "srad", XRC(31,794,0), X_MASK, PPC64, { RA, RS, RB } }, 4227{ "srad.", XRC(31,794,1), X_MASK, PPC64, { RA, RS, RB } }, 4228 4229{ "lhbrxe", X(31,798), X_MASK, BOOKE64, { RT, RA0, RB } }, 4230 4231{ "ldxe", X(31,799), X_MASK, BOOKE64, { RT, RA0, RB } }, 4232{ "lduxe", X(31,831), X_MASK, BOOKE64, { RT, RA0, RB } }, 4233 4234{ "rac", X(31,818), X_MASK, PWRCOM, { RT, RA, RB } }, 4235 4236{ "dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, { STRM } }, 4237{ "dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, { 0 } }, 4238 4239{ "srawi", XRC(31,824,0), X_MASK, PPCCOM, { RA, RS, SH } }, 4240{ "srai", XRC(31,824,0), X_MASK, PWRCOM, { RA, RS, SH } }, 4241{ "srawi.", XRC(31,824,1), X_MASK, PPCCOM, { RA, RS, SH } }, 4242{ "srai.", XRC(31,824,1), X_MASK, PWRCOM, { RA, RS, SH } }, 4243 4244{ "slbmfev", X(31,851), XRA_MASK, PPC64, { RT, RB } }, 4245 4246{ "mbar", X(31,854), X_MASK, BOOKE, { MO } }, 4247{ "eieio", X(31,854), 0xffffffff, PPC, { 0 } }, 4248 4249{ "tlbsx", XRC(31,914,0), X_MASK, BOOKE, { RA, RB } }, 4250{ "tlbsx", XRC(31,914,0), X_MASK, PPC403, { RT, RA, RB } }, 4251{ "tlbsx.", XRC(31,914,1), X_MASK, BOOKE, { RA, RB } }, 4252{ "tlbsx.", XRC(31,914,1), X_MASK, PPC403, { RT, RA, RB } }, 4253{ "tlbsxe", XRC(31,915,0), X_MASK, BOOKE64, { RA, RB } }, 4254{ "tlbsxe.", XRC(31,915,1), X_MASK, BOOKE64, { RA, RB } }, 4255 4256{ "slbmfee", X(31,915), XRA_MASK, PPC64, { RT, RB } }, 4257 4258{ "sthbrx", X(31,918), X_MASK, COM, { RS, RA0, RB } }, 4259 4260{ "sraq", XRC(31,920,0), X_MASK, M601, { RA, RS, RB } }, 4261{ "sraq.", XRC(31,920,1), X_MASK, M601, { RA, RS, RB } }, 4262 4263{ "srea", XRC(31,921,0), X_MASK, M601, { RA, RS, RB } }, 4264{ "srea.", XRC(31,921,1), X_MASK, M601, { RA, RS, RB } }, 4265 4266{ "extsh", XRC(31,922,0), XRB_MASK, PPCCOM, { RA, RS } }, 4267{ "exts", XRC(31,922,0), XRB_MASK, PWRCOM, { RA, RS } }, 4268{ "extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, { RA, RS } }, 4269{ "exts.", XRC(31,922,1), XRB_MASK, PWRCOM, { RA, RS } }, 4270 4271{ "sthbrxe", X(31,926), X_MASK, BOOKE64, { RS, RA0, RB } }, 4272 4273{ "stdxe", X(31,927), X_MASK, BOOKE64, { RS, RA0, RB } }, 4274 4275{ "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, { RT, RA } }, 4276{ "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, { RT, RA } }, 4277{ "tlbre", X(31,946), X_MASK, BOOKE, { 0 } }, 4278{ "tlbre", X(31,946), X_MASK, PPC403, { RS, RA, SH } }, 4279 4280{ "sraiq", XRC(31,952,0), X_MASK, M601, { RA, RS, SH } }, 4281{ "sraiq.", XRC(31,952,1), X_MASK, M601, { RA, RS, SH } }, 4282 4283{ "extsb", XRC(31,954,0), XRB_MASK, PPC, { RA, RS} }, 4284{ "extsb.", XRC(31,954,1), XRB_MASK, PPC, { RA, RS} }, 4285 4286{ "stduxe", X(31,959), X_MASK, BOOKE64, { RS, RAS, RB } }, 4287 4288{ "iccci", X(31,966), XRT_MASK, PPC403|PPC440, { RA, RB } }, 4289 4290{ "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, { RT, RA } }, 4291{ "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, { RT, RA } }, 4292{ "tlbwe", X(31,978), X_MASK, PPC403|BOOKE, { RSO, RAOPT, SHO } }, 4293{ "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } }, 4294 4295{ "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } }, 4296 4297{ "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA0, RB } }, 4298 4299{ "extsw", XRC(31,986,0), XRB_MASK, PPC64 | BOOKE64,{ RA, RS } }, 4300{ "extsw.", XRC(31,986,1), XRB_MASK, PPC64, { RA, RS } }, 4301 4302{ "icread", X(31,998), XRT_MASK, PPC403|PPC440, { RA, RB } }, 4303 4304{ "icbie", X(31,990), XRT_MASK, BOOKE64, { RA, RB } }, 4305{ "stfiwxe", X(31,991), X_MASK, BOOKE64, { FRS, RA0, RB } }, 4306 4307{ "tlbli", X(31,1010), XRTRA_MASK, PPC, { RB } }, 4308 4309{ "dcbzl", XOPL(31,1014,1), XRT_MASK,POWER4, { RA, RB } }, 4310{ "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } }, 4311{ "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } }, 4312 4313{ "dcbze", X(31,1022), XRT_MASK, BOOKE64, { RA, RB } }, 4314 4315{ "lvebx", X(31, 7), X_MASK, PPCVEC, { VD, RA, RB } }, 4316{ "lvehx", X(31, 39), X_MASK, PPCVEC, { VD, RA, RB } }, 4317{ "lvewx", X(31, 71), X_MASK, PPCVEC, { VD, RA, RB } }, 4318{ "lvsl", X(31, 6), X_MASK, PPCVEC, { VD, RA, RB } }, 4319{ "lvsr", X(31, 38), X_MASK, PPCVEC, { VD, RA, RB } }, 4320{ "lvx", X(31, 103), X_MASK, PPCVEC, { VD, RA, RB } }, 4321{ "lvxl", X(31, 359), X_MASK, PPCVEC, { VD, RA, RB } }, 4322{ "stvebx", X(31, 135), X_MASK, PPCVEC, { VS, RA, RB } }, 4323{ "stvehx", X(31, 167), X_MASK, PPCVEC, { VS, RA, RB } }, 4324{ "stvewx", X(31, 199), X_MASK, PPCVEC, { VS, RA, RB } }, 4325{ "stvx", X(31, 231), X_MASK, PPCVEC, { VS, RA, RB } }, 4326{ "stvxl", X(31, 487), X_MASK, PPCVEC, { VS, RA, RB } }, 4327 4328{ "lwz", OP(32), OP_MASK, PPCCOM, { RT, D, RA0 } }, 4329{ "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA0 } }, 4330 4331{ "lwzu", OP(33), OP_MASK, PPCCOM, { RT, D, RAL } }, 4332{ "lu", OP(33), OP_MASK, PWRCOM, { RT, D, RA0 } }, 4333 4334{ "lbz", OP(34), OP_MASK, COM, { RT, D, RA0 } }, 4335 4336{ "lbzu", OP(35), OP_MASK, COM, { RT, D, RAL } }, 4337 4338{ "stw", OP(36), OP_MASK, PPCCOM, { RS, D, RA0 } }, 4339{ "st", OP(36), OP_MASK, PWRCOM, { RS, D, RA0 } }, 4340 4341{ "stwu", OP(37), OP_MASK, PPCCOM, { RS, D, RAS } }, 4342{ "stu", OP(37), OP_MASK, PWRCOM, { RS, D, RA0 } }, 4343 4344{ "stb", OP(38), OP_MASK, COM, { RS, D, RA0 } }, 4345 4346{ "stbu", OP(39), OP_MASK, COM, { RS, D, RAS } }, 4347 4348{ "lhz", OP(40), OP_MASK, COM, { RT, D, RA0 } }, 4349 4350{ "lhzu", OP(41), OP_MASK, COM, { RT, D, RAL } }, 4351 4352{ "lha", OP(42), OP_MASK, COM, { RT, D, RA0 } }, 4353 4354{ "lhau", OP(43), OP_MASK, COM, { RT, D, RAL } }, 4355 4356{ "sth", OP(44), OP_MASK, COM, { RS, D, RA0 } }, 4357 4358{ "sthu", OP(45), OP_MASK, COM, { RS, D, RAS } }, 4359 4360{ "lmw", OP(46), OP_MASK, PPCCOM, { RT, D, RAM } }, 4361{ "lm", OP(46), OP_MASK, PWRCOM, { RT, D, RA0 } }, 4362 4363{ "stmw", OP(47), OP_MASK, PPCCOM, { RS, D, RA0 } }, 4364{ "stm", OP(47), OP_MASK, PWRCOM, { RS, D, RA0 } }, 4365 4366{ "lfs", OP(48), OP_MASK, COM, { FRT, D, RA0 } }, 4367 4368{ "lfsu", OP(49), OP_MASK, COM, { FRT, D, RAS } }, 4369 4370{ "lfd", OP(50), OP_MASK, COM, { FRT, D, RA0 } }, 4371 4372{ "lfdu", OP(51), OP_MASK, COM, { FRT, D, RAS } }, 4373 4374{ "stfs", OP(52), OP_MASK, COM, { FRS, D, RA0 } }, 4375 4376{ "stfsu", OP(53), OP_MASK, COM, { FRS, D, RAS } }, 4377 4378{ "stfd", OP(54), OP_MASK, COM, { FRS, D, RA0 } }, 4379 4380{ "stfdu", OP(55), OP_MASK, COM, { FRS, D, RAS } }, 4381 4382{ "lq", OP(56), OP_MASK, POWER4, { RTQ, DQ, RAQ } }, 4383 4384{ "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA0 } }, 4385 4386{ "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA0 } }, 4387 4388{ "lbze", DEO(58,0), DE_MASK, BOOKE64, { RT, DE, RA0 } }, 4389{ "lbzue", DEO(58,1), DE_MASK, BOOKE64, { RT, DE, RAL } }, 4390{ "lhze", DEO(58,2), DE_MASK, BOOKE64, { RT, DE, RA0 } }, 4391{ "lhzue", DEO(58,3), DE_MASK, BOOKE64, { RT, DE, RAL } }, 4392{ "lhae", DEO(58,4), DE_MASK, BOOKE64, { RT, DE, RA0 } }, 4393{ "lhaue", DEO(58,5), DE_MASK, BOOKE64, { RT, DE, RAL } }, 4394{ "lwze", DEO(58,6), DE_MASK, BOOKE64, { RT, DE, RA0 } }, 4395{ "lwzue", DEO(58,7), DE_MASK, BOOKE64, { RT, DE, RAL } }, 4396{ "stbe", DEO(58,8), DE_MASK, BOOKE64, { RS, DE, RA0 } }, 4397{ "stbue", DEO(58,9), DE_MASK, BOOKE64, { RS, DE, RAS } }, 4398{ "sthe", DEO(58,10), DE_MASK, BOOKE64, { RS, DE, RA0 } }, 4399{ "sthue", DEO(58,11), DE_MASK, BOOKE64, { RS, DE, RAS } }, 4400{ "stwe", DEO(58,14), DE_MASK, BOOKE64, { RS, DE, RA0 } }, 4401{ "stwue", DEO(58,15), DE_MASK, BOOKE64, { RS, DE, RAS } }, 4402 4403{ "ld", DSO(58,0), DS_MASK, PPC64, { RT, DS, RA0 } }, 4404 4405{ "ldu", DSO(58,1), DS_MASK, PPC64, { RT, DS, RAL } }, 4406 4407{ "lwa", DSO(58,2), DS_MASK, PPC64, { RT, DS, RA0 } }, 4408 4409{ "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, 4410{ "fdivs.", A(59,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } }, 4411 4412{ "fsubs", A(59,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, 4413{ "fsubs.", A(59,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB } }, 4414 4415{ "fadds", A(59,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, 4416{ "fadds.", A(59,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } }, 4417 4418{ "fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, { FRT, FRB } }, 4419{ "fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, { FRT, FRB } }, 4420 4421{ "fres", A(59,24,0), AFRAFRC_MASK, PPC, { FRT, FRB } }, 4422{ "fres.", A(59,24,1), AFRAFRC_MASK, PPC, { FRT, FRB } }, 4423 4424{ "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } }, 4425{ "fmuls.", A(59,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } }, 4426 4427{ "fmsubs", A(59,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 4428{ "fmsubs.", A(59,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 4429 4430{ "fmadds", A(59,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 4431{ "fmadds.", A(59,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 4432 4433{ "fnmsubs", A(59,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 4434{ "fnmsubs.",A(59,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 4435 4436{ "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 4437{ "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 4438 4439{ "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } }, 4440 4441{ "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } }, 4442 4443{ "lde", DEO(62,0), DE_MASK, BOOKE64, { RT, DES, RA0 } }, 4444{ "ldue", DEO(62,1), DE_MASK, BOOKE64, { RT, DES, RA0 } }, 4445{ "lfse", DEO(62,4), DE_MASK, BOOKE64, { FRT, DES, RA0 } }, 4446{ "lfsue", DEO(62,5), DE_MASK, BOOKE64, { FRT, DES, RAS } }, 4447{ "lfde", DEO(62,6), DE_MASK, BOOKE64, { FRT, DES, RA0 } }, 4448{ "lfdue", DEO(62,7), DE_MASK, BOOKE64, { FRT, DES, RAS } }, 4449{ "stde", DEO(62,8), DE_MASK, BOOKE64, { RS, DES, RA0 } }, 4450{ "stdue", DEO(62,9), DE_MASK, BOOKE64, { RS, DES, RAS } }, 4451{ "stfse", DEO(62,12), DE_MASK, BOOKE64, { FRS, DES, RA0 } }, 4452{ "stfsue", DEO(62,13), DE_MASK, BOOKE64, { FRS, DES, RAS } }, 4453{ "stfde", DEO(62,14), DE_MASK, BOOKE64, { FRS, DES, RA0 } }, 4454{ "stfdue", DEO(62,15), DE_MASK, BOOKE64, { FRS, DES, RAS } }, 4455 4456{ "std", DSO(62,0), DS_MASK, PPC64, { RS, DS, RA0 } }, 4457 4458{ "stdu", DSO(62,1), DS_MASK, PPC64, { RS, DS, RAS } }, 4459 4460{ "stq", DSO(62,2), DS_MASK, POWER4, { RSQ, DS, RA0 } }, 4461 4462{ "fcmpu", X(63,0), X_MASK|(3<<21), COM, { BF, FRA, FRB } }, 4463 4464{ "frsp", XRC(63,12,0), XRA_MASK, COM, { FRT, FRB } }, 4465{ "frsp.", XRC(63,12,1), XRA_MASK, COM, { FRT, FRB } }, 4466 4467{ "fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, { FRT, FRB } }, 4468{ "fcir", XRC(63,14,0), XRA_MASK, POWER2, { FRT, FRB } }, 4469{ "fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, { FRT, FRB } }, 4470{ "fcir.", XRC(63,14,1), XRA_MASK, POWER2, { FRT, FRB } }, 4471 4472{ "fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, { FRT, FRB } }, 4473{ "fcirz", XRC(63,15,0), XRA_MASK, POWER2, { FRT, FRB } }, 4474{ "fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, { FRT, FRB } }, 4475{ "fcirz.", XRC(63,15,1), XRA_MASK, POWER2, { FRT, FRB } }, 4476 4477{ "fdiv", A(63,18,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, 4478{ "fd", A(63,18,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } }, 4479{ "fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, 4480{ "fd.", A(63,18,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } }, 4481 4482{ "fsub", A(63,20,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, 4483{ "fs", A(63,20,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } }, 4484{ "fsub.", A(63,20,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, 4485{ "fs.", A(63,20,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } }, 4486 4487{ "fadd", A(63,21,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, 4488{ "fa", A(63,21,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } }, 4489{ "fadd.", A(63,21,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, 4490{ "fa.", A(63,21,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } }, 4491 4492{ "fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } }, 4493{ "fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } }, 4494 4495{ "fsel", A(63,23,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 4496{ "fsel.", A(63,23,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 4497 4498{ "fmul", A(63,25,0), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } }, 4499{ "fm", A(63,25,0), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } }, 4500{ "fmul.", A(63,25,1), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } }, 4501{ "fm.", A(63,25,1), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } }, 4502 4503{ "frsqrte", A(63,26,0), AFRAFRC_MASK, PPC, { FRT, FRB } }, 4504{ "frsqrte.",A(63,26,1), AFRAFRC_MASK, PPC, { FRT, FRB } }, 4505 4506{ "fmsub", A(63,28,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, 4507{ "fms", A(63,28,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, 4508{ "fmsub.", A(63,28,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, 4509{ "fms.", A(63,28,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, 4510 4511{ "fmadd", A(63,29,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, 4512{ "fma", A(63,29,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, 4513{ "fmadd.", A(63,29,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, 4514{ "fma.", A(63,29,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, 4515 4516{ "fnmsub", A(63,30,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, 4517{ "fnms", A(63,30,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, 4518{ "fnmsub.", A(63,30,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, 4519{ "fnms.", A(63,30,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, 4520 4521{ "fnmadd", A(63,31,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, 4522{ "fnma", A(63,31,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, 4523{ "fnmadd.", A(63,31,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, 4524{ "fnma.", A(63,31,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, 4525 4526{ "fcmpo", X(63,32), X_MASK|(3<<21), COM, { BF, FRA, FRB } }, 4527 4528{ "mtfsb1", XRC(63,38,0), XRARB_MASK, COM, { BT } }, 4529{ "mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, { BT } }, 4530 4531{ "fneg", XRC(63,40,0), XRA_MASK, COM, { FRT, FRB } }, 4532{ "fneg.", XRC(63,40,1), XRA_MASK, COM, { FRT, FRB } }, 4533 4534{ "mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } }, 4535 4536{ "mtfsb0", XRC(63,70,0), XRARB_MASK, COM, { BT } }, 4537{ "mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, { BT } }, 4538 4539{ "fmr", XRC(63,72,0), XRA_MASK, COM, { FRT, FRB } }, 4540{ "fmr.", XRC(63,72,1), XRA_MASK, COM, { FRT, FRB } }, 4541 4542{ "mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } }, 4543{ "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } }, 4544 4545{ "fnabs", XRC(63,136,0), XRA_MASK, COM, { FRT, FRB } }, 4546{ "fnabs.", XRC(63,136,1), XRA_MASK, COM, { FRT, FRB } }, 4547 4548{ "fabs", XRC(63,264,0), XRA_MASK, COM, { FRT, FRB } }, 4549{ "fabs.", XRC(63,264,1), XRA_MASK, COM, { FRT, FRB } }, 4550 4551{ "mffs", XRC(63,583,0), XRARB_MASK, COM, { FRT } }, 4552{ "mffs.", XRC(63,583,1), XRARB_MASK, COM, { FRT } }, 4553 4554{ "mtfsf", XFL(63,711,0), XFL_MASK, COM, { FLM, FRB } }, 4555{ "mtfsf.", XFL(63,711,1), XFL_MASK, COM, { FLM, FRB } }, 4556 4557{ "fctid", XRC(63,814,0), XRA_MASK, PPC64, { FRT, FRB } }, 4558{ "fctid.", XRC(63,814,1), XRA_MASK, PPC64, { FRT, FRB } }, 4559 4560{ "fctidz", XRC(63,815,0), XRA_MASK, PPC64, { FRT, FRB } }, 4561{ "fctidz.", XRC(63,815,1), XRA_MASK, PPC64, { FRT, FRB } }, 4562 4563{ "fcfid", XRC(63,846,0), XRA_MASK, PPC64, { FRT, FRB } }, 4564{ "fcfid.", XRC(63,846,1), XRA_MASK, PPC64, { FRT, FRB } }, 4565 4566}; 4567 4568const int powerpc_num_opcodes = 4569 sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]); 4570 4571/* The macro table. This is only used by the assembler. */ 4572 4573/* The expressions of the form (-x ! 31) & (x | 31) have the value 0 4574 when x=0; 32-x when x is between 1 and 31; are negative if x is 4575 negative; and are 32 or more otherwise. This is what you want 4576 when, for instance, you are emulating a right shift by a 4577 rotate-left-and-mask, because the underlying instructions support 4578 shifts of size 0 but not shifts of size 32. By comparison, when 4579 extracting x bits from some word you want to use just 32-x, because 4580 the underlying instructions don't support extracting 0 bits but do 4581 support extracting the whole word (32 bits in this case). */ 4582 4583const struct powerpc_macro powerpc_macros[] = { 4584{ "extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1" }, 4585{ "extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1" }, 4586{ "extrdi", 4, PPC64, "rldicl %0,%1,(%2)+(%3),64-(%2)" }, 4587{ "extrdi.", 4, PPC64, "rldicl. %0,%1,(%2)+(%3),64-(%2)" }, 4588{ "insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3" }, 4589{ "insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3" }, 4590{ "rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0" }, 4591{ "rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0" }, 4592{ "sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)" }, 4593{ "sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)" }, 4594{ "srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2" }, 4595{ "srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2" }, 4596{ "clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)" }, 4597{ "clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)" }, 4598{ "clrlsldi",4, PPC64, "rldic %0,%1,%3,(%2)-(%3)" }, 4599{ "clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)" }, 4600 4601{ "extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1" }, 4602{ "extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1" }, 4603{ "extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" }, 4604{ "extrwi.", 4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" }, 4605{ "inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" }, 4606{ "inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"}, 4607{ "insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" }, 4608{ "insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"}, 4609{ "rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31" }, 4610{ "rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31" }, 4611{ "slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)" }, 4612{ "sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)" }, 4613{ "slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)" }, 4614{ "sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)" }, 4615{ "srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" }, 4616{ "sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" }, 4617{ "srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" }, 4618{ "sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" }, 4619{ "clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)" }, 4620{ "clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)" }, 4621{ "clrlslwi",4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" }, 4622{ "clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" }, 4623}; 4624 4625const int powerpc_num_macros = 4626 sizeof (powerpc_macros) / sizeof (powerpc_macros[0]); 4627