1/* cris.h -- Header file for CRIS opcode and register tables.
2   Copyright (C) 2000, 2001 Free Software Foundation, Inc.
3   Contributed by Axis Communications AB, Lund, Sweden.
4   Originally written for GAS 1.38.1 by Mikael Asker.
5   Updated, BFDized and GNUified by Hans-Peter Nilsson.
6
7This file is part of GAS, GDB and the GNU binutils.
8
9GAS, GDB, and GNU binutils is free software; you can redistribute it
10and/or modify it under the terms of the GNU General Public License as
11published by the Free Software Foundation; either version 2, or (at your
12option) any later version.
13
14GAS, GDB, and GNU binutils are distributed in the hope that they will be
15useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
16MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17GNU General Public License for more details.
18
19You should have received a copy of the GNU General Public License
20along with this program; if not, write to the Free Software
21Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
22
23#ifndef __CRIS_H_INCLUDED_
24#define __CRIS_H_INCLUDED_
25
26#if !defined(__STDC__) && !defined(const)
27#define const
28#endif
29
30
31/* Registers.  */
32#define MAX_REG (15)
33#define REG_SP (14)
34#define REG_PC (15)
35
36/* CPU version control of disassembly and assembly of instructions.
37   May affect how the instruction is assembled, at least the size of
38   immediate operands.  */
39enum cris_insn_version_usage
40{
41  /* Any version. */
42  cris_ver_version_all=0,
43
44  /* Indeterminate (intended for disassembly only, or obsolete).  */
45  cris_ver_warning,
46
47  /* Simulator only (reserved).  */
48  cris_ver_sim,
49
50  /* Only for v0..3 (Etrax 1..4).  */
51  cris_ver_v0_3,
52
53  /* Only for v3 or higher (ETRAX 4 and beyond).  */
54  cris_ver_v3p,
55
56  /* Only for v8 (Etrax 100).  */
57  cris_ver_v8,
58
59  /* Only for v8 or higher (ETRAX 100, ETRAX 100 LX).  */
60  cris_ver_v8p,
61
62  /* Only for v10 or higher (ETRAX 100 LX).
63     Of course some or all these of may change to cris_ver_v10p if/when
64     there's a new revision. */
65  cris_ver_v10p
66};
67
68
69/* Special registers.  */
70struct cris_spec_reg
71{
72  const char *const name;
73  unsigned int number;
74
75  /* The size of the register.  */
76  unsigned int reg_size;
77
78  /* What CPU version the special register of that name is implemented
79     in.  If cris_ver_warning, emit an unimplemented-warning.  */
80  enum cris_insn_version_usage applicable_version;
81
82  /* There might be a specific warning for using a special register
83     here.  */
84  const char *const warning;
85};
86extern const struct cris_spec_reg cris_spec_regs[];
87
88/* Opcode-dependent constants.  */
89#define AUTOINCR_BIT (0x04)
90
91/* Prefixes.  */
92#define BDAP_QUICK_OPCODE (0x0100)
93#define BDAP_QUICK_Z_BITS (0x0e00)
94
95#define BIAP_OPCODE	  (0x0540)
96#define BIAP_Z_BITS	  (0x0a80)
97
98#define DIP_OPCODE	  (0x0970)
99#define DIP_Z_BITS	  (0xf280)
100
101#define BDAP_INDIR_LOW	  (0x40)
102#define BDAP_INDIR_LOW_Z  (0x80)
103#define BDAP_INDIR_HIGH	  (0x09)
104#define BDAP_INDIR_HIGH_Z (0x02)
105
106#define BDAP_INDIR_OPCODE (BDAP_INDIR_HIGH * 0x0100 + BDAP_INDIR_LOW)
107#define BDAP_INDIR_Z_BITS (BDAP_INDIR_HIGH_Z * 0x100 + BDAP_INDIR_LOW_Z)
108#define BDAP_PC_LOW	  (BDAP_INDIR_LOW + REG_PC)
109#define BDAP_INCR_HIGH	  (BDAP_INDIR_HIGH + AUTOINCR_BIT)
110
111/* No prefix must have this code for its "match" bits in the
112   opcode-table.  "BCC .+2" will do nicely.  */
113#define NO_CRIS_PREFIX 0
114
115/* Definitions for condition codes.  */
116#define CC_CC  0x0
117#define CC_HS  0x0
118#define CC_CS  0x1
119#define CC_LO  0x1
120#define CC_NE  0x2
121#define CC_EQ  0x3
122#define CC_VC  0x4
123#define CC_VS  0x5
124#define CC_PL  0x6
125#define CC_MI  0x7
126#define CC_LS  0x8
127#define CC_HI  0x9
128#define CC_GE  0xA
129#define CC_LT  0xB
130#define CC_GT  0xC
131#define CC_LE  0xD
132#define CC_A   0xE
133#define CC_EXT 0xF
134
135/* A table of strings "cc", "cs"... indexed with condition code
136   values as above.  */
137extern const char *const cris_cc_strings[];
138
139/* Bcc quick.  */
140#define BRANCH_QUICK_LOW  (0)
141#define BRANCH_QUICK_HIGH (0)
142#define BRANCH_QUICK_OPCODE (BRANCH_QUICK_HIGH * 0x0100 + BRANCH_QUICK_LOW)
143#define BRANCH_QUICK_Z_BITS (0x0F00)
144
145/* BA quick.  */
146#define BA_QUICK_HIGH (BRANCH_QUICK_HIGH + CC_A * 0x10)
147#define BA_QUICK_OPCODE (BA_QUICK_HIGH * 0x100 + BRANCH_QUICK_LOW)
148
149/* Bcc [PC+].  */
150#define BRANCH_PC_LOW	 (0xFF)
151#define BRANCH_INCR_HIGH (0x0D)
152#define BA_PC_INCR_OPCODE \
153 ((BRANCH_INCR_HIGH + CC_A * 0x10) * 0x0100 + BRANCH_PC_LOW)
154
155/* Jump.  */
156/* Note that old versions generated special register 8 (in high bits)
157   and not-that-old versions recognized it as a jump-instruction.
158   That opcode now belongs to JUMPU.  */
159#define JUMP_INDIR_OPCODE (0x0930)
160#define JUMP_INDIR_Z_BITS (0xf2c0)
161#define JUMP_PC_INCR_OPCODE \
162 (JUMP_INDIR_OPCODE + AUTOINCR_BIT * 0x0100 + REG_PC)
163#define ADD_PC_INCR_OPCODE \
164 (0xfa00 + (2 << 4) + AUTOINCR_BIT * 0x0100 + REG_PC)
165
166/* Nop.  */
167#define NOP_OPCODE (0x050F)
168#define NOP_Z_BITS (0xFAF0)
169
170/* Structure of an opcode table entry.  */
171enum cris_imm_oprnd_size_type
172{
173  /* No size is applicable.  */
174  SIZE_NONE,
175
176  /* Always 32 bits.  */
177  SIZE_FIX_32,
178
179  /* Indicated by size of special register.  */
180  SIZE_SPEC_REG,
181
182  /* Indicated by size field.  */
183  SIZE_FIELD
184};
185
186/* For GDB.  FIXME: Is this the best way to handle opcode
187   interpretation?  */
188enum cris_op_type
189{
190  cris_not_implemented_op = 0,
191  cris_abs_op,
192  cris_addi_op,
193  cris_asr_op,
194  cris_asrq_op,
195  cris_ax_ei_setf_op,
196  cris_bdap_prefix,
197  cris_biap_prefix,
198  cris_break_op,
199  cris_btst_nop_op,
200  cris_clearf_di_op,
201  cris_dip_prefix,
202  cris_dstep_logshift_mstep_neg_not_op,
203  cris_eight_bit_offset_branch_op,
204  cris_move_mem_to_reg_movem_op,
205  cris_move_reg_to_mem_movem_op,
206  cris_move_to_preg_op,
207  cris_muls_op,
208  cris_mulu_op,
209  cris_none_reg_mode_add_sub_cmp_and_or_move_op,
210  cris_none_reg_mode_clear_test_op,
211  cris_none_reg_mode_jump_op,
212  cris_none_reg_mode_move_from_preg_op,
213  cris_quick_mode_add_sub_op,
214  cris_quick_mode_and_cmp_move_or_op,
215  cris_quick_mode_bdap_prefix,
216  cris_reg_mode_add_sub_cmp_and_or_move_op,
217  cris_reg_mode_clear_op,
218  cris_reg_mode_jump_op,
219  cris_reg_mode_move_from_preg_op,
220  cris_reg_mode_test_op,
221  cris_scc_op,
222  cris_sixteen_bit_offset_branch_op,
223  cris_three_operand_add_sub_cmp_and_or_op,
224  cris_three_operand_bound_op,
225  cris_two_operand_bound_op,
226  cris_xor_op
227};
228
229struct cris_opcode
230{
231  /* The name of the insn.  */
232  const char *name;
233
234  /* Bits that must be 1 for a match.  */
235  unsigned int match;
236
237  /* Bits that must be 0 for a match.  */
238  unsigned int lose;
239
240  /* See the table in "opcodes/cris-opc.c".  */
241  const char *args;
242
243  /* Nonzero if this is a delayed branch instruction.  */
244  char delayed;
245
246  /* Size of immediate operands.  */
247  enum cris_imm_oprnd_size_type imm_oprnd_size;
248
249  /* Indicates which version this insn was first implemented in.  */
250  enum cris_insn_version_usage applicable_version;
251
252  /* What kind of operation this is.  */
253  enum cris_op_type op;
254};
255extern const struct cris_opcode cris_opcodes[];
256
257
258/* These macros are for the target-specific flags in disassemble_info
259   used at disassembly.  */
260
261/* This insn accesses memory.  This flag is more trustworthy than
262   checking insn_type for "dis_dref" which does not work for
263   e.g. "JSR [foo]".  */
264#define CRIS_DIS_FLAG_MEMREF (1 << 0)
265
266/* The "target" field holds a register number.  */
267#define CRIS_DIS_FLAG_MEM_TARGET_IS_REG (1 << 1)
268
269/* The "target2" field holds a register number; add it to "target".  */
270#define CRIS_DIS_FLAG_MEM_TARGET2_IS_REG (1 << 2)
271
272/* Yet another add-on: the register in "target2" must be multiplied
273   by 2 before adding to "target".  */
274#define CRIS_DIS_FLAG_MEM_TARGET2_MULT2 (1 << 3)
275
276/* Yet another add-on: the register in "target2" must be multiplied
277   by 4 (mutually exclusive with .._MULT2).  */
278#define CRIS_DIS_FLAG_MEM_TARGET2_MULT4 (1 << 4)
279
280/* The register in "target2" is an indirect memory reference (of the
281   register there), add to "target".  Assumed size is dword (mutually
282   exclusive with .._MULT[24]).  */
283#define CRIS_DIS_FLAG_MEM_TARGET2_MEM (1 << 5)
284
285/* Add-on to CRIS_DIS_FLAG_MEM_TARGET2_MEM; the memory access is "byte";
286   sign-extended before adding to "target".  */
287#define CRIS_DIS_FLAG_MEM_TARGET2_MEM_BYTE (1 << 6)
288
289/* Add-on to CRIS_DIS_FLAG_MEM_TARGET2_MEM; the memory access is "word";
290   sign-extended before adding to "target".  */
291#define CRIS_DIS_FLAG_MEM_TARGET2_MEM_WORD (1 << 7)
292
293#endif /* __CRIS_H_INCLUDED_ */
294
295/*
296 * Local variables:
297 * eval: (c-set-style "gnu")
298 * indent-tabs-mode: t
299 * End:
300 */
301