1/* Target-dependent code for Renesas Super-H, for GDB. 2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 3 2003, 2004 Free Software Foundation, Inc. 4 5 This file is part of GDB. 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 2 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program; if not, write to the Free Software 19 Foundation, Inc., 59 Temple Place - Suite 330, 20 Boston, MA 02111-1307, USA. */ 21 22/* 23 Contributed by Steve Chamberlain 24 sac@cygnus.com 25 */ 26 27#include "defs.h" 28#include "frame.h" 29#include "frame-base.h" 30#include "frame-unwind.h" 31#include "dwarf2-frame.h" 32#include "symtab.h" 33#include "gdbtypes.h" 34#include "gdbcmd.h" 35#include "gdbcore.h" 36#include "value.h" 37#include "dis-asm.h" 38#include "inferior.h" 39#include "gdb_string.h" 40#include "gdb_assert.h" 41#include "arch-utils.h" 42#include "floatformat.h" 43#include "regcache.h" 44#include "doublest.h" 45#include "osabi.h" 46 47#include "sh-tdep.h" 48 49#include "elf-bfd.h" 50#include "solib-svr4.h" 51 52/* sh flags */ 53#include "elf/sh.h" 54/* registers numbers shared with the simulator */ 55#include "gdb/sim-sh.h" 56 57static void (*sh_show_regs) (void); 58 59#define SH_NUM_REGS 67 60 61struct sh_frame_cache 62{ 63 /* Base address. */ 64 CORE_ADDR base; 65 LONGEST sp_offset; 66 CORE_ADDR pc; 67 68 /* Flag showing that a frame has been created in the prologue code. */ 69 int uses_fp; 70 71 /* Saved registers. */ 72 CORE_ADDR saved_regs[SH_NUM_REGS]; 73 CORE_ADDR saved_sp; 74}; 75 76static const char * 77sh_sh_register_name (int reg_nr) 78{ 79 static char *register_names[] = { 80 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 81 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 82 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", 83 "", "", 84 "", "", "", "", "", "", "", "", 85 "", "", "", "", "", "", "", "", 86 "", "", 87 "", "", "", "", "", "", "", "", 88 "", "", "", "", "", "", "", "", 89 "", "", "", "", "", "", "", "", 90 }; 91 if (reg_nr < 0) 92 return NULL; 93 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) 94 return NULL; 95 return register_names[reg_nr]; 96} 97 98static const char * 99sh_sh3_register_name (int reg_nr) 100{ 101 static char *register_names[] = { 102 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 103 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 104 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", 105 "", "", 106 "", "", "", "", "", "", "", "", 107 "", "", "", "", "", "", "", "", 108 "ssr", "spc", 109 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", 110 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1" 111 "", "", "", "", "", "", "", "", 112 }; 113 if (reg_nr < 0) 114 return NULL; 115 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) 116 return NULL; 117 return register_names[reg_nr]; 118} 119 120static const char * 121sh_sh3e_register_name (int reg_nr) 122{ 123 static char *register_names[] = { 124 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 125 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 126 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", 127 "fpul", "fpscr", 128 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", 129 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", 130 "ssr", "spc", 131 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", 132 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1", 133 "", "", "", "", "", "", "", "", 134 }; 135 if (reg_nr < 0) 136 return NULL; 137 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) 138 return NULL; 139 return register_names[reg_nr]; 140} 141 142static const char * 143sh_sh2e_register_name (int reg_nr) 144{ 145 static char *register_names[] = { 146 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 147 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 148 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", 149 "fpul", "fpscr", 150 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", 151 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", 152 "", "", 153 "", "", "", "", "", "", "", "", 154 "", "", "", "", "", "", "", "", 155 "", "", "", "", "", "", "", "", 156 }; 157 if (reg_nr < 0) 158 return NULL; 159 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) 160 return NULL; 161 return register_names[reg_nr]; 162} 163 164#ifdef notyet 165static const char * 166sh_sh2a_register_name (int reg_nr) 167{ 168 static char *register_names[] = { 169 /* general registers 0-15 */ 170 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 171 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 172 /* 16 - 22 */ 173 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", 174 /* 23, 24 */ 175 "fpul", "fpscr", 176 /* floating point registers 25 - 40 */ 177 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", 178 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", 179 /* 41, 42 */ 180 "", "", 181 /* 43 - 62. Banked registers. The bank number used is determined by 182 the bank register (63). */ 183 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b", 184 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", 185 "machb", "ivnb", "prb", "gbrb", "maclb", 186 /* 63: register bank number, not a real register but used to 187 communicate the register bank currently get/set. This register 188 is hidden to the user, who manipulates it using the pseudo 189 register called "bank" (67). See below. */ 190 "", 191 /* 64 - 66 */ 192 "ibcr", "ibnr", "tbr", 193 /* 67: register bank number, the user visible pseudo register. */ 194 "bank", 195 /* double precision (pseudo) 68 - 75 */ 196 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", 197 }; 198 if (reg_nr < 0) 199 return NULL; 200 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) 201 return NULL; 202 return register_names[reg_nr]; 203} 204 205static const char * 206sh_sh2a_nofpu_register_name (int reg_nr) 207{ 208 static char *register_names[] = { 209 /* general registers 0-15 */ 210 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 211 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 212 /* 16 - 22 */ 213 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", 214 /* 23, 24 */ 215 "", "", 216 /* floating point registers 25 - 40 */ 217 "", "", "", "", "", "", "", "", 218 "", "", "", "", "", "", "", "", 219 /* 41, 42 */ 220 "", "", 221 /* 43 - 62. Banked registers. The bank number used is determined by 222 the bank register (63). */ 223 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b", 224 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", 225 "machb", "ivnb", "prb", "gbrb", "maclb", 226 /* 63: register bank number, not a real register but used to 227 communicate the register bank currently get/set. This register 228 is hidden to the user, who manipulates it using the pseudo 229 register called "bank" (67). See below. */ 230 "", 231 /* 64 - 66 */ 232 "ibcr", "ibnr", "tbr", 233 /* 67: register bank number, the user visible pseudo register. */ 234 "bank", 235 /* double precision (pseudo) 68 - 75 */ 236 "", "", "", "", "", "", "", "", 237 }; 238 if (reg_nr < 0) 239 return NULL; 240 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) 241 return NULL; 242 return register_names[reg_nr]; 243} 244#endif 245 246static const char * 247sh_sh_dsp_register_name (int reg_nr) 248{ 249 static char *register_names[] = { 250 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 251 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 252 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", 253 "", "dsr", 254 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1", 255 "y0", "y1", "", "", "", "", "", "mod", 256 "", "", 257 "rs", "re", "", "", "", "", "", "", 258 "", "", "", "", "", "", "", "", 259 "", "", "", "", "", "", "", "", 260 }; 261 if (reg_nr < 0) 262 return NULL; 263 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) 264 return NULL; 265 return register_names[reg_nr]; 266} 267 268static const char * 269sh_sh3_dsp_register_name (int reg_nr) 270{ 271 static char *register_names[] = { 272 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 273 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 274 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", 275 "", "dsr", 276 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1", 277 "y0", "y1", "", "", "", "", "", "mod", 278 "ssr", "spc", 279 "rs", "re", "", "", "", "", "", "", 280 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b", 281 "", "", "", "", "", "", "", "", 282 "", "", "", "", "", "", "", "", 283 }; 284 if (reg_nr < 0) 285 return NULL; 286 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) 287 return NULL; 288 return register_names[reg_nr]; 289} 290 291static const char * 292sh_sh4_register_name (int reg_nr) 293{ 294 static char *register_names[] = { 295 /* general registers 0-15 */ 296 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 297 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 298 /* 16 - 22 */ 299 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", 300 /* 23, 24 */ 301 "fpul", "fpscr", 302 /* floating point registers 25 - 40 */ 303 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", 304 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", 305 /* 41, 42 */ 306 "ssr", "spc", 307 /* bank 0 43 - 50 */ 308 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", 309 /* bank 1 51 - 58 */ 310 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1", 311 "", "", "", "", "", "", "", "", 312 /* pseudo bank register. */ 313 "", 314 /* double precision (pseudo) 59 - 66 */ 315 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", 316 /* vectors (pseudo) 67 - 70 */ 317 "fv0", "fv4", "fv8", "fv12", 318 /* FIXME: missing XF 71 - 86 */ 319 /* FIXME: missing XD 87 - 94 */ 320 }; 321 if (reg_nr < 0) 322 return NULL; 323 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) 324 return NULL; 325 return register_names[reg_nr]; 326} 327 328static const char * 329sh_sh4_nofpu_register_name (int reg_nr) 330{ 331 static char *register_names[] = { 332 /* general registers 0-15 */ 333 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 334 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 335 /* 16 - 22 */ 336 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", 337 /* 23, 24 */ 338 "", "", 339 /* floating point registers 25 - 40 -- not for nofpu target */ 340 "", "", "", "", "", "", "", "", 341 "", "", "", "", "", "", "", "", 342 /* 41, 42 */ 343 "ssr", "spc", 344 /* bank 0 43 - 50 */ 345 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", 346 /* bank 1 51 - 58 */ 347 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1", 348 "", "", "", "", "", "", "", "", 349 /* pseudo bank register. */ 350 "", 351 /* double precision (pseudo) 59 - 66 -- not for nofpu target */ 352 "", "", "", "", "", "", "", "", 353 /* vectors (pseudo) 67 - 70 -- not for nofpu target */ 354 "", "", "", "", 355 }; 356 if (reg_nr < 0) 357 return NULL; 358 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) 359 return NULL; 360 return register_names[reg_nr]; 361} 362 363static const char * 364sh_sh4al_dsp_register_name (int reg_nr) 365{ 366 static char *register_names[] = { 367 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 368 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 369 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", 370 "", "dsr", 371 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1", 372 "y0", "y1", "", "", "", "", "", "mod", 373 "ssr", "spc", 374 "rs", "re", "", "", "", "", "", "", 375 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b", 376 "", "", "", "", "", "", "", "", 377 "", "", "", "", "", "", "", "", 378 }; 379 if (reg_nr < 0) 380 return NULL; 381 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) 382 return NULL; 383 return register_names[reg_nr]; 384} 385 386static const unsigned char * 387sh_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) 388{ 389 /* 0xc3c3 is trapa #c3, and it works in big and little endian modes */ 390 static unsigned char breakpoint[] = { 0xc3, 0xc3 }; 391 392 *lenptr = sizeof (breakpoint); 393 return breakpoint; 394} 395 396/* Prologue looks like 397 mov.l r14,@-r15 398 sts.l pr,@-r15 399 mov.l <regs>,@-r15 400 sub <room_for_loca_vars>,r15 401 mov r15,r14 402 403 Actually it can be more complicated than this but that's it, basically. 404 */ 405 406#define GET_SOURCE_REG(x) (((x) >> 4) & 0xf) 407#define GET_TARGET_REG(x) (((x) >> 8) & 0xf) 408 409/* JSR @Rm 0100mmmm00001011 */ 410#define IS_JSR(x) (((x) & 0xf0ff) == 0x400b) 411 412/* STS.L PR,@-r15 0100111100100010 413 r15-4-->r15, PR-->(r15) */ 414#define IS_STS(x) ((x) == 0x4f22) 415 416/* STS.L MACL,@-r15 0100111100010010 417 r15-4-->r15, MACL-->(r15) */ 418#define IS_MACL_STS(x) ((x) == 0x4f12) 419 420/* MOV.L Rm,@-r15 00101111mmmm0110 421 r15-4-->r15, Rm-->(R15) */ 422#define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06) 423 424/* MOV r15,r14 0110111011110011 425 r15-->r14 */ 426#define IS_MOV_SP_FP(x) ((x) == 0x6ef3) 427 428/* ADD #imm,r15 01111111iiiiiiii 429 r15+imm-->r15 */ 430#define IS_ADD_IMM_SP(x) (((x) & 0xff00) == 0x7f00) 431 432#define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00) 433#define IS_SHLL_R3(x) ((x) == 0x4300) 434 435/* ADD r3,r15 0011111100111100 436 r15+r3-->r15 */ 437#define IS_ADD_R3SP(x) ((x) == 0x3f3c) 438 439/* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011 440 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011 441 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */ 442/* CV, 2003-08-28: Only suitable with Rn == SP, therefore name changed to 443 make this entirely clear. */ 444/* #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b) */ 445#define IS_FPUSH(x) (((x) & 0xff0f) == 0xff0b) 446 447/* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011 4 <= m <= 7 */ 448#define IS_MOV_ARG_TO_REG(x) \ 449 (((x) & 0xf00f) == 0x6003 && \ 450 ((x) & 0x00f0) >= 0x0040 && \ 451 ((x) & 0x00f0) <= 0x0070) 452/* MOV.L Rm,@Rn 0010nnnnmmmm0010 n = 14, 4 <= m <= 7 */ 453#define IS_MOV_ARG_TO_IND_R14(x) \ 454 (((x) & 0xff0f) == 0x2e02 && \ 455 ((x) & 0x00f0) >= 0x0040 && \ 456 ((x) & 0x00f0) <= 0x0070) 457/* MOV.L Rm,@(disp*4,Rn) 00011110mmmmdddd n = 14, 4 <= m <= 7 */ 458#define IS_MOV_ARG_TO_IND_R14_WITH_DISP(x) \ 459 (((x) & 0xff00) == 0x1e00 && \ 460 ((x) & 0x00f0) >= 0x0040 && \ 461 ((x) & 0x00f0) <= 0x0070) 462 463/* MOV.W @(disp*2,PC),Rn 1001nnnndddddddd */ 464#define IS_MOVW_PCREL_TO_REG(x) (((x) & 0xf000) == 0x9000) 465/* MOV.L @(disp*4,PC),Rn 1101nnnndddddddd */ 466#define IS_MOVL_PCREL_TO_REG(x) (((x) & 0xf000) == 0xd000) 467/* MOVI20 #imm20,Rn 0000nnnniiii0000 */ 468#define IS_MOVI20(x) (((x) & 0xf00f) == 0x0000) 469/* SUB Rn,R15 00111111nnnn1000 */ 470#define IS_SUB_REG_FROM_SP(x) (((x) & 0xff0f) == 0x3f08) 471 472#define FPSCR_SZ (1 << 20) 473 474/* The following instructions are used for epilogue testing. */ 475#define IS_RESTORE_FP(x) ((x) == 0x6ef6) 476#define IS_RTS(x) ((x) == 0x000b) 477#define IS_LDS(x) ((x) == 0x4f26) 478#define IS_MACL_LDS(x) ((x) == 0x4f16) 479#define IS_MOV_FP_SP(x) ((x) == 0x6fe3) 480#define IS_ADD_REG_TO_FP(x) (((x) & 0xff0f) == 0x3e0c) 481#define IS_ADD_IMM_FP(x) (((x) & 0xff00) == 0x7e00) 482 483/* Disassemble an instruction. */ 484static int 485gdb_print_insn_sh (bfd_vma memaddr, disassemble_info * info) 486{ 487 info->endian = TARGET_BYTE_ORDER; 488 return print_insn_sh (memaddr, info); 489} 490 491static CORE_ADDR 492sh_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc, 493 struct sh_frame_cache *cache) 494{ 495 ULONGEST inst; 496 CORE_ADDR opc; 497 int offset; 498 int sav_offset = 0; 499 int r3_val = 0; 500 int reg, sav_reg = -1; 501 502 if (pc >= current_pc) 503 return current_pc; 504 505 cache->uses_fp = 0; 506 for (opc = pc + (2 * 28); pc < opc; pc += 2) 507 { 508 inst = read_memory_unsigned_integer (pc, 2); 509 /* See where the registers will be saved to */ 510 if (IS_PUSH (inst)) 511 { 512 cache->saved_regs[GET_SOURCE_REG (inst)] = cache->sp_offset; 513 cache->sp_offset += 4; 514 } 515 else if (IS_STS (inst)) 516 { 517 cache->saved_regs[PR_REGNUM] = cache->sp_offset; 518 cache->sp_offset += 4; 519 } 520 else if (IS_MACL_STS (inst)) 521 { 522 cache->saved_regs[MACL_REGNUM] = cache->sp_offset; 523 cache->sp_offset += 4; 524 } 525 else if (IS_MOV_R3 (inst)) 526 { 527 r3_val = ((inst & 0xff) ^ 0x80) - 0x80; 528 } 529 else if (IS_SHLL_R3 (inst)) 530 { 531 r3_val <<= 1; 532 } 533 else if (IS_ADD_R3SP (inst)) 534 { 535 cache->sp_offset += -r3_val; 536 } 537 else if (IS_ADD_IMM_SP (inst)) 538 { 539 offset = ((inst & 0xff) ^ 0x80) - 0x80; 540 cache->sp_offset -= offset; 541 } 542 else if (IS_MOVW_PCREL_TO_REG (inst)) 543 { 544 if (sav_reg < 0) 545 { 546 reg = GET_TARGET_REG (inst); 547 if (reg < 14) 548 { 549 sav_reg = reg; 550 offset = (inst & 0xff) << 1; 551 sav_offset = 552 read_memory_integer ((pc + 4) + offset, 2); 553 } 554 } 555 } 556 else if (IS_MOVL_PCREL_TO_REG (inst)) 557 { 558 if (sav_reg < 0) 559 { 560 reg = GET_TARGET_REG (inst); 561 if (reg < 14) 562 { 563 sav_reg = reg; 564 offset = (inst & 0xff) << 2; 565 sav_offset = 566 read_memory_integer (((pc & 0xfffffffc) + 4) + offset, 4); 567 } 568 } 569 } 570 else if (IS_MOVI20 (inst)) 571 { 572 if (sav_reg < 0) 573 { 574 reg = GET_TARGET_REG (inst); 575 if (reg < 14) 576 { 577 sav_reg = reg; 578 sav_offset = GET_SOURCE_REG (inst) << 16; 579 /* MOVI20 is a 32 bit instruction! */ 580 pc += 2; 581 sav_offset |= read_memory_unsigned_integer (pc, 2); 582 /* Now sav_offset contains an unsigned 20 bit value. 583 It must still get sign extended. */ 584 if (sav_offset & 0x00080000) 585 sav_offset |= 0xfff00000; 586 } 587 } 588 } 589 else if (IS_SUB_REG_FROM_SP (inst)) 590 { 591 reg = GET_SOURCE_REG (inst); 592 if (sav_reg > 0 && reg == sav_reg) 593 { 594 sav_reg = -1; 595 } 596 cache->sp_offset += sav_offset; 597 } 598 else if (IS_FPUSH (inst)) 599 { 600 if (read_register (FPSCR_REGNUM) & FPSCR_SZ) 601 { 602 cache->sp_offset += 8; 603 } 604 else 605 { 606 cache->sp_offset += 4; 607 } 608 } 609 else if (IS_MOV_SP_FP (inst)) 610 { 611 cache->uses_fp = 1; 612 /* At this point, only allow argument register moves to other 613 registers or argument register moves to @(X,fp) which are 614 moving the register arguments onto the stack area allocated 615 by a former add somenumber to SP call. Don't allow moving 616 to an fp indirect address above fp + cache->sp_offset. */ 617 pc += 2; 618 for (opc = pc + 12; pc < opc; pc += 2) 619 { 620 inst = read_memory_integer (pc, 2); 621 if (IS_MOV_ARG_TO_IND_R14 (inst)) 622 { 623 reg = GET_SOURCE_REG (inst); 624 if (cache->sp_offset > 0) 625 cache->saved_regs[reg] = cache->sp_offset; 626 } 627 else if (IS_MOV_ARG_TO_IND_R14_WITH_DISP (inst)) 628 { 629 reg = GET_SOURCE_REG (inst); 630 offset = (inst & 0xf) * 4; 631 if (cache->sp_offset > offset) 632 cache->saved_regs[reg] = cache->sp_offset - offset; 633 } 634 else if (IS_MOV_ARG_TO_REG (inst)) 635 continue; 636 else 637 break; 638 } 639 break; 640 } 641 else if (IS_JSR (inst)) 642 { 643 /* We have found a jsr that has been scheduled into the prologue. 644 If we continue the scan and return a pc someplace after this, 645 then setting a breakpoint on this function will cause it to 646 appear to be called after the function it is calling via the 647 jsr, which will be very confusing. Most likely the next 648 instruction is going to be IS_MOV_SP_FP in the delay slot. If 649 so, note that before returning the current pc. */ 650 inst = read_memory_integer (pc + 2, 2); 651 if (IS_MOV_SP_FP (inst)) 652 cache->uses_fp = 1; 653 break; 654 } 655#if 0 /* This used to just stop when it found an instruction that 656 was not considered part of the prologue. Now, we just 657 keep going looking for likely instructions. */ 658 else 659 break; 660#endif 661 } 662 663 return pc; 664} 665 666/* Skip any prologue before the guts of a function */ 667 668/* Skip the prologue using the debug information. If this fails we'll 669 fall back on the 'guess' method below. */ 670static CORE_ADDR 671after_prologue (CORE_ADDR pc) 672{ 673 struct symtab_and_line sal; 674 CORE_ADDR func_addr, func_end; 675 676 /* If we can not find the symbol in the partial symbol table, then 677 there is no hope we can determine the function's start address 678 with this code. */ 679 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) 680 return 0; 681 682 /* Get the line associated with FUNC_ADDR. */ 683 sal = find_pc_line (func_addr, 0); 684 685 /* There are only two cases to consider. First, the end of the source line 686 is within the function bounds. In that case we return the end of the 687 source line. Second is the end of the source line extends beyond the 688 bounds of the current function. We need to use the slow code to 689 examine instructions in that case. */ 690 if (sal.end < func_end) 691 return sal.end; 692 else 693 return 0; 694} 695 696static CORE_ADDR 697sh_skip_prologue (CORE_ADDR start_pc) 698{ 699 CORE_ADDR pc; 700 struct sh_frame_cache cache; 701 702 /* See if we can determine the end of the prologue via the symbol table. 703 If so, then return either PC, or the PC after the prologue, whichever 704 is greater. */ 705 pc = after_prologue (start_pc); 706 707 /* If after_prologue returned a useful address, then use it. Else 708 fall back on the instruction skipping code. */ 709 if (pc) 710 return max (pc, start_pc); 711 712 cache.sp_offset = -4; 713 pc = sh_analyze_prologue (start_pc, (CORE_ADDR) -1, &cache); 714 if (!cache.uses_fp) 715 return start_pc; 716 717 return pc; 718} 719 720/* The ABI says: 721 722 Aggregate types not bigger than 8 bytes that have the same size and 723 alignment as one of the integer scalar types are returned in the 724 same registers as the integer type they match. 725 726 For example, a 2-byte aligned structure with size 2 bytes has the 727 same size and alignment as a short int, and will be returned in R0. 728 A 4-byte aligned structure with size 8 bytes has the same size and 729 alignment as a long long int, and will be returned in R0 and R1. 730 731 When an aggregate type is returned in R0 and R1, R0 contains the 732 first four bytes of the aggregate, and R1 contains the 733 remainder. If the size of the aggregate type is not a multiple of 4 734 bytes, the aggregate is tail-padded up to a multiple of 4 735 bytes. The value of the padding is undefined. For little-endian 736 targets the padding will appear at the most significant end of the 737 last element, for big-endian targets the padding appears at the 738 least significant end of the last element. 739 740 All other aggregate types are returned by address. The caller 741 function passes the address of an area large enough to hold the 742 aggregate value in R2. The called function stores the result in 743 this location. 744 745 To reiterate, structs smaller than 8 bytes could also be returned 746 in memory, if they don't pass the "same size and alignment as an 747 integer type" rule. 748 749 For example, in 750 751 struct s { char c[3]; } wibble; 752 struct s foo(void) { return wibble; } 753 754 the return value from foo() will be in memory, not 755 in R0, because there is no 3-byte integer type. 756 757 Similarly, in 758 759 struct s { char c[2]; } wibble; 760 struct s foo(void) { return wibble; } 761 762 because a struct containing two chars has alignment 1, that matches 763 type char, but size 2, that matches type short. There's no integer 764 type that has alignment 1 and size 2, so the struct is returned in 765 memory. 766 767*/ 768 769static int 770sh_use_struct_convention (int gcc_p, struct type *type) 771{ 772 int len = TYPE_LENGTH (type); 773 int nelem = TYPE_NFIELDS (type); 774 775 /* Non-power of 2 length types and types bigger than 8 bytes (which don't 776 fit in two registers anyway) use struct convention. */ 777 if (len != 1 && len != 2 && len != 4 && len != 8) 778 return 1; 779 780 /* Scalar types and aggregate types with exactly one field are aligned 781 by definition. They are returned in registers. */ 782 if (nelem <= 1) 783 return 0; 784 785 /* If the first field in the aggregate has the same length as the entire 786 aggregate type, the type is returned in registers. */ 787 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == len) 788 return 0; 789 790 /* If the size of the aggregate is 8 bytes and the first field is 791 of size 4 bytes its alignment is equal to long long's alignment, 792 so it's returned in registers. */ 793 if (len == 8 && TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == 4) 794 return 0; 795 796 /* Otherwise use struct convention. */ 797 return 1; 798} 799 800/* Extract from an array REGBUF containing the (raw) register state 801 the address in which a function should return its structure value, 802 as a CORE_ADDR (or an expression that can be used as one). */ 803static CORE_ADDR 804sh_extract_struct_value_address (struct regcache *regcache) 805{ 806 ULONGEST addr; 807 808 regcache_cooked_read_unsigned (regcache, STRUCT_RETURN_REGNUM, &addr); 809 return addr; 810} 811 812static CORE_ADDR 813sh_frame_align (struct gdbarch *ignore, CORE_ADDR sp) 814{ 815 return sp & ~3; 816} 817 818/* Function: push_dummy_call (formerly push_arguments) 819 Setup the function arguments for calling a function in the inferior. 820 821 On the Renesas SH architecture, there are four registers (R4 to R7) 822 which are dedicated for passing function arguments. Up to the first 823 four arguments (depending on size) may go into these registers. 824 The rest go on the stack. 825 826 MVS: Except on SH variants that have floating point registers. 827 In that case, float and double arguments are passed in the same 828 manner, but using FP registers instead of GP registers. 829 830 Arguments that are smaller than 4 bytes will still take up a whole 831 register or a whole 32-bit word on the stack, and will be 832 right-justified in the register or the stack word. This includes 833 chars, shorts, and small aggregate types. 834 835 Arguments that are larger than 4 bytes may be split between two or 836 more registers. If there are not enough registers free, an argument 837 may be passed partly in a register (or registers), and partly on the 838 stack. This includes doubles, long longs, and larger aggregates. 839 As far as I know, there is no upper limit to the size of aggregates 840 that will be passed in this way; in other words, the convention of 841 passing a pointer to a large aggregate instead of a copy is not used. 842 843 MVS: The above appears to be true for the SH variants that do not 844 have an FPU, however those that have an FPU appear to copy the 845 aggregate argument onto the stack (and not place it in registers) 846 if it is larger than 16 bytes (four GP registers). 847 848 An exceptional case exists for struct arguments (and possibly other 849 aggregates such as arrays) if the size is larger than 4 bytes but 850 not a multiple of 4 bytes. In this case the argument is never split 851 between the registers and the stack, but instead is copied in its 852 entirety onto the stack, AND also copied into as many registers as 853 there is room for. In other words, space in registers permitting, 854 two copies of the same argument are passed in. As far as I can tell, 855 only the one on the stack is used, although that may be a function 856 of the level of compiler optimization. I suspect this is a compiler 857 bug. Arguments of these odd sizes are left-justified within the 858 word (as opposed to arguments smaller than 4 bytes, which are 859 right-justified). 860 861 If the function is to return an aggregate type such as a struct, it 862 is either returned in the normal return value register R0 (if its 863 size is no greater than one byte), or else the caller must allocate 864 space into which the callee will copy the return value (if the size 865 is greater than one byte). In this case, a pointer to the return 866 value location is passed into the callee in register R2, which does 867 not displace any of the other arguments passed in via registers R4 868 to R7. */ 869 870/* Helper function to justify value in register according to endianess. */ 871static char * 872sh_justify_value_in_reg (struct value *val, int len) 873{ 874 static char valbuf[4]; 875 876 memset (valbuf, 0, sizeof (valbuf)); 877 if (len < 4) 878 { 879 /* value gets right-justified in the register or stack word */ 880 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) 881 memcpy (valbuf + (4 - len), (char *) VALUE_CONTENTS (val), len); 882 else 883 memcpy (valbuf, (char *) VALUE_CONTENTS (val), len); 884 return valbuf; 885 } 886 return (char *) VALUE_CONTENTS (val); 887} 888 889/* Helper function to eval number of bytes to allocate on stack. */ 890static CORE_ADDR 891sh_stack_allocsize (int nargs, struct value **args) 892{ 893 int stack_alloc = 0; 894 while (nargs-- > 0) 895 stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[nargs])) + 3) & ~3); 896 return stack_alloc; 897} 898 899/* Helper functions for getting the float arguments right. Registers usage 900 depends on the ABI and the endianess. The comments should enlighten how 901 it's intended to work. */ 902 903/* This array stores which of the float arg registers are already in use. */ 904static int flt_argreg_array[FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM + 1]; 905 906/* This function just resets the above array to "no reg used so far". */ 907static void 908sh_init_flt_argreg (void) 909{ 910 memset (flt_argreg_array, 0, sizeof flt_argreg_array); 911} 912 913/* This function returns the next register to use for float arg passing. 914 It returns either a valid value between FLOAT_ARG0_REGNUM and 915 FLOAT_ARGLAST_REGNUM if a register is available, otherwise it returns 916 FLOAT_ARGLAST_REGNUM + 1 to indicate that no register is available. 917 918 Note that register number 0 in flt_argreg_array corresponds with the 919 real float register fr4. In contrast to FLOAT_ARG0_REGNUM (value is 920 29) the parity of the register number is preserved, which is important 921 for the double register passing test (see the "argreg & 1" test below). */ 922static int 923sh_next_flt_argreg (int len) 924{ 925 int argreg; 926 927 /* First search for the next free register. */ 928 for (argreg = 0; argreg <= FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM; 929 ++argreg) 930 if (!flt_argreg_array[argreg]) 931 break; 932 933 /* No register left? */ 934 if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM) 935 return FLOAT_ARGLAST_REGNUM + 1; 936 937 if (len == 8) 938 { 939 /* Doubles are always starting in a even register number. */ 940 if (argreg & 1) 941 { 942 flt_argreg_array[argreg] = 1; 943 944 ++argreg; 945 946 /* No register left? */ 947 if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM) 948 return FLOAT_ARGLAST_REGNUM + 1; 949 } 950 /* Also mark the next register as used. */ 951 flt_argreg_array[argreg + 1] = 1; 952 } 953 else if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) 954 { 955 /* In little endian, gcc passes floats like this: f5, f4, f7, f6, ... */ 956 if (!flt_argreg_array[argreg + 1]) 957 ++argreg; 958 } 959 flt_argreg_array[argreg] = 1; 960 return FLOAT_ARG0_REGNUM + argreg; 961} 962 963/* Helper function which figures out, if a type is treated like a float type. 964 965 The FPU ABIs have a special way how to treat types as float types. 966 Structures with exactly one member, which is of type float or double, are 967 treated exactly as the base types float or double: 968 969 struct sf { 970 float f; 971 }; 972 973 struct sd { 974 double d; 975 }; 976 977 are handled the same way as just 978 979 float f; 980 981 double d; 982 983 As a result, arguments of these struct types are pushed into floating point 984 registers exactly as floats or doubles, using the same decision algorithm. 985 986 The same is valid if these types are used as function return types. The 987 above structs are returned in fr0 resp. fr0,fr1 instead of in r0, r0,r1 988 or even using struct convention as it is for other structs. */ 989 990static int 991sh_treat_as_flt_p (struct type *type) 992{ 993 int len = TYPE_LENGTH (type); 994 995 /* Ordinary float types are obviously treated as float. */ 996 if (TYPE_CODE (type) == TYPE_CODE_FLT) 997 return 1; 998 /* Otherwise non-struct types are not treated as float. */ 999 if (TYPE_CODE (type) != TYPE_CODE_STRUCT) 1000 return 0; 1001 /* Otherwise structs with more than one memeber are not treated as float. */ 1002 if (TYPE_NFIELDS (type) != 1) 1003 return 0; 1004 /* Otherwise if the type of that member is float, the whole type is 1005 treated as float. */ 1006 if (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) == TYPE_CODE_FLT) 1007 return 1; 1008 /* Otherwise it's not treated as float. */ 1009 return 0; 1010} 1011 1012static CORE_ADDR 1013sh_push_dummy_call_fpu (struct gdbarch *gdbarch, 1014 struct value *function, 1015 struct regcache *regcache, 1016 CORE_ADDR bp_addr, int nargs, 1017 struct value **args, 1018 CORE_ADDR sp, int struct_return, 1019 CORE_ADDR struct_addr) 1020{ 1021 int stack_offset = 0; 1022 int argreg = ARG0_REGNUM; 1023 int flt_argreg = 0; 1024 int argnum; 1025 struct type *type; 1026 CORE_ADDR regval; 1027 char *val; 1028 int len, reg_size = 0; 1029 int pass_on_stack = 0; 1030 int treat_as_flt; 1031 1032 /* first force sp to a 4-byte alignment */ 1033 sp = sh_frame_align (gdbarch, sp); 1034 1035 if (struct_return) 1036 regcache_cooked_write_unsigned (regcache, 1037 STRUCT_RETURN_REGNUM, struct_addr); 1038 1039 /* make room on stack for args */ 1040 sp -= sh_stack_allocsize (nargs, args); 1041 1042 /* Initialize float argument mechanism. */ 1043 sh_init_flt_argreg (); 1044 1045 /* Now load as many as possible of the first arguments into 1046 registers, and push the rest onto the stack. There are 16 bytes 1047 in four registers available. Loop thru args from first to last. */ 1048 for (argnum = 0; argnum < nargs; argnum++) 1049 { 1050 type = VALUE_TYPE (args[argnum]); 1051 len = TYPE_LENGTH (type); 1052 val = sh_justify_value_in_reg (args[argnum], len); 1053 1054 /* Some decisions have to be made how various types are handled. 1055 This also differs in different ABIs. */ 1056 pass_on_stack = 0; 1057 1058 /* Find out the next register to use for a floating point value. */ 1059 treat_as_flt = sh_treat_as_flt_p (type); 1060 if (treat_as_flt) 1061 flt_argreg = sh_next_flt_argreg (len); 1062 /* In contrast to non-FPU CPUs, arguments are never split between 1063 registers and stack. If an argument doesn't fit in the remaining 1064 registers it's always pushed entirely on the stack. */ 1065 else if (len > ((ARGLAST_REGNUM - argreg + 1) * 4)) 1066 pass_on_stack = 1; 1067 1068 while (len > 0) 1069 { 1070 if ((treat_as_flt && flt_argreg > FLOAT_ARGLAST_REGNUM) 1071 || (!treat_as_flt && (argreg > ARGLAST_REGNUM 1072 || pass_on_stack))) 1073 { 1074 /* The data goes entirely on the stack, 4-byte aligned. */ 1075 reg_size = (len + 3) & ~3; 1076 write_memory (sp + stack_offset, val, reg_size); 1077 stack_offset += reg_size; 1078 } 1079 else if (treat_as_flt && flt_argreg <= FLOAT_ARGLAST_REGNUM) 1080 { 1081 /* Argument goes in a float argument register. */ 1082 reg_size = register_size (gdbarch, flt_argreg); 1083 regval = extract_unsigned_integer (val, reg_size); 1084 /* In little endian mode, float types taking two registers 1085 (doubles on sh4, long doubles on sh2e, sh3e and sh4) must 1086 be stored swapped in the argument registers. The below 1087 code first writes the first 32 bits in the next but one 1088 register, increments the val and len values accordingly 1089 and then proceeds as normal by writing the second 32 bits 1090 into the next register. */ 1091 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE 1092 && TYPE_LENGTH (type) == 2 * reg_size) 1093 { 1094 regcache_cooked_write_unsigned (regcache, flt_argreg + 1, 1095 regval); 1096 val += reg_size; 1097 len -= reg_size; 1098 regval = extract_unsigned_integer (val, reg_size); 1099 } 1100 regcache_cooked_write_unsigned (regcache, flt_argreg++, regval); 1101 } 1102 else if (!treat_as_flt && argreg <= ARGLAST_REGNUM) 1103 { 1104 /* there's room in a register */ 1105 reg_size = register_size (gdbarch, argreg); 1106 regval = extract_unsigned_integer (val, reg_size); 1107 regcache_cooked_write_unsigned (regcache, argreg++, regval); 1108 } 1109 /* Store the value one register at a time or in one step on stack. */ 1110 len -= reg_size; 1111 val += reg_size; 1112 } 1113 } 1114 1115 /* Store return address. */ 1116 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr); 1117 1118 /* Update stack pointer. */ 1119 regcache_cooked_write_unsigned (regcache, SP_REGNUM, sp); 1120 1121 return sp; 1122} 1123 1124static CORE_ADDR 1125sh_push_dummy_call_nofpu (struct gdbarch *gdbarch, 1126 struct value *function, 1127 struct regcache *regcache, 1128 CORE_ADDR bp_addr, 1129 int nargs, struct value **args, 1130 CORE_ADDR sp, int struct_return, 1131 CORE_ADDR struct_addr) 1132{ 1133 int stack_offset = 0; 1134 int argreg = ARG0_REGNUM; 1135 int argnum; 1136 struct type *type; 1137 CORE_ADDR regval; 1138 char *val; 1139 int len, reg_size; 1140 1141 /* first force sp to a 4-byte alignment */ 1142 sp = sh_frame_align (gdbarch, sp); 1143 1144 if (struct_return) 1145 regcache_cooked_write_unsigned (regcache, 1146 STRUCT_RETURN_REGNUM, struct_addr); 1147 1148 /* make room on stack for args */ 1149 sp -= sh_stack_allocsize (nargs, args); 1150 1151 /* Now load as many as possible of the first arguments into 1152 registers, and push the rest onto the stack. There are 16 bytes 1153 in four registers available. Loop thru args from first to last. */ 1154 for (argnum = 0; argnum < nargs; argnum++) 1155 { 1156 type = VALUE_TYPE (args[argnum]); 1157 len = TYPE_LENGTH (type); 1158 val = sh_justify_value_in_reg (args[argnum], len); 1159 1160 while (len > 0) 1161 { 1162 if (argreg > ARGLAST_REGNUM) 1163 { 1164 /* The remainder of the data goes entirely on the stack, 1165 4-byte aligned. */ 1166 reg_size = (len + 3) & ~3; 1167 write_memory (sp + stack_offset, val, reg_size); 1168 stack_offset += reg_size; 1169 } 1170 else if (argreg <= ARGLAST_REGNUM) 1171 { 1172 /* there's room in a register */ 1173 reg_size = register_size (gdbarch, argreg); 1174 regval = extract_unsigned_integer (val, reg_size); 1175 regcache_cooked_write_unsigned (regcache, argreg++, regval); 1176 } 1177 /* Store the value reg_size bytes at a time. This means that things 1178 larger than reg_size bytes may go partly in registers and partly 1179 on the stack. */ 1180 len -= reg_size; 1181 val += reg_size; 1182 } 1183 } 1184 1185 /* Store return address. */ 1186 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr); 1187 1188 /* Update stack pointer. */ 1189 regcache_cooked_write_unsigned (regcache, SP_REGNUM, sp); 1190 1191 return sp; 1192} 1193 1194/* Find a function's return value in the appropriate registers (in 1195 regbuf), and copy it into valbuf. Extract from an array REGBUF 1196 containing the (raw) register state a function return value of type 1197 TYPE, and copy that, in virtual format, into VALBUF. */ 1198static void 1199sh_default_extract_return_value (struct type *type, struct regcache *regcache, 1200 void *valbuf) 1201{ 1202 int len = TYPE_LENGTH (type); 1203 int return_register = R0_REGNUM; 1204 int offset; 1205 1206 if (len <= 4) 1207 { 1208 ULONGEST c; 1209 1210 regcache_cooked_read_unsigned (regcache, R0_REGNUM, &c); 1211 store_unsigned_integer (valbuf, len, c); 1212 } 1213 else if (len == 8) 1214 { 1215 int i, regnum = R0_REGNUM; 1216 for (i = 0; i < len; i += 4) 1217 regcache_raw_read (regcache, regnum++, (char *) valbuf + i); 1218 } 1219 else 1220 error ("bad size for return value"); 1221} 1222 1223static void 1224sh3e_sh4_extract_return_value (struct type *type, struct regcache *regcache, 1225 void *valbuf) 1226{ 1227 if (sh_treat_as_flt_p (type)) 1228 { 1229 int len = TYPE_LENGTH (type); 1230 int i, regnum = FP0_REGNUM; 1231 for (i = 0; i < len; i += 4) 1232 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) 1233 regcache_raw_read (regcache, regnum++, (char *) valbuf + len - 4 - i); 1234 else 1235 regcache_raw_read (regcache, regnum++, (char *) valbuf + i); 1236 } 1237 else 1238 sh_default_extract_return_value (type, regcache, valbuf); 1239} 1240 1241/* Write into appropriate registers a function return value 1242 of type TYPE, given in virtual format. 1243 If the architecture is sh4 or sh3e, store a function's return value 1244 in the R0 general register or in the FP0 floating point register, 1245 depending on the type of the return value. In all the other cases 1246 the result is stored in r0, left-justified. */ 1247static void 1248sh_default_store_return_value (struct type *type, struct regcache *regcache, 1249 const void *valbuf) 1250{ 1251 ULONGEST val; 1252 int len = TYPE_LENGTH (type); 1253 1254 if (len <= 4) 1255 { 1256 val = extract_unsigned_integer (valbuf, len); 1257 regcache_cooked_write_unsigned (regcache, R0_REGNUM, val); 1258 } 1259 else 1260 { 1261 int i, regnum = R0_REGNUM; 1262 for (i = 0; i < len; i += 4) 1263 regcache_raw_write (regcache, regnum++, (char *) valbuf + i); 1264 } 1265} 1266 1267static void 1268sh3e_sh4_store_return_value (struct type *type, struct regcache *regcache, 1269 const void *valbuf) 1270{ 1271 if (sh_treat_as_flt_p (type)) 1272 { 1273 int len = TYPE_LENGTH (type); 1274 int i, regnum = FP0_REGNUM; 1275 for (i = 0; i < len; i += 4) 1276 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) 1277 regcache_raw_write (regcache, regnum++, 1278 (char *) valbuf + len - 4 - i); 1279 else 1280 regcache_raw_write (regcache, regnum++, (char *) valbuf + i); 1281 } 1282 else 1283 sh_default_store_return_value (type, regcache, valbuf); 1284} 1285 1286static enum return_value_convention 1287sh_return_value_nofpu (struct gdbarch *gdbarch, struct type *type, 1288 struct regcache *regcache, 1289 void *readbuf, const void *writebuf) 1290{ 1291 if (sh_use_struct_convention (0, type)) 1292 return RETURN_VALUE_STRUCT_CONVENTION; 1293 if (writebuf) 1294 sh_default_store_return_value (type, regcache, writebuf); 1295 else if (readbuf) 1296 sh_default_extract_return_value (type, regcache, readbuf); 1297 return RETURN_VALUE_REGISTER_CONVENTION; 1298} 1299 1300static enum return_value_convention 1301sh_return_value_fpu (struct gdbarch *gdbarch, struct type *type, 1302 struct regcache *regcache, 1303 void *readbuf, const void *writebuf) 1304{ 1305 if (sh_use_struct_convention (0, type)) 1306 return RETURN_VALUE_STRUCT_CONVENTION; 1307 if (writebuf) 1308 sh3e_sh4_store_return_value (type, regcache, writebuf); 1309 else if (readbuf) 1310 sh3e_sh4_extract_return_value (type, regcache, readbuf); 1311 return RETURN_VALUE_REGISTER_CONVENTION; 1312} 1313 1314/* Print the registers in a form similar to the E7000 */ 1315 1316static void 1317sh_generic_show_regs (void) 1318{ 1319 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n", 1320 paddr (read_register (PC_REGNUM)), 1321 (long) read_register (SR_REGNUM), 1322 (long) read_register (PR_REGNUM), 1323 (long) read_register (MACH_REGNUM), 1324 (long) read_register (MACL_REGNUM)); 1325 1326 printf_filtered ("GBR=%08lx VBR=%08lx", 1327 (long) read_register (GBR_REGNUM), 1328 (long) read_register (VBR_REGNUM)); 1329 1330 printf_filtered 1331 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", 1332 (long) read_register (0), (long) read_register (1), 1333 (long) read_register (2), (long) read_register (3), 1334 (long) read_register (4), (long) read_register (5), 1335 (long) read_register (6), (long) read_register (7)); 1336 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", 1337 (long) read_register (8), (long) read_register (9), 1338 (long) read_register (10), (long) read_register (11), 1339 (long) read_register (12), (long) read_register (13), 1340 (long) read_register (14), (long) read_register (15)); 1341} 1342 1343static void 1344sh3_show_regs (void) 1345{ 1346 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n", 1347 paddr (read_register (PC_REGNUM)), 1348 (long) read_register (SR_REGNUM), 1349 (long) read_register (PR_REGNUM), 1350 (long) read_register (MACH_REGNUM), 1351 (long) read_register (MACL_REGNUM)); 1352 1353 printf_filtered ("GBR=%08lx VBR=%08lx", 1354 (long) read_register (GBR_REGNUM), 1355 (long) read_register (VBR_REGNUM)); 1356 printf_filtered (" SSR=%08lx SPC=%08lx", 1357 (long) read_register (SSR_REGNUM), 1358 (long) read_register (SPC_REGNUM)); 1359 1360 printf_filtered 1361 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", 1362 (long) read_register (0), (long) read_register (1), 1363 (long) read_register (2), (long) read_register (3), 1364 (long) read_register (4), (long) read_register (5), 1365 (long) read_register (6), (long) read_register (7)); 1366 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", 1367 (long) read_register (8), (long) read_register (9), 1368 (long) read_register (10), (long) read_register (11), 1369 (long) read_register (12), (long) read_register (13), 1370 (long) read_register (14), (long) read_register (15)); 1371} 1372 1373 1374static void 1375sh2e_show_regs (void) 1376{ 1377 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n", 1378 paddr (read_register (PC_REGNUM)), 1379 (long) read_register (SR_REGNUM), 1380 (long) read_register (PR_REGNUM), 1381 (long) read_register (MACH_REGNUM), 1382 (long) read_register (MACL_REGNUM)); 1383 1384 printf_filtered ("GBR=%08lx VBR=%08lx", 1385 (long) read_register (GBR_REGNUM), 1386 (long) read_register (VBR_REGNUM)); 1387 printf_filtered (" FPUL=%08lx FPSCR=%08lx", 1388 (long) read_register (FPUL_REGNUM), 1389 (long) read_register (FPSCR_REGNUM)); 1390 1391 printf_filtered 1392 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", 1393 (long) read_register (0), (long) read_register (1), 1394 (long) read_register (2), (long) read_register (3), 1395 (long) read_register (4), (long) read_register (5), 1396 (long) read_register (6), (long) read_register (7)); 1397 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", 1398 (long) read_register (8), (long) read_register (9), 1399 (long) read_register (10), (long) read_register (11), 1400 (long) read_register (12), (long) read_register (13), 1401 (long) read_register (14), (long) read_register (15)); 1402 1403 printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 0), (long) read_register (FP0_REGNUM + 1), (long) read_register (FP0_REGNUM + 2), (long) read_register (FP0_REGNUM + 3), (long) read_register (FP0_REGNUM + 4), (long) read_register (FP0_REGNUM + 5), (long) read_register (FP0_REGNUM + 6), (long) read_register (FP0_REGNUM + 7)); 1404 printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 8), (long) read_register (FP0_REGNUM + 9), (long) read_register (FP0_REGNUM + 10), (long) read_register (FP0_REGNUM + 11), (long) read_register (FP0_REGNUM + 12), (long) read_register (FP0_REGNUM + 13), (long) read_register (FP0_REGNUM + 14), (long) read_register (FP0_REGNUM + 15)); 1405} 1406 1407#ifdef notyet 1408static void 1409sh2a_show_regs (void) 1410{ 1411 int pr = read_register (FPSCR_REGNUM) & 0x80000; 1412 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n", 1413 paddr (read_register (PC_REGNUM)), 1414 (long) read_register (SR_REGNUM), 1415 (long) read_register (PR_REGNUM), 1416 (long) read_register (MACH_REGNUM), 1417 (long) read_register (MACL_REGNUM)); 1418 1419 printf_filtered ("GBR=%08lx VBR=%08lx TBR=%08lx", 1420 (long) read_register (GBR_REGNUM), 1421 (long) read_register (VBR_REGNUM), 1422 (long) read_register (TBR_REGNUM)); 1423 printf_filtered (" FPUL=%08lx FPSCR=%08lx\n", 1424 (long) read_register (FPUL_REGNUM), 1425 (long) read_register (FPSCR_REGNUM)); 1426 1427 printf_filtered ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", 1428 (long) read_register (0), (long) read_register (1), 1429 (long) read_register (2), (long) read_register (3), 1430 (long) read_register (4), (long) read_register (5), 1431 (long) read_register (6), (long) read_register (7)); 1432 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", 1433 (long) read_register (8), (long) read_register (9), 1434 (long) read_register (10), (long) read_register (11), 1435 (long) read_register (12), (long) read_register (13), 1436 (long) read_register (14), (long) read_register (15)); 1437 1438 printf_filtered ((pr 1439 ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n" 1440 : 1441 "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), 1442 (long) read_register (FP0_REGNUM + 0), 1443 (long) read_register (FP0_REGNUM + 1), 1444 (long) read_register (FP0_REGNUM + 2), 1445 (long) read_register (FP0_REGNUM + 3), 1446 (long) read_register (FP0_REGNUM + 4), 1447 (long) read_register (FP0_REGNUM + 5), 1448 (long) read_register (FP0_REGNUM + 6), 1449 (long) read_register (FP0_REGNUM + 7)); 1450 printf_filtered ((pr ? 1451 "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n" : 1452 "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), 1453 (long) read_register (FP0_REGNUM + 8), 1454 (long) read_register (FP0_REGNUM + 9), 1455 (long) read_register (FP0_REGNUM + 10), 1456 (long) read_register (FP0_REGNUM + 11), 1457 (long) read_register (FP0_REGNUM + 12), 1458 (long) read_register (FP0_REGNUM + 13), 1459 (long) read_register (FP0_REGNUM + 14), 1460 (long) read_register (FP0_REGNUM + 15)); 1461 printf_filtered ("BANK=%-3d\n", (int) read_register (BANK_REGNUM)); 1462 printf_filtered ("R0b - R7b %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", 1463 (long) read_register (R0_BANK0_REGNUM + 0), 1464 (long) read_register (R0_BANK0_REGNUM + 1), 1465 (long) read_register (R0_BANK0_REGNUM + 2), 1466 (long) read_register (R0_BANK0_REGNUM + 3), 1467 (long) read_register (R0_BANK0_REGNUM + 4), 1468 (long) read_register (R0_BANK0_REGNUM + 5), 1469 (long) read_register (R0_BANK0_REGNUM + 6), 1470 (long) read_register (R0_BANK0_REGNUM + 7)); 1471 printf_filtered ("R8b - R14b %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", 1472 (long) read_register (R0_BANK0_REGNUM + 8), 1473 (long) read_register (R0_BANK0_REGNUM + 9), 1474 (long) read_register (R0_BANK0_REGNUM + 10), 1475 (long) read_register (R0_BANK0_REGNUM + 11), 1476 (long) read_register (R0_BANK0_REGNUM + 12), 1477 (long) read_register (R0_BANK0_REGNUM + 13), 1478 (long) read_register (R0_BANK0_REGNUM + 14)); 1479 printf_filtered ("MACHb=%08lx IVNb=%08lx PRb=%08lx GBRb=%08lx MACLb=%08lx\n", 1480 (long) read_register (R0_BANK0_REGNUM + 15), 1481 (long) read_register (R0_BANK0_REGNUM + 16), 1482 (long) read_register (R0_BANK0_REGNUM + 17), 1483 (long) read_register (R0_BANK0_REGNUM + 18), 1484 (long) read_register (R0_BANK0_REGNUM + 19)); 1485} 1486 1487static void 1488sh2a_nofpu_show_regs (void) 1489{ 1490 int pr = read_register (FPSCR_REGNUM) & 0x80000; 1491 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n", 1492 paddr (read_register (PC_REGNUM)), 1493 (long) read_register (SR_REGNUM), 1494 (long) read_register (PR_REGNUM), 1495 (long) read_register (MACH_REGNUM), 1496 (long) read_register (MACL_REGNUM)); 1497 1498 printf_filtered ("GBR=%08lx VBR=%08lx TBR=%08lx", 1499 (long) read_register (GBR_REGNUM), 1500 (long) read_register (VBR_REGNUM), 1501 (long) read_register (TBR_REGNUM)); 1502 printf_filtered (" FPUL=%08lx FPSCR=%08lx\n", 1503 (long) read_register (FPUL_REGNUM), 1504 (long) read_register (FPSCR_REGNUM)); 1505 1506 printf_filtered ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", 1507 (long) read_register (0), (long) read_register (1), 1508 (long) read_register (2), (long) read_register (3), 1509 (long) read_register (4), (long) read_register (5), 1510 (long) read_register (6), (long) read_register (7)); 1511 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", 1512 (long) read_register (8), (long) read_register (9), 1513 (long) read_register (10), (long) read_register (11), 1514 (long) read_register (12), (long) read_register (13), 1515 (long) read_register (14), (long) read_register (15)); 1516 1517 printf_filtered ("BANK=%-3d\n", (int) read_register (BANK_REGNUM)); 1518 printf_filtered ("R0b - R7b %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", 1519 (long) read_register (R0_BANK0_REGNUM + 0), 1520 (long) read_register (R0_BANK0_REGNUM + 1), 1521 (long) read_register (R0_BANK0_REGNUM + 2), 1522 (long) read_register (R0_BANK0_REGNUM + 3), 1523 (long) read_register (R0_BANK0_REGNUM + 4), 1524 (long) read_register (R0_BANK0_REGNUM + 5), 1525 (long) read_register (R0_BANK0_REGNUM + 6), 1526 (long) read_register (R0_BANK0_REGNUM + 7)); 1527 printf_filtered ("R8b - R14b %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", 1528 (long) read_register (R0_BANK0_REGNUM + 8), 1529 (long) read_register (R0_BANK0_REGNUM + 9), 1530 (long) read_register (R0_BANK0_REGNUM + 10), 1531 (long) read_register (R0_BANK0_REGNUM + 11), 1532 (long) read_register (R0_BANK0_REGNUM + 12), 1533 (long) read_register (R0_BANK0_REGNUM + 13), 1534 (long) read_register (R0_BANK0_REGNUM + 14)); 1535 printf_filtered ("MACHb=%08lx IVNb=%08lx PRb=%08lx GBRb=%08lx MACLb=%08lx\n", 1536 (long) read_register (R0_BANK0_REGNUM + 15), 1537 (long) read_register (R0_BANK0_REGNUM + 16), 1538 (long) read_register (R0_BANK0_REGNUM + 17), 1539 (long) read_register (R0_BANK0_REGNUM + 18), 1540 (long) read_register (R0_BANK0_REGNUM + 19)); 1541} 1542#endif 1543 1544static void 1545sh3e_show_regs (void) 1546{ 1547 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n", 1548 paddr (read_register (PC_REGNUM)), 1549 (long) read_register (SR_REGNUM), 1550 (long) read_register (PR_REGNUM), 1551 (long) read_register (MACH_REGNUM), 1552 (long) read_register (MACL_REGNUM)); 1553 1554 printf_filtered ("GBR=%08lx VBR=%08lx", 1555 (long) read_register (GBR_REGNUM), 1556 (long) read_register (VBR_REGNUM)); 1557 printf_filtered (" SSR=%08lx SPC=%08lx", 1558 (long) read_register (SSR_REGNUM), 1559 (long) read_register (SPC_REGNUM)); 1560 printf_filtered (" FPUL=%08lx FPSCR=%08lx", 1561 (long) read_register (FPUL_REGNUM), 1562 (long) read_register (FPSCR_REGNUM)); 1563 1564 printf_filtered 1565 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", 1566 (long) read_register (0), (long) read_register (1), 1567 (long) read_register (2), (long) read_register (3), 1568 (long) read_register (4), (long) read_register (5), 1569 (long) read_register (6), (long) read_register (7)); 1570 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", 1571 (long) read_register (8), (long) read_register (9), 1572 (long) read_register (10), (long) read_register (11), 1573 (long) read_register (12), (long) read_register (13), 1574 (long) read_register (14), (long) read_register (15)); 1575 1576 printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 0), (long) read_register (FP0_REGNUM + 1), (long) read_register (FP0_REGNUM + 2), (long) read_register (FP0_REGNUM + 3), (long) read_register (FP0_REGNUM + 4), (long) read_register (FP0_REGNUM + 5), (long) read_register (FP0_REGNUM + 6), (long) read_register (FP0_REGNUM + 7)); 1577 printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 8), (long) read_register (FP0_REGNUM + 9), (long) read_register (FP0_REGNUM + 10), (long) read_register (FP0_REGNUM + 11), (long) read_register (FP0_REGNUM + 12), (long) read_register (FP0_REGNUM + 13), (long) read_register (FP0_REGNUM + 14), (long) read_register (FP0_REGNUM + 15)); 1578} 1579 1580static void 1581sh3_dsp_show_regs (void) 1582{ 1583 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n", 1584 paddr (read_register (PC_REGNUM)), 1585 (long) read_register (SR_REGNUM), 1586 (long) read_register (PR_REGNUM), 1587 (long) read_register (MACH_REGNUM), 1588 (long) read_register (MACL_REGNUM)); 1589 1590 printf_filtered ("GBR=%08lx VBR=%08lx", 1591 (long) read_register (GBR_REGNUM), 1592 (long) read_register (VBR_REGNUM)); 1593 1594 printf_filtered (" SSR=%08lx SPC=%08lx", 1595 (long) read_register (SSR_REGNUM), 1596 (long) read_register (SPC_REGNUM)); 1597 1598 printf_filtered (" DSR=%08lx", (long) read_register (DSR_REGNUM)); 1599 1600 printf_filtered 1601 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", 1602 (long) read_register (0), (long) read_register (1), 1603 (long) read_register (2), (long) read_register (3), 1604 (long) read_register (4), (long) read_register (5), 1605 (long) read_register (6), (long) read_register (7)); 1606 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", 1607 (long) read_register (8), (long) read_register (9), 1608 (long) read_register (10), (long) read_register (11), 1609 (long) read_register (12), (long) read_register (13), 1610 (long) read_register (14), (long) read_register (15)); 1611 1612 printf_filtered 1613 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n", 1614 (long) read_register (A0G_REGNUM) & 0xff, 1615 (long) read_register (A0_REGNUM), (long) read_register (M0_REGNUM), 1616 (long) read_register (X0_REGNUM), (long) read_register (Y0_REGNUM), 1617 (long) read_register (RS_REGNUM), (long) read_register (MOD_REGNUM)); 1618 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n", 1619 (long) read_register (A1G_REGNUM) & 0xff, 1620 (long) read_register (A1_REGNUM), 1621 (long) read_register (M1_REGNUM), 1622 (long) read_register (X1_REGNUM), 1623 (long) read_register (Y1_REGNUM), 1624 (long) read_register (RE_REGNUM)); 1625} 1626 1627static void 1628sh4_show_regs (void) 1629{ 1630 int pr = read_register (FPSCR_REGNUM) & 0x80000; 1631 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n", 1632 paddr (read_register (PC_REGNUM)), 1633 (long) read_register (SR_REGNUM), 1634 (long) read_register (PR_REGNUM), 1635 (long) read_register (MACH_REGNUM), 1636 (long) read_register (MACL_REGNUM)); 1637 1638 printf_filtered ("GBR=%08lx VBR=%08lx", 1639 (long) read_register (GBR_REGNUM), 1640 (long) read_register (VBR_REGNUM)); 1641 printf_filtered (" SSR=%08lx SPC=%08lx", 1642 (long) read_register (SSR_REGNUM), 1643 (long) read_register (SPC_REGNUM)); 1644 printf_filtered (" FPUL=%08lx FPSCR=%08lx", 1645 (long) read_register (FPUL_REGNUM), 1646 (long) read_register (FPSCR_REGNUM)); 1647 1648 printf_filtered 1649 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", 1650 (long) read_register (0), (long) read_register (1), 1651 (long) read_register (2), (long) read_register (3), 1652 (long) read_register (4), (long) read_register (5), 1653 (long) read_register (6), (long) read_register (7)); 1654 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", 1655 (long) read_register (8), (long) read_register (9), 1656 (long) read_register (10), (long) read_register (11), 1657 (long) read_register (12), (long) read_register (13), 1658 (long) read_register (14), (long) read_register (15)); 1659 1660 printf_filtered ((pr 1661 ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n" 1662 : 1663 "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), 1664 (long) read_register (FP0_REGNUM + 0), 1665 (long) read_register (FP0_REGNUM + 1), 1666 (long) read_register (FP0_REGNUM + 2), 1667 (long) read_register (FP0_REGNUM + 3), 1668 (long) read_register (FP0_REGNUM + 4), 1669 (long) read_register (FP0_REGNUM + 5), 1670 (long) read_register (FP0_REGNUM + 6), 1671 (long) read_register (FP0_REGNUM + 7)); 1672 printf_filtered ((pr ? 1673 "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n" : 1674 "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), 1675 (long) read_register (FP0_REGNUM + 8), 1676 (long) read_register (FP0_REGNUM + 9), 1677 (long) read_register (FP0_REGNUM + 10), 1678 (long) read_register (FP0_REGNUM + 11), 1679 (long) read_register (FP0_REGNUM + 12), 1680 (long) read_register (FP0_REGNUM + 13), 1681 (long) read_register (FP0_REGNUM + 14), 1682 (long) read_register (FP0_REGNUM + 15)); 1683} 1684 1685static void 1686sh4_nofpu_show_regs (void) 1687{ 1688 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n", 1689 paddr (read_register (PC_REGNUM)), 1690 (long) read_register (SR_REGNUM), 1691 (long) read_register (PR_REGNUM), 1692 (long) read_register (MACH_REGNUM), 1693 (long) read_register (MACL_REGNUM)); 1694 1695 printf_filtered ("GBR=%08lx VBR=%08lx", 1696 (long) read_register (GBR_REGNUM), 1697 (long) read_register (VBR_REGNUM)); 1698 printf_filtered (" SSR=%08lx SPC=%08lx", 1699 (long) read_register (SSR_REGNUM), 1700 (long) read_register (SPC_REGNUM)); 1701 1702 printf_filtered 1703 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", 1704 (long) read_register (0), (long) read_register (1), 1705 (long) read_register (2), (long) read_register (3), 1706 (long) read_register (4), (long) read_register (5), 1707 (long) read_register (6), (long) read_register (7)); 1708 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", 1709 (long) read_register (8), (long) read_register (9), 1710 (long) read_register (10), (long) read_register (11), 1711 (long) read_register (12), (long) read_register (13), 1712 (long) read_register (14), (long) read_register (15)); 1713} 1714 1715static void 1716sh_dsp_show_regs (void) 1717{ 1718 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n", 1719 paddr (read_register (PC_REGNUM)), 1720 (long) read_register (SR_REGNUM), 1721 (long) read_register (PR_REGNUM), 1722 (long) read_register (MACH_REGNUM), 1723 (long) read_register (MACL_REGNUM)); 1724 1725 printf_filtered ("GBR=%08lx VBR=%08lx", 1726 (long) read_register (GBR_REGNUM), 1727 (long) read_register (VBR_REGNUM)); 1728 1729 printf_filtered (" DSR=%08lx", (long) read_register (DSR_REGNUM)); 1730 1731 printf_filtered 1732 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", 1733 (long) read_register (0), (long) read_register (1), 1734 (long) read_register (2), (long) read_register (3), 1735 (long) read_register (4), (long) read_register (5), 1736 (long) read_register (6), (long) read_register (7)); 1737 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", 1738 (long) read_register (8), (long) read_register (9), 1739 (long) read_register (10), (long) read_register (11), 1740 (long) read_register (12), (long) read_register (13), 1741 (long) read_register (14), (long) read_register (15)); 1742 1743 printf_filtered 1744 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n", 1745 (long) read_register (A0G_REGNUM) & 0xff, 1746 (long) read_register (A0_REGNUM), (long) read_register (M0_REGNUM), 1747 (long) read_register (X0_REGNUM), (long) read_register (Y0_REGNUM), 1748 (long) read_register (RS_REGNUM), (long) read_register (MOD_REGNUM)); 1749 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n", 1750 (long) read_register (A1G_REGNUM) & 0xff, 1751 (long) read_register (A1_REGNUM), 1752 (long) read_register (M1_REGNUM), 1753 (long) read_register (X1_REGNUM), 1754 (long) read_register (Y1_REGNUM), 1755 (long) read_register (RE_REGNUM)); 1756} 1757 1758static void 1759sh_show_regs_command (char *args, int from_tty) 1760{ 1761 if (sh_show_regs) 1762 (*sh_show_regs) (); 1763} 1764 1765#ifdef notyet 1766static struct type * 1767sh_sh2a_register_type (struct gdbarch *gdbarch, int reg_nr) 1768{ 1769 if ((reg_nr >= FP0_REGNUM 1770 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM)) 1771 return builtin_type_float; 1772 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM) 1773 return builtin_type_double; 1774 else 1775 return builtin_type_int; 1776} 1777#endif 1778 1779/* Return the GDB type object for the "standard" data type 1780 of data in register N. */ 1781static struct type * 1782sh_sh3e_register_type (struct gdbarch *gdbarch, int reg_nr) 1783{ 1784 if ((reg_nr >= FP0_REGNUM 1785 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM)) 1786 return builtin_type_float; 1787 else 1788 return builtin_type_int; 1789} 1790 1791static struct type * 1792sh_sh4_build_float_register_type (int high) 1793{ 1794 struct type *temp; 1795 1796 temp = create_range_type (NULL, builtin_type_int, 0, high); 1797 return create_array_type (NULL, builtin_type_float, temp); 1798} 1799 1800static struct type * 1801sh_sh4_register_type (struct gdbarch *gdbarch, int reg_nr) 1802{ 1803 if ((reg_nr >= FP0_REGNUM 1804 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM)) 1805 return builtin_type_float; 1806 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM) 1807 return builtin_type_double; 1808 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM) 1809 return sh_sh4_build_float_register_type (3); 1810 else 1811 return builtin_type_int; 1812} 1813 1814static struct type * 1815sh_default_register_type (struct gdbarch *gdbarch, int reg_nr) 1816{ 1817 return builtin_type_int; 1818} 1819 1820/* On the sh4, the DRi pseudo registers are problematic if the target 1821 is little endian. When the user writes one of those registers, for 1822 instance with 'ser var $dr0=1', we want the double to be stored 1823 like this: 1824 fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f 1825 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1826 1827 This corresponds to little endian byte order & big endian word 1828 order. However if we let gdb write the register w/o conversion, it 1829 will write fr0 and fr1 this way: 1830 fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1831 fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f 1832 because it will consider fr0 and fr1 as a single LE stretch of memory. 1833 1834 To achieve what we want we must force gdb to store things in 1835 floatformat_ieee_double_littlebyte_bigword (which is defined in 1836 include/floatformat.h and libiberty/floatformat.c. 1837 1838 In case the target is big endian, there is no problem, the 1839 raw bytes will look like: 1840 fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00 1841 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1842 1843 The other pseudo registers (the FVs) also don't pose a problem 1844 because they are stored as 4 individual FP elements. */ 1845 1846static void 1847sh_register_convert_to_virtual (int regnum, struct type *type, 1848 char *from, char *to) 1849{ 1850 if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM) 1851 { 1852 DOUBLEST val; 1853 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword, 1854 from, &val); 1855 store_typed_floating (to, type, val); 1856 } 1857 else 1858 error 1859 ("sh_register_convert_to_virtual called with non DR register number"); 1860} 1861 1862static void 1863sh_register_convert_to_raw (struct type *type, int regnum, 1864 const void *from, void *to) 1865{ 1866 if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM) 1867 { 1868 DOUBLEST val = extract_typed_floating (from, type); 1869 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword, 1870 &val, to); 1871 } 1872 else 1873 error ("sh_register_convert_to_raw called with non DR register number"); 1874} 1875 1876/* For vectors of 4 floating point registers. */ 1877static int 1878fv_reg_base_num (int fv_regnum) 1879{ 1880 int fp_regnum; 1881 1882 fp_regnum = FP0_REGNUM + (fv_regnum - FV0_REGNUM) * 4; 1883 return fp_regnum; 1884} 1885 1886/* For double precision floating point registers, i.e 2 fp regs.*/ 1887static int 1888dr_reg_base_num (int dr_regnum) 1889{ 1890 int fp_regnum; 1891 1892 fp_regnum = FP0_REGNUM + (dr_regnum - DR0_REGNUM) * 2; 1893 return fp_regnum; 1894} 1895 1896static void 1897sh_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, 1898 int reg_nr, void *buffer) 1899{ 1900 int base_regnum, portion; 1901 char temp_buffer[MAX_REGISTER_SIZE]; 1902 1903 if (reg_nr == PSEUDO_BANK_REGNUM) 1904 regcache_raw_read (regcache, BANK_REGNUM, buffer); 1905 else 1906 if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM) 1907 { 1908 base_regnum = dr_reg_base_num (reg_nr); 1909 1910 /* Build the value in the provided buffer. */ 1911 /* Read the real regs for which this one is an alias. */ 1912 for (portion = 0; portion < 2; portion++) 1913 regcache_raw_read (regcache, base_regnum + portion, 1914 (temp_buffer 1915 + register_size (gdbarch, 1916 base_regnum) * portion)); 1917 /* We must pay attention to the endiannes. */ 1918 sh_register_convert_to_virtual (reg_nr, 1919 gdbarch_register_type (gdbarch, reg_nr), 1920 temp_buffer, buffer); 1921 } 1922 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM) 1923 { 1924 base_regnum = fv_reg_base_num (reg_nr); 1925 1926 /* Read the real regs for which this one is an alias. */ 1927 for (portion = 0; portion < 4; portion++) 1928 regcache_raw_read (regcache, base_regnum + portion, 1929 ((char *) buffer 1930 + register_size (gdbarch, 1931 base_regnum) * portion)); 1932 } 1933} 1934 1935static void 1936sh_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, 1937 int reg_nr, const void *buffer) 1938{ 1939 int base_regnum, portion; 1940 char temp_buffer[MAX_REGISTER_SIZE]; 1941 1942 if (reg_nr == PSEUDO_BANK_REGNUM) 1943 { 1944 /* When the bank register is written to, the whole register bank 1945 is switched and all values in the bank registers must be read 1946 from the target/sim again. We're just invalidating the regcache 1947 so that a re-read happens next time it's necessary. */ 1948 int bregnum; 1949 1950 regcache_raw_write (regcache, BANK_REGNUM, buffer); 1951 for (bregnum = R0_BANK0_REGNUM; bregnum < MACLB_REGNUM; ++bregnum) 1952 set_register_cached (bregnum, 0); 1953 } 1954 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM) 1955 { 1956 base_regnum = dr_reg_base_num (reg_nr); 1957 1958 /* We must pay attention to the endiannes. */ 1959 sh_register_convert_to_raw (gdbarch_register_type (gdbarch, reg_nr), 1960 reg_nr, buffer, temp_buffer); 1961 1962 /* Write the real regs for which this one is an alias. */ 1963 for (portion = 0; portion < 2; portion++) 1964 regcache_raw_write (regcache, base_regnum + portion, 1965 (temp_buffer 1966 + register_size (gdbarch, 1967 base_regnum) * portion)); 1968 } 1969 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM) 1970 { 1971 base_regnum = fv_reg_base_num (reg_nr); 1972 1973 /* Write the real regs for which this one is an alias. */ 1974 for (portion = 0; portion < 4; portion++) 1975 regcache_raw_write (regcache, base_regnum + portion, 1976 ((char *) buffer 1977 + register_size (gdbarch, 1978 base_regnum) * portion)); 1979 } 1980} 1981 1982/* Floating point vector of 4 float registers. */ 1983static void 1984do_fv_register_info (struct gdbarch *gdbarch, struct ui_file *file, 1985 int fv_regnum) 1986{ 1987 int first_fp_reg_num = fv_reg_base_num (fv_regnum); 1988 fprintf_filtered (file, "fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n", 1989 fv_regnum - FV0_REGNUM, 1990 (int) read_register (first_fp_reg_num), 1991 (int) read_register (first_fp_reg_num + 1), 1992 (int) read_register (first_fp_reg_num + 2), 1993 (int) read_register (first_fp_reg_num + 3)); 1994} 1995 1996/* Double precision registers. */ 1997static void 1998do_dr_register_info (struct gdbarch *gdbarch, struct ui_file *file, 1999 int dr_regnum) 2000{ 2001 int first_fp_reg_num = dr_reg_base_num (dr_regnum); 2002 2003 fprintf_filtered (file, "dr%d\t0x%08x%08x\n", 2004 dr_regnum - DR0_REGNUM, 2005 (int) read_register (first_fp_reg_num), 2006 (int) read_register (first_fp_reg_num + 1)); 2007} 2008static void 2009do_bank_register_info (struct gdbarch *gdbarch, struct ui_file *file) 2010{ 2011 fprintf_filtered (file, "bank %d\n", 2012 (int) read_register (BANK_REGNUM)); 2013} 2014 2015static void 2016sh_print_pseudo_register (struct gdbarch *gdbarch, struct ui_file *file, 2017 int regnum) 2018{ 2019 if (regnum < NUM_REGS || regnum >= NUM_REGS + NUM_PSEUDO_REGS) 2020 internal_error (__FILE__, __LINE__, 2021 "Invalid pseudo register number %d\n", regnum); 2022 else if (regnum == PSEUDO_BANK_REGNUM) 2023 do_bank_register_info (gdbarch, file); 2024 else if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM) 2025 do_dr_register_info (gdbarch, file, regnum); 2026 else if (regnum >= FV0_REGNUM && regnum <= FV_LAST_REGNUM) 2027 do_fv_register_info (gdbarch, file, regnum); 2028} 2029 2030static void 2031sh_do_fp_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum) 2032{ /* do values for FP (float) regs */ 2033 char *raw_buffer; 2034 double flt; /* double extracted from raw hex data */ 2035 int inv; 2036 int j; 2037 2038 /* Allocate space for the float. */ 2039 raw_buffer = (char *) alloca (register_size (gdbarch, FP0_REGNUM)); 2040 2041 /* Get the data in raw format. */ 2042 if (!frame_register_read (get_selected_frame (), regnum, raw_buffer)) 2043 error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum)); 2044 2045 /* Get the register as a number */ 2046 flt = unpack_double (builtin_type_float, raw_buffer, &inv); 2047 2048 /* Print the name and some spaces. */ 2049 fputs_filtered (REGISTER_NAME (regnum), file); 2050 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file); 2051 2052 /* Print the value. */ 2053 if (inv) 2054 fprintf_filtered (file, "<invalid float>"); 2055 else 2056 fprintf_filtered (file, "%-10.9g", flt); 2057 2058 /* Print the fp register as hex. */ 2059 fprintf_filtered (file, "\t(raw 0x"); 2060 for (j = 0; j < register_size (gdbarch, regnum); j++) 2061 { 2062 int idx = (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG 2063 ? j 2064 : register_size (gdbarch, regnum) - 1 - j); 2065 fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[idx]); 2066 } 2067 fprintf_filtered (file, ")"); 2068 fprintf_filtered (file, "\n"); 2069} 2070 2071static void 2072sh_do_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum) 2073{ 2074 char raw_buffer[MAX_REGISTER_SIZE]; 2075 2076 fputs_filtered (REGISTER_NAME (regnum), file); 2077 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file); 2078 2079 /* Get the data in raw format. */ 2080 if (!frame_register_read (get_selected_frame (), regnum, raw_buffer)) 2081 fprintf_filtered (file, "*value not available*\n"); 2082 2083 val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0, 2084 file, 'x', 1, 0, Val_pretty_default); 2085 fprintf_filtered (file, "\t"); 2086 val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0, 2087 file, 0, 1, 0, Val_pretty_default); 2088 fprintf_filtered (file, "\n"); 2089} 2090 2091static void 2092sh_print_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum) 2093{ 2094 if (regnum < 0 || regnum >= NUM_REGS + NUM_PSEUDO_REGS) 2095 internal_error (__FILE__, __LINE__, 2096 "Invalid register number %d\n", regnum); 2097 2098 else if (regnum >= 0 && regnum < NUM_REGS) 2099 { 2100 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == 2101 TYPE_CODE_FLT) 2102 sh_do_fp_register (gdbarch, file, regnum); /* FP regs */ 2103 else 2104 sh_do_register (gdbarch, file, regnum); /* All other regs */ 2105 } 2106 2107 else if (regnum < NUM_REGS + NUM_PSEUDO_REGS) 2108 { 2109 sh_print_pseudo_register (gdbarch, file, regnum); 2110 } 2111} 2112 2113static void 2114sh_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, 2115 struct frame_info *frame, int regnum, int fpregs) 2116{ 2117 if (regnum != -1) /* do one specified register */ 2118 { 2119 if (*(REGISTER_NAME (regnum)) == '\0') 2120 error ("Not a valid register for the current processor type"); 2121 2122 sh_print_register (gdbarch, file, regnum); 2123 } 2124 else 2125 /* do all (or most) registers */ 2126 { 2127 for (regnum = 0; regnum < NUM_REGS; ++regnum) 2128 { 2129 /* If the register name is empty, it is undefined for this 2130 processor, so don't display anything. */ 2131 if (REGISTER_NAME (regnum) == NULL 2132 || *(REGISTER_NAME (regnum)) == '\0') 2133 continue; 2134 2135 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == 2136 TYPE_CODE_FLT) 2137 { 2138 /* true for "INFO ALL-REGISTERS" command */ 2139 if (fpregs) 2140 sh_do_fp_register (gdbarch, file, regnum); /* FP regs */ 2141 } 2142 else 2143 sh_do_register (gdbarch, file, regnum); /* All other regs */ 2144 } 2145 2146 if (regnum == PSEUDO_BANK_REGNUM 2147 && REGISTER_NAME (regnum) 2148 && *REGISTER_NAME (regnum)) 2149 sh_print_pseudo_register (gdbarch, file, regnum++); 2150 2151 if (fpregs) 2152 while (regnum < NUM_REGS + NUM_PSEUDO_REGS) 2153 { 2154 sh_print_pseudo_register (gdbarch, file, regnum); 2155 regnum++; 2156 } 2157 } 2158} 2159 2160/* Fetch (and possibly build) an appropriate link_map_offsets structure 2161 for native i386 linux targets using the struct offsets defined in 2162 link.h (but without actual reference to that file). 2163 2164 This makes it possible to access i386-linux shared libraries from 2165 a gdb that was not built on an i386-linux host (for cross debugging). 2166 */ 2167 2168struct link_map_offsets * 2169sh_linux_svr4_fetch_link_map_offsets (void) 2170{ 2171 static struct link_map_offsets lmo; 2172 static struct link_map_offsets *lmp = 0; 2173 2174 if (lmp == 0) 2175 { 2176 lmp = &lmo; 2177 2178 lmo.r_debug_size = 8; /* 20 not actual size but all we need */ 2179 2180 lmo.r_map_offset = 4; 2181 lmo.r_map_size = 4; 2182 2183 lmo.link_map_size = 20; /* 552 not actual size but all we need */ 2184 2185 lmo.l_addr_offset = 0; 2186 lmo.l_addr_size = 4; 2187 2188 lmo.l_name_offset = 4; 2189 lmo.l_name_size = 4; 2190 2191 lmo.l_next_offset = 12; 2192 lmo.l_next_size = 4; 2193 2194 lmo.l_prev_offset = 16; 2195 lmo.l_prev_size = 4; 2196 } 2197 2198 return lmp; 2199} 2200 2201static int 2202sh_dsp_register_sim_regno (int nr) 2203{ 2204 if (legacy_register_sim_regno (nr) < 0) 2205 return legacy_register_sim_regno (nr); 2206 if (nr >= DSR_REGNUM && nr <= Y1_REGNUM) 2207 return nr - DSR_REGNUM + SIM_SH_DSR_REGNUM; 2208 if (nr == MOD_REGNUM) 2209 return SIM_SH_MOD_REGNUM; 2210 if (nr == RS_REGNUM) 2211 return SIM_SH_RS_REGNUM; 2212 if (nr == RE_REGNUM) 2213 return SIM_SH_RE_REGNUM; 2214 if (nr >= DSP_R0_BANK_REGNUM && nr <= DSP_R7_BANK_REGNUM) 2215 return nr - DSP_R0_BANK_REGNUM + SIM_SH_R0_BANK_REGNUM; 2216 return nr; 2217} 2218 2219#ifdef notyet 2220static int 2221sh_sh2a_register_sim_regno (int nr) 2222{ 2223 switch (nr) 2224 { 2225 case TBR_REGNUM: 2226 return SIM_SH_TBR_REGNUM; 2227 case IBNR_REGNUM: 2228 return SIM_SH_IBNR_REGNUM; 2229 case IBCR_REGNUM: 2230 return SIM_SH_IBCR_REGNUM; 2231 case BANK_REGNUM: 2232 return SIM_SH_BANK_REGNUM; 2233 case MACLB_REGNUM: 2234 return SIM_SH_BANK_MACL_REGNUM; 2235 case GBRB_REGNUM: 2236 return SIM_SH_BANK_GBR_REGNUM; 2237 case PRB_REGNUM: 2238 return SIM_SH_BANK_PR_REGNUM; 2239 case IVNB_REGNUM: 2240 return SIM_SH_BANK_IVN_REGNUM; 2241 case MACHB_REGNUM: 2242 return SIM_SH_BANK_MACH_REGNUM; 2243 default: 2244 break; 2245 } 2246 return legacy_register_sim_regno (nr); 2247} 2248#endif 2249 2250static struct sh_frame_cache * 2251sh_alloc_frame_cache (void) 2252{ 2253 struct sh_frame_cache *cache; 2254 int i; 2255 2256 cache = FRAME_OBSTACK_ZALLOC (struct sh_frame_cache); 2257 2258 /* Base address. */ 2259 cache->base = 0; 2260 cache->saved_sp = 0; 2261 cache->sp_offset = 0; 2262 cache->pc = 0; 2263 2264 /* Frameless until proven otherwise. */ 2265 cache->uses_fp = 0; 2266 2267 /* Saved registers. We initialize these to -1 since zero is a valid 2268 offset (that's where fp is supposed to be stored). */ 2269 for (i = 0; i < SH_NUM_REGS; i++) 2270 { 2271 cache->saved_regs[i] = -1; 2272 } 2273 2274 return cache; 2275} 2276 2277static struct sh_frame_cache * 2278sh_frame_cache (struct frame_info *next_frame, void **this_cache) 2279{ 2280 struct sh_frame_cache *cache; 2281 CORE_ADDR current_pc; 2282 int i; 2283 2284 if (*this_cache) 2285 return *this_cache; 2286 2287 cache = sh_alloc_frame_cache (); 2288 *this_cache = cache; 2289 2290 /* In principle, for normal frames, fp holds the frame pointer, 2291 which holds the base address for the current stack frame. 2292 However, for functions that don't need it, the frame pointer is 2293 optional. For these "frameless" functions the frame pointer is 2294 actually the frame pointer of the calling frame. */ 2295 cache->base = frame_unwind_register_unsigned (next_frame, FP_REGNUM); 2296 if (cache->base == 0) 2297 return cache; 2298 2299 cache->pc = frame_func_unwind (next_frame); 2300 current_pc = frame_pc_unwind (next_frame); 2301 if (cache->pc != 0) 2302 sh_analyze_prologue (cache->pc, current_pc, cache); 2303 2304 if (!cache->uses_fp) 2305 { 2306 /* We didn't find a valid frame, which means that CACHE->base 2307 currently holds the frame pointer for our calling frame. If 2308 we're at the start of a function, or somewhere half-way its 2309 prologue, the function's frame probably hasn't been fully 2310 setup yet. Try to reconstruct the base address for the stack 2311 frame by looking at the stack pointer. For truly "frameless" 2312 functions this might work too. */ 2313 cache->base = frame_unwind_register_unsigned (next_frame, SP_REGNUM); 2314 } 2315 2316 /* Now that we have the base address for the stack frame we can 2317 calculate the value of sp in the calling frame. */ 2318 cache->saved_sp = cache->base + cache->sp_offset; 2319 2320 /* Adjust all the saved registers such that they contain addresses 2321 instead of offsets. */ 2322 for (i = 0; i < SH_NUM_REGS; i++) 2323 if (cache->saved_regs[i] != -1) 2324 cache->saved_regs[i] = cache->saved_sp - cache->saved_regs[i] - 4; 2325 2326 return cache; 2327} 2328 2329static void 2330sh_frame_prev_register (struct frame_info *next_frame, void **this_cache, 2331 int regnum, int *optimizedp, 2332 enum lval_type *lvalp, CORE_ADDR *addrp, 2333 int *realnump, void *valuep) 2334{ 2335 struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache); 2336 2337 gdb_assert (regnum >= 0); 2338 2339 if (regnum == SP_REGNUM && cache->saved_sp) 2340 { 2341 *optimizedp = 0; 2342 *lvalp = not_lval; 2343 *addrp = 0; 2344 *realnump = -1; 2345 if (valuep) 2346 { 2347 /* Store the value. */ 2348 store_unsigned_integer (valuep, 4, cache->saved_sp); 2349 } 2350 return; 2351 } 2352 2353 /* The PC of the previous frame is stored in the PR register of 2354 the current frame. Frob regnum so that we pull the value from 2355 the correct place. */ 2356 if (regnum == PC_REGNUM) 2357 regnum = PR_REGNUM; 2358 2359 if (regnum < SH_NUM_REGS && cache->saved_regs[regnum] != -1) 2360 { 2361 *optimizedp = 0; 2362 *lvalp = lval_memory; 2363 *addrp = cache->saved_regs[regnum]; 2364 *realnump = -1; 2365 if (valuep) 2366 { 2367 /* Read the value in from memory. */ 2368 read_memory (*addrp, valuep, 2369 register_size (current_gdbarch, regnum)); 2370 } 2371 return; 2372 } 2373 2374 frame_register_unwind (next_frame, regnum, 2375 optimizedp, lvalp, addrp, realnump, valuep); 2376} 2377 2378static void 2379sh_frame_this_id (struct frame_info *next_frame, void **this_cache, 2380 struct frame_id *this_id) 2381{ 2382 struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache); 2383 2384 /* This marks the outermost frame. */ 2385 if (cache->base == 0) 2386 return; 2387 2388 *this_id = frame_id_build (cache->saved_sp, cache->pc); 2389} 2390 2391static const struct frame_unwind sh_frame_unwind = { 2392 NORMAL_FRAME, 2393 sh_frame_this_id, 2394 sh_frame_prev_register 2395}; 2396 2397static const struct frame_unwind * 2398sh_frame_sniffer (struct frame_info *next_frame) 2399{ 2400 return &sh_frame_unwind; 2401} 2402 2403static CORE_ADDR 2404sh_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) 2405{ 2406 return frame_unwind_register_unsigned (next_frame, SP_REGNUM); 2407} 2408 2409static CORE_ADDR 2410sh_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) 2411{ 2412 return frame_unwind_register_unsigned (next_frame, PC_REGNUM); 2413} 2414 2415static struct frame_id 2416sh_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) 2417{ 2418 return frame_id_build (sh_unwind_sp (gdbarch, next_frame), 2419 frame_pc_unwind (next_frame)); 2420} 2421 2422static CORE_ADDR 2423sh_frame_base_address (struct frame_info *next_frame, void **this_cache) 2424{ 2425 struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache); 2426 2427 return cache->base; 2428} 2429 2430static const struct frame_base sh_frame_base = { 2431 &sh_frame_unwind, 2432 sh_frame_base_address, 2433 sh_frame_base_address, 2434 sh_frame_base_address 2435}; 2436 2437/* The epilogue is defined here as the area at the end of a function, 2438 either on the `ret' instruction itself or after an instruction which 2439 destroys the function's stack frame. */ 2440static int 2441sh_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) 2442{ 2443 CORE_ADDR func_addr = 0, func_end = 0; 2444 2445 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) 2446 { 2447 ULONGEST inst; 2448 /* The sh epilogue is max. 14 bytes long. Give another 14 bytes 2449 for a nop and some fixed data (e.g. big offsets) which are 2450 unfortunately also treated as part of the function (which 2451 means, they are below func_end. */ 2452 CORE_ADDR addr = func_end - 28; 2453 if (addr < func_addr + 4) 2454 addr = func_addr + 4; 2455 if (pc < addr) 2456 return 0; 2457 2458 /* First search forward until hitting an rts. */ 2459 while (addr < func_end 2460 && !IS_RTS (read_memory_unsigned_integer (addr, 2))) 2461 addr += 2; 2462 if (addr >= func_end) 2463 return 0; 2464 2465 /* At this point we should find a mov.l @r15+,r14 instruction, 2466 either before or after the rts. If not, then the function has 2467 probably no "normal" epilogue and we bail out here. */ 2468 inst = read_memory_unsigned_integer (addr - 2, 2); 2469 if (IS_RESTORE_FP (read_memory_unsigned_integer (addr - 2, 2))) 2470 addr -= 2; 2471 else if (!IS_RESTORE_FP (read_memory_unsigned_integer (addr + 2, 2))) 2472 return 0; 2473 2474 inst = read_memory_unsigned_integer (addr - 2, 2); 2475 2476 /* Step over possible lds.l @r15+,macl. */ 2477 if (IS_MACL_LDS (inst)) 2478 { 2479 addr -= 2; 2480 inst = read_memory_unsigned_integer (addr - 2, 2); 2481 } 2482 2483 /* Step over possible lds.l @r15+,pr. */ 2484 if (IS_LDS (inst)) 2485 { 2486 addr -= 2; 2487 inst = read_memory_unsigned_integer (addr - 2, 2); 2488 } 2489 2490 /* Step over possible mov r14,r15. */ 2491 if (IS_MOV_FP_SP (inst)) 2492 { 2493 addr -= 2; 2494 inst = read_memory_unsigned_integer (addr - 2, 2); 2495 } 2496 2497 /* Now check for FP adjustments, using add #imm,r14 or add rX, r14 2498 instructions. */ 2499 while (addr > func_addr + 4 2500 && (IS_ADD_REG_TO_FP (inst) || IS_ADD_IMM_FP (inst))) 2501 { 2502 addr -= 2; 2503 inst = read_memory_unsigned_integer (addr - 2, 2); 2504 } 2505 2506#ifdef notyet 2507 /* On SH2a check if the previous instruction was perhaps a MOVI20. 2508 That's allowed for the epilogue. */ 2509 if ((gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a 2510 || gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a_nofpu) 2511 && addr > func_addr + 6 2512 && IS_MOVI20 (read_memory_unsigned_integer (addr - 4, 2))) 2513 addr -= 4; 2514#endif 2515 2516 if (pc >= addr) 2517 return 1; 2518 } 2519 return 0; 2520} 2521 2522static gdbarch_init_ftype sh_gdbarch_init; 2523 2524static struct gdbarch * 2525sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) 2526{ 2527 struct gdbarch *gdbarch; 2528 2529 sh_show_regs = sh_generic_show_regs; 2530 switch (info.bfd_arch_info->mach) 2531 { 2532 case bfd_mach_sh2e: 2533 sh_show_regs = sh2e_show_regs; 2534 break; 2535#ifdef notyet 2536 case bfd_mach_sh2a: 2537 sh_show_regs = sh2a_show_regs; 2538 break; 2539 case bfd_mach_sh2a_nofpu: 2540 sh_show_regs = sh2a_nofpu_show_regs; 2541 break; 2542#endif 2543 case bfd_mach_sh_dsp: 2544 sh_show_regs = sh_dsp_show_regs; 2545 break; 2546 2547 case bfd_mach_sh3: 2548 sh_show_regs = sh3_show_regs; 2549 break; 2550 2551 case bfd_mach_sh3e: 2552 sh_show_regs = sh3e_show_regs; 2553 break; 2554 2555 case bfd_mach_sh3_dsp: 2556 case bfd_mach_sh4al_dsp: 2557 sh_show_regs = sh3_dsp_show_regs; 2558 break; 2559 2560 case bfd_mach_sh4: 2561 case bfd_mach_sh4a: 2562 sh_show_regs = sh4_show_regs; 2563 break; 2564 2565 case bfd_mach_sh4_nofpu: 2566 case bfd_mach_sh4a_nofpu: 2567 sh_show_regs = sh4_nofpu_show_regs; 2568 break; 2569 2570#if 0 2571 case bfd_mach_sh5: 2572 sh_show_regs = sh64_show_regs; 2573 /* SH5 is handled entirely in sh64-tdep.c */ 2574 return sh64_gdbarch_init (info, arches); 2575#endif 2576 } 2577 2578 /* If there is already a candidate, use it. */ 2579 arches = gdbarch_list_lookup_by_info (arches, &info); 2580 if (arches != NULL) 2581 return arches->gdbarch; 2582 2583 /* None found, create a new architecture from the information 2584 provided. */ 2585 gdbarch = gdbarch_alloc (&info, NULL); 2586 2587 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); 2588 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT); 2589 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT); 2590 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); 2591 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); 2592 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); 2593 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); 2594 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT); 2595 2596 set_gdbarch_num_regs (gdbarch, SH_NUM_REGS); 2597 set_gdbarch_sp_regnum (gdbarch, 15); 2598 set_gdbarch_pc_regnum (gdbarch, 16); 2599 set_gdbarch_fp0_regnum (gdbarch, -1); 2600 set_gdbarch_num_pseudo_regs (gdbarch, 0); 2601 2602 set_gdbarch_register_type (gdbarch, sh_default_register_type); 2603 2604 set_gdbarch_print_registers_info (gdbarch, sh_print_registers_info); 2605 2606 set_gdbarch_breakpoint_from_pc (gdbarch, sh_breakpoint_from_pc); 2607 2608 set_gdbarch_print_insn (gdbarch, gdb_print_insn_sh); 2609 set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno); 2610 2611 set_gdbarch_write_pc (gdbarch, generic_target_write_pc); 2612 2613 set_gdbarch_return_value (gdbarch, sh_return_value_nofpu); 2614 set_gdbarch_deprecated_extract_struct_value_address (gdbarch, 2615 sh_extract_struct_value_address); 2616 2617 set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue); 2618 set_gdbarch_inner_than (gdbarch, core_addr_lessthan); 2619 2620 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_nofpu); 2621 2622 set_gdbarch_believe_pcc_promotion (gdbarch, 1); 2623 2624 set_gdbarch_frame_align (gdbarch, sh_frame_align); 2625 set_gdbarch_unwind_sp (gdbarch, sh_unwind_sp); 2626 set_gdbarch_unwind_pc (gdbarch, sh_unwind_pc); 2627 set_gdbarch_unwind_dummy_id (gdbarch, sh_unwind_dummy_id); 2628 frame_base_set_default (gdbarch, &sh_frame_base); 2629 2630 set_gdbarch_in_function_epilogue_p (gdbarch, sh_in_function_epilogue_p); 2631 2632 switch (info.bfd_arch_info->mach) 2633 { 2634 case bfd_mach_sh: 2635 set_gdbarch_register_name (gdbarch, sh_sh_register_name); 2636 break; 2637 2638 case bfd_mach_sh2: 2639 set_gdbarch_register_name (gdbarch, sh_sh_register_name); 2640 break; 2641 2642 case bfd_mach_sh2e: 2643 /* doubles on sh2e and sh3e are actually 4 byte. */ 2644 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT); 2645 2646 set_gdbarch_register_name (gdbarch, sh_sh2e_register_name); 2647 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type); 2648 set_gdbarch_fp0_regnum (gdbarch, 25); 2649 set_gdbarch_return_value (gdbarch, sh_return_value_fpu); 2650 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu); 2651 break; 2652 2653#ifdef notyet 2654 case bfd_mach_sh2a: 2655 set_gdbarch_register_name (gdbarch, sh_sh2a_register_name); 2656 set_gdbarch_register_type (gdbarch, sh_sh2a_register_type); 2657 set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno); 2658 2659 set_gdbarch_fp0_regnum (gdbarch, 25); 2660 set_gdbarch_num_pseudo_regs (gdbarch, 9); 2661 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read); 2662 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write); 2663 set_gdbarch_return_value (gdbarch, sh_return_value_fpu); 2664 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu); 2665 break; 2666 2667 case bfd_mach_sh2a_nofpu: 2668 set_gdbarch_register_name (gdbarch, sh_sh2a_nofpu_register_name); 2669 set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno); 2670 2671 set_gdbarch_num_pseudo_regs (gdbarch, 1); 2672 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read); 2673 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write); 2674 break; 2675#endif 2676 2677 case bfd_mach_sh_dsp: 2678 set_gdbarch_register_name (gdbarch, sh_sh_dsp_register_name); 2679 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno); 2680 break; 2681 2682 case bfd_mach_sh3: 2683 set_gdbarch_register_name (gdbarch, sh_sh3_register_name); 2684 break; 2685 2686 case bfd_mach_sh3e: 2687 /* doubles on sh2e and sh3e are actually 4 byte. */ 2688 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT); 2689 2690 set_gdbarch_register_name (gdbarch, sh_sh3e_register_name); 2691 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type); 2692 set_gdbarch_fp0_regnum (gdbarch, 25); 2693 set_gdbarch_return_value (gdbarch, sh_return_value_fpu); 2694 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu); 2695 break; 2696 2697 case bfd_mach_sh3_dsp: 2698 set_gdbarch_register_name (gdbarch, sh_sh3_dsp_register_name); 2699 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno); 2700 break; 2701 2702 case bfd_mach_sh4: 2703 case bfd_mach_sh4a: 2704 set_gdbarch_register_name (gdbarch, sh_sh4_register_name); 2705 set_gdbarch_register_type (gdbarch, sh_sh4_register_type); 2706 set_gdbarch_fp0_regnum (gdbarch, 25); 2707 set_gdbarch_num_pseudo_regs (gdbarch, 13); 2708 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read); 2709 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write); 2710 set_gdbarch_return_value (gdbarch, sh_return_value_fpu); 2711 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu); 2712 break; 2713 2714 case bfd_mach_sh4_nofpu: 2715 case bfd_mach_sh4a_nofpu: 2716 set_gdbarch_register_name (gdbarch, sh_sh4_nofpu_register_name); 2717 break; 2718 2719 case bfd_mach_sh4al_dsp: 2720 set_gdbarch_register_name (gdbarch, sh_sh4al_dsp_register_name); 2721 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno); 2722 break; 2723 2724 default: 2725 set_gdbarch_register_name (gdbarch, sh_sh_register_name); 2726 break; 2727 } 2728 2729 /* Hook in ABI-specific overrides, if they have been registered. */ 2730 gdbarch_init_osabi (info, gdbarch); 2731 2732 frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer); 2733 frame_unwind_append_sniffer (gdbarch, sh_frame_sniffer); 2734 2735 return gdbarch; 2736} 2737 2738extern initialize_file_ftype _initialize_sh_tdep; /* -Wmissing-prototypes */ 2739 2740void 2741_initialize_sh_tdep (void) 2742{ 2743 struct cmd_list_element *c; 2744 2745 gdbarch_register (bfd_arch_sh, sh_gdbarch_init, NULL); 2746 2747 add_com ("regs", class_vars, sh_show_regs_command, "Print all registers"); 2748} 2749