1/* Target-dependent code for GDB, the GNU debugger. 2 3 Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 4 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software 5 Foundation, Inc. 6 7 This file is part of GDB. 8 9 This program is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 2 of the License, or 12 (at your option) any later version. 13 14 This program is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 GNU General Public License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with this program; if not, write to the Free Software 21 Foundation, Inc., 59 Temple Place - Suite 330, 22 Boston, MA 02111-1307, USA. */ 23 24#include "defs.h" 25#include "frame.h" 26#include "inferior.h" 27#include "symtab.h" 28#include "target.h" 29#include "gdbcore.h" 30#include "gdbcmd.h" 31#include "objfiles.h" 32#include "arch-utils.h" 33#include "regcache.h" 34#include "regset.h" 35#include "doublest.h" 36#include "value.h" 37#include "parser-defs.h" 38#include "osabi.h" 39#include "infcall.h" 40#include "sim-regno.h" 41#include "gdb/sim-ppc.h" 42#include "reggroups.h" 43 44#include "libbfd.h" /* for bfd_default_set_arch_mach */ 45#include "coff/internal.h" /* for libcoff.h */ 46#include "libcoff.h" /* for xcoff_data */ 47#include "coff/xcoff.h" 48#include "libxcoff.h" 49 50#include "elf-bfd.h" 51 52#include "solib-svr4.h" 53#include "ppc-tdep.h" 54 55#include "gdb_assert.h" 56#include "dis-asm.h" 57 58#include "trad-frame.h" 59#include "frame-unwind.h" 60#include "frame-base.h" 61 62/* If the kernel has to deliver a signal, it pushes a sigcontext 63 structure on the stack and then calls the signal handler, passing 64 the address of the sigcontext in an argument register. Usually 65 the signal handler doesn't save this register, so we have to 66 access the sigcontext structure via an offset from the signal handler 67 frame. 68 The following constants were determined by experimentation on AIX 3.2. */ 69#define SIG_FRAME_PC_OFFSET 96 70#define SIG_FRAME_LR_OFFSET 108 71#define SIG_FRAME_FP_OFFSET 284 72 73/* To be used by skip_prologue. */ 74 75struct rs6000_framedata 76 { 77 int offset; /* total size of frame --- the distance 78 by which we decrement sp to allocate 79 the frame */ 80 int saved_gpr; /* smallest # of saved gpr */ 81 int saved_fpr; /* smallest # of saved fpr */ 82 int saved_vr; /* smallest # of saved vr */ 83 int saved_ev; /* smallest # of saved ev */ 84 int alloca_reg; /* alloca register number (frame ptr) */ 85 char frameless; /* true if frameless functions. */ 86 char nosavedpc; /* true if pc not saved. */ 87 int gpr_offset; /* offset of saved gprs from prev sp */ 88 int fpr_offset; /* offset of saved fprs from prev sp */ 89 int vr_offset; /* offset of saved vrs from prev sp */ 90 int ev_offset; /* offset of saved evs from prev sp */ 91 int lr_offset; /* offset of saved lr */ 92 int cr_offset; /* offset of saved cr */ 93 int vrsave_offset; /* offset of saved vrsave register */ 94 }; 95 96/* Description of a single register. */ 97 98struct reg 99 { 100 char *name; /* name of register */ 101 unsigned char sz32; /* size on 32-bit arch, 0 if nonextant */ 102 unsigned char sz64; /* size on 64-bit arch, 0 if nonextant */ 103 unsigned char fpr; /* whether register is floating-point */ 104 unsigned char pseudo; /* whether register is pseudo */ 105 int spr_num; /* PowerPC SPR number, or -1 if not an SPR. 106 This is an ISA SPR number, not a GDB 107 register number. */ 108 }; 109 110/* Breakpoint shadows for the single step instructions will be kept here. */ 111 112static struct sstep_breaks 113 { 114 /* Address, or 0 if this is not in use. */ 115 CORE_ADDR address; 116 /* Shadow contents. */ 117 char data[4]; 118 } 119stepBreaks[2]; 120 121/* Hook for determining the TOC address when calling functions in the 122 inferior under AIX. The initialization code in rs6000-nat.c sets 123 this hook to point to find_toc_address. */ 124 125CORE_ADDR (*rs6000_find_toc_address_hook) (CORE_ADDR) = NULL; 126 127/* Hook to set the current architecture when starting a child process. 128 rs6000-nat.c sets this. */ 129 130void (*rs6000_set_host_arch_hook) (int) = NULL; 131 132/* Static function prototypes */ 133 134static CORE_ADDR branch_dest (int opcode, int instr, CORE_ADDR pc, 135 CORE_ADDR safety); 136static CORE_ADDR skip_prologue (CORE_ADDR, CORE_ADDR, 137 struct rs6000_framedata *); 138 139/* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */ 140int 141altivec_register_p (int regno) 142{ 143 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); 144 if (tdep->ppc_vr0_regnum < 0 || tdep->ppc_vrsave_regnum < 0) 145 return 0; 146 else 147 return (regno >= tdep->ppc_vr0_regnum && regno <= tdep->ppc_vrsave_regnum); 148} 149 150 151/* Return true if REGNO is an SPE register, false otherwise. */ 152int 153spe_register_p (int regno) 154{ 155 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); 156 157 /* Is it a reference to EV0 -- EV31, and do we have those? */ 158 if (tdep->ppc_ev0_regnum >= 0 159 && tdep->ppc_ev31_regnum >= 0 160 && tdep->ppc_ev0_regnum <= regno && regno <= tdep->ppc_ev31_regnum) 161 return 1; 162 163 /* Is it a reference to one of the raw upper GPR halves? */ 164 if (tdep->ppc_ev0_upper_regnum >= 0 165 && tdep->ppc_ev0_upper_regnum <= regno 166 && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs) 167 return 1; 168 169 /* Is it a reference to the 64-bit accumulator, and do we have that? */ 170 if (tdep->ppc_acc_regnum >= 0 171 && tdep->ppc_acc_regnum == regno) 172 return 1; 173 174 /* Is it a reference to the SPE floating-point status and control register, 175 and do we have that? */ 176 if (tdep->ppc_spefscr_regnum >= 0 177 && tdep->ppc_spefscr_regnum == regno) 178 return 1; 179 180 return 0; 181} 182 183 184/* Return non-zero if the architecture described by GDBARCH has 185 floating-point registers (f0 --- f31 and fpscr). */ 186int 187ppc_floating_point_unit_p (struct gdbarch *gdbarch) 188{ 189 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 190 191 return (tdep->ppc_fp0_regnum >= 0 192 && tdep->ppc_fpscr_regnum >= 0); 193} 194 195 196/* Check that TABLE[GDB_REGNO] is not already initialized, and then 197 set it to SIM_REGNO. 198 199 This is a helper function for init_sim_regno_table, constructing 200 the table mapping GDB register numbers to sim register numbers; we 201 initialize every element in that table to -1 before we start 202 filling it in. */ 203static void 204set_sim_regno (int *table, int gdb_regno, int sim_regno) 205{ 206 /* Make sure we don't try to assign any given GDB register a sim 207 register number more than once. */ 208 gdb_assert (table[gdb_regno] == -1); 209 table[gdb_regno] = sim_regno; 210} 211 212 213/* Initialize ARCH->tdep->sim_regno, the table mapping GDB register 214 numbers to simulator register numbers, based on the values placed 215 in the ARCH->tdep->ppc_foo_regnum members. */ 216static void 217init_sim_regno_table (struct gdbarch *arch) 218{ 219 struct gdbarch_tdep *tdep = gdbarch_tdep (arch); 220 int total_regs = gdbarch_num_regs (arch) + gdbarch_num_pseudo_regs (arch); 221 const struct reg *regs = tdep->regs; 222 int *sim_regno = GDBARCH_OBSTACK_CALLOC (arch, total_regs, int); 223 int i; 224 225 /* Presume that all registers not explicitly mentioned below are 226 unavailable from the sim. */ 227 for (i = 0; i < total_regs; i++) 228 sim_regno[i] = -1; 229 230 /* General-purpose registers. */ 231 for (i = 0; i < ppc_num_gprs; i++) 232 set_sim_regno (sim_regno, tdep->ppc_gp0_regnum + i, sim_ppc_r0_regnum + i); 233 234 /* Floating-point registers. */ 235 if (tdep->ppc_fp0_regnum >= 0) 236 for (i = 0; i < ppc_num_fprs; i++) 237 set_sim_regno (sim_regno, 238 tdep->ppc_fp0_regnum + i, 239 sim_ppc_f0_regnum + i); 240 if (tdep->ppc_fpscr_regnum >= 0) 241 set_sim_regno (sim_regno, tdep->ppc_fpscr_regnum, sim_ppc_fpscr_regnum); 242 243 set_sim_regno (sim_regno, gdbarch_pc_regnum (arch), sim_ppc_pc_regnum); 244 set_sim_regno (sim_regno, tdep->ppc_ps_regnum, sim_ppc_ps_regnum); 245 set_sim_regno (sim_regno, tdep->ppc_cr_regnum, sim_ppc_cr_regnum); 246 247 /* Segment registers. */ 248 if (tdep->ppc_sr0_regnum >= 0) 249 for (i = 0; i < ppc_num_srs; i++) 250 set_sim_regno (sim_regno, 251 tdep->ppc_sr0_regnum + i, 252 sim_ppc_sr0_regnum + i); 253 254 /* Altivec registers. */ 255 if (tdep->ppc_vr0_regnum >= 0) 256 { 257 for (i = 0; i < ppc_num_vrs; i++) 258 set_sim_regno (sim_regno, 259 tdep->ppc_vr0_regnum + i, 260 sim_ppc_vr0_regnum + i); 261 262 /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum, 263 we can treat this more like the other cases. */ 264 set_sim_regno (sim_regno, 265 tdep->ppc_vr0_regnum + ppc_num_vrs, 266 sim_ppc_vscr_regnum); 267 } 268 /* vsave is a special-purpose register, so the code below handles it. */ 269 270 /* SPE APU (E500) registers. */ 271 if (tdep->ppc_ev0_regnum >= 0) 272 for (i = 0; i < ppc_num_gprs; i++) 273 set_sim_regno (sim_regno, 274 tdep->ppc_ev0_regnum + i, 275 sim_ppc_ev0_regnum + i); 276 if (tdep->ppc_ev0_upper_regnum >= 0) 277 for (i = 0; i < ppc_num_gprs; i++) 278 set_sim_regno (sim_regno, 279 tdep->ppc_ev0_upper_regnum + i, 280 sim_ppc_rh0_regnum + i); 281 if (tdep->ppc_acc_regnum >= 0) 282 set_sim_regno (sim_regno, tdep->ppc_acc_regnum, sim_ppc_acc_regnum); 283 /* spefscr is a special-purpose register, so the code below handles it. */ 284 285 /* Now handle all special-purpose registers. Verify that they 286 haven't mistakenly been assigned numbers by any of the above 287 code). */ 288 for (i = 0; i < total_regs; i++) 289 if (regs[i].spr_num >= 0) 290 set_sim_regno (sim_regno, i, regs[i].spr_num + sim_ppc_spr0_regnum); 291 292 /* Drop the initialized array into place. */ 293 tdep->sim_regno = sim_regno; 294} 295 296 297/* Given a GDB register number REG, return the corresponding SIM 298 register number. */ 299static int 300rs6000_register_sim_regno (int reg) 301{ 302 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); 303 int sim_regno; 304 305 gdb_assert (0 <= reg && reg <= NUM_REGS + NUM_PSEUDO_REGS); 306 sim_regno = tdep->sim_regno[reg]; 307 308 if (sim_regno >= 0) 309 return sim_regno; 310 else 311 return LEGACY_SIM_REGNO_IGNORE; 312} 313 314 315 316/* Register set support functions. */ 317 318static void 319ppc_supply_reg (struct regcache *regcache, int regnum, 320 const char *regs, size_t offset) 321{ 322 if (regnum != -1 && offset != -1) 323 regcache_raw_supply (regcache, regnum, regs + offset); 324} 325 326static void 327ppc_collect_reg (const struct regcache *regcache, int regnum, 328 char *regs, size_t offset) 329{ 330 if (regnum != -1 && offset != -1) 331 regcache_raw_collect (regcache, regnum, regs + offset); 332} 333 334/* Supply register REGNUM in the general-purpose register set REGSET 335 from the buffer specified by GREGS and LEN to register cache 336 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ 337 338void 339ppc_supply_gregset (const struct regset *regset, struct regcache *regcache, 340 int regnum, const void *gregs, size_t len) 341{ 342 struct gdbarch *gdbarch = get_regcache_arch (regcache); 343 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 344 const struct ppc_reg_offsets *offsets = regset->descr; 345 size_t offset; 346 int i; 347 348 for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset; 349 i < tdep->ppc_gp0_regnum + ppc_num_gprs; 350 i++, offset += 4) 351 { 352 if (regnum == -1 || regnum == i) 353 ppc_supply_reg (regcache, i, gregs, offset); 354 } 355 356 if (regnum == -1 || regnum == PC_REGNUM) 357 ppc_supply_reg (regcache, PC_REGNUM, gregs, offsets->pc_offset); 358 if (regnum == -1 || regnum == tdep->ppc_ps_regnum) 359 ppc_supply_reg (regcache, tdep->ppc_ps_regnum, 360 gregs, offsets->ps_offset); 361 if (regnum == -1 || regnum == tdep->ppc_cr_regnum) 362 ppc_supply_reg (regcache, tdep->ppc_cr_regnum, 363 gregs, offsets->cr_offset); 364 if (regnum == -1 || regnum == tdep->ppc_lr_regnum) 365 ppc_supply_reg (regcache, tdep->ppc_lr_regnum, 366 gregs, offsets->lr_offset); 367 if (regnum == -1 || regnum == tdep->ppc_ctr_regnum) 368 ppc_supply_reg (regcache, tdep->ppc_ctr_regnum, 369 gregs, offsets->ctr_offset); 370 if (regnum == -1 || regnum == tdep->ppc_xer_regnum) 371 ppc_supply_reg (regcache, tdep->ppc_xer_regnum, 372 gregs, offsets->cr_offset); 373 if (regnum == -1 || regnum == tdep->ppc_mq_regnum) 374 ppc_supply_reg (regcache, tdep->ppc_mq_regnum, gregs, offsets->mq_offset); 375} 376 377/* Supply register REGNUM in the floating-point register set REGSET 378 from the buffer specified by FPREGS and LEN to register cache 379 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ 380 381void 382ppc_supply_fpregset (const struct regset *regset, struct regcache *regcache, 383 int regnum, const void *fpregs, size_t len) 384{ 385 struct gdbarch *gdbarch = get_regcache_arch (regcache); 386 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 387 const struct ppc_reg_offsets *offsets = regset->descr; 388 size_t offset; 389 int i; 390 391 gdb_assert (ppc_floating_point_unit_p (gdbarch)); 392 393 offset = offsets->f0_offset; 394 for (i = tdep->ppc_fp0_regnum; 395 i < tdep->ppc_fp0_regnum + ppc_num_fprs; 396 i++, offset += 4) 397 { 398 if (regnum == -1 || regnum == i) 399 ppc_supply_reg (regcache, i, fpregs, offset); 400 } 401 402 if (regnum == -1 || regnum == tdep->ppc_fpscr_regnum) 403 ppc_supply_reg (regcache, tdep->ppc_fpscr_regnum, 404 fpregs, offsets->fpscr_offset); 405} 406 407/* Collect register REGNUM in the general-purpose register set 408 REGSET. from register cache REGCACHE into the buffer specified by 409 GREGS and LEN. If REGNUM is -1, do this for all registers in 410 REGSET. */ 411 412void 413ppc_collect_gregset (const struct regset *regset, 414 const struct regcache *regcache, 415 int regnum, void *gregs, size_t len) 416{ 417 struct gdbarch *gdbarch = get_regcache_arch (regcache); 418 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 419 const struct ppc_reg_offsets *offsets = regset->descr; 420 size_t offset; 421 int i; 422 423 offset = offsets->r0_offset; 424 for (i = tdep->ppc_gp0_regnum; 425 i < tdep->ppc_gp0_regnum + ppc_num_gprs; 426 i++, offset += 4) 427 { 428 if (regnum == -1 || regnum == i) 429 ppc_collect_reg (regcache, i, gregs, offset); 430 } 431 432 if (regnum == -1 || regnum == PC_REGNUM) 433 ppc_collect_reg (regcache, PC_REGNUM, gregs, offsets->pc_offset); 434 if (regnum == -1 || regnum == tdep->ppc_ps_regnum) 435 ppc_collect_reg (regcache, tdep->ppc_ps_regnum, 436 gregs, offsets->ps_offset); 437 if (regnum == -1 || regnum == tdep->ppc_cr_regnum) 438 ppc_collect_reg (regcache, tdep->ppc_cr_regnum, 439 gregs, offsets->cr_offset); 440 if (regnum == -1 || regnum == tdep->ppc_lr_regnum) 441 ppc_collect_reg (regcache, tdep->ppc_lr_regnum, 442 gregs, offsets->lr_offset); 443 if (regnum == -1 || regnum == tdep->ppc_ctr_regnum) 444 ppc_collect_reg (regcache, tdep->ppc_ctr_regnum, 445 gregs, offsets->ctr_offset); 446 if (regnum == -1 || regnum == tdep->ppc_xer_regnum) 447 ppc_collect_reg (regcache, tdep->ppc_xer_regnum, 448 gregs, offsets->xer_offset); 449 if (regnum == -1 || regnum == tdep->ppc_mq_regnum) 450 ppc_collect_reg (regcache, tdep->ppc_mq_regnum, 451 gregs, offsets->mq_offset); 452} 453 454/* Collect register REGNUM in the floating-point register set 455 REGSET. from register cache REGCACHE into the buffer specified by 456 FPREGS and LEN. If REGNUM is -1, do this for all registers in 457 REGSET. */ 458 459void 460ppc_collect_fpregset (const struct regset *regset, 461 const struct regcache *regcache, 462 int regnum, void *fpregs, size_t len) 463{ 464 struct gdbarch *gdbarch = get_regcache_arch (regcache); 465 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 466 const struct ppc_reg_offsets *offsets = regset->descr; 467 size_t offset; 468 int i; 469 470 gdb_assert (ppc_floating_point_unit_p (gdbarch)); 471 472 offset = offsets->f0_offset; 473 for (i = tdep->ppc_fp0_regnum; 474 i <= tdep->ppc_fp0_regnum + ppc_num_fprs; 475 i++, offset += 4) 476 { 477 if (regnum == -1 || regnum == i) 478 ppc_collect_reg (regcache, regnum, fpregs, offset); 479 } 480 481 if (regnum == -1 || regnum == tdep->ppc_fpscr_regnum) 482 ppc_collect_reg (regcache, tdep->ppc_fpscr_regnum, 483 fpregs, offsets->fpscr_offset); 484} 485 486 487/* Read a LEN-byte address from debugged memory address MEMADDR. */ 488 489static CORE_ADDR 490read_memory_addr (CORE_ADDR memaddr, int len) 491{ 492 return read_memory_unsigned_integer (memaddr, len); 493} 494 495static CORE_ADDR 496rs6000_skip_prologue (CORE_ADDR pc) 497{ 498 struct rs6000_framedata frame; 499 pc = skip_prologue (pc, 0, &frame); 500 return pc; 501} 502 503 504/* Fill in fi->saved_regs */ 505 506struct frame_extra_info 507{ 508 /* Functions calling alloca() change the value of the stack 509 pointer. We need to use initial stack pointer (which is saved in 510 r31 by gcc) in such cases. If a compiler emits traceback table, 511 then we should use the alloca register specified in traceback 512 table. FIXME. */ 513 CORE_ADDR initial_sp; /* initial stack pointer. */ 514}; 515 516/* Get the ith function argument for the current function. */ 517static CORE_ADDR 518rs6000_fetch_pointer_argument (struct frame_info *frame, int argi, 519 struct type *type) 520{ 521 CORE_ADDR addr; 522 get_frame_register (frame, 3 + argi, &addr); 523 return addr; 524} 525 526/* Calculate the destination of a branch/jump. Return -1 if not a branch. */ 527 528static CORE_ADDR 529branch_dest (int opcode, int instr, CORE_ADDR pc, CORE_ADDR safety) 530{ 531 CORE_ADDR dest; 532 int immediate; 533 int absolute; 534 int ext_op; 535 536 absolute = (int) ((instr >> 1) & 1); 537 538 switch (opcode) 539 { 540 case 18: 541 immediate = ((instr & ~3) << 6) >> 6; /* br unconditional */ 542 if (absolute) 543 dest = immediate; 544 else 545 dest = pc + immediate; 546 break; 547 548 case 16: 549 immediate = ((instr & ~3) << 16) >> 16; /* br conditional */ 550 if (absolute) 551 dest = immediate; 552 else 553 dest = pc + immediate; 554 break; 555 556 case 19: 557 ext_op = (instr >> 1) & 0x3ff; 558 559 if (ext_op == 16) /* br conditional register */ 560 { 561 dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum) & ~3; 562 563 /* If we are about to return from a signal handler, dest is 564 something like 0x3c90. The current frame is a signal handler 565 caller frame, upon completion of the sigreturn system call 566 execution will return to the saved PC in the frame. */ 567 if (dest < TEXT_SEGMENT_BASE) 568 { 569 struct frame_info *fi; 570 571 fi = get_current_frame (); 572 if (fi != NULL) 573 dest = read_memory_addr (get_frame_base (fi) + SIG_FRAME_PC_OFFSET, 574 gdbarch_tdep (current_gdbarch)->wordsize); 575 } 576 } 577 578 else if (ext_op == 528) /* br cond to count reg */ 579 { 580 dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_ctr_regnum) & ~3; 581 582 /* If we are about to execute a system call, dest is something 583 like 0x22fc or 0x3b00. Upon completion the system call 584 will return to the address in the link register. */ 585 if (dest < TEXT_SEGMENT_BASE) 586 dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum) & ~3; 587 } 588 else 589 return -1; 590 break; 591 592 default: 593 return -1; 594 } 595 return (dest < TEXT_SEGMENT_BASE) ? safety : dest; 596} 597 598 599/* Sequence of bytes for breakpoint instruction. */ 600 601const static unsigned char * 602rs6000_breakpoint_from_pc (CORE_ADDR *bp_addr, int *bp_size) 603{ 604 static unsigned char big_breakpoint[] = { 0x7d, 0x82, 0x10, 0x08 }; 605 static unsigned char little_breakpoint[] = { 0x08, 0x10, 0x82, 0x7d }; 606 *bp_size = 4; 607 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) 608 return big_breakpoint; 609 else 610 return little_breakpoint; 611} 612 613 614/* AIX does not support PT_STEP. Simulate it. */ 615 616void 617rs6000_software_single_step (enum target_signal signal, 618 int insert_breakpoints_p) 619{ 620 CORE_ADDR dummy; 621 int breakp_sz; 622 const char *breakp = rs6000_breakpoint_from_pc (&dummy, &breakp_sz); 623 int ii, insn; 624 CORE_ADDR loc; 625 CORE_ADDR breaks[2]; 626 int opcode; 627 628 if (insert_breakpoints_p) 629 { 630 631 loc = read_pc (); 632 633 insn = read_memory_integer (loc, 4); 634 635 breaks[0] = loc + breakp_sz; 636 opcode = insn >> 26; 637 breaks[1] = branch_dest (opcode, insn, loc, breaks[0]); 638 639 /* Don't put two breakpoints on the same address. */ 640 if (breaks[1] == breaks[0]) 641 breaks[1] = -1; 642 643 stepBreaks[1].address = 0; 644 645 for (ii = 0; ii < 2; ++ii) 646 { 647 648 /* ignore invalid breakpoint. */ 649 if (breaks[ii] == -1) 650 continue; 651 target_insert_breakpoint (breaks[ii], stepBreaks[ii].data); 652 stepBreaks[ii].address = breaks[ii]; 653 } 654 655 } 656 else 657 { 658 659 /* remove step breakpoints. */ 660 for (ii = 0; ii < 2; ++ii) 661 if (stepBreaks[ii].address != 0) 662 target_remove_breakpoint (stepBreaks[ii].address, 663 stepBreaks[ii].data); 664 } 665 errno = 0; /* FIXME, don't ignore errors! */ 666 /* What errors? {read,write}_memory call error(). */ 667} 668 669 670/* return pc value after skipping a function prologue and also return 671 information about a function frame. 672 673 in struct rs6000_framedata fdata: 674 - frameless is TRUE, if function does not have a frame. 675 - nosavedpc is TRUE, if function does not save %pc value in its frame. 676 - offset is the initial size of this stack frame --- the amount by 677 which we decrement the sp to allocate the frame. 678 - saved_gpr is the number of the first saved gpr. 679 - saved_fpr is the number of the first saved fpr. 680 - saved_vr is the number of the first saved vr. 681 - saved_ev is the number of the first saved ev. 682 - alloca_reg is the number of the register used for alloca() handling. 683 Otherwise -1. 684 - gpr_offset is the offset of the first saved gpr from the previous frame. 685 - fpr_offset is the offset of the first saved fpr from the previous frame. 686 - vr_offset is the offset of the first saved vr from the previous frame. 687 - ev_offset is the offset of the first saved ev from the previous frame. 688 - lr_offset is the offset of the saved lr 689 - cr_offset is the offset of the saved cr 690 - vrsave_offset is the offset of the saved vrsave register 691 */ 692 693#define SIGNED_SHORT(x) \ 694 ((sizeof (short) == 2) \ 695 ? ((int)(short)(x)) \ 696 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000))) 697 698#define GET_SRC_REG(x) (((x) >> 21) & 0x1f) 699 700/* Limit the number of skipped non-prologue instructions, as the examining 701 of the prologue is expensive. */ 702static int max_skip_non_prologue_insns = 10; 703 704/* Given PC representing the starting address of a function, and 705 LIM_PC which is the (sloppy) limit to which to scan when looking 706 for a prologue, attempt to further refine this limit by using 707 the line data in the symbol table. If successful, a better guess 708 on where the prologue ends is returned, otherwise the previous 709 value of lim_pc is returned. */ 710 711/* FIXME: cagney/2004-02-14: This function and logic have largely been 712 superseded by skip_prologue_using_sal. */ 713 714static CORE_ADDR 715refine_prologue_limit (CORE_ADDR pc, CORE_ADDR lim_pc) 716{ 717 struct symtab_and_line prologue_sal; 718 719 prologue_sal = find_pc_line (pc, 0); 720 if (prologue_sal.line != 0) 721 { 722 int i; 723 CORE_ADDR addr = prologue_sal.end; 724 725 /* Handle the case in which compiler's optimizer/scheduler 726 has moved instructions into the prologue. We scan ahead 727 in the function looking for address ranges whose corresponding 728 line number is less than or equal to the first one that we 729 found for the function. (It can be less than when the 730 scheduler puts a body instruction before the first prologue 731 instruction.) */ 732 for (i = 2 * max_skip_non_prologue_insns; 733 i > 0 && (lim_pc == 0 || addr < lim_pc); 734 i--) 735 { 736 struct symtab_and_line sal; 737 738 sal = find_pc_line (addr, 0); 739 if (sal.line == 0) 740 break; 741 if (sal.line <= prologue_sal.line 742 && sal.symtab == prologue_sal.symtab) 743 { 744 prologue_sal = sal; 745 } 746 addr = sal.end; 747 } 748 749 if (lim_pc == 0 || prologue_sal.end < lim_pc) 750 lim_pc = prologue_sal.end; 751 } 752 return lim_pc; 753} 754 755/* Return nonzero if the given instruction OP can be part of the prologue 756 of a function and saves a parameter on the stack. FRAMEP should be 757 set if one of the previous instructions in the function has set the 758 Frame Pointer. */ 759 760static int 761store_param_on_stack_p (unsigned long op, int framep, int *r0_contains_arg) 762{ 763 /* Move parameters from argument registers to temporary register. */ 764 if ((op & 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */ 765 { 766 /* Rx must be scratch register r0. */ 767 const int rx_regno = (op >> 16) & 31; 768 /* Ry: Only r3 - r10 are used for parameter passing. */ 769 const int ry_regno = GET_SRC_REG (op); 770 771 if (rx_regno == 0 && ry_regno >= 3 && ry_regno <= 10) 772 { 773 *r0_contains_arg = 1; 774 return 1; 775 } 776 else 777 return 0; 778 } 779 780 /* Save a General Purpose Register on stack. */ 781 782 if ((op & 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */ 783 (op & 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */ 784 { 785 /* Rx: Only r3 - r10 are used for parameter passing. */ 786 const int rx_regno = GET_SRC_REG (op); 787 788 return (rx_regno >= 3 && rx_regno <= 10); 789 } 790 791 /* Save a General Purpose Register on stack via the Frame Pointer. */ 792 793 if (framep && 794 ((op & 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */ 795 (op & 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */ 796 (op & 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */ 797 { 798 /* Rx: Usually, only r3 - r10 are used for parameter passing. 799 However, the compiler sometimes uses r0 to hold an argument. */ 800 const int rx_regno = GET_SRC_REG (op); 801 802 return ((rx_regno >= 3 && rx_regno <= 10) 803 || (rx_regno == 0 && *r0_contains_arg)); 804 } 805 806 if ((op & 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */ 807 { 808 /* Only f2 - f8 are used for parameter passing. */ 809 const int src_regno = GET_SRC_REG (op); 810 811 return (src_regno >= 2 && src_regno <= 8); 812 } 813 814 if (framep && ((op & 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */ 815 { 816 /* Only f2 - f8 are used for parameter passing. */ 817 const int src_regno = GET_SRC_REG (op); 818 819 return (src_regno >= 2 && src_regno <= 8); 820 } 821 822 /* Not an insn that saves a parameter on stack. */ 823 return 0; 824} 825 826static CORE_ADDR 827skip_prologue (CORE_ADDR pc, CORE_ADDR lim_pc, struct rs6000_framedata *fdata) 828{ 829 CORE_ADDR orig_pc = pc; 830 CORE_ADDR last_prologue_pc = pc; 831 CORE_ADDR li_found_pc = 0; 832 char buf[4]; 833 unsigned long op; 834 long offset = 0; 835 long vr_saved_offset = 0; 836 int lr_reg = -1; 837 int cr_reg = -1; 838 int vr_reg = -1; 839 int ev_reg = -1; 840 long ev_offset = 0; 841 int vrsave_reg = -1; 842 int reg; 843 int framep = 0; 844 int minimal_toc_loaded = 0; 845 int prev_insn_was_prologue_insn = 1; 846 int num_skip_non_prologue_insns = 0; 847 int r0_contains_arg = 0; 848 const struct bfd_arch_info *arch_info = gdbarch_bfd_arch_info (current_gdbarch); 849 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); 850 851 /* Attempt to find the end of the prologue when no limit is specified. 852 Note that refine_prologue_limit() has been written so that it may 853 be used to "refine" the limits of non-zero PC values too, but this 854 is only safe if we 1) trust the line information provided by the 855 compiler and 2) iterate enough to actually find the end of the 856 prologue. 857 858 It may become a good idea at some point (for both performance and 859 accuracy) to unconditionally call refine_prologue_limit(). But, 860 until we can make a clear determination that this is beneficial, 861 we'll play it safe and only use it to obtain a limit when none 862 has been specified. */ 863 if (lim_pc == 0) 864 lim_pc = refine_prologue_limit (pc, lim_pc); 865 866 memset (fdata, 0, sizeof (struct rs6000_framedata)); 867 fdata->saved_gpr = -1; 868 fdata->saved_fpr = -1; 869 fdata->saved_vr = -1; 870 fdata->saved_ev = -1; 871 fdata->alloca_reg = -1; 872 fdata->frameless = 1; 873 fdata->nosavedpc = 1; 874 875 for (;; pc += 4) 876 { 877 /* Sometimes it isn't clear if an instruction is a prologue 878 instruction or not. When we encounter one of these ambiguous 879 cases, we'll set prev_insn_was_prologue_insn to 0 (false). 880 Otherwise, we'll assume that it really is a prologue instruction. */ 881 if (prev_insn_was_prologue_insn) 882 last_prologue_pc = pc; 883 884 /* Stop scanning if we've hit the limit. */ 885 if (lim_pc != 0 && pc >= lim_pc) 886 break; 887 888 prev_insn_was_prologue_insn = 1; 889 890 /* Fetch the instruction and convert it to an integer. */ 891 if (target_read_memory (pc, buf, 4)) 892 break; 893 op = extract_signed_integer (buf, 4); 894 895 if ((op & 0xfc1fffff) == 0x7c0802a6) 896 { /* mflr Rx */ 897 /* Since shared library / PIC code, which needs to get its 898 address at runtime, can appear to save more than one link 899 register vis: 900 901 *INDENT-OFF* 902 stwu r1,-304(r1) 903 mflr r3 904 bl 0xff570d0 (blrl) 905 stw r30,296(r1) 906 mflr r30 907 stw r31,300(r1) 908 stw r3,308(r1); 909 ... 910 *INDENT-ON* 911 912 remember just the first one, but skip over additional 913 ones. */ 914 if (lr_reg < 0) 915 lr_reg = (op & 0x03e00000); 916 if (lr_reg == 0) 917 r0_contains_arg = 0; 918 continue; 919 } 920 else if ((op & 0xfc1fffff) == 0x7c000026) 921 { /* mfcr Rx */ 922 cr_reg = (op & 0x03e00000); 923 if (cr_reg == 0) 924 r0_contains_arg = 0; 925 continue; 926 927 } 928 else if ((op & 0xfc1f0000) == 0xd8010000) 929 { /* stfd Rx,NUM(r1) */ 930 reg = GET_SRC_REG (op); 931 if (fdata->saved_fpr == -1 || fdata->saved_fpr > reg) 932 { 933 fdata->saved_fpr = reg; 934 fdata->fpr_offset = SIGNED_SHORT (op) + offset; 935 } 936 continue; 937 938 } 939 else if (((op & 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */ 940 (((op & 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */ 941 (op & 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */ 942 (op & 0x03e00000) >= 0x01a00000)) /* rx >= r13 */ 943 { 944 945 reg = GET_SRC_REG (op); 946 if (fdata->saved_gpr == -1 || fdata->saved_gpr > reg) 947 { 948 fdata->saved_gpr = reg; 949 if ((op & 0xfc1f0003) == 0xf8010000) 950 op &= ~3UL; 951 fdata->gpr_offset = SIGNED_SHORT (op) + offset; 952 } 953 continue; 954 955 } 956 else if ((op & 0xffff0000) == 0x60000000) 957 { 958 /* nop */ 959 /* Allow nops in the prologue, but do not consider them to 960 be part of the prologue unless followed by other prologue 961 instructions. */ 962 prev_insn_was_prologue_insn = 0; 963 continue; 964 965 } 966 else if ((op & 0xffff0000) == 0x3c000000) 967 { /* addis 0,0,NUM, used 968 for >= 32k frames */ 969 fdata->offset = (op & 0x0000ffff) << 16; 970 fdata->frameless = 0; 971 r0_contains_arg = 0; 972 continue; 973 974 } 975 else if ((op & 0xffff0000) == 0x60000000) 976 { /* ori 0,0,NUM, 2nd ha 977 lf of >= 32k frames */ 978 fdata->offset |= (op & 0x0000ffff); 979 fdata->frameless = 0; 980 r0_contains_arg = 0; 981 continue; 982 983 } 984 else if (lr_reg != -1 && 985 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */ 986 (((op & 0xffff0000) == (lr_reg | 0xf8010000)) || 987 /* stw Rx, NUM(r1) */ 988 ((op & 0xffff0000) == (lr_reg | 0x90010000)) || 989 /* stwu Rx, NUM(r1) */ 990 ((op & 0xffff0000) == (lr_reg | 0x94010000)))) 991 { /* where Rx == lr */ 992 fdata->lr_offset = offset; 993 fdata->nosavedpc = 0; 994 lr_reg = 0; 995 if ((op & 0xfc000003) == 0xf8000000 || /* std */ 996 (op & 0xfc000000) == 0x90000000) /* stw */ 997 { 998 /* Does not update r1, so add displacement to lr_offset. */ 999 fdata->lr_offset += SIGNED_SHORT (op); 1000 } 1001 continue; 1002 1003 } 1004 else if (cr_reg != -1 && 1005 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */ 1006 (((op & 0xffff0000) == (cr_reg | 0xf8010000)) || 1007 /* stw Rx, NUM(r1) */ 1008 ((op & 0xffff0000) == (cr_reg | 0x90010000)) || 1009 /* stwu Rx, NUM(r1) */ 1010 ((op & 0xffff0000) == (cr_reg | 0x94010000)))) 1011 { /* where Rx == cr */ 1012 fdata->cr_offset = offset; 1013 cr_reg = 0; 1014 if ((op & 0xfc000003) == 0xf8000000 || 1015 (op & 0xfc000000) == 0x90000000) 1016 { 1017 /* Does not update r1, so add displacement to cr_offset. */ 1018 fdata->cr_offset += SIGNED_SHORT (op); 1019 } 1020 continue; 1021 1022 } 1023 else if (op == 0x48000005) 1024 { /* bl .+4 used in 1025 -mrelocatable */ 1026 continue; 1027 1028 } 1029 else if (op == 0x48000004) 1030 { /* b .+4 (xlc) */ 1031 break; 1032 1033 } 1034 else if ((op & 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used 1035 in V.4 -mminimal-toc */ 1036 (op & 0xffff0000) == 0x3bde0000) 1037 { /* addi 30,30,foo@l */ 1038 continue; 1039 1040 } 1041 else if ((op & 0xfc000001) == 0x48000001) 1042 { /* bl foo, 1043 to save fprs??? */ 1044 1045 fdata->frameless = 0; 1046 /* Don't skip over the subroutine call if it is not within 1047 the first three instructions of the prologue. */ 1048 if ((pc - orig_pc) > 8) 1049 break; 1050 1051 op = read_memory_integer (pc + 4, 4); 1052 1053 /* At this point, make sure this is not a trampoline 1054 function (a function that simply calls another functions, 1055 and nothing else). If the next is not a nop, this branch 1056 was part of the function prologue. */ 1057 1058 if (op == 0x4def7b82 || op == 0) /* crorc 15, 15, 15 */ 1059 break; /* don't skip over 1060 this branch */ 1061 continue; 1062 1063 } 1064 /* update stack pointer */ 1065 else if ((op & 0xfc1f0000) == 0x94010000) 1066 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */ 1067 fdata->frameless = 0; 1068 fdata->offset = SIGNED_SHORT (op); 1069 offset = fdata->offset; 1070 continue; 1071 } 1072 else if ((op & 0xfc1f016a) == 0x7c01016e) 1073 { /* stwux rX,r1,rY */ 1074 /* no way to figure out what r1 is going to be */ 1075 fdata->frameless = 0; 1076 offset = fdata->offset; 1077 continue; 1078 } 1079 else if ((op & 0xfc1f0003) == 0xf8010001) 1080 { /* stdu rX,NUM(r1) */ 1081 fdata->frameless = 0; 1082 fdata->offset = SIGNED_SHORT (op & ~3UL); 1083 offset = fdata->offset; 1084 continue; 1085 } 1086 else if ((op & 0xfc1f016a) == 0x7c01016a) 1087 { /* stdux rX,r1,rY */ 1088 /* no way to figure out what r1 is going to be */ 1089 fdata->frameless = 0; 1090 offset = fdata->offset; 1091 continue; 1092 } 1093 /* Load up minimal toc pointer */ 1094 else if (((op >> 22) == 0x20f || /* l r31,... or l r30,... */ 1095 (op >> 22) == 0x3af) /* ld r31,... or ld r30,... */ 1096 && !minimal_toc_loaded) 1097 { 1098 minimal_toc_loaded = 1; 1099 continue; 1100 1101 /* move parameters from argument registers to local variable 1102 registers */ 1103 } 1104 else if ((op & 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */ 1105 (((op >> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */ 1106 (((op >> 21) & 31) <= 10) && 1107 ((long) ((op >> 16) & 31) >= fdata->saved_gpr)) /* Rx: local var reg */ 1108 { 1109 continue; 1110 1111 /* store parameters in stack */ 1112 } 1113 /* Move parameters from argument registers to temporary register. */ 1114 else if (store_param_on_stack_p (op, framep, &r0_contains_arg)) 1115 { 1116 continue; 1117 1118 /* Set up frame pointer */ 1119 } 1120 else if (op == 0x603f0000 /* oril r31, r1, 0x0 */ 1121 || op == 0x7c3f0b78) 1122 { /* mr r31, r1 */ 1123 fdata->frameless = 0; 1124 framep = 1; 1125 fdata->alloca_reg = (tdep->ppc_gp0_regnum + 31); 1126 continue; 1127 1128 /* Another way to set up the frame pointer. */ 1129 } 1130 else if ((op & 0xfc1fffff) == 0x38010000) 1131 { /* addi rX, r1, 0x0 */ 1132 fdata->frameless = 0; 1133 framep = 1; 1134 fdata->alloca_reg = (tdep->ppc_gp0_regnum 1135 + ((op & ~0x38010000) >> 21)); 1136 continue; 1137 } 1138 /* AltiVec related instructions. */ 1139 /* Store the vrsave register (spr 256) in another register for 1140 later manipulation, or load a register into the vrsave 1141 register. 2 instructions are used: mfvrsave and 1142 mtvrsave. They are shorthand notation for mfspr Rn, SPR256 1143 and mtspr SPR256, Rn. */ 1144 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110 1145 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */ 1146 else if ((op & 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */ 1147 { 1148 vrsave_reg = GET_SRC_REG (op); 1149 continue; 1150 } 1151 else if ((op & 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */ 1152 { 1153 continue; 1154 } 1155 /* Store the register where vrsave was saved to onto the stack: 1156 rS is the register where vrsave was stored in a previous 1157 instruction. */ 1158 /* 100100 sssss 00001 dddddddd dddddddd */ 1159 else if ((op & 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */ 1160 { 1161 if (vrsave_reg == GET_SRC_REG (op)) 1162 { 1163 fdata->vrsave_offset = SIGNED_SHORT (op) + offset; 1164 vrsave_reg = -1; 1165 } 1166 continue; 1167 } 1168 /* Compute the new value of vrsave, by modifying the register 1169 where vrsave was saved to. */ 1170 else if (((op & 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */ 1171 || ((op & 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */ 1172 { 1173 continue; 1174 } 1175 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first 1176 in a pair of insns to save the vector registers on the 1177 stack. */ 1178 /* 001110 00000 00000 iiii iiii iiii iiii */ 1179 /* 001110 01110 00000 iiii iiii iiii iiii */ 1180 else if ((op & 0xffff0000) == 0x38000000 /* li r0, SIMM */ 1181 || (op & 0xffff0000) == 0x39c00000) /* li r14, SIMM */ 1182 { 1183 if ((op & 0xffff0000) == 0x38000000) 1184 r0_contains_arg = 0; 1185 li_found_pc = pc; 1186 vr_saved_offset = SIGNED_SHORT (op); 1187 1188 /* This insn by itself is not part of the prologue, unless 1189 if part of the pair of insns mentioned above. So do not 1190 record this insn as part of the prologue yet. */ 1191 prev_insn_was_prologue_insn = 0; 1192 } 1193 /* Store vector register S at (r31+r0) aligned to 16 bytes. */ 1194 /* 011111 sssss 11111 00000 00111001110 */ 1195 else if ((op & 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */ 1196 { 1197 if (pc == (li_found_pc + 4)) 1198 { 1199 vr_reg = GET_SRC_REG (op); 1200 /* If this is the first vector reg to be saved, or if 1201 it has a lower number than others previously seen, 1202 reupdate the frame info. */ 1203 if (fdata->saved_vr == -1 || fdata->saved_vr > vr_reg) 1204 { 1205 fdata->saved_vr = vr_reg; 1206 fdata->vr_offset = vr_saved_offset + offset; 1207 } 1208 vr_saved_offset = -1; 1209 vr_reg = -1; 1210 li_found_pc = 0; 1211 } 1212 } 1213 /* End AltiVec related instructions. */ 1214 1215 /* Start BookE related instructions. */ 1216 /* Store gen register S at (r31+uimm). 1217 Any register less than r13 is volatile, so we don't care. */ 1218 /* 000100 sssss 11111 iiiii 01100100001 */ 1219 else if (arch_info->mach == bfd_mach_ppc_e500 1220 && (op & 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */ 1221 { 1222 if ((op & 0x03e00000) >= 0x01a00000) /* Rs >= r13 */ 1223 { 1224 unsigned int imm; 1225 ev_reg = GET_SRC_REG (op); 1226 imm = (op >> 11) & 0x1f; 1227 ev_offset = imm * 8; 1228 /* If this is the first vector reg to be saved, or if 1229 it has a lower number than others previously seen, 1230 reupdate the frame info. */ 1231 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) 1232 { 1233 fdata->saved_ev = ev_reg; 1234 fdata->ev_offset = ev_offset + offset; 1235 } 1236 } 1237 continue; 1238 } 1239 /* Store gen register rS at (r1+rB). */ 1240 /* 000100 sssss 00001 bbbbb 01100100000 */ 1241 else if (arch_info->mach == bfd_mach_ppc_e500 1242 && (op & 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */ 1243 { 1244 if (pc == (li_found_pc + 4)) 1245 { 1246 ev_reg = GET_SRC_REG (op); 1247 /* If this is the first vector reg to be saved, or if 1248 it has a lower number than others previously seen, 1249 reupdate the frame info. */ 1250 /* We know the contents of rB from the previous instruction. */ 1251 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) 1252 { 1253 fdata->saved_ev = ev_reg; 1254 fdata->ev_offset = vr_saved_offset + offset; 1255 } 1256 vr_saved_offset = -1; 1257 ev_reg = -1; 1258 li_found_pc = 0; 1259 } 1260 continue; 1261 } 1262 /* Store gen register r31 at (rA+uimm). */ 1263 /* 000100 11111 aaaaa iiiii 01100100001 */ 1264 else if (arch_info->mach == bfd_mach_ppc_e500 1265 && (op & 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */ 1266 { 1267 /* Wwe know that the source register is 31 already, but 1268 it can't hurt to compute it. */ 1269 ev_reg = GET_SRC_REG (op); 1270 ev_offset = ((op >> 11) & 0x1f) * 8; 1271 /* If this is the first vector reg to be saved, or if 1272 it has a lower number than others previously seen, 1273 reupdate the frame info. */ 1274 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) 1275 { 1276 fdata->saved_ev = ev_reg; 1277 fdata->ev_offset = ev_offset + offset; 1278 } 1279 1280 continue; 1281 } 1282 /* Store gen register S at (r31+r0). 1283 Store param on stack when offset from SP bigger than 4 bytes. */ 1284 /* 000100 sssss 11111 00000 01100100000 */ 1285 else if (arch_info->mach == bfd_mach_ppc_e500 1286 && (op & 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */ 1287 { 1288 if (pc == (li_found_pc + 4)) 1289 { 1290 if ((op & 0x03e00000) >= 0x01a00000) 1291 { 1292 ev_reg = GET_SRC_REG (op); 1293 /* If this is the first vector reg to be saved, or if 1294 it has a lower number than others previously seen, 1295 reupdate the frame info. */ 1296 /* We know the contents of r0 from the previous 1297 instruction. */ 1298 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) 1299 { 1300 fdata->saved_ev = ev_reg; 1301 fdata->ev_offset = vr_saved_offset + offset; 1302 } 1303 ev_reg = -1; 1304 } 1305 vr_saved_offset = -1; 1306 li_found_pc = 0; 1307 continue; 1308 } 1309 } 1310 /* End BookE related instructions. */ 1311 1312 else 1313 { 1314 /* Not a recognized prologue instruction. 1315 Handle optimizer code motions into the prologue by continuing 1316 the search if we have no valid frame yet or if the return 1317 address is not yet saved in the frame. */ 1318 if (fdata->frameless == 0 1319 && (lr_reg == -1 || fdata->nosavedpc == 0)) 1320 break; 1321 1322 if (op == 0x4e800020 /* blr */ 1323 || op == 0x4e800420) /* bctr */ 1324 /* Do not scan past epilogue in frameless functions or 1325 trampolines. */ 1326 break; 1327 if ((op & 0xf4000000) == 0x40000000) /* bxx */ 1328 /* Never skip branches. */ 1329 break; 1330 1331 if (num_skip_non_prologue_insns++ > max_skip_non_prologue_insns) 1332 /* Do not scan too many insns, scanning insns is expensive with 1333 remote targets. */ 1334 break; 1335 1336 /* Continue scanning. */ 1337 prev_insn_was_prologue_insn = 0; 1338 continue; 1339 } 1340 } 1341 1342#if 0 1343/* I have problems with skipping over __main() that I need to address 1344 * sometime. Previously, I used to use misc_function_vector which 1345 * didn't work as well as I wanted to be. -MGO */ 1346 1347 /* If the first thing after skipping a prolog is a branch to a function, 1348 this might be a call to an initializer in main(), introduced by gcc2. 1349 We'd like to skip over it as well. Fortunately, xlc does some extra 1350 work before calling a function right after a prologue, thus we can 1351 single out such gcc2 behaviour. */ 1352 1353 1354 if ((op & 0xfc000001) == 0x48000001) 1355 { /* bl foo, an initializer function? */ 1356 op = read_memory_integer (pc + 4, 4); 1357 1358 if (op == 0x4def7b82) 1359 { /* cror 0xf, 0xf, 0xf (nop) */ 1360 1361 /* Check and see if we are in main. If so, skip over this 1362 initializer function as well. */ 1363 1364 tmp = find_pc_misc_function (pc); 1365 if (tmp >= 0 1366 && strcmp (misc_function_vector[tmp].name, main_name ()) == 0) 1367 return pc + 8; 1368 } 1369 } 1370#endif /* 0 */ 1371 1372 fdata->offset = -fdata->offset; 1373 return last_prologue_pc; 1374} 1375 1376 1377/************************************************************************* 1378 Support for creating pushing a dummy frame into the stack, and popping 1379 frames, etc. 1380*************************************************************************/ 1381 1382 1383/* All the ABI's require 16 byte alignment. */ 1384static CORE_ADDR 1385rs6000_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) 1386{ 1387 return (addr & -16); 1388} 1389 1390/* Pass the arguments in either registers, or in the stack. In RS/6000, 1391 the first eight words of the argument list (that might be less than 1392 eight parameters if some parameters occupy more than one word) are 1393 passed in r3..r10 registers. float and double parameters are 1394 passed in fpr's, in addition to that. Rest of the parameters if any 1395 are passed in user stack. There might be cases in which half of the 1396 parameter is copied into registers, the other half is pushed into 1397 stack. 1398 1399 Stack must be aligned on 64-bit boundaries when synthesizing 1400 function calls. 1401 1402 If the function is returning a structure, then the return address is passed 1403 in r3, then the first 7 words of the parameters can be passed in registers, 1404 starting from r4. */ 1405 1406static CORE_ADDR 1407rs6000_push_dummy_call (struct gdbarch *gdbarch, struct value *function, 1408 struct regcache *regcache, CORE_ADDR bp_addr, 1409 int nargs, struct value **args, CORE_ADDR sp, 1410 int struct_return, CORE_ADDR struct_addr) 1411{ 1412 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); 1413 int ii; 1414 int len = 0; 1415 int argno; /* current argument number */ 1416 int argbytes; /* current argument byte */ 1417 char tmp_buffer[50]; 1418 int f_argno = 0; /* current floating point argno */ 1419 int wordsize = gdbarch_tdep (current_gdbarch)->wordsize; 1420 CORE_ADDR func_addr = find_function_addr (function, NULL); 1421 1422 struct value *arg = 0; 1423 struct type *type; 1424 1425 CORE_ADDR saved_sp; 1426 1427 /* The calling convention this function implements assumes the 1428 processor has floating-point registers. We shouldn't be using it 1429 on PPC variants that lack them. */ 1430 gdb_assert (ppc_floating_point_unit_p (current_gdbarch)); 1431 1432 /* The first eight words of ther arguments are passed in registers. 1433 Copy them appropriately. */ 1434 ii = 0; 1435 1436 /* If the function is returning a `struct', then the first word 1437 (which will be passed in r3) is used for struct return address. 1438 In that case we should advance one word and start from r4 1439 register to copy parameters. */ 1440 if (struct_return) 1441 { 1442 regcache_raw_write_unsigned (regcache, tdep->ppc_gp0_regnum + 3, 1443 struct_addr); 1444 ii++; 1445 } 1446 1447/* 1448 effectively indirect call... gcc does... 1449 1450 return_val example( float, int); 1451 1452 eabi: 1453 float in fp0, int in r3 1454 offset of stack on overflow 8/16 1455 for varargs, must go by type. 1456 power open: 1457 float in r3&r4, int in r5 1458 offset of stack on overflow different 1459 both: 1460 return in r3 or f0. If no float, must study how gcc emulates floats; 1461 pay attention to arg promotion. 1462 User may have to cast\args to handle promotion correctly 1463 since gdb won't know if prototype supplied or not. 1464 */ 1465 1466 for (argno = 0, argbytes = 0; argno < nargs && ii < 8; ++ii) 1467 { 1468 int reg_size = register_size (current_gdbarch, ii + 3); 1469 1470 arg = args[argno]; 1471 type = check_typedef (VALUE_TYPE (arg)); 1472 len = TYPE_LENGTH (type); 1473 1474 if (TYPE_CODE (type) == TYPE_CODE_FLT) 1475 { 1476 1477 /* Floating point arguments are passed in fpr's, as well as gpr's. 1478 There are 13 fpr's reserved for passing parameters. At this point 1479 there is no way we would run out of them. */ 1480 1481 gdb_assert (len <= 8); 1482 1483 regcache_cooked_write (regcache, 1484 tdep->ppc_fp0_regnum + 1 + f_argno, 1485 VALUE_CONTENTS (arg)); 1486 ++f_argno; 1487 } 1488 1489 if (len > reg_size) 1490 { 1491 1492 /* Argument takes more than one register. */ 1493 while (argbytes < len) 1494 { 1495 char word[MAX_REGISTER_SIZE]; 1496 memset (word, 0, reg_size); 1497 memcpy (word, 1498 ((char *) VALUE_CONTENTS (arg)) + argbytes, 1499 (len - argbytes) > reg_size 1500 ? reg_size : len - argbytes); 1501 regcache_cooked_write (regcache, 1502 tdep->ppc_gp0_regnum + 3 + ii, 1503 word); 1504 ++ii, argbytes += reg_size; 1505 1506 if (ii >= 8) 1507 goto ran_out_of_registers_for_arguments; 1508 } 1509 argbytes = 0; 1510 --ii; 1511 } 1512 else 1513 { 1514 /* Argument can fit in one register. No problem. */ 1515 int adj = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? reg_size - len : 0; 1516 char word[MAX_REGISTER_SIZE]; 1517 1518 memset (word, 0, reg_size); 1519 memcpy (word, VALUE_CONTENTS (arg), len); 1520 regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + 3 +ii, word); 1521 } 1522 ++argno; 1523 } 1524 1525ran_out_of_registers_for_arguments: 1526 1527 saved_sp = read_sp (); 1528 1529 /* Location for 8 parameters are always reserved. */ 1530 sp -= wordsize * 8; 1531 1532 /* Another six words for back chain, TOC register, link register, etc. */ 1533 sp -= wordsize * 6; 1534 1535 /* Stack pointer must be quadword aligned. */ 1536 sp &= -16; 1537 1538 /* If there are more arguments, allocate space for them in 1539 the stack, then push them starting from the ninth one. */ 1540 1541 if ((argno < nargs) || argbytes) 1542 { 1543 int space = 0, jj; 1544 1545 if (argbytes) 1546 { 1547 space += ((len - argbytes + 3) & -4); 1548 jj = argno + 1; 1549 } 1550 else 1551 jj = argno; 1552 1553 for (; jj < nargs; ++jj) 1554 { 1555 struct value *val = args[jj]; 1556 space += ((TYPE_LENGTH (VALUE_TYPE (val))) + 3) & -4; 1557 } 1558 1559 /* Add location required for the rest of the parameters. */ 1560 space = (space + 15) & -16; 1561 sp -= space; 1562 1563 /* This is another instance we need to be concerned about 1564 securing our stack space. If we write anything underneath %sp 1565 (r1), we might conflict with the kernel who thinks he is free 1566 to use this area. So, update %sp first before doing anything 1567 else. */ 1568 1569 regcache_raw_write_signed (regcache, SP_REGNUM, sp); 1570 1571 /* If the last argument copied into the registers didn't fit there 1572 completely, push the rest of it into stack. */ 1573 1574 if (argbytes) 1575 { 1576 write_memory (sp + 24 + (ii * 4), 1577 ((char *) VALUE_CONTENTS (arg)) + argbytes, 1578 len - argbytes); 1579 ++argno; 1580 ii += ((len - argbytes + 3) & -4) / 4; 1581 } 1582 1583 /* Push the rest of the arguments into stack. */ 1584 for (; argno < nargs; ++argno) 1585 { 1586 1587 arg = args[argno]; 1588 type = check_typedef (VALUE_TYPE (arg)); 1589 len = TYPE_LENGTH (type); 1590 1591 1592 /* Float types should be passed in fpr's, as well as in the 1593 stack. */ 1594 if (TYPE_CODE (type) == TYPE_CODE_FLT && f_argno < 13) 1595 { 1596 1597 gdb_assert (len <= 8); 1598 1599 regcache_cooked_write (regcache, 1600 tdep->ppc_fp0_regnum + 1 + f_argno, 1601 VALUE_CONTENTS (arg)); 1602 ++f_argno; 1603 } 1604 1605 write_memory (sp + 24 + (ii * 4), 1606 (char *) VALUE_CONTENTS (arg), 1607 len); 1608 ii += ((len + 3) & -4) / 4; 1609 } 1610 } 1611 1612 /* Set the stack pointer. According to the ABI, the SP is meant to 1613 be set _before_ the corresponding stack space is used. On AIX, 1614 this even applies when the target has been completely stopped! 1615 Not doing this can lead to conflicts with the kernel which thinks 1616 that it still has control over this not-yet-allocated stack 1617 region. */ 1618 regcache_raw_write_signed (regcache, SP_REGNUM, sp); 1619 1620 /* Set back chain properly. */ 1621 store_unsigned_integer (tmp_buffer, 4, saved_sp); 1622 write_memory (sp, tmp_buffer, 4); 1623 1624 /* Point the inferior function call's return address at the dummy's 1625 breakpoint. */ 1626 regcache_raw_write_signed (regcache, tdep->ppc_lr_regnum, bp_addr); 1627 1628 /* Set the TOC register, get the value from the objfile reader 1629 which, in turn, gets it from the VMAP table. */ 1630 if (rs6000_find_toc_address_hook != NULL) 1631 { 1632 CORE_ADDR tocvalue = (*rs6000_find_toc_address_hook) (func_addr); 1633 regcache_raw_write_signed (regcache, tdep->ppc_toc_regnum, tocvalue); 1634 } 1635 1636 target_store_registers (-1); 1637 return sp; 1638} 1639 1640/* PowerOpen always puts structures in memory. Vectors, which were 1641 added later, do get returned in a register though. */ 1642 1643static int 1644rs6000_use_struct_convention (int gcc_p, struct type *value_type) 1645{ 1646 if ((TYPE_LENGTH (value_type) == 16 || TYPE_LENGTH (value_type) == 8) 1647 && TYPE_VECTOR (value_type)) 1648 return 0; 1649 return 1; 1650} 1651 1652static void 1653rs6000_extract_return_value (struct type *valtype, char *regbuf, char *valbuf) 1654{ 1655 int offset = 0; 1656 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); 1657 1658 /* The calling convention this function implements assumes the 1659 processor has floating-point registers. We shouldn't be using it 1660 on PPC variants that lack them. */ 1661 gdb_assert (ppc_floating_point_unit_p (current_gdbarch)); 1662 1663 if (TYPE_CODE (valtype) == TYPE_CODE_FLT) 1664 { 1665 1666 /* floats and doubles are returned in fpr1. fpr's have a size of 8 bytes. 1667 We need to truncate the return value into float size (4 byte) if 1668 necessary. */ 1669 1670 convert_typed_floating (®buf[DEPRECATED_REGISTER_BYTE 1671 (tdep->ppc_fp0_regnum + 1)], 1672 builtin_type_double, 1673 valbuf, 1674 valtype); 1675 } 1676 else if (TYPE_CODE (valtype) == TYPE_CODE_ARRAY 1677 && TYPE_LENGTH (valtype) == 16 1678 && TYPE_VECTOR (valtype)) 1679 { 1680 memcpy (valbuf, regbuf + DEPRECATED_REGISTER_BYTE (tdep->ppc_vr0_regnum + 2), 1681 TYPE_LENGTH (valtype)); 1682 } 1683 else 1684 { 1685 /* return value is copied starting from r3. */ 1686 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG 1687 && TYPE_LENGTH (valtype) < register_size (current_gdbarch, 3)) 1688 offset = register_size (current_gdbarch, 3) - TYPE_LENGTH (valtype); 1689 1690 memcpy (valbuf, 1691 regbuf + DEPRECATED_REGISTER_BYTE (3) + offset, 1692 TYPE_LENGTH (valtype)); 1693 } 1694} 1695 1696/* Return whether handle_inferior_event() should proceed through code 1697 starting at PC in function NAME when stepping. 1698 1699 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to 1700 handle memory references that are too distant to fit in instructions 1701 generated by the compiler. For example, if 'foo' in the following 1702 instruction: 1703 1704 lwz r9,foo(r2) 1705 1706 is greater than 32767, the linker might replace the lwz with a branch to 1707 somewhere in @FIX1 that does the load in 2 instructions and then branches 1708 back to where execution should continue. 1709 1710 GDB should silently step over @FIX code, just like AIX dbx does. 1711 Unfortunately, the linker uses the "b" instruction for the branches, 1712 meaning that the link register doesn't get set. Therefore, GDB's usual 1713 step_over_function() mechanism won't work. 1714 1715 Instead, use the IN_SOLIB_RETURN_TRAMPOLINE and SKIP_TRAMPOLINE_CODE hooks 1716 in handle_inferior_event() to skip past @FIX code. */ 1717 1718int 1719rs6000_in_solib_return_trampoline (CORE_ADDR pc, char *name) 1720{ 1721 return name && !strncmp (name, "@FIX", 4); 1722} 1723 1724/* Skip code that the user doesn't want to see when stepping: 1725 1726 1. Indirect function calls use a piece of trampoline code to do context 1727 switching, i.e. to set the new TOC table. Skip such code if we are on 1728 its first instruction (as when we have single-stepped to here). 1729 1730 2. Skip shared library trampoline code (which is different from 1731 indirect function call trampolines). 1732 1733 3. Skip bigtoc fixup code. 1734 1735 Result is desired PC to step until, or NULL if we are not in 1736 code that should be skipped. */ 1737 1738CORE_ADDR 1739rs6000_skip_trampoline_code (CORE_ADDR pc) 1740{ 1741 unsigned int ii, op; 1742 int rel; 1743 CORE_ADDR solib_target_pc; 1744 struct minimal_symbol *msymbol; 1745 1746 static unsigned trampoline_code[] = 1747 { 1748 0x800b0000, /* l r0,0x0(r11) */ 1749 0x90410014, /* st r2,0x14(r1) */ 1750 0x7c0903a6, /* mtctr r0 */ 1751 0x804b0004, /* l r2,0x4(r11) */ 1752 0x816b0008, /* l r11,0x8(r11) */ 1753 0x4e800420, /* bctr */ 1754 0x4e800020, /* br */ 1755 0 1756 }; 1757 1758 /* Check for bigtoc fixup code. */ 1759 msymbol = lookup_minimal_symbol_by_pc (pc); 1760 if (msymbol && rs6000_in_solib_return_trampoline (pc, DEPRECATED_SYMBOL_NAME (msymbol))) 1761 { 1762 /* Double-check that the third instruction from PC is relative "b". */ 1763 op = read_memory_integer (pc + 8, 4); 1764 if ((op & 0xfc000003) == 0x48000000) 1765 { 1766 /* Extract bits 6-29 as a signed 24-bit relative word address and 1767 add it to the containing PC. */ 1768 rel = ((int)(op << 6) >> 6); 1769 return pc + 8 + rel; 1770 } 1771 } 1772 1773 /* If pc is in a shared library trampoline, return its target. */ 1774 solib_target_pc = find_solib_trampoline_target (pc); 1775 if (solib_target_pc) 1776 return solib_target_pc; 1777 1778 for (ii = 0; trampoline_code[ii]; ++ii) 1779 { 1780 op = read_memory_integer (pc + (ii * 4), 4); 1781 if (op != trampoline_code[ii]) 1782 return 0; 1783 } 1784 ii = read_register (11); /* r11 holds destination addr */ 1785 pc = read_memory_addr (ii, gdbarch_tdep (current_gdbarch)->wordsize); /* (r11) value */ 1786 return pc; 1787} 1788 1789/* Return the size of register REG when words are WORDSIZE bytes long. If REG 1790 isn't available with that word size, return 0. */ 1791 1792static int 1793regsize (const struct reg *reg, int wordsize) 1794{ 1795 return wordsize == 8 ? reg->sz64 : reg->sz32; 1796} 1797 1798/* Return the name of register number N, or null if no such register exists 1799 in the current architecture. */ 1800 1801static const char * 1802rs6000_register_name (int n) 1803{ 1804 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); 1805 const struct reg *reg = tdep->regs + n; 1806 1807 if (!regsize (reg, tdep->wordsize)) 1808 return NULL; 1809 return reg->name; 1810} 1811 1812/* Return the GDB type object for the "standard" data type 1813 of data in register N. */ 1814 1815static struct type * 1816rs6000_register_type (struct gdbarch *gdbarch, int n) 1817{ 1818 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 1819 const struct reg *reg = tdep->regs + n; 1820 1821 if (reg->fpr) 1822 return builtin_type_double; 1823 else 1824 { 1825 int size = regsize (reg, tdep->wordsize); 1826 switch (size) 1827 { 1828 case 0: 1829 return builtin_type_int0; 1830 case 4: 1831 return builtin_type_uint32; 1832 case 8: 1833 if (tdep->ppc_ev0_regnum <= n && n <= tdep->ppc_ev31_regnum) 1834 return builtin_type_vec64; 1835 else 1836 return builtin_type_uint64; 1837 break; 1838 case 16: 1839 return builtin_type_vec128; 1840 break; 1841 default: 1842 internal_error (__FILE__, __LINE__, "Register %d size %d unknown", 1843 n, size); 1844 } 1845 } 1846} 1847 1848/* The register format for RS/6000 floating point registers is always 1849 double, we need a conversion if the memory format is float. */ 1850 1851static int 1852rs6000_convert_register_p (int regnum, struct type *type) 1853{ 1854 const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + regnum; 1855 1856 return (reg->fpr 1857 && TYPE_CODE (type) == TYPE_CODE_FLT 1858 && TYPE_LENGTH (type) != TYPE_LENGTH (builtin_type_double)); 1859} 1860 1861static void 1862rs6000_register_to_value (struct frame_info *frame, 1863 int regnum, 1864 struct type *type, 1865 void *to) 1866{ 1867 const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + regnum; 1868 char from[MAX_REGISTER_SIZE]; 1869 1870 gdb_assert (reg->fpr); 1871 gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT); 1872 1873 get_frame_register (frame, regnum, from); 1874 convert_typed_floating (from, builtin_type_double, to, type); 1875} 1876 1877static void 1878rs6000_value_to_register (struct frame_info *frame, 1879 int regnum, 1880 struct type *type, 1881 const void *from) 1882{ 1883 const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + regnum; 1884 char to[MAX_REGISTER_SIZE]; 1885 1886 gdb_assert (reg->fpr); 1887 gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT); 1888 1889 convert_typed_floating (from, type, to, builtin_type_double); 1890 put_frame_register (frame, regnum, to); 1891} 1892 1893/* Move SPE vector register values between a 64-bit buffer and the two 1894 32-bit raw register halves in a regcache. This function handles 1895 both splitting a 64-bit value into two 32-bit halves, and joining 1896 two halves into a whole 64-bit value, depending on the function 1897 passed as the MOVE argument. 1898 1899 EV_REG must be the number of an SPE evN vector register --- a 1900 pseudoregister. REGCACHE must be a regcache, and BUFFER must be a 1901 64-bit buffer. 1902 1903 Call MOVE once for each 32-bit half of that register, passing 1904 REGCACHE, the number of the raw register corresponding to that 1905 half, and the address of the appropriate half of BUFFER. 1906 1907 For example, passing 'regcache_raw_read' as the MOVE function will 1908 fill BUFFER with the full 64-bit contents of EV_REG. Or, passing 1909 'regcache_raw_supply' will supply the contents of BUFFER to the 1910 appropriate pair of raw registers in REGCACHE. 1911 1912 You may need to cast away some 'const' qualifiers when passing 1913 MOVE, since this function can't tell at compile-time which of 1914 REGCACHE or BUFFER is acting as the source of the data. If C had 1915 co-variant type qualifiers, ... */ 1916static void 1917e500_move_ev_register (void (*move) (struct regcache *regcache, 1918 int regnum, void *buf), 1919 struct regcache *regcache, int ev_reg, 1920 void *buffer) 1921{ 1922 struct gdbarch *arch = get_regcache_arch (regcache); 1923 struct gdbarch_tdep *tdep = gdbarch_tdep (arch); 1924 int reg_index; 1925 char *byte_buffer = buffer; 1926 1927 gdb_assert (tdep->ppc_ev0_regnum <= ev_reg 1928 && ev_reg < tdep->ppc_ev0_regnum + ppc_num_gprs); 1929 1930 reg_index = ev_reg - tdep->ppc_ev0_regnum; 1931 1932 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) 1933 { 1934 move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, byte_buffer); 1935 move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer + 4); 1936 } 1937 else 1938 { 1939 move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer); 1940 move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, byte_buffer + 4); 1941 } 1942} 1943 1944static void 1945e500_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, 1946 int reg_nr, void *buffer) 1947{ 1948 struct gdbarch *regcache_arch = get_regcache_arch (regcache); 1949 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 1950 1951 gdb_assert (regcache_arch == gdbarch); 1952 1953 if (tdep->ppc_ev0_regnum <= reg_nr 1954 && reg_nr < tdep->ppc_ev0_regnum + ppc_num_gprs) 1955 e500_move_ev_register (regcache_raw_read, regcache, reg_nr, buffer); 1956 else 1957 internal_error (__FILE__, __LINE__, 1958 "e500_pseudo_register_read: " 1959 "called on unexpected register '%s' (%d)", 1960 gdbarch_register_name (gdbarch, reg_nr), reg_nr); 1961} 1962 1963static void 1964e500_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, 1965 int reg_nr, const void *buffer) 1966{ 1967 struct gdbarch *regcache_arch = get_regcache_arch (regcache); 1968 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 1969 1970 gdb_assert (regcache_arch == gdbarch); 1971 1972 if (tdep->ppc_ev0_regnum <= reg_nr 1973 && reg_nr < tdep->ppc_ev0_regnum + ppc_num_gprs) 1974 e500_move_ev_register ((void (*) (struct regcache *, int, void *)) 1975 regcache_raw_write, 1976 regcache, reg_nr, (void *) buffer); 1977 else 1978 internal_error (__FILE__, __LINE__, 1979 "e500_pseudo_register_read: " 1980 "called on unexpected register '%s' (%d)", 1981 gdbarch_register_name (gdbarch, reg_nr), reg_nr); 1982} 1983 1984/* The E500 needs a custom reggroup function: it has anonymous raw 1985 registers, and default_register_reggroup_p assumes that anonymous 1986 registers are not members of any reggroup. */ 1987static int 1988e500_register_reggroup_p (struct gdbarch *gdbarch, 1989 int regnum, 1990 struct reggroup *group) 1991{ 1992 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 1993 1994 /* The save and restore register groups need to include the 1995 upper-half registers, even though they're anonymous. */ 1996 if ((group == save_reggroup 1997 || group == restore_reggroup) 1998 && (tdep->ppc_ev0_upper_regnum <= regnum 1999 && regnum < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)) 2000 return 1; 2001 2002 /* In all other regards, the default reggroup definition is fine. */ 2003 return default_register_reggroup_p (gdbarch, regnum, group); 2004} 2005 2006/* Convert a DBX STABS register number to a GDB register number. */ 2007static int 2008rs6000_stab_reg_to_regnum (int num) 2009{ 2010 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); 2011 2012 if (0 <= num && num <= 31) 2013 return tdep->ppc_gp0_regnum + num; 2014 else if (32 <= num && num <= 63) 2015 /* FIXME: jimb/2004-05-05: What should we do when the debug info 2016 specifies registers the architecture doesn't have? Our 2017 callers don't check the value we return. */ 2018 return tdep->ppc_fp0_regnum + (num - 32); 2019 else if (77 <= num && num <= 108) 2020 return tdep->ppc_vr0_regnum + (num - 77); 2021 else if (1200 <= num && num < 1200 + 32) 2022 return tdep->ppc_ev0_regnum + (num - 1200); 2023 else 2024 switch (num) 2025 { 2026 case 64: 2027 return tdep->ppc_mq_regnum; 2028 case 65: 2029 return tdep->ppc_lr_regnum; 2030 case 66: 2031 return tdep->ppc_ctr_regnum; 2032 case 76: 2033 return tdep->ppc_xer_regnum; 2034 case 109: 2035 return tdep->ppc_vrsave_regnum; 2036 case 110: 2037 return tdep->ppc_vrsave_regnum - 1; /* vscr */ 2038 case 111: 2039 return tdep->ppc_acc_regnum; 2040 case 112: 2041 return tdep->ppc_spefscr_regnum; 2042 default: 2043 return num; 2044 } 2045} 2046 2047 2048/* Convert a Dwarf 2 register number to a GDB register number. */ 2049static int 2050rs6000_dwarf2_reg_to_regnum (int num) 2051{ 2052 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); 2053 2054 if (0 <= num && num <= 31) 2055 return tdep->ppc_gp0_regnum + num; 2056 else if (32 <= num && num <= 63) 2057 /* FIXME: jimb/2004-05-05: What should we do when the debug info 2058 specifies registers the architecture doesn't have? Our 2059 callers don't check the value we return. */ 2060 return tdep->ppc_fp0_regnum + (num - 32); 2061 else if (1124 <= num && num < 1124 + 32) 2062 return tdep->ppc_vr0_regnum + (num - 1124); 2063 else if (1200 <= num && num < 1200 + 32) 2064 return tdep->ppc_ev0_regnum + (num - 1200); 2065 else 2066 switch (num) 2067 { 2068 case 67: 2069 return tdep->ppc_vrsave_regnum - 1; /* vscr */ 2070 case 99: 2071 return tdep->ppc_acc_regnum; 2072 case 100: 2073 return tdep->ppc_mq_regnum; 2074 case 101: 2075 return tdep->ppc_xer_regnum; 2076 case 108: 2077 return tdep->ppc_lr_regnum; 2078 case 109: 2079 return tdep->ppc_ctr_regnum; 2080 case 356: 2081 return tdep->ppc_vrsave_regnum; 2082 case 612: 2083 return tdep->ppc_spefscr_regnum; 2084 default: 2085 return num; 2086 } 2087} 2088 2089 2090static void 2091rs6000_store_return_value (struct type *type, 2092 struct regcache *regcache, 2093 const void *valbuf) 2094{ 2095 struct gdbarch *gdbarch = get_regcache_arch (regcache); 2096 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2097 int regnum = -1; 2098 2099 /* The calling convention this function implements assumes the 2100 processor has floating-point registers. We shouldn't be using it 2101 on PPC variants that lack them. */ 2102 gdb_assert (ppc_floating_point_unit_p (gdbarch)); 2103 2104 if (TYPE_CODE (type) == TYPE_CODE_FLT) 2105 /* Floating point values are returned starting from FPR1 and up. 2106 Say a double_double_double type could be returned in 2107 FPR1/FPR2/FPR3 triple. */ 2108 regnum = tdep->ppc_fp0_regnum + 1; 2109 else if (TYPE_CODE (type) == TYPE_CODE_ARRAY) 2110 { 2111 if (TYPE_LENGTH (type) == 16 2112 && TYPE_VECTOR (type)) 2113 regnum = tdep->ppc_vr0_regnum + 2; 2114 else 2115 internal_error (__FILE__, __LINE__, 2116 "rs6000_store_return_value: " 2117 "unexpected array return type"); 2118 } 2119 else 2120 /* Everything else is returned in GPR3 and up. */ 2121 regnum = tdep->ppc_gp0_regnum + 3; 2122 2123 { 2124 size_t bytes_written = 0; 2125 2126 while (bytes_written < TYPE_LENGTH (type)) 2127 { 2128 /* How much of this value can we write to this register? */ 2129 size_t bytes_to_write = min (TYPE_LENGTH (type) - bytes_written, 2130 register_size (gdbarch, regnum)); 2131 regcache_cooked_write_part (regcache, regnum, 2132 0, bytes_to_write, 2133 (char *) valbuf + bytes_written); 2134 regnum++; 2135 bytes_written += bytes_to_write; 2136 } 2137 } 2138} 2139 2140 2141/* Extract from an array REGBUF containing the (raw) register state 2142 the address in which a function should return its structure value, 2143 as a CORE_ADDR (or an expression that can be used as one). */ 2144 2145static CORE_ADDR 2146rs6000_extract_struct_value_address (struct regcache *regcache) 2147{ 2148 /* FIXME: cagney/2002-09-26: PR gdb/724: When making an inferior 2149 function call GDB knows the address of the struct return value 2150 and hence, should not need to call this function. Unfortunately, 2151 the current call_function_by_hand() code only saves the most 2152 recent struct address leading to occasional calls. The code 2153 should instead maintain a stack of such addresses (in the dummy 2154 frame object). */ 2155 /* NOTE: cagney/2002-09-26: Return 0 which indicates that we've 2156 really got no idea where the return value is being stored. While 2157 r3, on function entry, contained the address it will have since 2158 been reused (scratch) and hence wouldn't be valid */ 2159 return 0; 2160} 2161 2162/* Hook called when a new child process is started. */ 2163 2164void 2165rs6000_create_inferior (int pid) 2166{ 2167 if (rs6000_set_host_arch_hook) 2168 rs6000_set_host_arch_hook (pid); 2169} 2170 2171/* Support for CONVERT_FROM_FUNC_PTR_ADDR (ARCH, ADDR, TARG). 2172 2173 Usually a function pointer's representation is simply the address 2174 of the function. On the RS/6000 however, a function pointer is 2175 represented by a pointer to a TOC entry. This TOC entry contains 2176 three words, the first word is the address of the function, the 2177 second word is the TOC pointer (r2), and the third word is the 2178 static chain value. Throughout GDB it is currently assumed that a 2179 function pointer contains the address of the function, which is not 2180 easy to fix. In addition, the conversion of a function address to 2181 a function pointer would require allocation of a TOC entry in the 2182 inferior's memory space, with all its drawbacks. To be able to 2183 call C++ virtual methods in the inferior (which are called via 2184 function pointers), find_function_addr uses this function to get the 2185 function address from a function pointer. */ 2186 2187/* Return real function address if ADDR (a function pointer) is in the data 2188 space and is therefore a special function pointer. */ 2189 2190static CORE_ADDR 2191rs6000_convert_from_func_ptr_addr (struct gdbarch *gdbarch, 2192 CORE_ADDR addr, 2193 struct target_ops *targ) 2194{ 2195 struct obj_section *s; 2196 2197 s = find_pc_section (addr); 2198 if (s && s->the_bfd_section->flags & SEC_CODE) 2199 return addr; 2200 2201 /* ADDR is in the data space, so it's a special function pointer. */ 2202 return read_memory_addr (addr, gdbarch_tdep (current_gdbarch)->wordsize); 2203} 2204 2205 2206/* Handling the various POWER/PowerPC variants. */ 2207 2208 2209/* The arrays here called registers_MUMBLE hold information about available 2210 registers. 2211 2212 For each family of PPC variants, I've tried to isolate out the 2213 common registers and put them up front, so that as long as you get 2214 the general family right, GDB will correctly identify the registers 2215 common to that family. The common register sets are: 2216 2217 For the 60x family: hid0 hid1 iabr dabr pir 2218 2219 For the 505 and 860 family: eie eid nri 2220 2221 For the 403 and 403GC: icdbdr esr dear evpr cdbcr tsr tcr pit tbhi 2222 tblo srr2 srr3 dbsr dbcr iac1 iac2 dac1 dac2 dccr iccr pbl1 2223 pbu1 pbl2 pbu2 2224 2225 Most of these register groups aren't anything formal. I arrived at 2226 them by looking at the registers that occurred in more than one 2227 processor. 2228 2229 Note: kevinb/2002-04-30: Support for the fpscr register was added 2230 during April, 2002. Slot 70 is being used for PowerPC and slot 71 2231 for Power. For PowerPC, slot 70 was unused and was already in the 2232 PPC_UISA_SPRS which is ideally where fpscr should go. For Power, 2233 slot 70 was being used for "mq", so the next available slot (71) 2234 was chosen. It would have been nice to be able to make the 2235 register numbers the same across processor cores, but this wasn't 2236 possible without either 1) renumbering some registers for some 2237 processors or 2) assigning fpscr to a really high slot that's 2238 larger than any current register number. Doing (1) is bad because 2239 existing stubs would break. Doing (2) is undesirable because it 2240 would introduce a really large gap between fpscr and the rest of 2241 the registers for most processors. */ 2242 2243/* Convenience macros for populating register arrays. */ 2244 2245/* Within another macro, convert S to a string. */ 2246 2247#define STR(s) #s 2248 2249/* Return a struct reg defining register NAME that's 32 bits on 32-bit systems 2250 and 64 bits on 64-bit systems. */ 2251#define R(name) { STR(name), 4, 8, 0, 0, -1 } 2252 2253/* Return a struct reg defining register NAME that's 32 bits on all 2254 systems. */ 2255#define R4(name) { STR(name), 4, 4, 0, 0, -1 } 2256 2257/* Return a struct reg defining register NAME that's 64 bits on all 2258 systems. */ 2259#define R8(name) { STR(name), 8, 8, 0, 0, -1 } 2260 2261/* Return a struct reg defining register NAME that's 128 bits on all 2262 systems. */ 2263#define R16(name) { STR(name), 16, 16, 0, 0, -1 } 2264 2265/* Return a struct reg defining floating-point register NAME. */ 2266#define F(name) { STR(name), 8, 8, 1, 0, -1 } 2267 2268/* Return a struct reg defining a pseudo register NAME that is 64 bits 2269 long on all systems. */ 2270#define P8(name) { STR(name), 8, 8, 0, 1, -1 } 2271 2272/* Return a struct reg defining register NAME that's 32 bits on 32-bit 2273 systems and that doesn't exist on 64-bit systems. */ 2274#define R32(name) { STR(name), 4, 0, 0, 0, -1 } 2275 2276/* Return a struct reg defining register NAME that's 64 bits on 64-bit 2277 systems and that doesn't exist on 32-bit systems. */ 2278#define R64(name) { STR(name), 0, 8, 0, 0, -1 } 2279 2280/* Return a struct reg placeholder for a register that doesn't exist. */ 2281#define R0 { 0, 0, 0, 0, 0, -1 } 2282 2283/* Return a struct reg defining an anonymous raw register that's 32 2284 bits on all systems. */ 2285#define A4 { 0, 4, 4, 0, 0, -1 } 2286 2287/* Return a struct reg defining an SPR named NAME that is 32 bits on 2288 32-bit systems and 64 bits on 64-bit systems. */ 2289#define S(name) { STR(name), 4, 8, 0, 0, ppc_spr_ ## name } 2290 2291/* Return a struct reg defining an SPR named NAME that is 32 bits on 2292 all systems. */ 2293#define S4(name) { STR(name), 4, 4, 0, 0, ppc_spr_ ## name } 2294 2295/* Return a struct reg defining an SPR named NAME that is 32 bits on 2296 all systems, and whose SPR number is NUMBER. */ 2297#define SN4(name, number) { STR(name), 4, 4, 0, 0, (number) } 2298 2299/* Return a struct reg defining an SPR named NAME that's 64 bits on 2300 64-bit systems and that doesn't exist on 32-bit systems. */ 2301#define S64(name) { STR(name), 0, 8, 0, 0, ppc_spr_ ## name } 2302 2303/* UISA registers common across all architectures, including POWER. */ 2304 2305#define COMMON_UISA_REGS \ 2306 /* 0 */ R(r0), R(r1), R(r2), R(r3), R(r4), R(r5), R(r6), R(r7), \ 2307 /* 8 */ R(r8), R(r9), R(r10),R(r11),R(r12),R(r13),R(r14),R(r15), \ 2308 /* 16 */ R(r16),R(r17),R(r18),R(r19),R(r20),R(r21),R(r22),R(r23), \ 2309 /* 24 */ R(r24),R(r25),R(r26),R(r27),R(r28),R(r29),R(r30),R(r31), \ 2310 /* 32 */ F(f0), F(f1), F(f2), F(f3), F(f4), F(f5), F(f6), F(f7), \ 2311 /* 40 */ F(f8), F(f9), F(f10),F(f11),F(f12),F(f13),F(f14),F(f15), \ 2312 /* 48 */ F(f16),F(f17),F(f18),F(f19),F(f20),F(f21),F(f22),F(f23), \ 2313 /* 56 */ F(f24),F(f25),F(f26),F(f27),F(f28),F(f29),F(f30),F(f31), \ 2314 /* 64 */ R(pc), R(ps) 2315 2316/* UISA-level SPRs for PowerPC. */ 2317#define PPC_UISA_SPRS \ 2318 /* 66 */ R4(cr), S(lr), S(ctr), S4(xer), R4(fpscr) 2319 2320/* UISA-level SPRs for PowerPC without floating point support. */ 2321#define PPC_UISA_NOFP_SPRS \ 2322 /* 66 */ R4(cr), S(lr), S(ctr), S4(xer), R0 2323 2324/* Segment registers, for PowerPC. */ 2325#define PPC_SEGMENT_REGS \ 2326 /* 71 */ R32(sr0), R32(sr1), R32(sr2), R32(sr3), \ 2327 /* 75 */ R32(sr4), R32(sr5), R32(sr6), R32(sr7), \ 2328 /* 79 */ R32(sr8), R32(sr9), R32(sr10), R32(sr11), \ 2329 /* 83 */ R32(sr12), R32(sr13), R32(sr14), R32(sr15) 2330 2331/* OEA SPRs for PowerPC. */ 2332#define PPC_OEA_SPRS \ 2333 /* 87 */ S4(pvr), \ 2334 /* 88 */ S(ibat0u), S(ibat0l), S(ibat1u), S(ibat1l), \ 2335 /* 92 */ S(ibat2u), S(ibat2l), S(ibat3u), S(ibat3l), \ 2336 /* 96 */ S(dbat0u), S(dbat0l), S(dbat1u), S(dbat1l), \ 2337 /* 100 */ S(dbat2u), S(dbat2l), S(dbat3u), S(dbat3l), \ 2338 /* 104 */ S(sdr1), S64(asr), S(dar), S4(dsisr), \ 2339 /* 108 */ S(sprg0), S(sprg1), S(sprg2), S(sprg3), \ 2340 /* 112 */ S(srr0), S(srr1), S(tbl), S(tbu), \ 2341 /* 116 */ S4(dec), S(dabr), S4(ear) 2342 2343/* AltiVec registers. */ 2344#define PPC_ALTIVEC_REGS \ 2345 /*119*/R16(vr0), R16(vr1), R16(vr2), R16(vr3), R16(vr4), R16(vr5), R16(vr6), R16(vr7), \ 2346 /*127*/R16(vr8), R16(vr9), R16(vr10),R16(vr11),R16(vr12),R16(vr13),R16(vr14),R16(vr15), \ 2347 /*135*/R16(vr16),R16(vr17),R16(vr18),R16(vr19),R16(vr20),R16(vr21),R16(vr22),R16(vr23), \ 2348 /*143*/R16(vr24),R16(vr25),R16(vr26),R16(vr27),R16(vr28),R16(vr29),R16(vr30),R16(vr31), \ 2349 /*151*/R4(vscr), R4(vrsave) 2350 2351 2352/* On machines supporting the SPE APU, the general-purpose registers 2353 are 64 bits long. There are SIMD vector instructions to treat them 2354 as pairs of floats, but the rest of the instruction set treats them 2355 as 32-bit registers, and only operates on their lower halves. 2356 2357 In the GDB regcache, we treat their high and low halves as separate 2358 registers. The low halves we present as the general-purpose 2359 registers, and then we have pseudo-registers that stitch together 2360 the upper and lower halves and present them as pseudo-registers. */ 2361 2362/* SPE GPR lower halves --- raw registers. */ 2363#define PPC_SPE_GP_REGS \ 2364 /* 0 */ R4(r0), R4(r1), R4(r2), R4(r3), R4(r4), R4(r5), R4(r6), R4(r7), \ 2365 /* 8 */ R4(r8), R4(r9), R4(r10),R4(r11),R4(r12),R4(r13),R4(r14),R4(r15), \ 2366 /* 16 */ R4(r16),R4(r17),R4(r18),R4(r19),R4(r20),R4(r21),R4(r22),R4(r23), \ 2367 /* 24 */ R4(r24),R4(r25),R4(r26),R4(r27),R4(r28),R4(r29),R4(r30),R4(r31) 2368 2369/* SPE GPR upper halves --- anonymous raw registers. */ 2370#define PPC_SPE_UPPER_GP_REGS \ 2371 /* 0 */ A4, A4, A4, A4, A4, A4, A4, A4, \ 2372 /* 8 */ A4, A4, A4, A4, A4, A4, A4, A4, \ 2373 /* 16 */ A4, A4, A4, A4, A4, A4, A4, A4, \ 2374 /* 24 */ A4, A4, A4, A4, A4, A4, A4, A4 2375 2376/* SPE GPR vector registers --- pseudo registers based on underlying 2377 gprs and the anonymous upper half raw registers. */ 2378#define PPC_EV_PSEUDO_REGS \ 2379/* 0*/P8(ev0), P8(ev1), P8(ev2), P8(ev3), P8(ev4), P8(ev5), P8(ev6), P8(ev7), \ 2380/* 8*/P8(ev8), P8(ev9), P8(ev10),P8(ev11),P8(ev12),P8(ev13),P8(ev14),P8(ev15),\ 2381/*16*/P8(ev16),P8(ev17),P8(ev18),P8(ev19),P8(ev20),P8(ev21),P8(ev22),P8(ev23),\ 2382/*24*/P8(ev24),P8(ev25),P8(ev26),P8(ev27),P8(ev28),P8(ev29),P8(ev30),P8(ev31) 2383 2384/* IBM POWER (pre-PowerPC) architecture, user-level view. We only cover 2385 user-level SPR's. */ 2386static const struct reg registers_power[] = 2387{ 2388 COMMON_UISA_REGS, 2389 /* 66 */ R4(cnd), S(lr), S(cnt), S4(xer), S4(mq), 2390 /* 71 */ R4(fpscr) 2391}; 2392 2393/* PowerPC UISA - a PPC processor as viewed by user-level code. A UISA-only 2394 view of the PowerPC. */ 2395static const struct reg registers_powerpc[] = 2396{ 2397 COMMON_UISA_REGS, 2398 PPC_UISA_SPRS, 2399 PPC_ALTIVEC_REGS 2400}; 2401 2402/* IBM PowerPC 403. 2403 2404 Some notes about the "tcr" special-purpose register: 2405 - On the 403 and 403GC, SPR 986 is named "tcr", and it controls the 2406 403's programmable interval timer, fixed interval timer, and 2407 watchdog timer. 2408 - On the 602, SPR 984 is named "tcr", and it controls the 602's 2409 watchdog timer, and nothing else. 2410 2411 Some of the fields are similar between the two, but they're not 2412 compatible with each other. Since the two variants have different 2413 registers, with different numbers, but the same name, we can't 2414 splice the register name to get the SPR number. */ 2415static const struct reg registers_403[] = 2416{ 2417 COMMON_UISA_REGS, 2418 PPC_UISA_SPRS, 2419 PPC_SEGMENT_REGS, 2420 PPC_OEA_SPRS, 2421 /* 119 */ S(icdbdr), S(esr), S(dear), S(evpr), 2422 /* 123 */ S(cdbcr), S(tsr), SN4(tcr, ppc_spr_403_tcr), S(pit), 2423 /* 127 */ S(tbhi), S(tblo), S(srr2), S(srr3), 2424 /* 131 */ S(dbsr), S(dbcr), S(iac1), S(iac2), 2425 /* 135 */ S(dac1), S(dac2), S(dccr), S(iccr), 2426 /* 139 */ S(pbl1), S(pbu1), S(pbl2), S(pbu2) 2427}; 2428 2429/* IBM PowerPC 403GC. 2430 See the comments about 'tcr' for the 403, above. */ 2431static const struct reg registers_403GC[] = 2432{ 2433 COMMON_UISA_REGS, 2434 PPC_UISA_SPRS, 2435 PPC_SEGMENT_REGS, 2436 PPC_OEA_SPRS, 2437 /* 119 */ S(icdbdr), S(esr), S(dear), S(evpr), 2438 /* 123 */ S(cdbcr), S(tsr), SN4(tcr, ppc_spr_403_tcr), S(pit), 2439 /* 127 */ S(tbhi), S(tblo), S(srr2), S(srr3), 2440 /* 131 */ S(dbsr), S(dbcr), S(iac1), S(iac2), 2441 /* 135 */ S(dac1), S(dac2), S(dccr), S(iccr), 2442 /* 139 */ S(pbl1), S(pbu1), S(pbl2), S(pbu2), 2443 /* 143 */ S(zpr), S(pid), S(sgr), S(dcwr), 2444 /* 147 */ S(tbhu), S(tblu) 2445}; 2446 2447/* Motorola PowerPC 505. */ 2448static const struct reg registers_505[] = 2449{ 2450 COMMON_UISA_REGS, 2451 PPC_UISA_SPRS, 2452 PPC_SEGMENT_REGS, 2453 PPC_OEA_SPRS, 2454 /* 119 */ S(eie), S(eid), S(nri) 2455}; 2456 2457/* Motorola PowerPC 860 or 850. */ 2458static const struct reg registers_860[] = 2459{ 2460 COMMON_UISA_REGS, 2461 PPC_UISA_SPRS, 2462 PPC_SEGMENT_REGS, 2463 PPC_OEA_SPRS, 2464 /* 119 */ S(eie), S(eid), S(nri), S(cmpa), 2465 /* 123 */ S(cmpb), S(cmpc), S(cmpd), S(icr), 2466 /* 127 */ S(der), S(counta), S(countb), S(cmpe), 2467 /* 131 */ S(cmpf), S(cmpg), S(cmph), S(lctrl1), 2468 /* 135 */ S(lctrl2), S(ictrl), S(bar), S(ic_cst), 2469 /* 139 */ S(ic_adr), S(ic_dat), S(dc_cst), S(dc_adr), 2470 /* 143 */ S(dc_dat), S(dpdr), S(dpir), S(immr), 2471 /* 147 */ S(mi_ctr), S(mi_ap), S(mi_epn), S(mi_twc), 2472 /* 151 */ S(mi_rpn), S(md_ctr), S(m_casid), S(md_ap), 2473 /* 155 */ S(md_epn), S(m_twb), S(md_twc), S(md_rpn), 2474 /* 159 */ S(m_tw), S(mi_dbcam), S(mi_dbram0), S(mi_dbram1), 2475 /* 163 */ S(md_dbcam), S(md_dbram0), S(md_dbram1) 2476}; 2477 2478/* Motorola PowerPC 601. Note that the 601 has different register numbers 2479 for reading and writing RTCU and RTCL. However, how one reads and writes a 2480 register is the stub's problem. */ 2481static const struct reg registers_601[] = 2482{ 2483 COMMON_UISA_REGS, 2484 PPC_UISA_SPRS, 2485 PPC_SEGMENT_REGS, 2486 PPC_OEA_SPRS, 2487 /* 119 */ S(hid0), S(hid1), S(iabr), S(dabr), 2488 /* 123 */ S(pir), S(mq), S(rtcu), S(rtcl) 2489}; 2490 2491/* Motorola PowerPC 602. 2492 See the notes under the 403 about 'tcr'. */ 2493static const struct reg registers_602[] = 2494{ 2495 COMMON_UISA_REGS, 2496 PPC_UISA_SPRS, 2497 PPC_SEGMENT_REGS, 2498 PPC_OEA_SPRS, 2499 /* 119 */ S(hid0), S(hid1), S(iabr), R0, 2500 /* 123 */ R0, SN4(tcr, ppc_spr_602_tcr), S(ibr), S(esasrr), 2501 /* 127 */ S(sebr), S(ser), S(sp), S(lt) 2502}; 2503 2504/* Motorola/IBM PowerPC 603 or 603e. */ 2505static const struct reg registers_603[] = 2506{ 2507 COMMON_UISA_REGS, 2508 PPC_UISA_SPRS, 2509 PPC_SEGMENT_REGS, 2510 PPC_OEA_SPRS, 2511 /* 119 */ S(hid0), S(hid1), S(iabr), R0, 2512 /* 123 */ R0, S(dmiss), S(dcmp), S(hash1), 2513 /* 127 */ S(hash2), S(imiss), S(icmp), S(rpa) 2514}; 2515 2516/* Motorola PowerPC 604 or 604e. */ 2517static const struct reg registers_604[] = 2518{ 2519 COMMON_UISA_REGS, 2520 PPC_UISA_SPRS, 2521 PPC_SEGMENT_REGS, 2522 PPC_OEA_SPRS, 2523 /* 119 */ S(hid0), S(hid1), S(iabr), S(dabr), 2524 /* 123 */ S(pir), S(mmcr0), S(pmc1), S(pmc2), 2525 /* 127 */ S(sia), S(sda) 2526}; 2527 2528/* Motorola/IBM PowerPC 750 or 740. */ 2529static const struct reg registers_750[] = 2530{ 2531 COMMON_UISA_REGS, 2532 PPC_UISA_SPRS, 2533 PPC_SEGMENT_REGS, 2534 PPC_OEA_SPRS, 2535 /* 119 */ S(hid0), S(hid1), S(iabr), S(dabr), 2536 /* 123 */ R0, S(ummcr0), S(upmc1), S(upmc2), 2537 /* 127 */ S(usia), S(ummcr1), S(upmc3), S(upmc4), 2538 /* 131 */ S(mmcr0), S(pmc1), S(pmc2), S(sia), 2539 /* 135 */ S(mmcr1), S(pmc3), S(pmc4), S(l2cr), 2540 /* 139 */ S(ictc), S(thrm1), S(thrm2), S(thrm3) 2541}; 2542 2543 2544/* Motorola PowerPC 7400. */ 2545static const struct reg registers_7400[] = 2546{ 2547 /* gpr0-gpr31, fpr0-fpr31 */ 2548 COMMON_UISA_REGS, 2549 /* cr, lr, ctr, xer, fpscr */ 2550 PPC_UISA_SPRS, 2551 /* sr0-sr15 */ 2552 PPC_SEGMENT_REGS, 2553 PPC_OEA_SPRS, 2554 /* vr0-vr31, vrsave, vscr */ 2555 PPC_ALTIVEC_REGS 2556 /* FIXME? Add more registers? */ 2557}; 2558 2559/* Motorola e500. */ 2560static const struct reg registers_e500[] = 2561{ 2562 /* 0 .. 31 */ PPC_SPE_GP_REGS, 2563 /* 32 .. 63 */ PPC_SPE_UPPER_GP_REGS, 2564 /* 64 .. 65 */ R(pc), R(ps), 2565 /* 66 .. 70 */ PPC_UISA_NOFP_SPRS, 2566 /* 71 .. 72 */ R8(acc), S4(spefscr), 2567 /* NOTE: Add new registers here the end of the raw register 2568 list and just before the first pseudo register. */ 2569 /* 73 .. 104 */ PPC_EV_PSEUDO_REGS 2570}; 2571 2572/* Information about a particular processor variant. */ 2573 2574struct variant 2575 { 2576 /* Name of this variant. */ 2577 char *name; 2578 2579 /* English description of the variant. */ 2580 char *description; 2581 2582 /* bfd_arch_info.arch corresponding to variant. */ 2583 enum bfd_architecture arch; 2584 2585 /* bfd_arch_info.mach corresponding to variant. */ 2586 unsigned long mach; 2587 2588 /* Number of real registers. */ 2589 int nregs; 2590 2591 /* Number of pseudo registers. */ 2592 int npregs; 2593 2594 /* Number of total registers (the sum of nregs and npregs). */ 2595 int num_tot_regs; 2596 2597 /* Table of register names; registers[R] is the name of the register 2598 number R. */ 2599 const struct reg *regs; 2600 }; 2601 2602#define tot_num_registers(list) (sizeof (list) / sizeof((list)[0])) 2603 2604static int 2605num_registers (const struct reg *reg_list, int num_tot_regs) 2606{ 2607 int i; 2608 int nregs = 0; 2609 2610 for (i = 0; i < num_tot_regs; i++) 2611 if (!reg_list[i].pseudo) 2612 nregs++; 2613 2614 return nregs; 2615} 2616 2617static int 2618num_pseudo_registers (const struct reg *reg_list, int num_tot_regs) 2619{ 2620 int i; 2621 int npregs = 0; 2622 2623 for (i = 0; i < num_tot_regs; i++) 2624 if (reg_list[i].pseudo) 2625 npregs ++; 2626 2627 return npregs; 2628} 2629 2630/* Information in this table comes from the following web sites: 2631 IBM: http://www.chips.ibm.com:80/products/embedded/ 2632 Motorola: http://www.mot.com/SPS/PowerPC/ 2633 2634 I'm sure I've got some of the variant descriptions not quite right. 2635 Please report any inaccuracies you find to GDB's maintainer. 2636 2637 If you add entries to this table, please be sure to allow the new 2638 value as an argument to the --with-cpu flag, in configure.in. */ 2639 2640static struct variant variants[] = 2641{ 2642 2643 {"powerpc", "PowerPC user-level", bfd_arch_powerpc, 2644 bfd_mach_ppc, -1, -1, tot_num_registers (registers_powerpc), 2645 registers_powerpc}, 2646 {"power", "POWER user-level", bfd_arch_rs6000, 2647 bfd_mach_rs6k, -1, -1, tot_num_registers (registers_power), 2648 registers_power}, 2649 {"403", "IBM PowerPC 403", bfd_arch_powerpc, 2650 bfd_mach_ppc_403, -1, -1, tot_num_registers (registers_403), 2651 registers_403}, 2652 {"601", "Motorola PowerPC 601", bfd_arch_powerpc, 2653 bfd_mach_ppc_601, -1, -1, tot_num_registers (registers_601), 2654 registers_601}, 2655 {"602", "Motorola PowerPC 602", bfd_arch_powerpc, 2656 bfd_mach_ppc_602, -1, -1, tot_num_registers (registers_602), 2657 registers_602}, 2658 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc, 2659 bfd_mach_ppc_603, -1, -1, tot_num_registers (registers_603), 2660 registers_603}, 2661 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc, 2662 604, -1, -1, tot_num_registers (registers_604), 2663 registers_604}, 2664 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc, 2665 bfd_mach_ppc_403gc, -1, -1, tot_num_registers (registers_403GC), 2666 registers_403GC}, 2667 {"505", "Motorola PowerPC 505", bfd_arch_powerpc, 2668 bfd_mach_ppc_505, -1, -1, tot_num_registers (registers_505), 2669 registers_505}, 2670 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc, 2671 bfd_mach_ppc_860, -1, -1, tot_num_registers (registers_860), 2672 registers_860}, 2673 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc, 2674 bfd_mach_ppc_750, -1, -1, tot_num_registers (registers_750), 2675 registers_750}, 2676 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc, 2677 bfd_mach_ppc_7400, -1, -1, tot_num_registers (registers_7400), 2678 registers_7400}, 2679 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc, 2680 bfd_mach_ppc_e500, -1, -1, tot_num_registers (registers_e500), 2681 registers_e500}, 2682 2683 /* 64-bit */ 2684 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc, 2685 bfd_mach_ppc64, -1, -1, tot_num_registers (registers_powerpc), 2686 registers_powerpc}, 2687 {"620", "Motorola PowerPC 620", bfd_arch_powerpc, 2688 bfd_mach_ppc_620, -1, -1, tot_num_registers (registers_powerpc), 2689 registers_powerpc}, 2690 {"630", "Motorola PowerPC 630", bfd_arch_powerpc, 2691 bfd_mach_ppc_630, -1, -1, tot_num_registers (registers_powerpc), 2692 registers_powerpc}, 2693 {"a35", "PowerPC A35", bfd_arch_powerpc, 2694 bfd_mach_ppc_a35, -1, -1, tot_num_registers (registers_powerpc), 2695 registers_powerpc}, 2696 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc, 2697 bfd_mach_ppc_rs64ii, -1, -1, tot_num_registers (registers_powerpc), 2698 registers_powerpc}, 2699 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc, 2700 bfd_mach_ppc_rs64iii, -1, -1, tot_num_registers (registers_powerpc), 2701 registers_powerpc}, 2702 2703 /* FIXME: I haven't checked the register sets of the following. */ 2704 {"rs1", "IBM POWER RS1", bfd_arch_rs6000, 2705 bfd_mach_rs6k_rs1, -1, -1, tot_num_registers (registers_power), 2706 registers_power}, 2707 {"rsc", "IBM POWER RSC", bfd_arch_rs6000, 2708 bfd_mach_rs6k_rsc, -1, -1, tot_num_registers (registers_power), 2709 registers_power}, 2710 {"rs2", "IBM POWER RS2", bfd_arch_rs6000, 2711 bfd_mach_rs6k_rs2, -1, -1, tot_num_registers (registers_power), 2712 registers_power}, 2713 2714 {0, 0, 0, 0, 0, 0, 0, 0} 2715}; 2716 2717/* Initialize the number of registers and pseudo registers in each variant. */ 2718 2719static void 2720init_variants (void) 2721{ 2722 struct variant *v; 2723 2724 for (v = variants; v->name; v++) 2725 { 2726 if (v->nregs == -1) 2727 v->nregs = num_registers (v->regs, v->num_tot_regs); 2728 if (v->npregs == -1) 2729 v->npregs = num_pseudo_registers (v->regs, v->num_tot_regs); 2730 } 2731} 2732 2733/* Return the variant corresponding to architecture ARCH and machine number 2734 MACH. If no such variant exists, return null. */ 2735 2736static const struct variant * 2737find_variant_by_arch (enum bfd_architecture arch, unsigned long mach) 2738{ 2739 const struct variant *v; 2740 2741 for (v = variants; v->name; v++) 2742 if (arch == v->arch && mach == v->mach) 2743 return v; 2744 2745 return NULL; 2746} 2747 2748static int 2749gdb_print_insn_powerpc (bfd_vma memaddr, disassemble_info *info) 2750{ 2751 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) 2752 return print_insn_big_powerpc (memaddr, info); 2753 else 2754 return print_insn_little_powerpc (memaddr, info); 2755} 2756 2757static CORE_ADDR 2758rs6000_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) 2759{ 2760 return frame_unwind_register_unsigned (next_frame, PC_REGNUM); 2761} 2762 2763static struct frame_id 2764rs6000_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) 2765{ 2766 return frame_id_build (frame_unwind_register_unsigned (next_frame, 2767 SP_REGNUM), 2768 frame_pc_unwind (next_frame)); 2769} 2770 2771struct rs6000_frame_cache 2772{ 2773 CORE_ADDR base; 2774 CORE_ADDR initial_sp; 2775 struct trad_frame_saved_reg *saved_regs; 2776}; 2777 2778static struct rs6000_frame_cache * 2779rs6000_frame_cache (struct frame_info *next_frame, void **this_cache) 2780{ 2781 struct rs6000_frame_cache *cache; 2782 struct gdbarch *gdbarch = get_frame_arch (next_frame); 2783 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2784 struct rs6000_framedata fdata; 2785 int wordsize = tdep->wordsize; 2786 2787 if ((*this_cache) != NULL) 2788 return (*this_cache); 2789 cache = FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache); 2790 (*this_cache) = cache; 2791 cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); 2792 2793 skip_prologue (frame_func_unwind (next_frame), frame_pc_unwind (next_frame), 2794 &fdata); 2795 2796 /* If there were any saved registers, figure out parent's stack 2797 pointer. */ 2798 /* The following is true only if the frame doesn't have a call to 2799 alloca(), FIXME. */ 2800 2801 if (fdata.saved_fpr == 0 2802 && fdata.saved_gpr == 0 2803 && fdata.saved_vr == 0 2804 && fdata.saved_ev == 0 2805 && fdata.lr_offset == 0 2806 && fdata.cr_offset == 0 2807 && fdata.vr_offset == 0 2808 && fdata.ev_offset == 0) 2809 cache->base = frame_unwind_register_unsigned (next_frame, SP_REGNUM); 2810 else 2811 { 2812 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most 2813 address of the current frame. Things might be easier if the 2814 ->frame pointed to the outer-most address of the frame. In 2815 the mean time, the address of the prev frame is used as the 2816 base address of this frame. */ 2817 cache->base = frame_unwind_register_unsigned (next_frame, SP_REGNUM); 2818 if (!fdata.frameless) 2819 /* Frameless really means stackless. */ 2820 cache->base = read_memory_addr (cache->base, wordsize); 2821 } 2822 trad_frame_set_value (cache->saved_regs, SP_REGNUM, cache->base); 2823 2824 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr. 2825 All fpr's from saved_fpr to fp31 are saved. */ 2826 2827 if (fdata.saved_fpr >= 0) 2828 { 2829 int i; 2830 CORE_ADDR fpr_addr = cache->base + fdata.fpr_offset; 2831 2832 /* If skip_prologue says floating-point registers were saved, 2833 but the current architecture has no floating-point registers, 2834 then that's strange. But we have no indices to even record 2835 the addresses under, so we just ignore it. */ 2836 if (ppc_floating_point_unit_p (gdbarch)) 2837 for (i = fdata.saved_fpr; i < ppc_num_fprs; i++) 2838 { 2839 cache->saved_regs[tdep->ppc_fp0_regnum + i].addr = fpr_addr; 2840 fpr_addr += 8; 2841 } 2842 } 2843 2844 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr. 2845 All gpr's from saved_gpr to gpr31 are saved. */ 2846 2847 if (fdata.saved_gpr >= 0) 2848 { 2849 int i; 2850 CORE_ADDR gpr_addr = cache->base + fdata.gpr_offset; 2851 for (i = fdata.saved_gpr; i < ppc_num_gprs; i++) 2852 { 2853 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = gpr_addr; 2854 gpr_addr += wordsize; 2855 } 2856 } 2857 2858 /* if != -1, fdata.saved_vr is the smallest number of saved_vr. 2859 All vr's from saved_vr to vr31 are saved. */ 2860 if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) 2861 { 2862 if (fdata.saved_vr >= 0) 2863 { 2864 int i; 2865 CORE_ADDR vr_addr = cache->base + fdata.vr_offset; 2866 for (i = fdata.saved_vr; i < 32; i++) 2867 { 2868 cache->saved_regs[tdep->ppc_vr0_regnum + i].addr = vr_addr; 2869 vr_addr += register_size (gdbarch, tdep->ppc_vr0_regnum); 2870 } 2871 } 2872 } 2873 2874 /* if != -1, fdata.saved_ev is the smallest number of saved_ev. 2875 All vr's from saved_ev to ev31 are saved. ????? */ 2876 if (tdep->ppc_ev0_regnum != -1 && tdep->ppc_ev31_regnum != -1) 2877 { 2878 if (fdata.saved_ev >= 0) 2879 { 2880 int i; 2881 CORE_ADDR ev_addr = cache->base + fdata.ev_offset; 2882 for (i = fdata.saved_ev; i < ppc_num_gprs; i++) 2883 { 2884 cache->saved_regs[tdep->ppc_ev0_regnum + i].addr = ev_addr; 2885 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = ev_addr + 4; 2886 ev_addr += register_size (gdbarch, tdep->ppc_ev0_regnum); 2887 } 2888 } 2889 } 2890 2891 /* If != 0, fdata.cr_offset is the offset from the frame that 2892 holds the CR. */ 2893 if (fdata.cr_offset != 0) 2894 cache->saved_regs[tdep->ppc_cr_regnum].addr = cache->base + fdata.cr_offset; 2895 2896 /* If != 0, fdata.lr_offset is the offset from the frame that 2897 holds the LR. */ 2898 if (fdata.lr_offset != 0) 2899 cache->saved_regs[tdep->ppc_lr_regnum].addr = cache->base + fdata.lr_offset; 2900 /* The PC is found in the link register. */ 2901 cache->saved_regs[PC_REGNUM] = cache->saved_regs[tdep->ppc_lr_regnum]; 2902 2903 /* If != 0, fdata.vrsave_offset is the offset from the frame that 2904 holds the VRSAVE. */ 2905 if (fdata.vrsave_offset != 0) 2906 cache->saved_regs[tdep->ppc_vrsave_regnum].addr = cache->base + fdata.vrsave_offset; 2907 2908 if (fdata.alloca_reg < 0) 2909 /* If no alloca register used, then fi->frame is the value of the 2910 %sp for this frame, and it is good enough. */ 2911 cache->initial_sp = frame_unwind_register_unsigned (next_frame, SP_REGNUM); 2912 else 2913 cache->initial_sp = frame_unwind_register_unsigned (next_frame, 2914 fdata.alloca_reg); 2915 2916 return cache; 2917} 2918 2919static void 2920rs6000_frame_this_id (struct frame_info *next_frame, void **this_cache, 2921 struct frame_id *this_id) 2922{ 2923 struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame, 2924 this_cache); 2925 (*this_id) = frame_id_build (info->base, frame_func_unwind (next_frame)); 2926} 2927 2928static void 2929rs6000_frame_prev_register (struct frame_info *next_frame, 2930 void **this_cache, 2931 int regnum, int *optimizedp, 2932 enum lval_type *lvalp, CORE_ADDR *addrp, 2933 int *realnump, void *valuep) 2934{ 2935 struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame, 2936 this_cache); 2937 trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, 2938 optimizedp, lvalp, addrp, realnump, valuep); 2939} 2940 2941static const struct frame_unwind rs6000_frame_unwind = 2942{ 2943 NORMAL_FRAME, 2944 rs6000_frame_this_id, 2945 rs6000_frame_prev_register 2946}; 2947 2948static const struct frame_unwind * 2949rs6000_frame_sniffer (struct frame_info *next_frame) 2950{ 2951 return &rs6000_frame_unwind; 2952} 2953 2954 2955 2956static CORE_ADDR 2957rs6000_frame_base_address (struct frame_info *next_frame, 2958 void **this_cache) 2959{ 2960 struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame, 2961 this_cache); 2962 return info->initial_sp; 2963} 2964 2965static const struct frame_base rs6000_frame_base = { 2966 &rs6000_frame_unwind, 2967 rs6000_frame_base_address, 2968 rs6000_frame_base_address, 2969 rs6000_frame_base_address 2970}; 2971 2972static const struct frame_base * 2973rs6000_frame_base_sniffer (struct frame_info *next_frame) 2974{ 2975 return &rs6000_frame_base; 2976} 2977 2978/* Initialize the current architecture based on INFO. If possible, re-use an 2979 architecture from ARCHES, which is a list of architectures already created 2980 during this debugging session. 2981 2982 Called e.g. at program startup, when reading a core file, and when reading 2983 a binary file. */ 2984 2985static struct gdbarch * 2986rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) 2987{ 2988 struct gdbarch *gdbarch; 2989 struct gdbarch_tdep *tdep; 2990 int wordsize, from_xcoff_exec, from_elf_exec, i, off; 2991 struct reg *regs; 2992 const struct variant *v; 2993 enum bfd_architecture arch; 2994 unsigned long mach; 2995 bfd abfd; 2996 int sysv_abi; 2997 asection *sect; 2998 2999 from_xcoff_exec = info.abfd && info.abfd->format == bfd_object && 3000 bfd_get_flavour (info.abfd) == bfd_target_xcoff_flavour; 3001 3002 from_elf_exec = info.abfd && info.abfd->format == bfd_object && 3003 bfd_get_flavour (info.abfd) == bfd_target_elf_flavour; 3004 3005 sysv_abi = info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour; 3006 3007 /* Check word size. If INFO is from a binary file, infer it from 3008 that, else choose a likely default. */ 3009 if (from_xcoff_exec) 3010 { 3011 if (bfd_xcoff_is_xcoff64 (info.abfd)) 3012 wordsize = 8; 3013 else 3014 wordsize = 4; 3015 } 3016 else if (from_elf_exec) 3017 { 3018 if (elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) 3019 wordsize = 8; 3020 else 3021 wordsize = 4; 3022 } 3023 else 3024 { 3025 if (info.bfd_arch_info != NULL && info.bfd_arch_info->bits_per_word != 0) 3026 wordsize = info.bfd_arch_info->bits_per_word / 3027 info.bfd_arch_info->bits_per_byte; 3028 else 3029 wordsize = 4; 3030 } 3031 3032 /* Find a candidate among extant architectures. */ 3033 for (arches = gdbarch_list_lookup_by_info (arches, &info); 3034 arches != NULL; 3035 arches = gdbarch_list_lookup_by_info (arches->next, &info)) 3036 { 3037 /* Word size in the various PowerPC bfd_arch_info structs isn't 3038 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform 3039 separate word size check. */ 3040 tdep = gdbarch_tdep (arches->gdbarch); 3041 if (tdep && tdep->wordsize == wordsize) 3042 return arches->gdbarch; 3043 } 3044 3045 /* None found, create a new architecture from INFO, whose bfd_arch_info 3046 validity depends on the source: 3047 - executable useless 3048 - rs6000_host_arch() good 3049 - core file good 3050 - "set arch" trust blindly 3051 - GDB startup useless but harmless */ 3052 3053 if (!from_xcoff_exec) 3054 { 3055 arch = info.bfd_arch_info->arch; 3056 mach = info.bfd_arch_info->mach; 3057 } 3058 else 3059 { 3060 arch = bfd_arch_powerpc; 3061 bfd_default_set_arch_mach (&abfd, arch, 0); 3062 info.bfd_arch_info = bfd_get_arch_info (&abfd); 3063 mach = info.bfd_arch_info->mach; 3064 } 3065 tdep = xmalloc (sizeof (struct gdbarch_tdep)); 3066 tdep->wordsize = wordsize; 3067 3068 /* For e500 executables, the apuinfo section is of help here. Such 3069 section contains the identifier and revision number of each 3070 Application-specific Processing Unit that is present on the 3071 chip. The content of the section is determined by the assembler 3072 which looks at each instruction and determines which unit (and 3073 which version of it) can execute it. In our case we just look for 3074 the existance of the section. */ 3075 3076 if (info.abfd) 3077 { 3078 sect = bfd_get_section_by_name (info.abfd, ".PPC.EMB.apuinfo"); 3079 if (sect) 3080 { 3081 arch = info.bfd_arch_info->arch; 3082 mach = bfd_mach_ppc_e500; 3083 bfd_default_set_arch_mach (&abfd, arch, mach); 3084 info.bfd_arch_info = bfd_get_arch_info (&abfd); 3085 } 3086 } 3087 3088 gdbarch = gdbarch_alloc (&info, tdep); 3089 3090 /* Initialize the number of real and pseudo registers in each variant. */ 3091 init_variants (); 3092 3093 /* Choose variant. */ 3094 v = find_variant_by_arch (arch, mach); 3095 if (!v) 3096 return NULL; 3097 3098 tdep->regs = v->regs; 3099 3100 tdep->ppc_gp0_regnum = 0; 3101 tdep->ppc_toc_regnum = 2; 3102 tdep->ppc_ps_regnum = 65; 3103 tdep->ppc_cr_regnum = 66; 3104 tdep->ppc_lr_regnum = 67; 3105 tdep->ppc_ctr_regnum = 68; 3106 tdep->ppc_xer_regnum = 69; 3107 if (v->mach == bfd_mach_ppc_601) 3108 tdep->ppc_mq_regnum = 124; 3109 else if (arch == bfd_arch_rs6000) 3110 tdep->ppc_mq_regnum = 70; 3111 else 3112 tdep->ppc_mq_regnum = -1; 3113 tdep->ppc_fp0_regnum = 32; 3114 tdep->ppc_fpscr_regnum = (arch == bfd_arch_rs6000) ? 71 : 70; 3115 tdep->ppc_sr0_regnum = 71; 3116 tdep->ppc_vr0_regnum = -1; 3117 tdep->ppc_vrsave_regnum = -1; 3118 tdep->ppc_ev0_upper_regnum = -1; 3119 tdep->ppc_ev0_regnum = -1; 3120 tdep->ppc_ev31_regnum = -1; 3121 tdep->ppc_acc_regnum = -1; 3122 tdep->ppc_spefscr_regnum = -1; 3123 3124 set_gdbarch_pc_regnum (gdbarch, 64); 3125 set_gdbarch_sp_regnum (gdbarch, 1); 3126 set_gdbarch_deprecated_fp_regnum (gdbarch, 1); 3127 set_gdbarch_register_sim_regno (gdbarch, rs6000_register_sim_regno); 3128 if (sysv_abi && wordsize == 8) 3129 set_gdbarch_return_value (gdbarch, ppc64_sysv_abi_return_value); 3130 else if (sysv_abi && wordsize == 4) 3131 set_gdbarch_return_value (gdbarch, ppc_sysv_abi_return_value); 3132 else 3133 { 3134 set_gdbarch_deprecated_extract_return_value (gdbarch, rs6000_extract_return_value); 3135 set_gdbarch_store_return_value (gdbarch, rs6000_store_return_value); 3136 } 3137 3138 /* Set lr_frame_offset. */ 3139 if (wordsize == 8) 3140 tdep->lr_frame_offset = 16; 3141 else if (sysv_abi) 3142 tdep->lr_frame_offset = 4; 3143 else 3144 tdep->lr_frame_offset = 8; 3145 3146 if (v->arch == bfd_arch_rs6000) 3147 tdep->ppc_sr0_regnum = -1; 3148 else if (v->arch == bfd_arch_powerpc) 3149 switch (v->mach) 3150 { 3151 case bfd_mach_ppc: 3152 tdep->ppc_sr0_regnum = -1; 3153 tdep->ppc_vr0_regnum = 71; 3154 tdep->ppc_vrsave_regnum = 104; 3155 break; 3156 case bfd_mach_ppc_7400: 3157 tdep->ppc_vr0_regnum = 119; 3158 tdep->ppc_vrsave_regnum = 152; 3159 break; 3160 case bfd_mach_ppc_e500: 3161 tdep->ppc_toc_regnum = -1; 3162 tdep->ppc_ev0_upper_regnum = 32; 3163 tdep->ppc_ev0_regnum = 73; 3164 tdep->ppc_ev31_regnum = 104; 3165 tdep->ppc_acc_regnum = 71; 3166 tdep->ppc_spefscr_regnum = 72; 3167 tdep->ppc_fp0_regnum = -1; 3168 tdep->ppc_fpscr_regnum = -1; 3169 tdep->ppc_sr0_regnum = -1; 3170 set_gdbarch_pseudo_register_read (gdbarch, e500_pseudo_register_read); 3171 set_gdbarch_pseudo_register_write (gdbarch, e500_pseudo_register_write); 3172 set_gdbarch_register_reggroup_p (gdbarch, e500_register_reggroup_p); 3173 break; 3174 3175 case bfd_mach_ppc64: 3176 case bfd_mach_ppc_620: 3177 case bfd_mach_ppc_630: 3178 case bfd_mach_ppc_a35: 3179 case bfd_mach_ppc_rs64ii: 3180 case bfd_mach_ppc_rs64iii: 3181 /* These processor's register sets don't have segment registers. */ 3182 tdep->ppc_sr0_regnum = -1; 3183 break; 3184 } 3185 else 3186 internal_error (__FILE__, __LINE__, 3187 "rs6000_gdbarch_init: " 3188 "received unexpected BFD 'arch' value"); 3189 3190 /* Sanity check on registers. */ 3191 gdb_assert (strcmp (tdep->regs[tdep->ppc_gp0_regnum].name, "r0") == 0); 3192 3193 /* Select instruction printer. */ 3194 if (arch == bfd_arch_rs6000) 3195 set_gdbarch_print_insn (gdbarch, print_insn_rs6000); 3196 else 3197 set_gdbarch_print_insn (gdbarch, gdb_print_insn_powerpc); 3198 3199 set_gdbarch_write_pc (gdbarch, generic_target_write_pc); 3200 3201 set_gdbarch_num_regs (gdbarch, v->nregs); 3202 set_gdbarch_num_pseudo_regs (gdbarch, v->npregs); 3203 set_gdbarch_register_name (gdbarch, rs6000_register_name); 3204 set_gdbarch_register_type (gdbarch, rs6000_register_type); 3205 3206 set_gdbarch_ptr_bit (gdbarch, wordsize * TARGET_CHAR_BIT); 3207 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); 3208 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT); 3209 set_gdbarch_long_bit (gdbarch, wordsize * TARGET_CHAR_BIT); 3210 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); 3211 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); 3212 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); 3213 if (sysv_abi) 3214 set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT); 3215 else 3216 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); 3217 set_gdbarch_char_signed (gdbarch, 0); 3218 3219 set_gdbarch_frame_align (gdbarch, rs6000_frame_align); 3220 if (sysv_abi && wordsize == 8) 3221 /* PPC64 SYSV. */ 3222 set_gdbarch_frame_red_zone_size (gdbarch, 288); 3223 else if (!sysv_abi && wordsize == 4) 3224 /* PowerOpen / AIX 32 bit. The saved area or red zone consists of 3225 19 4 byte GPRS + 18 8 byte FPRs giving a total of 220 bytes. 3226 Problem is, 220 isn't frame (16 byte) aligned. Round it up to 3227 224. */ 3228 set_gdbarch_frame_red_zone_size (gdbarch, 224); 3229 3230 set_gdbarch_convert_register_p (gdbarch, rs6000_convert_register_p); 3231 set_gdbarch_register_to_value (gdbarch, rs6000_register_to_value); 3232 set_gdbarch_value_to_register (gdbarch, rs6000_value_to_register); 3233 3234 set_gdbarch_stab_reg_to_regnum (gdbarch, rs6000_stab_reg_to_regnum); 3235 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rs6000_dwarf2_reg_to_regnum); 3236 /* Note: kevinb/2002-04-12: I'm not convinced that rs6000_push_arguments() 3237 is correct for the SysV ABI when the wordsize is 8, but I'm also 3238 fairly certain that ppc_sysv_abi_push_arguments() will give even 3239 worse results since it only works for 32-bit code. So, for the moment, 3240 we're better off calling rs6000_push_arguments() since it works for 3241 64-bit code. At some point in the future, this matter needs to be 3242 revisited. */ 3243 if (sysv_abi && wordsize == 4) 3244 set_gdbarch_push_dummy_call (gdbarch, ppc_sysv_abi_push_dummy_call); 3245 else if (sysv_abi && wordsize == 8) 3246 set_gdbarch_push_dummy_call (gdbarch, ppc64_sysv_abi_push_dummy_call); 3247 else 3248 set_gdbarch_push_dummy_call (gdbarch, rs6000_push_dummy_call); 3249 3250 set_gdbarch_deprecated_extract_struct_value_address (gdbarch, rs6000_extract_struct_value_address); 3251 3252 set_gdbarch_skip_prologue (gdbarch, rs6000_skip_prologue); 3253 set_gdbarch_inner_than (gdbarch, core_addr_lessthan); 3254 set_gdbarch_breakpoint_from_pc (gdbarch, rs6000_breakpoint_from_pc); 3255 3256 /* Handle the 64-bit SVR4 minimal-symbol convention of using "FN" 3257 for the descriptor and ".FN" for the entry-point -- a user 3258 specifying "break FN" will unexpectedly end up with a breakpoint 3259 on the descriptor and not the function. This architecture method 3260 transforms any breakpoints on descriptors into breakpoints on the 3261 corresponding entry point. */ 3262 if (sysv_abi && wordsize == 8) 3263 set_gdbarch_adjust_breakpoint_address (gdbarch, ppc64_sysv_abi_adjust_breakpoint_address); 3264 3265 /* Not sure on this. FIXMEmgo */ 3266 set_gdbarch_frame_args_skip (gdbarch, 8); 3267 3268 if (!sysv_abi) 3269 set_gdbarch_deprecated_use_struct_convention (gdbarch, rs6000_use_struct_convention); 3270 3271 if (!sysv_abi) 3272 { 3273 /* Handle RS/6000 function pointers (which are really function 3274 descriptors). */ 3275 set_gdbarch_convert_from_func_ptr_addr (gdbarch, 3276 rs6000_convert_from_func_ptr_addr); 3277 } 3278 3279 /* Helpers for function argument information. */ 3280 set_gdbarch_fetch_pointer_argument (gdbarch, rs6000_fetch_pointer_argument); 3281 3282 /* Hook in ABI-specific overrides, if they have been registered. */ 3283 gdbarch_init_osabi (info, gdbarch); 3284 3285 switch (info.osabi) 3286 { 3287 case GDB_OSABI_NETBSD_AOUT: 3288 case GDB_OSABI_NETBSD_ELF: 3289 case GDB_OSABI_UNKNOWN: 3290 case GDB_OSABI_LINUX: 3291 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc); 3292 frame_unwind_append_sniffer (gdbarch, rs6000_frame_sniffer); 3293 set_gdbarch_unwind_dummy_id (gdbarch, rs6000_unwind_dummy_id); 3294 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer); 3295 break; 3296 default: 3297 set_gdbarch_believe_pcc_promotion (gdbarch, 1); 3298 3299 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc); 3300 frame_unwind_append_sniffer (gdbarch, rs6000_frame_sniffer); 3301 set_gdbarch_unwind_dummy_id (gdbarch, rs6000_unwind_dummy_id); 3302 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer); 3303 } 3304 3305 if (from_xcoff_exec) 3306 { 3307 /* NOTE: jimix/2003-06-09: This test should really check for 3308 GDB_OSABI_AIX when that is defined and becomes 3309 available. (Actually, once things are properly split apart, 3310 the test goes away.) */ 3311 /* RS6000/AIX does not support PT_STEP. Has to be simulated. */ 3312 set_gdbarch_software_single_step (gdbarch, rs6000_software_single_step); 3313 } 3314 3315 init_sim_regno_table (gdbarch); 3316 3317 return gdbarch; 3318} 3319 3320static void 3321rs6000_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) 3322{ 3323 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); 3324 3325 if (tdep == NULL) 3326 return; 3327 3328 /* FIXME: Dump gdbarch_tdep. */ 3329} 3330 3331static struct cmd_list_element *info_powerpc_cmdlist = NULL; 3332 3333static void 3334rs6000_info_powerpc_command (char *args, int from_tty) 3335{ 3336 help_list (info_powerpc_cmdlist, "info powerpc ", class_info, gdb_stdout); 3337} 3338 3339/* Initialization code. */ 3340 3341extern initialize_file_ftype _initialize_rs6000_tdep; /* -Wmissing-prototypes */ 3342 3343void 3344_initialize_rs6000_tdep (void) 3345{ 3346 gdbarch_register (bfd_arch_rs6000, rs6000_gdbarch_init, rs6000_dump_tdep); 3347 gdbarch_register (bfd_arch_powerpc, rs6000_gdbarch_init, rs6000_dump_tdep); 3348 3349 /* Add root prefix command for "info powerpc" commands */ 3350 add_prefix_cmd ("powerpc", class_info, rs6000_info_powerpc_command, 3351 "Various POWERPC info specific commands.", 3352 &info_powerpc_cmdlist, "info powerpc ", 0, &infolist); 3353} 3354