1/* Target-dependent code for AMD64. 2 3 Copyright 2001, 2002, 2003, 2004 Free Software Foundation, Inc. 4 Contributed by Jiri Smid, SuSE Labs. 5 6 This file is part of GDB. 7 8 This program is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 2 of the License, or 11 (at your option) any later version. 12 13 This program is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program; if not, write to the Free Software 20 Foundation, Inc., 59 Temple Place - Suite 330, 21 Boston, MA 02111-1307, USA. */ 22 23#include "defs.h" 24#include "arch-utils.h" 25#include "block.h" 26#include "dummy-frame.h" 27#include "frame.h" 28#include "frame-base.h" 29#include "frame-unwind.h" 30#include "inferior.h" 31#include "gdbcmd.h" 32#include "gdbcore.h" 33#include "objfiles.h" 34#include "regcache.h" 35#include "regset.h" 36#include "symfile.h" 37 38#include "gdb_assert.h" 39 40#include "amd64-tdep.h" 41#include "i387-tdep.h" 42 43/* Note that the AMD64 architecture was previously known as x86-64. 44 The latter is (forever) engraved into the canonical system name as 45 returned by config.guess, and used as the name for the AMD64 port 46 of GNU/Linux. The BSD's have renamed their ports to amd64; they 47 don't like to shout. For GDB we prefer the amd64_-prefix over the 48 x86_64_-prefix since it's so much easier to type. */ 49 50/* Register information. */ 51 52struct amd64_register_info 53{ 54 char *name; 55 struct type **type; 56}; 57 58static struct amd64_register_info amd64_register_info[] = 59{ 60 { "rax", &builtin_type_int64 }, 61 { "rbx", &builtin_type_int64 }, 62 { "rcx", &builtin_type_int64 }, 63 { "rdx", &builtin_type_int64 }, 64 { "rsi", &builtin_type_int64 }, 65 { "rdi", &builtin_type_int64 }, 66 { "rbp", &builtin_type_void_data_ptr }, 67 { "rsp", &builtin_type_void_data_ptr }, 68 69 /* %r8 is indeed register number 8. */ 70 { "r8", &builtin_type_int64 }, 71 { "r9", &builtin_type_int64 }, 72 { "r10", &builtin_type_int64 }, 73 { "r11", &builtin_type_int64 }, 74 { "r12", &builtin_type_int64 }, 75 { "r13", &builtin_type_int64 }, 76 { "r14", &builtin_type_int64 }, 77 { "r15", &builtin_type_int64 }, 78 { "rip", &builtin_type_void_func_ptr }, 79 { "eflags", &builtin_type_int32 }, 80 { "cs", &builtin_type_int32 }, 81 { "ss", &builtin_type_int32 }, 82 { "ds", &builtin_type_int32 }, 83 { "es", &builtin_type_int32 }, 84 { "fs", &builtin_type_int32 }, 85 { "gs", &builtin_type_int32 }, 86 87 /* %st0 is register number 24. */ 88 { "st0", &builtin_type_i387_ext }, 89 { "st1", &builtin_type_i387_ext }, 90 { "st2", &builtin_type_i387_ext }, 91 { "st3", &builtin_type_i387_ext }, 92 { "st4", &builtin_type_i387_ext }, 93 { "st5", &builtin_type_i387_ext }, 94 { "st6", &builtin_type_i387_ext }, 95 { "st7", &builtin_type_i387_ext }, 96 { "fctrl", &builtin_type_int32 }, 97 { "fstat", &builtin_type_int32 }, 98 { "ftag", &builtin_type_int32 }, 99 { "fiseg", &builtin_type_int32 }, 100 { "fioff", &builtin_type_int32 }, 101 { "foseg", &builtin_type_int32 }, 102 { "fooff", &builtin_type_int32 }, 103 { "fop", &builtin_type_int32 }, 104 105 /* %xmm0 is register number 40. */ 106 { "xmm0", &builtin_type_v4sf }, 107 { "xmm1", &builtin_type_v4sf }, 108 { "xmm2", &builtin_type_v4sf }, 109 { "xmm3", &builtin_type_v4sf }, 110 { "xmm4", &builtin_type_v4sf }, 111 { "xmm5", &builtin_type_v4sf }, 112 { "xmm6", &builtin_type_v4sf }, 113 { "xmm7", &builtin_type_v4sf }, 114 { "xmm8", &builtin_type_v4sf }, 115 { "xmm9", &builtin_type_v4sf }, 116 { "xmm10", &builtin_type_v4sf }, 117 { "xmm11", &builtin_type_v4sf }, 118 { "xmm12", &builtin_type_v4sf }, 119 { "xmm13", &builtin_type_v4sf }, 120 { "xmm14", &builtin_type_v4sf }, 121 { "xmm15", &builtin_type_v4sf }, 122 { "mxcsr", &builtin_type_int32 } 123}; 124 125/* Total number of registers. */ 126#define AMD64_NUM_REGS \ 127 (sizeof (amd64_register_info) / sizeof (amd64_register_info[0])) 128 129/* Return the name of register REGNUM. */ 130 131static const char * 132amd64_register_name (int regnum) 133{ 134 if (regnum >= 0 && regnum < AMD64_NUM_REGS) 135 return amd64_register_info[regnum].name; 136 137 return NULL; 138} 139 140/* Return the GDB type object for the "standard" data type of data in 141 register REGNUM. */ 142 143static struct type * 144amd64_register_type (struct gdbarch *gdbarch, int regnum) 145{ 146 gdb_assert (regnum >= 0 && regnum < AMD64_NUM_REGS); 147 148 return *amd64_register_info[regnum].type; 149} 150 151/* DWARF Register Number Mapping as defined in the System V psABI, 152 section 3.6. */ 153 154static int amd64_dwarf_regmap[] = 155{ 156 /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */ 157 AMD64_RAX_REGNUM, AMD64_RDX_REGNUM, 158 AMD64_RCX_REGNUM, AMD64_RBX_REGNUM, 159 AMD64_RSI_REGNUM, AMD64_RDI_REGNUM, 160 161 /* Frame Pointer Register RBP. */ 162 AMD64_RBP_REGNUM, 163 164 /* Stack Pointer Register RSP. */ 165 AMD64_RSP_REGNUM, 166 167 /* Extended Integer Registers 8 - 15. */ 168 8, 9, 10, 11, 12, 13, 14, 15, 169 170 /* Return Address RA. Mapped to RIP. */ 171 AMD64_RIP_REGNUM, 172 173 /* SSE Registers 0 - 7. */ 174 AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM, 175 AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3, 176 AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5, 177 AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7, 178 179 /* Extended SSE Registers 8 - 15. */ 180 AMD64_XMM0_REGNUM + 8, AMD64_XMM0_REGNUM + 9, 181 AMD64_XMM0_REGNUM + 10, AMD64_XMM0_REGNUM + 11, 182 AMD64_XMM0_REGNUM + 12, AMD64_XMM0_REGNUM + 13, 183 AMD64_XMM0_REGNUM + 14, AMD64_XMM0_REGNUM + 15, 184 185 /* Floating Point Registers 0-7. */ 186 AMD64_ST0_REGNUM + 0, AMD64_ST0_REGNUM + 1, 187 AMD64_ST0_REGNUM + 2, AMD64_ST0_REGNUM + 3, 188 AMD64_ST0_REGNUM + 4, AMD64_ST0_REGNUM + 5, 189 AMD64_ST0_REGNUM + 6, AMD64_ST0_REGNUM + 7 190}; 191 192static const int amd64_dwarf_regmap_len = 193 (sizeof (amd64_dwarf_regmap) / sizeof (amd64_dwarf_regmap[0])); 194 195/* Convert DWARF register number REG to the appropriate register 196 number used by GDB. */ 197 198static int 199amd64_dwarf_reg_to_regnum (int reg) 200{ 201 int regnum = -1; 202 203 if (reg >= 0 || reg < amd64_dwarf_regmap_len) 204 regnum = amd64_dwarf_regmap[reg]; 205 206 if (regnum == -1) 207 warning ("Unmapped DWARF Register #%d encountered\n", reg); 208 209 return regnum; 210} 211 212/* Return nonzero if a value of type TYPE stored in register REGNUM 213 needs any special handling. */ 214 215static int 216amd64_convert_register_p (int regnum, struct type *type) 217{ 218 return i386_fp_regnum_p (regnum); 219} 220 221 222/* Register classes as defined in the psABI. */ 223 224enum amd64_reg_class 225{ 226 AMD64_INTEGER, 227 AMD64_SSE, 228 AMD64_SSEUP, 229 AMD64_X87, 230 AMD64_X87UP, 231 AMD64_COMPLEX_X87, 232 AMD64_NO_CLASS, 233 AMD64_MEMORY 234}; 235 236/* Return the union class of CLASS1 and CLASS2. See the psABI for 237 details. */ 238 239static enum amd64_reg_class 240amd64_merge_classes (enum amd64_reg_class class1, enum amd64_reg_class class2) 241{ 242 /* Rule (a): If both classes are equal, this is the resulting class. */ 243 if (class1 == class2) 244 return class1; 245 246 /* Rule (b): If one of the classes is NO_CLASS, the resulting class 247 is the other class. */ 248 if (class1 == AMD64_NO_CLASS) 249 return class2; 250 if (class2 == AMD64_NO_CLASS) 251 return class1; 252 253 /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */ 254 if (class1 == AMD64_MEMORY || class2 == AMD64_MEMORY) 255 return AMD64_MEMORY; 256 257 /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */ 258 if (class1 == AMD64_INTEGER || class2 == AMD64_INTEGER) 259 return AMD64_INTEGER; 260 261 /* Rule (e): If one of the classes is X87, X87UP, COMPLEX_X87 class, 262 MEMORY is used as class. */ 263 if (class1 == AMD64_X87 || class1 == AMD64_X87UP 264 || class1 == AMD64_COMPLEX_X87 || class2 == AMD64_X87 265 || class2 == AMD64_X87UP || class2 == AMD64_COMPLEX_X87) 266 return AMD64_MEMORY; 267 268 /* Rule (f): Otherwise class SSE is used. */ 269 return AMD64_SSE; 270} 271 272static void amd64_classify (struct type *type, enum amd64_reg_class class[2]); 273 274/* Return non-zero if TYPE is a non-POD structure or union type. */ 275 276static int 277amd64_non_pod_p (struct type *type) 278{ 279 /* ??? A class with a base class certainly isn't POD, but does this 280 catch all non-POD structure types? */ 281 if (TYPE_CODE (type) == TYPE_CODE_STRUCT && TYPE_N_BASECLASSES (type) > 0) 282 return 1; 283 284 return 0; 285} 286 287/* Classify TYPE according to the rules for aggregate (structures and 288 arrays) and union types, and store the result in CLASS. */ 289 290static void 291amd64_classify_aggregate (struct type *type, enum amd64_reg_class class[2]) 292{ 293 int len = TYPE_LENGTH (type); 294 295 /* 1. If the size of an object is larger than two eightbytes, or in 296 C++, is a non-POD structure or union type, or contains 297 unaligned fields, it has class memory. */ 298 if (len > 16 || amd64_non_pod_p (type)) 299 { 300 class[0] = class[1] = AMD64_MEMORY; 301 return; 302 } 303 304 /* 2. Both eightbytes get initialized to class NO_CLASS. */ 305 class[0] = class[1] = AMD64_NO_CLASS; 306 307 /* 3. Each field of an object is classified recursively so that 308 always two fields are considered. The resulting class is 309 calculated according to the classes of the fields in the 310 eightbyte: */ 311 312 if (TYPE_CODE (type) == TYPE_CODE_ARRAY) 313 { 314 struct type *subtype = check_typedef (TYPE_TARGET_TYPE (type)); 315 316 /* All fields in an array have the same type. */ 317 amd64_classify (subtype, class); 318 if (len > 8 && class[1] == AMD64_NO_CLASS) 319 class[1] = class[0]; 320 } 321 else 322 { 323 int i; 324 325 /* Structure or union. */ 326 gdb_assert (TYPE_CODE (type) == TYPE_CODE_STRUCT 327 || TYPE_CODE (type) == TYPE_CODE_UNION); 328 329 for (i = 0; i < TYPE_NFIELDS (type); i++) 330 { 331 struct type *subtype = check_typedef (TYPE_FIELD_TYPE (type, i)); 332 int pos = TYPE_FIELD_BITPOS (type, i) / 64; 333 enum amd64_reg_class subclass[2]; 334 335 /* Ignore static fields. */ 336 if (TYPE_FIELD_STATIC (type, i)) 337 continue; 338 339 gdb_assert (pos == 0 || pos == 1); 340 341 amd64_classify (subtype, subclass); 342 class[pos] = amd64_merge_classes (class[pos], subclass[0]); 343 if (pos == 0) 344 class[1] = amd64_merge_classes (class[1], subclass[1]); 345 } 346 } 347 348 /* 4. Then a post merger cleanup is done: */ 349 350 /* Rule (a): If one of the classes is MEMORY, the whole argument is 351 passed in memory. */ 352 if (class[0] == AMD64_MEMORY || class[1] == AMD64_MEMORY) 353 class[0] = class[1] = AMD64_MEMORY; 354 355 /* Rule (b): If SSEUP is not preceeded by SSE, it is converted to 356 SSE. */ 357 if (class[0] == AMD64_SSEUP) 358 class[0] = AMD64_SSE; 359 if (class[1] == AMD64_SSEUP && class[0] != AMD64_SSE) 360 class[1] = AMD64_SSE; 361} 362 363/* Classify TYPE, and store the result in CLASS. */ 364 365static void 366amd64_classify (struct type *type, enum amd64_reg_class class[2]) 367{ 368 enum type_code code = TYPE_CODE (type); 369 int len = TYPE_LENGTH (type); 370 371 class[0] = class[1] = AMD64_NO_CLASS; 372 373 /* Arguments of types (signed and unsigned) _Bool, char, short, int, 374 long, long long, and pointers are in the INTEGER class. Similarly, 375 range types, used by languages such as Ada, are also in the INTEGER 376 class. */ 377 if ((code == TYPE_CODE_INT || code == TYPE_CODE_ENUM 378 || code == TYPE_CODE_RANGE 379 || code == TYPE_CODE_PTR || code == TYPE_CODE_REF) 380 && (len == 1 || len == 2 || len == 4 || len == 8)) 381 class[0] = AMD64_INTEGER; 382 383 /* Arguments of types float, double and __m64 are in class SSE. */ 384 else if (code == TYPE_CODE_FLT && (len == 4 || len == 8)) 385 /* FIXME: __m64 . */ 386 class[0] = AMD64_SSE; 387 388 /* Arguments of types __float128 and __m128 are split into two 389 halves. The least significant ones belong to class SSE, the most 390 significant one to class SSEUP. */ 391 /* FIXME: __float128, __m128. */ 392 393 /* The 64-bit mantissa of arguments of type long double belongs to 394 class X87, the 16-bit exponent plus 6 bytes of padding belongs to 395 class X87UP. */ 396 else if (code == TYPE_CODE_FLT && len == 16) 397 /* Class X87 and X87UP. */ 398 class[0] = AMD64_X87, class[1] = AMD64_X87UP; 399 400 /* Aggregates. */ 401 else if (code == TYPE_CODE_ARRAY || code == TYPE_CODE_STRUCT 402 || code == TYPE_CODE_UNION) 403 amd64_classify_aggregate (type, class); 404} 405 406static enum return_value_convention 407amd64_return_value (struct gdbarch *gdbarch, struct type *type, 408 struct regcache *regcache, 409 void *readbuf, const void *writebuf) 410{ 411 enum amd64_reg_class class[2]; 412 int len = TYPE_LENGTH (type); 413 static int integer_regnum[] = { AMD64_RAX_REGNUM, AMD64_RDX_REGNUM }; 414 static int sse_regnum[] = { AMD64_XMM0_REGNUM, AMD64_XMM1_REGNUM }; 415 int integer_reg = 0; 416 int sse_reg = 0; 417 int i; 418 419 gdb_assert (!(readbuf && writebuf)); 420 421 /* 1. Classify the return type with the classification algorithm. */ 422 amd64_classify (type, class); 423 424 /* 2. If the type has class MEMORY, then the caller provides space 425 for the return value and passes the address of this storage in 426 %rdi as if it were the first argument to the function. In effect, 427 this address becomes a hidden first argument. 428 429 On return %rax will contain the address that has been passed in 430 by the caller in %rdi. */ 431 if (class[0] == AMD64_MEMORY) 432 { 433 /* As indicated by the comment above, the ABI guarantees that we 434 can always find the return value just after the function has 435 returned. */ 436 437 if (readbuf) 438 { 439 ULONGEST addr; 440 441 regcache_raw_read_unsigned (regcache, AMD64_RAX_REGNUM, &addr); 442 read_memory (addr, readbuf, TYPE_LENGTH (type)); 443 } 444 445 return RETURN_VALUE_ABI_RETURNS_ADDRESS; 446 } 447 448 gdb_assert (class[1] != AMD64_MEMORY); 449 gdb_assert (len <= 16); 450 451 for (i = 0; len > 0; i++, len -= 8) 452 { 453 int regnum = -1; 454 int offset = 0; 455 456 switch (class[i]) 457 { 458 case AMD64_INTEGER: 459 /* 3. If the class is INTEGER, the next available register 460 of the sequence %rax, %rdx is used. */ 461 regnum = integer_regnum[integer_reg++]; 462 break; 463 464 case AMD64_SSE: 465 /* 4. If the class is SSE, the next available SSE register 466 of the sequence %xmm0, %xmm1 is used. */ 467 regnum = sse_regnum[sse_reg++]; 468 break; 469 470 case AMD64_SSEUP: 471 /* 5. If the class is SSEUP, the eightbyte is passed in the 472 upper half of the last used SSE register. */ 473 gdb_assert (sse_reg > 0); 474 regnum = sse_regnum[sse_reg - 1]; 475 offset = 8; 476 break; 477 478 case AMD64_X87: 479 /* 6. If the class is X87, the value is returned on the X87 480 stack in %st0 as 80-bit x87 number. */ 481 regnum = AMD64_ST0_REGNUM; 482 if (writebuf) 483 i387_return_value (gdbarch, regcache); 484 break; 485 486 case AMD64_X87UP: 487 /* 7. If the class is X87UP, the value is returned together 488 with the previous X87 value in %st0. */ 489 gdb_assert (i > 0 && class[0] == AMD64_X87); 490 regnum = AMD64_ST0_REGNUM; 491 offset = 8; 492 len = 2; 493 break; 494 495 case AMD64_NO_CLASS: 496 continue; 497 498 default: 499 gdb_assert (!"Unexpected register class."); 500 } 501 502 gdb_assert (regnum != -1); 503 504 if (readbuf) 505 regcache_raw_read_part (regcache, regnum, offset, min (len, 8), 506 (char *) readbuf + i * 8); 507 if (writebuf) 508 regcache_raw_write_part (regcache, regnum, offset, min (len, 8), 509 (const char *) writebuf + i * 8); 510 } 511 512 return RETURN_VALUE_REGISTER_CONVENTION; 513} 514 515 516static CORE_ADDR 517amd64_push_arguments (struct regcache *regcache, int nargs, 518 struct value **args, CORE_ADDR sp, int struct_return) 519{ 520 static int integer_regnum[] = 521 { 522 AMD64_RDI_REGNUM, /* %rdi */ 523 AMD64_RSI_REGNUM, /* %rsi */ 524 AMD64_RDX_REGNUM, /* %rdx */ 525 AMD64_RCX_REGNUM, /* %rcx */ 526 8, /* %r8 */ 527 9 /* %r9 */ 528 }; 529 static int sse_regnum[] = 530 { 531 /* %xmm0 ... %xmm7 */ 532 AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM, 533 AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3, 534 AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5, 535 AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7, 536 }; 537 struct value **stack_args = alloca (nargs * sizeof (struct value *)); 538 int num_stack_args = 0; 539 int num_elements = 0; 540 int element = 0; 541 int integer_reg = 0; 542 int sse_reg = 0; 543 int i; 544 545 /* Reserve a register for the "hidden" argument. */ 546 if (struct_return) 547 integer_reg++; 548 549 for (i = 0; i < nargs; i++) 550 { 551 struct type *type = VALUE_TYPE (args[i]); 552 int len = TYPE_LENGTH (type); 553 enum amd64_reg_class class[2]; 554 int needed_integer_regs = 0; 555 int needed_sse_regs = 0; 556 int j; 557 558 /* Classify argument. */ 559 amd64_classify (type, class); 560 561 /* Calculate the number of integer and SSE registers needed for 562 this argument. */ 563 for (j = 0; j < 2; j++) 564 { 565 if (class[j] == AMD64_INTEGER) 566 needed_integer_regs++; 567 else if (class[j] == AMD64_SSE) 568 needed_sse_regs++; 569 } 570 571 /* Check whether enough registers are available, and if the 572 argument should be passed in registers at all. */ 573 if (integer_reg + needed_integer_regs > ARRAY_SIZE (integer_regnum) 574 || sse_reg + needed_sse_regs > ARRAY_SIZE (sse_regnum) 575 || (needed_integer_regs == 0 && needed_sse_regs == 0)) 576 { 577 /* The argument will be passed on the stack. */ 578 num_elements += ((len + 7) / 8); 579 stack_args[num_stack_args++] = args[i]; 580 } 581 else 582 { 583 /* The argument will be passed in registers. */ 584 char *valbuf = VALUE_CONTENTS (args[i]); 585 char buf[8]; 586 587 gdb_assert (len <= 16); 588 589 for (j = 0; len > 0; j++, len -= 8) 590 { 591 int regnum = -1; 592 int offset = 0; 593 594 switch (class[j]) 595 { 596 case AMD64_INTEGER: 597 regnum = integer_regnum[integer_reg++]; 598 break; 599 600 case AMD64_SSE: 601 regnum = sse_regnum[sse_reg++]; 602 break; 603 604 case AMD64_SSEUP: 605 gdb_assert (sse_reg > 0); 606 regnum = sse_regnum[sse_reg - 1]; 607 offset = 8; 608 break; 609 610 default: 611 gdb_assert (!"Unexpected register class."); 612 } 613 614 gdb_assert (regnum != -1); 615 memset (buf, 0, sizeof buf); 616 memcpy (buf, valbuf + j * 8, min (len, 8)); 617 regcache_raw_write_part (regcache, regnum, offset, 8, buf); 618 } 619 } 620 } 621 622 /* Allocate space for the arguments on the stack. */ 623 sp -= num_elements * 8; 624 625 /* The psABI says that "The end of the input argument area shall be 626 aligned on a 16 byte boundary." */ 627 sp &= ~0xf; 628 629 /* Write out the arguments to the stack. */ 630 for (i = 0; i < num_stack_args; i++) 631 { 632 struct type *type = VALUE_TYPE (stack_args[i]); 633 char *valbuf = VALUE_CONTENTS (stack_args[i]); 634 int len = TYPE_LENGTH (type); 635 636 write_memory (sp + element * 8, valbuf, len); 637 element += ((len + 7) / 8); 638 } 639 640 /* The psABI says that "For calls that may call functions that use 641 varargs or stdargs (prototype-less calls or calls to functions 642 containing ellipsis (...) in the declaration) %al is used as 643 hidden argument to specify the number of SSE registers used. */ 644 regcache_raw_write_unsigned (regcache, AMD64_RAX_REGNUM, sse_reg); 645 return sp; 646} 647 648static CORE_ADDR 649amd64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, 650 struct regcache *regcache, CORE_ADDR bp_addr, 651 int nargs, struct value **args, CORE_ADDR sp, 652 int struct_return, CORE_ADDR struct_addr) 653{ 654 char buf[8]; 655 656 /* Pass arguments. */ 657 sp = amd64_push_arguments (regcache, nargs, args, sp, struct_return); 658 659 /* Pass "hidden" argument". */ 660 if (struct_return) 661 { 662 store_unsigned_integer (buf, 8, struct_addr); 663 regcache_cooked_write (regcache, AMD64_RDI_REGNUM, buf); 664 } 665 666 /* Store return address. */ 667 sp -= 8; 668 store_unsigned_integer (buf, 8, bp_addr); 669 write_memory (sp, buf, 8); 670 671 /* Finally, update the stack pointer... */ 672 store_unsigned_integer (buf, 8, sp); 673 regcache_cooked_write (regcache, AMD64_RSP_REGNUM, buf); 674 675 /* ...and fake a frame pointer. */ 676 regcache_cooked_write (regcache, AMD64_RBP_REGNUM, buf); 677 678 return sp + 16; 679} 680 681 682/* The maximum number of saved registers. This should include %rip. */ 683#define AMD64_NUM_SAVED_REGS AMD64_NUM_GREGS 684 685struct amd64_frame_cache 686{ 687 /* Base address. */ 688 CORE_ADDR base; 689 CORE_ADDR sp_offset; 690 CORE_ADDR pc; 691 692 /* Saved registers. */ 693 CORE_ADDR saved_regs[AMD64_NUM_SAVED_REGS]; 694 CORE_ADDR saved_sp; 695 696 /* Do we have a frame? */ 697 int frameless_p; 698}; 699 700/* Initialize the frame cache. */ 701 702static void 703amd64_init_frame_cache (struct amd64_frame_cache *cache) 704{ 705 int i; 706 707 /* Base address. */ 708 cache->base = 0; 709 cache->sp_offset = -8; 710 cache->pc = 0; 711 712 /* Saved registers. We initialize these to -1 since zero is a valid 713 offset (that's where %rbp is supposed to be stored). */ 714 for (i = 0; i < AMD64_NUM_SAVED_REGS; i++) 715 cache->saved_regs[i] = -1; 716 cache->saved_sp = 0; 717 718 /* Frameless until proven otherwise. */ 719 cache->frameless_p = 1; 720} 721 722/* Allocate a frame cache. */ 723 724static struct amd64_frame_cache * 725amd64_alloc_frame_cache (void) 726{ 727 struct amd64_frame_cache *cache; 728 729 cache = FRAME_OBSTACK_ZALLOC (struct amd64_frame_cache); 730 amd64_init_frame_cache(cache); 731 732 return cache; 733} 734 735/* Do a limited analysis of the prologue at PC and update CACHE 736 accordingly. Bail out early if CURRENT_PC is reached. Return the 737 address where the analysis stopped. 738 739 We will handle only functions beginning with: 740 741 movq $retguard(%rip), $reg (0x4c or 0x48) 0x8b ?? ?? ?? ?? ?? 742 xorq $off(%rsp), $reg (0x4c or 0x48) 0x33 ?? 0x24 743 pushq %rbp 0x55 744 movq %rsp, %rbp 0x48 0x89 0xe5 745 746 First 2 instructions for retguard are optional. 747 748 Any function that doesn't start with this sequence will be assumed 749 to have no prologue and thus no valid frame pointer in %rbp. */ 750 751static CORE_ADDR 752amd64_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc, 753 struct amd64_frame_cache *cache) 754{ 755 static unsigned char proto[3] = { 0x48, 0x89, 0xe5 }; 756 unsigned char buf[10]; 757 unsigned char op; 758 759 if (current_pc <= pc) 760 return current_pc; 761 762 op = read_memory_unsigned_integer (pc, 1); 763 764 /* Check for retguard */ 765 if ((op == 0x4c || op == 0x48) && (current_pc > pc + 11)) 766 { 767 read_memory (pc + 1, buf, 10); 768 769 /* Check for `movq (__retguard_ ## x)(%rip), %reg;'. */ 770 if (buf[0] != 0x8b) 771 return pc; 772 773 /* Check for `xorq off(%rsp), %reg'. */ 774 if ((buf[6] != 0x4c && buf[6] != 0x48) 775 || buf[7] != 0x33 || buf[9] != 0x24) 776 return pc; 777 pc += 11; 778 op = read_memory_unsigned_integer (pc, 1); 779 } 780 781 if (op == 0x55) /* pushq %rbp */ 782 { 783 /* Take into account that we've executed the `pushq %rbp' that 784 starts this instruction sequence. */ 785 cache->saved_regs[AMD64_RBP_REGNUM] = 0; 786 cache->sp_offset += 8; 787 788 /* If that's all, return now. */ 789 if (current_pc <= pc + 1) 790 return current_pc; 791 792 /* Check for `movq %rsp, %rbp'. */ 793 read_memory (pc + 1, buf, 3); 794 if (memcmp (buf, proto, 3) != 0) 795 return pc + 1; 796 797 /* OK, we actually have a frame. */ 798 cache->frameless_p = 0; 799 return pc + 4; 800 } 801 802 return pc; 803} 804 805/* Return PC of first real instruction. */ 806 807static CORE_ADDR 808amd64_skip_prologue (CORE_ADDR start_pc) 809{ 810 struct amd64_frame_cache cache; 811 CORE_ADDR pc; 812 813 amd64_init_frame_cache (&cache); 814 pc = amd64_analyze_prologue (start_pc, 0xffffffffffffffffLL, &cache); 815 if (cache.frameless_p) 816 return start_pc; 817 818 return pc; 819} 820 821 822/* Normal frames. */ 823 824static struct amd64_frame_cache * 825amd64_frame_cache (struct frame_info *next_frame, void **this_cache) 826{ 827 struct amd64_frame_cache *cache; 828 char buf[8]; 829 int i; 830 831 if (*this_cache) 832 return *this_cache; 833 834 cache = amd64_alloc_frame_cache (); 835 *this_cache = cache; 836 837 cache->pc = frame_func_unwind (next_frame); 838 if (cache->pc != 0) 839 amd64_analyze_prologue (cache->pc, frame_pc_unwind (next_frame), cache); 840 841 if (cache->frameless_p) 842 { 843 /* We didn't find a valid frame. If we're at the start of a 844 function, or somewhere half-way its prologue, the function's 845 frame probably hasn't been fully setup yet. Try to 846 reconstruct the base address for the stack frame by looking 847 at the stack pointer. For truly "frameless" functions this 848 might work too. */ 849 850 frame_unwind_register (next_frame, AMD64_RSP_REGNUM, buf); 851 cache->base = extract_unsigned_integer (buf, 8) + cache->sp_offset; 852 } 853 else 854 { 855 frame_unwind_register (next_frame, AMD64_RBP_REGNUM, buf); 856 cache->base = extract_unsigned_integer (buf, 8); 857 } 858 859 /* Now that we have the base address for the stack frame we can 860 calculate the value of %rsp in the calling frame. */ 861 cache->saved_sp = cache->base + 16; 862 863 /* For normal frames, %rip is stored at 8(%rbp). If we don't have a 864 frame we find it at the same offset from the reconstructed base 865 address. */ 866 cache->saved_regs[AMD64_RIP_REGNUM] = 8; 867 868 /* Adjust all the saved registers such that they contain addresses 869 instead of offsets. */ 870 for (i = 0; i < AMD64_NUM_SAVED_REGS; i++) 871 if (cache->saved_regs[i] != -1) 872 cache->saved_regs[i] += cache->base; 873 874 return cache; 875} 876 877static void 878amd64_frame_this_id (struct frame_info *next_frame, void **this_cache, 879 struct frame_id *this_id) 880{ 881 struct amd64_frame_cache *cache = 882 amd64_frame_cache (next_frame, this_cache); 883 884 /* This marks the outermost frame. */ 885 if (cache->base == 0) 886 return; 887 888 (*this_id) = frame_id_build (cache->base + 16, cache->pc); 889} 890 891static void 892amd64_frame_prev_register (struct frame_info *next_frame, void **this_cache, 893 int regnum, int *optimizedp, 894 enum lval_type *lvalp, CORE_ADDR *addrp, 895 int *realnump, void *valuep) 896{ 897 struct amd64_frame_cache *cache = 898 amd64_frame_cache (next_frame, this_cache); 899 900 gdb_assert (regnum >= 0); 901 902 if (regnum == SP_REGNUM && cache->saved_sp) 903 { 904 *optimizedp = 0; 905 *lvalp = not_lval; 906 *addrp = 0; 907 *realnump = -1; 908 if (valuep) 909 { 910 /* Store the value. */ 911 store_unsigned_integer (valuep, 8, cache->saved_sp); 912 } 913 return; 914 } 915 916 if (regnum < AMD64_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1) 917 { 918 *optimizedp = 0; 919 *lvalp = lval_memory; 920 *addrp = cache->saved_regs[regnum]; 921 *realnump = -1; 922 if (valuep) 923 { 924 /* Read the value in from memory. */ 925 read_memory (*addrp, valuep, 926 register_size (current_gdbarch, regnum)); 927 } 928 return; 929 } 930 931 frame_register_unwind (next_frame, regnum, 932 optimizedp, lvalp, addrp, realnump, valuep); 933} 934 935static const struct frame_unwind amd64_frame_unwind = 936{ 937 NORMAL_FRAME, 938 amd64_frame_this_id, 939 amd64_frame_prev_register 940}; 941 942static const struct frame_unwind * 943amd64_frame_sniffer (struct frame_info *next_frame) 944{ 945 return &amd64_frame_unwind; 946} 947 948 949/* Signal trampolines. */ 950 951/* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and 952 64-bit variants. This would require using identical frame caches 953 on both platforms. */ 954 955static struct amd64_frame_cache * 956amd64_sigtramp_frame_cache (struct frame_info *next_frame, void **this_cache) 957{ 958 struct amd64_frame_cache *cache; 959 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); 960 CORE_ADDR addr; 961 char buf[8]; 962 int i; 963 964 if (*this_cache) 965 return *this_cache; 966 967 cache = amd64_alloc_frame_cache (); 968 969 frame_unwind_register (next_frame, AMD64_RSP_REGNUM, buf); 970 cache->base = extract_unsigned_integer (buf, 8) - 8; 971 972 addr = tdep->sigcontext_addr (next_frame); 973 gdb_assert (tdep->sc_reg_offset); 974 gdb_assert (tdep->sc_num_regs <= AMD64_NUM_SAVED_REGS); 975 for (i = 0; i < tdep->sc_num_regs; i++) 976 if (tdep->sc_reg_offset[i] != -1) 977 cache->saved_regs[i] = addr + tdep->sc_reg_offset[i]; 978 979 *this_cache = cache; 980 return cache; 981} 982 983static void 984amd64_sigtramp_frame_this_id (struct frame_info *next_frame, 985 void **this_cache, struct frame_id *this_id) 986{ 987 struct amd64_frame_cache *cache = 988 amd64_sigtramp_frame_cache (next_frame, this_cache); 989 990 (*this_id) = frame_id_build (cache->base + 16, frame_pc_unwind (next_frame)); 991} 992 993static void 994amd64_sigtramp_frame_prev_register (struct frame_info *next_frame, 995 void **this_cache, 996 int regnum, int *optimizedp, 997 enum lval_type *lvalp, CORE_ADDR *addrp, 998 int *realnump, void *valuep) 999{ 1000 /* Make sure we've initialized the cache. */ 1001 amd64_sigtramp_frame_cache (next_frame, this_cache); 1002 1003 amd64_frame_prev_register (next_frame, this_cache, regnum, 1004 optimizedp, lvalp, addrp, realnump, valuep); 1005} 1006 1007static const struct frame_unwind amd64_sigtramp_frame_unwind = 1008{ 1009 SIGTRAMP_FRAME, 1010 amd64_sigtramp_frame_this_id, 1011 amd64_sigtramp_frame_prev_register 1012}; 1013 1014static const struct frame_unwind * 1015amd64_sigtramp_frame_sniffer (struct frame_info *next_frame) 1016{ 1017 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (next_frame)); 1018 1019 /* We shouldn't even bother if we don't have a sigcontext_addr 1020 handler. */ 1021 if (tdep->sigcontext_addr == NULL) 1022 return NULL; 1023 1024 if (tdep->sigtramp_p != NULL) 1025 { 1026 if (tdep->sigtramp_p (next_frame)) 1027 return &amd64_sigtramp_frame_unwind; 1028 } 1029 1030 if (tdep->sigtramp_start != 0) 1031 { 1032 CORE_ADDR pc = frame_pc_unwind (next_frame); 1033 1034 gdb_assert (tdep->sigtramp_end != 0); 1035 if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end) 1036 return &amd64_sigtramp_frame_unwind; 1037 } 1038 1039 return NULL; 1040} 1041 1042 1043static CORE_ADDR 1044amd64_frame_base_address (struct frame_info *next_frame, void **this_cache) 1045{ 1046 struct amd64_frame_cache *cache = 1047 amd64_frame_cache (next_frame, this_cache); 1048 1049 return cache->base; 1050} 1051 1052static const struct frame_base amd64_frame_base = 1053{ 1054 &amd64_frame_unwind, 1055 amd64_frame_base_address, 1056 amd64_frame_base_address, 1057 amd64_frame_base_address 1058}; 1059 1060static struct frame_id 1061amd64_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) 1062{ 1063 char buf[8]; 1064 CORE_ADDR fp; 1065 1066 frame_unwind_register (next_frame, AMD64_RBP_REGNUM, buf); 1067 fp = extract_unsigned_integer (buf, 8); 1068 1069 return frame_id_build (fp + 16, frame_pc_unwind (next_frame)); 1070} 1071 1072/* 16 byte align the SP per frame requirements. */ 1073 1074static CORE_ADDR 1075amd64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) 1076{ 1077 return sp & -(CORE_ADDR)16; 1078} 1079 1080 1081/* Supply register REGNUM from the buffer specified by FPREGS and LEN 1082 in the floating-point register set REGSET to register cache 1083 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ 1084 1085static void 1086amd64_supply_fpregset (const struct regset *regset, struct regcache *regcache, 1087 int regnum, const void *fpregs, size_t len) 1088{ 1089 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); 1090 1091 gdb_assert (len == tdep->sizeof_fpregset); 1092 amd64_supply_fxsave (regcache, regnum, fpregs); 1093} 1094 1095/* Collect register REGNUM from the register cache REGCACHE and store 1096 it in the buffer specified by FPREGS and LEN as described by the 1097 floating-point register set REGSET. If REGNUM is -1, do this for 1098 all registers in REGSET. */ 1099 1100static void 1101amd64_collect_fpregset (const struct regset *regset, 1102 const struct regcache *regcache, 1103 int regnum, void *fpregs, size_t len) 1104{ 1105 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); 1106 1107 gdb_assert (len == tdep->sizeof_fpregset); 1108 amd64_collect_fxsave (regcache, regnum, fpregs); 1109} 1110 1111/* Return the appropriate register set for the core section identified 1112 by SECT_NAME and SECT_SIZE. */ 1113 1114static const struct regset * 1115amd64_regset_from_core_section (struct gdbarch *gdbarch, 1116 const char *sect_name, size_t sect_size) 1117{ 1118 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 1119 1120 if (strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset) 1121 { 1122 if (tdep->fpregset == NULL) 1123 tdep->fpregset = regset_alloc (gdbarch, amd64_supply_fpregset, 1124 amd64_collect_fpregset); 1125 1126 return tdep->fpregset; 1127 } 1128 1129 return i386_regset_from_core_section (gdbarch, sect_name, sect_size); 1130} 1131 1132 1133void 1134amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) 1135{ 1136 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 1137 1138 /* AMD64 generally uses `fxsave' instead of `fsave' for saving its 1139 floating-point registers. */ 1140 tdep->sizeof_fpregset = I387_SIZEOF_FXSAVE; 1141 1142 /* AMD64 has an FPU and 16 SSE registers. */ 1143 tdep->st0_regnum = AMD64_ST0_REGNUM; 1144 tdep->num_xmm_regs = 16; 1145 1146 /* This is what all the fuss is about. */ 1147 set_gdbarch_long_bit (gdbarch, 64); 1148 set_gdbarch_long_long_bit (gdbarch, 64); 1149 set_gdbarch_ptr_bit (gdbarch, 64); 1150 1151 /* In contrast to the i386, on AMD64 a `long double' actually takes 1152 up 128 bits, even though it's still based on the i387 extended 1153 floating-point format which has only 80 significant bits. */ 1154 set_gdbarch_long_double_bit (gdbarch, 128); 1155 1156 set_gdbarch_num_regs (gdbarch, AMD64_NUM_REGS); 1157 set_gdbarch_register_name (gdbarch, amd64_register_name); 1158 set_gdbarch_register_type (gdbarch, amd64_register_type); 1159 1160 /* Register numbers of various important registers. */ 1161 set_gdbarch_sp_regnum (gdbarch, AMD64_RSP_REGNUM); /* %rsp */ 1162 set_gdbarch_pc_regnum (gdbarch, AMD64_RIP_REGNUM); /* %rip */ 1163 set_gdbarch_ps_regnum (gdbarch, AMD64_EFLAGS_REGNUM); /* %eflags */ 1164 set_gdbarch_fp0_regnum (gdbarch, AMD64_ST0_REGNUM); /* %st(0) */ 1165 1166 /* The "default" register numbering scheme for AMD64 is referred to 1167 as the "DWARF Register Number Mapping" in the System V psABI. 1168 The preferred debugging format for all known AMD64 targets is 1169 actually DWARF2, and GCC doesn't seem to support DWARF (that is 1170 DWARF-1), but we provide the same mapping just in case. This 1171 mapping is also used for stabs, which GCC does support. */ 1172 set_gdbarch_stab_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum); 1173 set_gdbarch_dwarf_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum); 1174 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum); 1175 1176 /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to 1177 be in use on any of the supported AMD64 targets. */ 1178 1179 /* Call dummy code. */ 1180 set_gdbarch_push_dummy_call (gdbarch, amd64_push_dummy_call); 1181 set_gdbarch_frame_align (gdbarch, amd64_frame_align); 1182 set_gdbarch_frame_red_zone_size (gdbarch, 128); 1183 1184 set_gdbarch_convert_register_p (gdbarch, amd64_convert_register_p); 1185 set_gdbarch_register_to_value (gdbarch, i387_register_to_value); 1186 set_gdbarch_value_to_register (gdbarch, i387_value_to_register); 1187 1188 set_gdbarch_return_value (gdbarch, amd64_return_value); 1189 1190 set_gdbarch_skip_prologue (gdbarch, amd64_skip_prologue); 1191 1192 /* Avoid wiring in the MMX registers for now. */ 1193 set_gdbarch_num_pseudo_regs (gdbarch, 0); 1194 tdep->mm0_regnum = -1; 1195 1196 set_gdbarch_unwind_dummy_id (gdbarch, amd64_unwind_dummy_id); 1197 1198 /* FIXME: kettenis/20021026: This is ELF-specific. Fine for now, 1199 since all supported AMD64 targets are ELF, but that might change 1200 in the future. */ 1201 set_gdbarch_in_solib_call_trampoline (gdbarch, in_plt_section); 1202 1203 frame_unwind_append_sniffer (gdbarch, amd64_sigtramp_frame_sniffer); 1204 frame_unwind_append_sniffer (gdbarch, amd64_frame_sniffer); 1205 frame_base_set_default (gdbarch, &amd64_frame_base); 1206 1207 /* If we have a register mapping, enable the generic core file support. */ 1208 if (tdep->gregset_reg_offset) 1209 set_gdbarch_regset_from_core_section (gdbarch, 1210 amd64_regset_from_core_section); 1211} 1212 1213 1214#define I387_ST0_REGNUM AMD64_ST0_REGNUM 1215 1216/* The 64-bit FXSAVE format differs from the 32-bit format in the 1217 sense that the instruction pointer and data pointer are simply 1218 64-bit offsets into the code segment and the data segment instead 1219 of a selector offset pair. The functions below store the upper 32 1220 bits of these pointers (instead of just the 16-bits of the segment 1221 selector). */ 1222 1223/* Fill register REGNUM in REGCACHE with the appropriate 1224 floating-point or SSE register value from *FXSAVE. If REGNUM is 1225 -1, do this for all registers. This function masks off any of the 1226 reserved bits in *FXSAVE. */ 1227 1228void 1229amd64_supply_fxsave (struct regcache *regcache, int regnum, 1230 const void *fxsave) 1231{ 1232 i387_supply_fxsave (regcache, regnum, fxsave); 1233 1234 if (fxsave && gdbarch_ptr_bit (get_regcache_arch (regcache)) == 64) 1235 { 1236 const char *regs = fxsave; 1237 1238 if (regnum == -1 || regnum == I387_FISEG_REGNUM) 1239 regcache_raw_supply (regcache, I387_FISEG_REGNUM, regs + 12); 1240 if (regnum == -1 || regnum == I387_FOSEG_REGNUM) 1241 regcache_raw_supply (regcache, I387_FOSEG_REGNUM, regs + 20); 1242 } 1243} 1244 1245/* Fill register REGNUM (if it is a floating-point or SSE register) in 1246 *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for 1247 all registers. This function doesn't touch any of the reserved 1248 bits in *FXSAVE. */ 1249 1250void 1251amd64_collect_fxsave (const struct regcache *regcache, int regnum, 1252 void *fxsave) 1253{ 1254 char *regs = fxsave; 1255 1256 i387_collect_fxsave (regcache, regnum, fxsave); 1257 1258 if (gdbarch_ptr_bit (get_regcache_arch (regcache)) == 64) 1259 { 1260 if (regnum == -1 || regnum == I387_FISEG_REGNUM) 1261 regcache_raw_collect (regcache, I387_FISEG_REGNUM, regs + 12); 1262 if (regnum == -1 || regnum == I387_FOSEG_REGNUM) 1263 regcache_raw_collect (regcache, I387_FOSEG_REGNUM, regs + 20); 1264 } 1265} 1266