1/* BFD back-end for Renesas Super-H COFF binaries. 2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 3 Free Software Foundation, Inc. 4 Contributed by Cygnus Support. 5 Written by Steve Chamberlain, <sac@cygnus.com>. 6 Relaxing code written by Ian Lance Taylor, <ian@cygnus.com>. 7 8 This file is part of BFD, the Binary File Descriptor library. 9 10 This program is free software; you can redistribute it and/or modify 11 it under the terms of the GNU General Public License as published by 12 the Free Software Foundation; either version 2 of the License, or 13 (at your option) any later version. 14 15 This program is distributed in the hope that it will be useful, 16 but WITHOUT ANY WARRANTY; without even the implied warranty of 17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 GNU General Public License for more details. 19 20 You should have received a copy of the GNU General Public License 21 along with this program; if not, write to the Free Software 22 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ 23 24#include "bfd.h" 25#include "sysdep.h" 26#include "libiberty.h" 27#include "libbfd.h" 28#include "bfdlink.h" 29#include "coff/sh.h" 30#include "coff/internal.h" 31 32#ifdef COFF_WITH_PE 33#include "coff/pe.h" 34 35#ifndef COFF_IMAGE_WITH_PE 36static bfd_boolean sh_align_load_span 37 PARAMS ((bfd *, asection *, bfd_byte *, 38 bfd_boolean (*) (bfd *, asection *, PTR, bfd_byte *, bfd_vma), 39 PTR, bfd_vma **, bfd_vma *, bfd_vma, bfd_vma, bfd_boolean *)); 40 41#define _bfd_sh_align_load_span sh_align_load_span 42#endif 43#endif 44 45#include "libcoff.h" 46 47/* Internal functions. */ 48static bfd_reloc_status_type sh_reloc 49 PARAMS ((bfd *, arelent *, asymbol *, PTR, asection *, bfd *, char **)); 50static long get_symbol_value PARAMS ((asymbol *)); 51static bfd_boolean sh_relax_section 52 PARAMS ((bfd *, asection *, struct bfd_link_info *, bfd_boolean *)); 53static bfd_boolean sh_relax_delete_bytes 54 PARAMS ((bfd *, asection *, bfd_vma, int)); 55#ifndef COFF_IMAGE_WITH_PE 56static const struct sh_opcode *sh_insn_info PARAMS ((unsigned int)); 57#endif 58static bfd_boolean sh_align_loads 59 PARAMS ((bfd *, asection *, struct internal_reloc *, bfd_byte *, 60 bfd_boolean *)); 61static bfd_boolean sh_swap_insns 62 PARAMS ((bfd *, asection *, PTR, bfd_byte *, bfd_vma)); 63static bfd_boolean sh_relocate_section 64 PARAMS ((bfd *, struct bfd_link_info *, bfd *, asection *, bfd_byte *, 65 struct internal_reloc *, struct internal_syment *, asection **)); 66static bfd_byte *sh_coff_get_relocated_section_contents 67 PARAMS ((bfd *, struct bfd_link_info *, struct bfd_link_order *, 68 bfd_byte *, bfd_boolean, asymbol **)); 69static reloc_howto_type * sh_coff_reloc_type_lookup PARAMS ((bfd *, bfd_reloc_code_real_type)); 70 71#ifdef COFF_WITH_PE 72/* Can't build import tables with 2**4 alignment. */ 73#define COFF_DEFAULT_SECTION_ALIGNMENT_POWER 2 74#else 75/* Default section alignment to 2**4. */ 76#define COFF_DEFAULT_SECTION_ALIGNMENT_POWER 4 77#endif 78 79#ifdef COFF_IMAGE_WITH_PE 80/* Align PE executables. */ 81#define COFF_PAGE_SIZE 0x1000 82#endif 83 84/* Generate long file names. */ 85#define COFF_LONG_FILENAMES 86 87#ifdef COFF_WITH_PE 88static bfd_boolean in_reloc_p PARAMS ((bfd *, reloc_howto_type *)); 89/* Return TRUE if this relocation should 90 appear in the output .reloc section. */ 91static bfd_boolean in_reloc_p (abfd, howto) 92 bfd * abfd ATTRIBUTE_UNUSED; 93 reloc_howto_type * howto; 94{ 95 return ! howto->pc_relative && howto->type != R_SH_IMAGEBASE; 96} 97#endif 98 99/* The supported relocations. There are a lot of relocations defined 100 in coff/internal.h which we do not expect to ever see. */ 101static reloc_howto_type sh_coff_howtos[] = 102{ 103 EMPTY_HOWTO (0), 104 EMPTY_HOWTO (1), 105#ifdef COFF_WITH_PE 106 /* Windows CE */ 107 HOWTO (R_SH_IMM32CE, /* type */ 108 0, /* rightshift */ 109 2, /* size (0 = byte, 1 = short, 2 = long) */ 110 32, /* bitsize */ 111 FALSE, /* pc_relative */ 112 0, /* bitpos */ 113 complain_overflow_bitfield, /* complain_on_overflow */ 114 sh_reloc, /* special_function */ 115 "r_imm32ce", /* name */ 116 TRUE, /* partial_inplace */ 117 0xffffffff, /* src_mask */ 118 0xffffffff, /* dst_mask */ 119 FALSE), /* pcrel_offset */ 120#else 121 EMPTY_HOWTO (2), 122#endif 123 EMPTY_HOWTO (3), /* R_SH_PCREL8 */ 124 EMPTY_HOWTO (4), /* R_SH_PCREL16 */ 125 EMPTY_HOWTO (5), /* R_SH_HIGH8 */ 126 EMPTY_HOWTO (6), /* R_SH_IMM24 */ 127 EMPTY_HOWTO (7), /* R_SH_LOW16 */ 128 EMPTY_HOWTO (8), 129 EMPTY_HOWTO (9), /* R_SH_PCDISP8BY4 */ 130 131 HOWTO (R_SH_PCDISP8BY2, /* type */ 132 1, /* rightshift */ 133 1, /* size (0 = byte, 1 = short, 2 = long) */ 134 8, /* bitsize */ 135 TRUE, /* pc_relative */ 136 0, /* bitpos */ 137 complain_overflow_signed, /* complain_on_overflow */ 138 sh_reloc, /* special_function */ 139 "r_pcdisp8by2", /* name */ 140 TRUE, /* partial_inplace */ 141 0xff, /* src_mask */ 142 0xff, /* dst_mask */ 143 TRUE), /* pcrel_offset */ 144 145 EMPTY_HOWTO (11), /* R_SH_PCDISP8 */ 146 147 HOWTO (R_SH_PCDISP, /* type */ 148 1, /* rightshift */ 149 1, /* size (0 = byte, 1 = short, 2 = long) */ 150 12, /* bitsize */ 151 TRUE, /* pc_relative */ 152 0, /* bitpos */ 153 complain_overflow_signed, /* complain_on_overflow */ 154 sh_reloc, /* special_function */ 155 "r_pcdisp12by2", /* name */ 156 TRUE, /* partial_inplace */ 157 0xfff, /* src_mask */ 158 0xfff, /* dst_mask */ 159 TRUE), /* pcrel_offset */ 160 161 EMPTY_HOWTO (13), 162 163 HOWTO (R_SH_IMM32, /* type */ 164 0, /* rightshift */ 165 2, /* size (0 = byte, 1 = short, 2 = long) */ 166 32, /* bitsize */ 167 FALSE, /* pc_relative */ 168 0, /* bitpos */ 169 complain_overflow_bitfield, /* complain_on_overflow */ 170 sh_reloc, /* special_function */ 171 "r_imm32", /* name */ 172 TRUE, /* partial_inplace */ 173 0xffffffff, /* src_mask */ 174 0xffffffff, /* dst_mask */ 175 FALSE), /* pcrel_offset */ 176 177 EMPTY_HOWTO (15), 178#ifdef COFF_WITH_PE 179 HOWTO (R_SH_IMAGEBASE, /* type */ 180 0, /* rightshift */ 181 2, /* size (0 = byte, 1 = short, 2 = long) */ 182 32, /* bitsize */ 183 FALSE, /* pc_relative */ 184 0, /* bitpos */ 185 complain_overflow_bitfield, /* complain_on_overflow */ 186 sh_reloc, /* special_function */ 187 "rva32", /* name */ 188 TRUE, /* partial_inplace */ 189 0xffffffff, /* src_mask */ 190 0xffffffff, /* dst_mask */ 191 FALSE), /* pcrel_offset */ 192#else 193 EMPTY_HOWTO (16), /* R_SH_IMM8 */ 194#endif 195 EMPTY_HOWTO (17), /* R_SH_IMM8BY2 */ 196 EMPTY_HOWTO (18), /* R_SH_IMM8BY4 */ 197 EMPTY_HOWTO (19), /* R_SH_IMM4 */ 198 EMPTY_HOWTO (20), /* R_SH_IMM4BY2 */ 199 EMPTY_HOWTO (21), /* R_SH_IMM4BY4 */ 200 201 HOWTO (R_SH_PCRELIMM8BY2, /* type */ 202 1, /* rightshift */ 203 1, /* size (0 = byte, 1 = short, 2 = long) */ 204 8, /* bitsize */ 205 TRUE, /* pc_relative */ 206 0, /* bitpos */ 207 complain_overflow_unsigned, /* complain_on_overflow */ 208 sh_reloc, /* special_function */ 209 "r_pcrelimm8by2", /* name */ 210 TRUE, /* partial_inplace */ 211 0xff, /* src_mask */ 212 0xff, /* dst_mask */ 213 TRUE), /* pcrel_offset */ 214 215 HOWTO (R_SH_PCRELIMM8BY4, /* type */ 216 2, /* rightshift */ 217 1, /* size (0 = byte, 1 = short, 2 = long) */ 218 8, /* bitsize */ 219 TRUE, /* pc_relative */ 220 0, /* bitpos */ 221 complain_overflow_unsigned, /* complain_on_overflow */ 222 sh_reloc, /* special_function */ 223 "r_pcrelimm8by4", /* name */ 224 TRUE, /* partial_inplace */ 225 0xff, /* src_mask */ 226 0xff, /* dst_mask */ 227 TRUE), /* pcrel_offset */ 228 229 HOWTO (R_SH_IMM16, /* type */ 230 0, /* rightshift */ 231 1, /* size (0 = byte, 1 = short, 2 = long) */ 232 16, /* bitsize */ 233 FALSE, /* pc_relative */ 234 0, /* bitpos */ 235 complain_overflow_bitfield, /* complain_on_overflow */ 236 sh_reloc, /* special_function */ 237 "r_imm16", /* name */ 238 TRUE, /* partial_inplace */ 239 0xffff, /* src_mask */ 240 0xffff, /* dst_mask */ 241 FALSE), /* pcrel_offset */ 242 243 HOWTO (R_SH_SWITCH16, /* type */ 244 0, /* rightshift */ 245 1, /* size (0 = byte, 1 = short, 2 = long) */ 246 16, /* bitsize */ 247 FALSE, /* pc_relative */ 248 0, /* bitpos */ 249 complain_overflow_bitfield, /* complain_on_overflow */ 250 sh_reloc, /* special_function */ 251 "r_switch16", /* name */ 252 TRUE, /* partial_inplace */ 253 0xffff, /* src_mask */ 254 0xffff, /* dst_mask */ 255 FALSE), /* pcrel_offset */ 256 257 HOWTO (R_SH_SWITCH32, /* type */ 258 0, /* rightshift */ 259 2, /* size (0 = byte, 1 = short, 2 = long) */ 260 32, /* bitsize */ 261 FALSE, /* pc_relative */ 262 0, /* bitpos */ 263 complain_overflow_bitfield, /* complain_on_overflow */ 264 sh_reloc, /* special_function */ 265 "r_switch32", /* name */ 266 TRUE, /* partial_inplace */ 267 0xffffffff, /* src_mask */ 268 0xffffffff, /* dst_mask */ 269 FALSE), /* pcrel_offset */ 270 271 HOWTO (R_SH_USES, /* type */ 272 0, /* rightshift */ 273 1, /* size (0 = byte, 1 = short, 2 = long) */ 274 16, /* bitsize */ 275 FALSE, /* pc_relative */ 276 0, /* bitpos */ 277 complain_overflow_bitfield, /* complain_on_overflow */ 278 sh_reloc, /* special_function */ 279 "r_uses", /* name */ 280 TRUE, /* partial_inplace */ 281 0xffff, /* src_mask */ 282 0xffff, /* dst_mask */ 283 FALSE), /* pcrel_offset */ 284 285 HOWTO (R_SH_COUNT, /* type */ 286 0, /* rightshift */ 287 2, /* size (0 = byte, 1 = short, 2 = long) */ 288 32, /* bitsize */ 289 FALSE, /* pc_relative */ 290 0, /* bitpos */ 291 complain_overflow_bitfield, /* complain_on_overflow */ 292 sh_reloc, /* special_function */ 293 "r_count", /* name */ 294 TRUE, /* partial_inplace */ 295 0xffffffff, /* src_mask */ 296 0xffffffff, /* dst_mask */ 297 FALSE), /* pcrel_offset */ 298 299 HOWTO (R_SH_ALIGN, /* type */ 300 0, /* rightshift */ 301 2, /* size (0 = byte, 1 = short, 2 = long) */ 302 32, /* bitsize */ 303 FALSE, /* pc_relative */ 304 0, /* bitpos */ 305 complain_overflow_bitfield, /* complain_on_overflow */ 306 sh_reloc, /* special_function */ 307 "r_align", /* name */ 308 TRUE, /* partial_inplace */ 309 0xffffffff, /* src_mask */ 310 0xffffffff, /* dst_mask */ 311 FALSE), /* pcrel_offset */ 312 313 HOWTO (R_SH_CODE, /* type */ 314 0, /* rightshift */ 315 2, /* size (0 = byte, 1 = short, 2 = long) */ 316 32, /* bitsize */ 317 FALSE, /* pc_relative */ 318 0, /* bitpos */ 319 complain_overflow_bitfield, /* complain_on_overflow */ 320 sh_reloc, /* special_function */ 321 "r_code", /* name */ 322 TRUE, /* partial_inplace */ 323 0xffffffff, /* src_mask */ 324 0xffffffff, /* dst_mask */ 325 FALSE), /* pcrel_offset */ 326 327 HOWTO (R_SH_DATA, /* type */ 328 0, /* rightshift */ 329 2, /* size (0 = byte, 1 = short, 2 = long) */ 330 32, /* bitsize */ 331 FALSE, /* pc_relative */ 332 0, /* bitpos */ 333 complain_overflow_bitfield, /* complain_on_overflow */ 334 sh_reloc, /* special_function */ 335 "r_data", /* name */ 336 TRUE, /* partial_inplace */ 337 0xffffffff, /* src_mask */ 338 0xffffffff, /* dst_mask */ 339 FALSE), /* pcrel_offset */ 340 341 HOWTO (R_SH_LABEL, /* type */ 342 0, /* rightshift */ 343 2, /* size (0 = byte, 1 = short, 2 = long) */ 344 32, /* bitsize */ 345 FALSE, /* pc_relative */ 346 0, /* bitpos */ 347 complain_overflow_bitfield, /* complain_on_overflow */ 348 sh_reloc, /* special_function */ 349 "r_label", /* name */ 350 TRUE, /* partial_inplace */ 351 0xffffffff, /* src_mask */ 352 0xffffffff, /* dst_mask */ 353 FALSE), /* pcrel_offset */ 354 355 HOWTO (R_SH_SWITCH8, /* type */ 356 0, /* rightshift */ 357 0, /* size (0 = byte, 1 = short, 2 = long) */ 358 8, /* bitsize */ 359 FALSE, /* pc_relative */ 360 0, /* bitpos */ 361 complain_overflow_bitfield, /* complain_on_overflow */ 362 sh_reloc, /* special_function */ 363 "r_switch8", /* name */ 364 TRUE, /* partial_inplace */ 365 0xff, /* src_mask */ 366 0xff, /* dst_mask */ 367 FALSE) /* pcrel_offset */ 368}; 369 370#define SH_COFF_HOWTO_COUNT (sizeof sh_coff_howtos / sizeof sh_coff_howtos[0]) 371 372/* Check for a bad magic number. */ 373#define BADMAG(x) SHBADMAG(x) 374 375/* Customize coffcode.h (this is not currently used). */ 376#define SH 1 377 378/* FIXME: This should not be set here. */ 379#define __A_MAGIC_SET__ 380 381#ifndef COFF_WITH_PE 382/* Swap the r_offset field in and out. */ 383#define SWAP_IN_RELOC_OFFSET H_GET_32 384#define SWAP_OUT_RELOC_OFFSET H_PUT_32 385 386/* Swap out extra information in the reloc structure. */ 387#define SWAP_OUT_RELOC_EXTRA(abfd, src, dst) \ 388 do \ 389 { \ 390 dst->r_stuff[0] = 'S'; \ 391 dst->r_stuff[1] = 'C'; \ 392 } \ 393 while (0) 394#endif 395 396/* Get the value of a symbol, when performing a relocation. */ 397 398static long 399get_symbol_value (symbol) 400 asymbol *symbol; 401{ 402 bfd_vma relocation; 403 404 if (bfd_is_com_section (symbol->section)) 405 relocation = 0; 406 else 407 relocation = (symbol->value + 408 symbol->section->output_section->vma + 409 symbol->section->output_offset); 410 411 return relocation; 412} 413 414#ifdef COFF_WITH_PE 415/* Convert an rtype to howto for the COFF backend linker. 416 Copied from coff-i386. */ 417#define coff_rtype_to_howto coff_sh_rtype_to_howto 418static reloc_howto_type * coff_sh_rtype_to_howto PARAMS ((bfd *, asection *, struct internal_reloc *, struct coff_link_hash_entry *, struct internal_syment *, bfd_vma *)); 419 420static reloc_howto_type * 421coff_sh_rtype_to_howto (abfd, sec, rel, h, sym, addendp) 422 bfd * abfd ATTRIBUTE_UNUSED; 423 asection * sec; 424 struct internal_reloc * rel; 425 struct coff_link_hash_entry * h; 426 struct internal_syment * sym; 427 bfd_vma * addendp; 428{ 429 reloc_howto_type * howto; 430 431 howto = sh_coff_howtos + rel->r_type; 432 433 *addendp = 0; 434 435 if (howto->pc_relative) 436 *addendp += sec->vma; 437 438 if (sym != NULL && sym->n_scnum == 0 && sym->n_value != 0) 439 { 440 /* This is a common symbol. The section contents include the 441 size (sym->n_value) as an addend. The relocate_section 442 function will be adding in the final value of the symbol. We 443 need to subtract out the current size in order to get the 444 correct result. */ 445 BFD_ASSERT (h != NULL); 446 } 447 448 if (howto->pc_relative) 449 { 450 *addendp -= 4; 451 452 /* If the symbol is defined, then the generic code is going to 453 add back the symbol value in order to cancel out an 454 adjustment it made to the addend. However, we set the addend 455 to 0 at the start of this function. We need to adjust here, 456 to avoid the adjustment the generic code will make. FIXME: 457 This is getting a bit hackish. */ 458 if (sym != NULL && sym->n_scnum != 0) 459 *addendp -= sym->n_value; 460 } 461 462 if (rel->r_type == R_SH_IMAGEBASE) 463 *addendp -= pe_data (sec->output_section->owner)->pe_opthdr.ImageBase; 464 465 return howto; 466} 467 468#endif /* COFF_WITH_PE */ 469 470/* This structure is used to map BFD reloc codes to SH PE relocs. */ 471struct shcoff_reloc_map 472{ 473 bfd_reloc_code_real_type bfd_reloc_val; 474 unsigned char shcoff_reloc_val; 475}; 476 477#ifdef COFF_WITH_PE 478/* An array mapping BFD reloc codes to SH PE relocs. */ 479static const struct shcoff_reloc_map sh_reloc_map[] = 480{ 481 { BFD_RELOC_32, R_SH_IMM32CE }, 482 { BFD_RELOC_RVA, R_SH_IMAGEBASE }, 483 { BFD_RELOC_CTOR, R_SH_IMM32CE }, 484}; 485#else 486/* An array mapping BFD reloc codes to SH PE relocs. */ 487static const struct shcoff_reloc_map sh_reloc_map[] = 488{ 489 { BFD_RELOC_32, R_SH_IMM32 }, 490 { BFD_RELOC_CTOR, R_SH_IMM32 }, 491}; 492#endif 493 494/* Given a BFD reloc code, return the howto structure for the 495 corresponding SH PE reloc. */ 496#define coff_bfd_reloc_type_lookup sh_coff_reloc_type_lookup 497 498static reloc_howto_type * 499sh_coff_reloc_type_lookup (abfd, code) 500 bfd * abfd ATTRIBUTE_UNUSED; 501 bfd_reloc_code_real_type code; 502{ 503 unsigned int i; 504 505 for (i = ARRAY_SIZE (sh_reloc_map); i--;) 506 if (sh_reloc_map[i].bfd_reloc_val == code) 507 return &sh_coff_howtos[(int) sh_reloc_map[i].shcoff_reloc_val]; 508 509 fprintf (stderr, "SH Error: unknown reloc type %d\n", code); 510 return NULL; 511} 512 513/* This macro is used in coffcode.h to get the howto corresponding to 514 an internal reloc. */ 515 516#define RTYPE2HOWTO(relent, internal) \ 517 ((relent)->howto = \ 518 ((internal)->r_type < SH_COFF_HOWTO_COUNT \ 519 ? &sh_coff_howtos[(internal)->r_type] \ 520 : (reloc_howto_type *) NULL)) 521 522/* This is the same as the macro in coffcode.h, except that it copies 523 r_offset into reloc_entry->addend for some relocs. */ 524#define CALC_ADDEND(abfd, ptr, reloc, cache_ptr) \ 525 { \ 526 coff_symbol_type *coffsym = (coff_symbol_type *) NULL; \ 527 if (ptr && bfd_asymbol_bfd (ptr) != abfd) \ 528 coffsym = (obj_symbols (abfd) \ 529 + (cache_ptr->sym_ptr_ptr - symbols)); \ 530 else if (ptr) \ 531 coffsym = coff_symbol_from (abfd, ptr); \ 532 if (coffsym != (coff_symbol_type *) NULL \ 533 && coffsym->native->u.syment.n_scnum == 0) \ 534 cache_ptr->addend = 0; \ 535 else if (ptr && bfd_asymbol_bfd (ptr) == abfd \ 536 && ptr->section != (asection *) NULL) \ 537 cache_ptr->addend = - (ptr->section->vma + ptr->value); \ 538 else \ 539 cache_ptr->addend = 0; \ 540 if ((reloc).r_type == R_SH_SWITCH8 \ 541 || (reloc).r_type == R_SH_SWITCH16 \ 542 || (reloc).r_type == R_SH_SWITCH32 \ 543 || (reloc).r_type == R_SH_USES \ 544 || (reloc).r_type == R_SH_COUNT \ 545 || (reloc).r_type == R_SH_ALIGN) \ 546 cache_ptr->addend = (reloc).r_offset; \ 547 } 548 549/* This is the howto function for the SH relocations. */ 550 551static bfd_reloc_status_type 552sh_reloc (abfd, reloc_entry, symbol_in, data, input_section, output_bfd, 553 error_message) 554 bfd *abfd; 555 arelent *reloc_entry; 556 asymbol *symbol_in; 557 PTR data; 558 asection *input_section; 559 bfd *output_bfd; 560 char **error_message ATTRIBUTE_UNUSED; 561{ 562 unsigned long insn; 563 bfd_vma sym_value; 564 unsigned short r_type; 565 bfd_vma addr = reloc_entry->address; 566 bfd_byte *hit_data = addr + (bfd_byte *) data; 567 568 r_type = reloc_entry->howto->type; 569 570 if (output_bfd != NULL) 571 { 572 /* Partial linking--do nothing. */ 573 reloc_entry->address += input_section->output_offset; 574 return bfd_reloc_ok; 575 } 576 577 /* Almost all relocs have to do with relaxing. If any work must be 578 done for them, it has been done in sh_relax_section. */ 579 if (r_type != R_SH_IMM32 580#ifdef COFF_WITH_PE 581 && r_type != R_SH_IMM32CE 582 && r_type != R_SH_IMAGEBASE 583#endif 584 && (r_type != R_SH_PCDISP 585 || (symbol_in->flags & BSF_LOCAL) != 0)) 586 return bfd_reloc_ok; 587 588 if (symbol_in != NULL 589 && bfd_is_und_section (symbol_in->section)) 590 return bfd_reloc_undefined; 591 592 sym_value = get_symbol_value (symbol_in); 593 594 switch (r_type) 595 { 596 case R_SH_IMM32: 597#ifdef COFF_WITH_PE 598 case R_SH_IMM32CE: 599#endif 600 insn = bfd_get_32 (abfd, hit_data); 601 insn += sym_value + reloc_entry->addend; 602 bfd_put_32 (abfd, (bfd_vma) insn, hit_data); 603 break; 604#ifdef COFF_WITH_PE 605 case R_SH_IMAGEBASE: 606 insn = bfd_get_32 (abfd, hit_data); 607 insn += sym_value + reloc_entry->addend; 608 insn -= pe_data (input_section->output_section->owner)->pe_opthdr.ImageBase; 609 bfd_put_32 (abfd, (bfd_vma) insn, hit_data); 610 break; 611#endif 612 case R_SH_PCDISP: 613 insn = bfd_get_16 (abfd, hit_data); 614 sym_value += reloc_entry->addend; 615 sym_value -= (input_section->output_section->vma 616 + input_section->output_offset 617 + addr 618 + 4); 619 sym_value += (insn & 0xfff) << 1; 620 if (insn & 0x800) 621 sym_value -= 0x1000; 622 insn = (insn & 0xf000) | (sym_value & 0xfff); 623 bfd_put_16 (abfd, (bfd_vma) insn, hit_data); 624 if (sym_value < (bfd_vma) -0x1000 || sym_value >= 0x1000) 625 return bfd_reloc_overflow; 626 break; 627 default: 628 abort (); 629 break; 630 } 631 632 return bfd_reloc_ok; 633} 634 635#define coff_bfd_merge_private_bfd_data _bfd_generic_verify_endian_match 636 637/* We can do relaxing. */ 638#define coff_bfd_relax_section sh_relax_section 639 640/* We use the special COFF backend linker. */ 641#define coff_relocate_section sh_relocate_section 642 643/* When relaxing, we need to use special code to get the relocated 644 section contents. */ 645#define coff_bfd_get_relocated_section_contents \ 646 sh_coff_get_relocated_section_contents 647 648#include "coffcode.h" 649 650/* This function handles relaxing on the SH. 651 652 Function calls on the SH look like this: 653 654 movl L1,r0 655 ... 656 jsr @r0 657 ... 658 L1: 659 .long function 660 661 The compiler and assembler will cooperate to create R_SH_USES 662 relocs on the jsr instructions. The r_offset field of the 663 R_SH_USES reloc is the PC relative offset to the instruction which 664 loads the register (the r_offset field is computed as though it 665 were a jump instruction, so the offset value is actually from four 666 bytes past the instruction). The linker can use this reloc to 667 determine just which function is being called, and thus decide 668 whether it is possible to replace the jsr with a bsr. 669 670 If multiple function calls are all based on a single register load 671 (i.e., the same function is called multiple times), the compiler 672 guarantees that each function call will have an R_SH_USES reloc. 673 Therefore, if the linker is able to convert each R_SH_USES reloc 674 which refers to that address, it can safely eliminate the register 675 load. 676 677 When the assembler creates an R_SH_USES reloc, it examines it to 678 determine which address is being loaded (L1 in the above example). 679 It then counts the number of references to that address, and 680 creates an R_SH_COUNT reloc at that address. The r_offset field of 681 the R_SH_COUNT reloc will be the number of references. If the 682 linker is able to eliminate a register load, it can use the 683 R_SH_COUNT reloc to see whether it can also eliminate the function 684 address. 685 686 SH relaxing also handles another, unrelated, matter. On the SH, if 687 a load or store instruction is not aligned on a four byte boundary, 688 the memory cycle interferes with the 32 bit instruction fetch, 689 causing a one cycle bubble in the pipeline. Therefore, we try to 690 align load and store instructions on four byte boundaries if we 691 can, by swapping them with one of the adjacent instructions. */ 692 693static bfd_boolean 694sh_relax_section (abfd, sec, link_info, again) 695 bfd *abfd; 696 asection *sec; 697 struct bfd_link_info *link_info; 698 bfd_boolean *again; 699{ 700 struct internal_reloc *internal_relocs; 701 struct internal_reloc *free_relocs = NULL; 702 bfd_boolean have_code; 703 struct internal_reloc *irel, *irelend; 704 bfd_byte *contents = NULL; 705 bfd_byte *free_contents = NULL; 706 707 *again = FALSE; 708 709 if (link_info->relocatable 710 || (sec->flags & SEC_RELOC) == 0 711 || sec->reloc_count == 0) 712 return TRUE; 713 714 /* If this is the first time we have been called for this section, 715 initialize the cooked size. */ 716 if (sec->_cooked_size == 0) 717 sec->_cooked_size = sec->_raw_size; 718 719 internal_relocs = (_bfd_coff_read_internal_relocs 720 (abfd, sec, link_info->keep_memory, 721 (bfd_byte *) NULL, FALSE, 722 (struct internal_reloc *) NULL)); 723 if (internal_relocs == NULL) 724 goto error_return; 725 if (! link_info->keep_memory) 726 free_relocs = internal_relocs; 727 728 have_code = FALSE; 729 730 irelend = internal_relocs + sec->reloc_count; 731 for (irel = internal_relocs; irel < irelend; irel++) 732 { 733 bfd_vma laddr, paddr, symval; 734 unsigned short insn; 735 struct internal_reloc *irelfn, *irelscan, *irelcount; 736 struct internal_syment sym; 737 bfd_signed_vma foff; 738 739 if (irel->r_type == R_SH_CODE) 740 have_code = TRUE; 741 742 if (irel->r_type != R_SH_USES) 743 continue; 744 745 /* Get the section contents. */ 746 if (contents == NULL) 747 { 748 if (coff_section_data (abfd, sec) != NULL 749 && coff_section_data (abfd, sec)->contents != NULL) 750 contents = coff_section_data (abfd, sec)->contents; 751 else 752 { 753 contents = (bfd_byte *) bfd_malloc (sec->_raw_size); 754 if (contents == NULL) 755 goto error_return; 756 free_contents = contents; 757 758 if (! bfd_get_section_contents (abfd, sec, contents, 759 (file_ptr) 0, sec->_raw_size)) 760 goto error_return; 761 } 762 } 763 764 /* The r_offset field of the R_SH_USES reloc will point us to 765 the register load. The 4 is because the r_offset field is 766 computed as though it were a jump offset, which are based 767 from 4 bytes after the jump instruction. */ 768 laddr = irel->r_vaddr - sec->vma + 4; 769 /* Careful to sign extend the 32-bit offset. */ 770 laddr += ((irel->r_offset & 0xffffffff) ^ 0x80000000) - 0x80000000; 771 if (laddr >= sec->_raw_size) 772 { 773 (*_bfd_error_handler) ("%s: 0x%lx: warning: bad R_SH_USES offset", 774 bfd_archive_filename (abfd), 775 (unsigned long) irel->r_vaddr); 776 continue; 777 } 778 insn = bfd_get_16 (abfd, contents + laddr); 779 780 /* If the instruction is not mov.l NN,rN, we don't know what to do. */ 781 if ((insn & 0xf000) != 0xd000) 782 { 783 ((*_bfd_error_handler) 784 ("%s: 0x%lx: warning: R_SH_USES points to unrecognized insn 0x%x", 785 bfd_archive_filename (abfd), (unsigned long) irel->r_vaddr, insn)); 786 continue; 787 } 788 789 /* Get the address from which the register is being loaded. The 790 displacement in the mov.l instruction is quadrupled. It is a 791 displacement from four bytes after the movl instruction, but, 792 before adding in the PC address, two least significant bits 793 of the PC are cleared. We assume that the section is aligned 794 on a four byte boundary. */ 795 paddr = insn & 0xff; 796 paddr *= 4; 797 paddr += (laddr + 4) &~ (bfd_vma) 3; 798 if (paddr >= sec->_raw_size) 799 { 800 ((*_bfd_error_handler) 801 ("%s: 0x%lx: warning: bad R_SH_USES load offset", 802 bfd_archive_filename (abfd), (unsigned long) irel->r_vaddr)); 803 continue; 804 } 805 806 /* Get the reloc for the address from which the register is 807 being loaded. This reloc will tell us which function is 808 actually being called. */ 809 paddr += sec->vma; 810 for (irelfn = internal_relocs; irelfn < irelend; irelfn++) 811 if (irelfn->r_vaddr == paddr 812#ifdef COFF_WITH_PE 813 && (irelfn->r_type == R_SH_IMM32 814 || irelfn->r_type == R_SH_IMM32CE 815 || irelfn->r_type == R_SH_IMAGEBASE)) 816 817#else 818 && irelfn->r_type == R_SH_IMM32) 819#endif 820 break; 821 if (irelfn >= irelend) 822 { 823 ((*_bfd_error_handler) 824 ("%s: 0x%lx: warning: could not find expected reloc", 825 bfd_archive_filename (abfd), (unsigned long) paddr)); 826 continue; 827 } 828 829 /* Get the value of the symbol referred to by the reloc. */ 830 if (! _bfd_coff_get_external_symbols (abfd)) 831 goto error_return; 832 bfd_coff_swap_sym_in (abfd, 833 ((bfd_byte *) obj_coff_external_syms (abfd) 834 + (irelfn->r_symndx 835 * bfd_coff_symesz (abfd))), 836 &sym); 837 if (sym.n_scnum != 0 && sym.n_scnum != sec->target_index) 838 { 839 ((*_bfd_error_handler) 840 ("%s: 0x%lx: warning: symbol in unexpected section", 841 bfd_archive_filename (abfd), (unsigned long) paddr)); 842 continue; 843 } 844 845 if (sym.n_sclass != C_EXT) 846 { 847 symval = (sym.n_value 848 - sec->vma 849 + sec->output_section->vma 850 + sec->output_offset); 851 } 852 else 853 { 854 struct coff_link_hash_entry *h; 855 856 h = obj_coff_sym_hashes (abfd)[irelfn->r_symndx]; 857 BFD_ASSERT (h != NULL); 858 if (h->root.type != bfd_link_hash_defined 859 && h->root.type != bfd_link_hash_defweak) 860 { 861 /* This appears to be a reference to an undefined 862 symbol. Just ignore it--it will be caught by the 863 regular reloc processing. */ 864 continue; 865 } 866 867 symval = (h->root.u.def.value 868 + h->root.u.def.section->output_section->vma 869 + h->root.u.def.section->output_offset); 870 } 871 872 symval += bfd_get_32 (abfd, contents + paddr - sec->vma); 873 874 /* See if this function call can be shortened. */ 875 foff = (symval 876 - (irel->r_vaddr 877 - sec->vma 878 + sec->output_section->vma 879 + sec->output_offset 880 + 4)); 881 if (foff < -0x1000 || foff >= 0x1000) 882 { 883 /* After all that work, we can't shorten this function call. */ 884 continue; 885 } 886 887 /* Shorten the function call. */ 888 889 /* For simplicity of coding, we are going to modify the section 890 contents, the section relocs, and the BFD symbol table. We 891 must tell the rest of the code not to free up this 892 information. It would be possible to instead create a table 893 of changes which have to be made, as is done in coff-mips.c; 894 that would be more work, but would require less memory when 895 the linker is run. */ 896 897 if (coff_section_data (abfd, sec) == NULL) 898 { 899 bfd_size_type amt = sizeof (struct coff_section_tdata); 900 sec->used_by_bfd = (PTR) bfd_zalloc (abfd, amt); 901 if (sec->used_by_bfd == NULL) 902 goto error_return; 903 } 904 905 coff_section_data (abfd, sec)->relocs = internal_relocs; 906 coff_section_data (abfd, sec)->keep_relocs = TRUE; 907 free_relocs = NULL; 908 909 coff_section_data (abfd, sec)->contents = contents; 910 coff_section_data (abfd, sec)->keep_contents = TRUE; 911 free_contents = NULL; 912 913 obj_coff_keep_syms (abfd) = TRUE; 914 915 /* Replace the jsr with a bsr. */ 916 917 /* Change the R_SH_USES reloc into an R_SH_PCDISP reloc, and 918 replace the jsr with a bsr. */ 919 irel->r_type = R_SH_PCDISP; 920 irel->r_symndx = irelfn->r_symndx; 921 if (sym.n_sclass != C_EXT) 922 { 923 /* If this needs to be changed because of future relaxing, 924 it will be handled here like other internal PCDISP 925 relocs. */ 926 bfd_put_16 (abfd, 927 (bfd_vma) 0xb000 | ((foff >> 1) & 0xfff), 928 contents + irel->r_vaddr - sec->vma); 929 } 930 else 931 { 932 /* We can't fully resolve this yet, because the external 933 symbol value may be changed by future relaxing. We let 934 the final link phase handle it. */ 935 bfd_put_16 (abfd, (bfd_vma) 0xb000, 936 contents + irel->r_vaddr - sec->vma); 937 } 938 939 /* See if there is another R_SH_USES reloc referring to the same 940 register load. */ 941 for (irelscan = internal_relocs; irelscan < irelend; irelscan++) 942 if (irelscan->r_type == R_SH_USES 943 && laddr == irelscan->r_vaddr - sec->vma + 4 + irelscan->r_offset) 944 break; 945 if (irelscan < irelend) 946 { 947 /* Some other function call depends upon this register load, 948 and we have not yet converted that function call. 949 Indeed, we may never be able to convert it. There is 950 nothing else we can do at this point. */ 951 continue; 952 } 953 954 /* Look for a R_SH_COUNT reloc on the location where the 955 function address is stored. Do this before deleting any 956 bytes, to avoid confusion about the address. */ 957 for (irelcount = internal_relocs; irelcount < irelend; irelcount++) 958 if (irelcount->r_vaddr == paddr 959 && irelcount->r_type == R_SH_COUNT) 960 break; 961 962 /* Delete the register load. */ 963 if (! sh_relax_delete_bytes (abfd, sec, laddr, 2)) 964 goto error_return; 965 966 /* That will change things, so, just in case it permits some 967 other function call to come within range, we should relax 968 again. Note that this is not required, and it may be slow. */ 969 *again = TRUE; 970 971 /* Now check whether we got a COUNT reloc. */ 972 if (irelcount >= irelend) 973 { 974 ((*_bfd_error_handler) 975 ("%s: 0x%lx: warning: could not find expected COUNT reloc", 976 bfd_archive_filename (abfd), (unsigned long) paddr)); 977 continue; 978 } 979 980 /* The number of uses is stored in the r_offset field. We've 981 just deleted one. */ 982 if (irelcount->r_offset == 0) 983 { 984 ((*_bfd_error_handler) ("%s: 0x%lx: warning: bad count", 985 bfd_archive_filename (abfd), 986 (unsigned long) paddr)); 987 continue; 988 } 989 990 --irelcount->r_offset; 991 992 /* If there are no more uses, we can delete the address. Reload 993 the address from irelfn, in case it was changed by the 994 previous call to sh_relax_delete_bytes. */ 995 if (irelcount->r_offset == 0) 996 { 997 if (! sh_relax_delete_bytes (abfd, sec, 998 irelfn->r_vaddr - sec->vma, 4)) 999 goto error_return; 1000 } 1001 1002 /* We've done all we can with that function call. */ 1003 } 1004 1005 /* Look for load and store instructions that we can align on four 1006 byte boundaries. */ 1007 if (have_code) 1008 { 1009 bfd_boolean swapped; 1010 1011 /* Get the section contents. */ 1012 if (contents == NULL) 1013 { 1014 if (coff_section_data (abfd, sec) != NULL 1015 && coff_section_data (abfd, sec)->contents != NULL) 1016 contents = coff_section_data (abfd, sec)->contents; 1017 else 1018 { 1019 contents = (bfd_byte *) bfd_malloc (sec->_raw_size); 1020 if (contents == NULL) 1021 goto error_return; 1022 free_contents = contents; 1023 1024 if (! bfd_get_section_contents (abfd, sec, contents, 1025 (file_ptr) 0, sec->_raw_size)) 1026 goto error_return; 1027 } 1028 } 1029 1030 if (! sh_align_loads (abfd, sec, internal_relocs, contents, &swapped)) 1031 goto error_return; 1032 1033 if (swapped) 1034 { 1035 if (coff_section_data (abfd, sec) == NULL) 1036 { 1037 bfd_size_type amt = sizeof (struct coff_section_tdata); 1038 sec->used_by_bfd = (PTR) bfd_zalloc (abfd, amt); 1039 if (sec->used_by_bfd == NULL) 1040 goto error_return; 1041 } 1042 1043 coff_section_data (abfd, sec)->relocs = internal_relocs; 1044 coff_section_data (abfd, sec)->keep_relocs = TRUE; 1045 free_relocs = NULL; 1046 1047 coff_section_data (abfd, sec)->contents = contents; 1048 coff_section_data (abfd, sec)->keep_contents = TRUE; 1049 free_contents = NULL; 1050 1051 obj_coff_keep_syms (abfd) = TRUE; 1052 } 1053 } 1054 1055 if (free_relocs != NULL) 1056 { 1057 free (free_relocs); 1058 free_relocs = NULL; 1059 } 1060 1061 if (free_contents != NULL) 1062 { 1063 if (! link_info->keep_memory) 1064 free (free_contents); 1065 else 1066 { 1067 /* Cache the section contents for coff_link_input_bfd. */ 1068 if (coff_section_data (abfd, sec) == NULL) 1069 { 1070 bfd_size_type amt = sizeof (struct coff_section_tdata); 1071 sec->used_by_bfd = (PTR) bfd_zalloc (abfd, amt); 1072 if (sec->used_by_bfd == NULL) 1073 goto error_return; 1074 coff_section_data (abfd, sec)->relocs = NULL; 1075 } 1076 coff_section_data (abfd, sec)->contents = contents; 1077 } 1078 } 1079 1080 return TRUE; 1081 1082 error_return: 1083 if (free_relocs != NULL) 1084 free (free_relocs); 1085 if (free_contents != NULL) 1086 free (free_contents); 1087 return FALSE; 1088} 1089 1090/* Delete some bytes from a section while relaxing. */ 1091 1092static bfd_boolean 1093sh_relax_delete_bytes (abfd, sec, addr, count) 1094 bfd *abfd; 1095 asection *sec; 1096 bfd_vma addr; 1097 int count; 1098{ 1099 bfd_byte *contents; 1100 struct internal_reloc *irel, *irelend; 1101 struct internal_reloc *irelalign; 1102 bfd_vma toaddr; 1103 bfd_byte *esym, *esymend; 1104 bfd_size_type symesz; 1105 struct coff_link_hash_entry **sym_hash; 1106 asection *o; 1107 1108 contents = coff_section_data (abfd, sec)->contents; 1109 1110 /* The deletion must stop at the next ALIGN reloc for an aligment 1111 power larger than the number of bytes we are deleting. */ 1112 1113 irelalign = NULL; 1114 toaddr = sec->_cooked_size; 1115 1116 irel = coff_section_data (abfd, sec)->relocs; 1117 irelend = irel + sec->reloc_count; 1118 for (; irel < irelend; irel++) 1119 { 1120 if (irel->r_type == R_SH_ALIGN 1121 && irel->r_vaddr - sec->vma > addr 1122 && count < (1 << irel->r_offset)) 1123 { 1124 irelalign = irel; 1125 toaddr = irel->r_vaddr - sec->vma; 1126 break; 1127 } 1128 } 1129 1130 /* Actually delete the bytes. */ 1131 memmove (contents + addr, contents + addr + count, 1132 (size_t) (toaddr - addr - count)); 1133 if (irelalign == NULL) 1134 sec->_cooked_size -= count; 1135 else 1136 { 1137 int i; 1138 1139#define NOP_OPCODE (0x0009) 1140 1141 BFD_ASSERT ((count & 1) == 0); 1142 for (i = 0; i < count; i += 2) 1143 bfd_put_16 (abfd, (bfd_vma) NOP_OPCODE, contents + toaddr - count + i); 1144 } 1145 1146 /* Adjust all the relocs. */ 1147 for (irel = coff_section_data (abfd, sec)->relocs; irel < irelend; irel++) 1148 { 1149 bfd_vma nraddr, stop; 1150 bfd_vma start = 0; 1151 int insn = 0; 1152 struct internal_syment sym; 1153 int off, adjust, oinsn; 1154 bfd_signed_vma voff = 0; 1155 bfd_boolean overflow; 1156 1157 /* Get the new reloc address. */ 1158 nraddr = irel->r_vaddr - sec->vma; 1159 if ((irel->r_vaddr - sec->vma > addr 1160 && irel->r_vaddr - sec->vma < toaddr) 1161 || (irel->r_type == R_SH_ALIGN 1162 && irel->r_vaddr - sec->vma == toaddr)) 1163 nraddr -= count; 1164 1165 /* See if this reloc was for the bytes we have deleted, in which 1166 case we no longer care about it. Don't delete relocs which 1167 represent addresses, though. */ 1168 if (irel->r_vaddr - sec->vma >= addr 1169 && irel->r_vaddr - sec->vma < addr + count 1170 && irel->r_type != R_SH_ALIGN 1171 && irel->r_type != R_SH_CODE 1172 && irel->r_type != R_SH_DATA 1173 && irel->r_type != R_SH_LABEL) 1174 irel->r_type = R_SH_UNUSED; 1175 1176 /* If this is a PC relative reloc, see if the range it covers 1177 includes the bytes we have deleted. */ 1178 switch (irel->r_type) 1179 { 1180 default: 1181 break; 1182 1183 case R_SH_PCDISP8BY2: 1184 case R_SH_PCDISP: 1185 case R_SH_PCRELIMM8BY2: 1186 case R_SH_PCRELIMM8BY4: 1187 start = irel->r_vaddr - sec->vma; 1188 insn = bfd_get_16 (abfd, contents + nraddr); 1189 break; 1190 } 1191 1192 switch (irel->r_type) 1193 { 1194 default: 1195 start = stop = addr; 1196 break; 1197 1198 case R_SH_IMM32: 1199#ifdef COFF_WITH_PE 1200 case R_SH_IMM32CE: 1201 case R_SH_IMAGEBASE: 1202#endif 1203 /* If this reloc is against a symbol defined in this 1204 section, and the symbol will not be adjusted below, we 1205 must check the addend to see it will put the value in 1206 range to be adjusted, and hence must be changed. */ 1207 bfd_coff_swap_sym_in (abfd, 1208 ((bfd_byte *) obj_coff_external_syms (abfd) 1209 + (irel->r_symndx 1210 * bfd_coff_symesz (abfd))), 1211 &sym); 1212 if (sym.n_sclass != C_EXT 1213 && sym.n_scnum == sec->target_index 1214 && ((bfd_vma) sym.n_value <= addr 1215 || (bfd_vma) sym.n_value >= toaddr)) 1216 { 1217 bfd_vma val; 1218 1219 val = bfd_get_32 (abfd, contents + nraddr); 1220 val += sym.n_value; 1221 if (val > addr && val < toaddr) 1222 bfd_put_32 (abfd, val - count, contents + nraddr); 1223 } 1224 start = stop = addr; 1225 break; 1226 1227 case R_SH_PCDISP8BY2: 1228 off = insn & 0xff; 1229 if (off & 0x80) 1230 off -= 0x100; 1231 stop = (bfd_vma) ((bfd_signed_vma) start + 4 + off * 2); 1232 break; 1233 1234 case R_SH_PCDISP: 1235 bfd_coff_swap_sym_in (abfd, 1236 ((bfd_byte *) obj_coff_external_syms (abfd) 1237 + (irel->r_symndx 1238 * bfd_coff_symesz (abfd))), 1239 &sym); 1240 if (sym.n_sclass == C_EXT) 1241 start = stop = addr; 1242 else 1243 { 1244 off = insn & 0xfff; 1245 if (off & 0x800) 1246 off -= 0x1000; 1247 stop = (bfd_vma) ((bfd_signed_vma) start + 4 + off * 2); 1248 } 1249 break; 1250 1251 case R_SH_PCRELIMM8BY2: 1252 off = insn & 0xff; 1253 stop = start + 4 + off * 2; 1254 break; 1255 1256 case R_SH_PCRELIMM8BY4: 1257 off = insn & 0xff; 1258 stop = (start &~ (bfd_vma) 3) + 4 + off * 4; 1259 break; 1260 1261 case R_SH_SWITCH8: 1262 case R_SH_SWITCH16: 1263 case R_SH_SWITCH32: 1264 /* These relocs types represent 1265 .word L2-L1 1266 The r_offset field holds the difference between the reloc 1267 address and L1. That is the start of the reloc, and 1268 adding in the contents gives us the top. We must adjust 1269 both the r_offset field and the section contents. */ 1270 1271 start = irel->r_vaddr - sec->vma; 1272 stop = (bfd_vma) ((bfd_signed_vma) start - (long) irel->r_offset); 1273 1274 if (start > addr 1275 && start < toaddr 1276 && (stop <= addr || stop >= toaddr)) 1277 irel->r_offset += count; 1278 else if (stop > addr 1279 && stop < toaddr 1280 && (start <= addr || start >= toaddr)) 1281 irel->r_offset -= count; 1282 1283 start = stop; 1284 1285 if (irel->r_type == R_SH_SWITCH16) 1286 voff = bfd_get_signed_16 (abfd, contents + nraddr); 1287 else if (irel->r_type == R_SH_SWITCH8) 1288 voff = bfd_get_8 (abfd, contents + nraddr); 1289 else 1290 voff = bfd_get_signed_32 (abfd, contents + nraddr); 1291 stop = (bfd_vma) ((bfd_signed_vma) start + voff); 1292 1293 break; 1294 1295 case R_SH_USES: 1296 start = irel->r_vaddr - sec->vma; 1297 stop = (bfd_vma) ((bfd_signed_vma) start 1298 + (long) irel->r_offset 1299 + 4); 1300 break; 1301 } 1302 1303 if (start > addr 1304 && start < toaddr 1305 && (stop <= addr || stop >= toaddr)) 1306 adjust = count; 1307 else if (stop > addr 1308 && stop < toaddr 1309 && (start <= addr || start >= toaddr)) 1310 adjust = - count; 1311 else 1312 adjust = 0; 1313 1314 if (adjust != 0) 1315 { 1316 oinsn = insn; 1317 overflow = FALSE; 1318 switch (irel->r_type) 1319 { 1320 default: 1321 abort (); 1322 break; 1323 1324 case R_SH_PCDISP8BY2: 1325 case R_SH_PCRELIMM8BY2: 1326 insn += adjust / 2; 1327 if ((oinsn & 0xff00) != (insn & 0xff00)) 1328 overflow = TRUE; 1329 bfd_put_16 (abfd, (bfd_vma) insn, contents + nraddr); 1330 break; 1331 1332 case R_SH_PCDISP: 1333 insn += adjust / 2; 1334 if ((oinsn & 0xf000) != (insn & 0xf000)) 1335 overflow = TRUE; 1336 bfd_put_16 (abfd, (bfd_vma) insn, contents + nraddr); 1337 break; 1338 1339 case R_SH_PCRELIMM8BY4: 1340 BFD_ASSERT (adjust == count || count >= 4); 1341 if (count >= 4) 1342 insn += adjust / 4; 1343 else 1344 { 1345 if ((irel->r_vaddr & 3) == 0) 1346 ++insn; 1347 } 1348 if ((oinsn & 0xff00) != (insn & 0xff00)) 1349 overflow = TRUE; 1350 bfd_put_16 (abfd, (bfd_vma) insn, contents + nraddr); 1351 break; 1352 1353 case R_SH_SWITCH8: 1354 voff += adjust; 1355 if (voff < 0 || voff >= 0xff) 1356 overflow = TRUE; 1357 bfd_put_8 (abfd, (bfd_vma) voff, contents + nraddr); 1358 break; 1359 1360 case R_SH_SWITCH16: 1361 voff += adjust; 1362 if (voff < - 0x8000 || voff >= 0x8000) 1363 overflow = TRUE; 1364 bfd_put_signed_16 (abfd, (bfd_vma) voff, contents + nraddr); 1365 break; 1366 1367 case R_SH_SWITCH32: 1368 voff += adjust; 1369 bfd_put_signed_32 (abfd, (bfd_vma) voff, contents + nraddr); 1370 break; 1371 1372 case R_SH_USES: 1373 irel->r_offset += adjust; 1374 break; 1375 } 1376 1377 if (overflow) 1378 { 1379 ((*_bfd_error_handler) 1380 ("%s: 0x%lx: fatal: reloc overflow while relaxing", 1381 bfd_archive_filename (abfd), (unsigned long) irel->r_vaddr)); 1382 bfd_set_error (bfd_error_bad_value); 1383 return FALSE; 1384 } 1385 } 1386 1387 irel->r_vaddr = nraddr + sec->vma; 1388 } 1389 1390 /* Look through all the other sections. If there contain any IMM32 1391 relocs against internal symbols which we are not going to adjust 1392 below, we may need to adjust the addends. */ 1393 for (o = abfd->sections; o != NULL; o = o->next) 1394 { 1395 struct internal_reloc *internal_relocs; 1396 struct internal_reloc *irelscan, *irelscanend; 1397 bfd_byte *ocontents; 1398 1399 if (o == sec 1400 || (o->flags & SEC_RELOC) == 0 1401 || o->reloc_count == 0) 1402 continue; 1403 1404 /* We always cache the relocs. Perhaps, if info->keep_memory is 1405 FALSE, we should free them, if we are permitted to, when we 1406 leave sh_coff_relax_section. */ 1407 internal_relocs = (_bfd_coff_read_internal_relocs 1408 (abfd, o, TRUE, (bfd_byte *) NULL, FALSE, 1409 (struct internal_reloc *) NULL)); 1410 if (internal_relocs == NULL) 1411 return FALSE; 1412 1413 ocontents = NULL; 1414 irelscanend = internal_relocs + o->reloc_count; 1415 for (irelscan = internal_relocs; irelscan < irelscanend; irelscan++) 1416 { 1417 struct internal_syment sym; 1418 1419#ifdef COFF_WITH_PE 1420 if (irelscan->r_type != R_SH_IMM32 1421 && irelscan->r_type != R_SH_IMAGEBASE 1422 && irelscan->r_type != R_SH_IMM32CE) 1423#else 1424 if (irelscan->r_type != R_SH_IMM32) 1425#endif 1426 continue; 1427 1428 bfd_coff_swap_sym_in (abfd, 1429 ((bfd_byte *) obj_coff_external_syms (abfd) 1430 + (irelscan->r_symndx 1431 * bfd_coff_symesz (abfd))), 1432 &sym); 1433 if (sym.n_sclass != C_EXT 1434 && sym.n_scnum == sec->target_index 1435 && ((bfd_vma) sym.n_value <= addr 1436 || (bfd_vma) sym.n_value >= toaddr)) 1437 { 1438 bfd_vma val; 1439 1440 if (ocontents == NULL) 1441 { 1442 if (coff_section_data (abfd, o)->contents != NULL) 1443 ocontents = coff_section_data (abfd, o)->contents; 1444 else 1445 { 1446 /* We always cache the section contents. 1447 Perhaps, if info->keep_memory is FALSE, we 1448 should free them, if we are permitted to, 1449 when we leave sh_coff_relax_section. */ 1450 ocontents = (bfd_byte *) bfd_malloc (o->_raw_size); 1451 if (ocontents == NULL) 1452 return FALSE; 1453 if (! bfd_get_section_contents (abfd, o, ocontents, 1454 (file_ptr) 0, 1455 o->_raw_size)) 1456 return FALSE; 1457 coff_section_data (abfd, o)->contents = ocontents; 1458 } 1459 } 1460 1461 val = bfd_get_32 (abfd, ocontents + irelscan->r_vaddr - o->vma); 1462 val += sym.n_value; 1463 if (val > addr && val < toaddr) 1464 bfd_put_32 (abfd, val - count, 1465 ocontents + irelscan->r_vaddr - o->vma); 1466 1467 coff_section_data (abfd, o)->keep_contents = TRUE; 1468 } 1469 } 1470 } 1471 1472 /* Adjusting the internal symbols will not work if something has 1473 already retrieved the generic symbols. It would be possible to 1474 make this work by adjusting the generic symbols at the same time. 1475 However, this case should not arise in normal usage. */ 1476 if (obj_symbols (abfd) != NULL 1477 || obj_raw_syments (abfd) != NULL) 1478 { 1479 ((*_bfd_error_handler) 1480 ("%s: fatal: generic symbols retrieved before relaxing", 1481 bfd_archive_filename (abfd))); 1482 bfd_set_error (bfd_error_invalid_operation); 1483 return FALSE; 1484 } 1485 1486 /* Adjust all the symbols. */ 1487 sym_hash = obj_coff_sym_hashes (abfd); 1488 symesz = bfd_coff_symesz (abfd); 1489 esym = (bfd_byte *) obj_coff_external_syms (abfd); 1490 esymend = esym + obj_raw_syment_count (abfd) * symesz; 1491 while (esym < esymend) 1492 { 1493 struct internal_syment isym; 1494 1495 bfd_coff_swap_sym_in (abfd, (PTR) esym, (PTR) &isym); 1496 1497 if (isym.n_scnum == sec->target_index 1498 && (bfd_vma) isym.n_value > addr 1499 && (bfd_vma) isym.n_value < toaddr) 1500 { 1501 isym.n_value -= count; 1502 1503 bfd_coff_swap_sym_out (abfd, (PTR) &isym, (PTR) esym); 1504 1505 if (*sym_hash != NULL) 1506 { 1507 BFD_ASSERT ((*sym_hash)->root.type == bfd_link_hash_defined 1508 || (*sym_hash)->root.type == bfd_link_hash_defweak); 1509 BFD_ASSERT ((*sym_hash)->root.u.def.value >= addr 1510 && (*sym_hash)->root.u.def.value < toaddr); 1511 (*sym_hash)->root.u.def.value -= count; 1512 } 1513 } 1514 1515 esym += (isym.n_numaux + 1) * symesz; 1516 sym_hash += isym.n_numaux + 1; 1517 } 1518 1519 /* See if we can move the ALIGN reloc forward. We have adjusted 1520 r_vaddr for it already. */ 1521 if (irelalign != NULL) 1522 { 1523 bfd_vma alignto, alignaddr; 1524 1525 alignto = BFD_ALIGN (toaddr, 1 << irelalign->r_offset); 1526 alignaddr = BFD_ALIGN (irelalign->r_vaddr - sec->vma, 1527 1 << irelalign->r_offset); 1528 if (alignto != alignaddr) 1529 { 1530 /* Tail recursion. */ 1531 return sh_relax_delete_bytes (abfd, sec, alignaddr, 1532 (int) (alignto - alignaddr)); 1533 } 1534 } 1535 1536 return TRUE; 1537} 1538 1539/* This is yet another version of the SH opcode table, used to rapidly 1540 get information about a particular instruction. */ 1541 1542/* The opcode map is represented by an array of these structures. The 1543 array is indexed by the high order four bits in the instruction. */ 1544 1545struct sh_major_opcode 1546{ 1547 /* A pointer to the instruction list. This is an array which 1548 contains all the instructions with this major opcode. */ 1549 const struct sh_minor_opcode *minor_opcodes; 1550 /* The number of elements in minor_opcodes. */ 1551 unsigned short count; 1552}; 1553 1554/* This structure holds information for a set of SH opcodes. The 1555 instruction code is anded with the mask value, and the resulting 1556 value is used to search the order opcode list. */ 1557 1558struct sh_minor_opcode 1559{ 1560 /* The sorted opcode list. */ 1561 const struct sh_opcode *opcodes; 1562 /* The number of elements in opcodes. */ 1563 unsigned short count; 1564 /* The mask value to use when searching the opcode list. */ 1565 unsigned short mask; 1566}; 1567 1568/* This structure holds information for an SH instruction. An array 1569 of these structures is sorted in order by opcode. */ 1570 1571struct sh_opcode 1572{ 1573 /* The code for this instruction, after it has been anded with the 1574 mask value in the sh_major_opcode structure. */ 1575 unsigned short opcode; 1576 /* Flags for this instruction. */ 1577 unsigned long flags; 1578}; 1579 1580/* Flag which appear in the sh_opcode structure. */ 1581 1582/* This instruction loads a value from memory. */ 1583#define LOAD (0x1) 1584 1585/* This instruction stores a value to memory. */ 1586#define STORE (0x2) 1587 1588/* This instruction is a branch. */ 1589#define BRANCH (0x4) 1590 1591/* This instruction has a delay slot. */ 1592#define DELAY (0x8) 1593 1594/* This instruction uses the value in the register in the field at 1595 mask 0x0f00 of the instruction. */ 1596#define USES1 (0x10) 1597#define USES1_REG(x) ((x & 0x0f00) >> 8) 1598 1599/* This instruction uses the value in the register in the field at 1600 mask 0x00f0 of the instruction. */ 1601#define USES2 (0x20) 1602#define USES2_REG(x) ((x & 0x00f0) >> 4) 1603 1604/* This instruction uses the value in register 0. */ 1605#define USESR0 (0x40) 1606 1607/* This instruction sets the value in the register in the field at 1608 mask 0x0f00 of the instruction. */ 1609#define SETS1 (0x80) 1610#define SETS1_REG(x) ((x & 0x0f00) >> 8) 1611 1612/* This instruction sets the value in the register in the field at 1613 mask 0x00f0 of the instruction. */ 1614#define SETS2 (0x100) 1615#define SETS2_REG(x) ((x & 0x00f0) >> 4) 1616 1617/* This instruction sets register 0. */ 1618#define SETSR0 (0x200) 1619 1620/* This instruction sets a special register. */ 1621#define SETSSP (0x400) 1622 1623/* This instruction uses a special register. */ 1624#define USESSP (0x800) 1625 1626/* This instruction uses the floating point register in the field at 1627 mask 0x0f00 of the instruction. */ 1628#define USESF1 (0x1000) 1629#define USESF1_REG(x) ((x & 0x0f00) >> 8) 1630 1631/* This instruction uses the floating point register in the field at 1632 mask 0x00f0 of the instruction. */ 1633#define USESF2 (0x2000) 1634#define USESF2_REG(x) ((x & 0x00f0) >> 4) 1635 1636/* This instruction uses floating point register 0. */ 1637#define USESF0 (0x4000) 1638 1639/* This instruction sets the floating point register in the field at 1640 mask 0x0f00 of the instruction. */ 1641#define SETSF1 (0x8000) 1642#define SETSF1_REG(x) ((x & 0x0f00) >> 8) 1643 1644#define USESAS (0x10000) 1645#define USESAS_REG(x) (((((x) >> 8) - 2) & 3) + 2) 1646#define USESR8 (0x20000) 1647#define SETSAS (0x40000) 1648#define SETSAS_REG(x) USESAS_REG (x) 1649 1650#define MAP(a) a, sizeof a / sizeof a[0] 1651 1652#ifndef COFF_IMAGE_WITH_PE 1653static bfd_boolean sh_insn_uses_reg 1654 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int)); 1655static bfd_boolean sh_insn_sets_reg 1656 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int)); 1657static bfd_boolean sh_insn_uses_or_sets_reg 1658 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int)); 1659static bfd_boolean sh_insn_uses_freg 1660 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int)); 1661static bfd_boolean sh_insn_sets_freg 1662 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int)); 1663static bfd_boolean sh_insn_uses_or_sets_freg 1664 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int)); 1665static bfd_boolean sh_insns_conflict 1666 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int, 1667 const struct sh_opcode *)); 1668static bfd_boolean sh_load_use 1669 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int, 1670 const struct sh_opcode *)); 1671 1672/* The opcode maps. */ 1673 1674static const struct sh_opcode sh_opcode00[] = 1675{ 1676 { 0x0008, SETSSP }, /* clrt */ 1677 { 0x0009, 0 }, /* nop */ 1678 { 0x000b, BRANCH | DELAY | USESSP }, /* rts */ 1679 { 0x0018, SETSSP }, /* sett */ 1680 { 0x0019, SETSSP }, /* div0u */ 1681 { 0x001b, 0 }, /* sleep */ 1682 { 0x0028, SETSSP }, /* clrmac */ 1683 { 0x002b, BRANCH | DELAY | SETSSP }, /* rte */ 1684 { 0x0038, USESSP | SETSSP }, /* ldtlb */ 1685 { 0x0048, SETSSP }, /* clrs */ 1686 { 0x0058, SETSSP } /* sets */ 1687}; 1688 1689static const struct sh_opcode sh_opcode01[] = 1690{ 1691 { 0x0003, BRANCH | DELAY | USES1 | SETSSP }, /* bsrf rn */ 1692 { 0x000a, SETS1 | USESSP }, /* sts mach,rn */ 1693 { 0x001a, SETS1 | USESSP }, /* sts macl,rn */ 1694 { 0x0023, BRANCH | DELAY | USES1 }, /* braf rn */ 1695 { 0x0029, SETS1 | USESSP }, /* movt rn */ 1696 { 0x002a, SETS1 | USESSP }, /* sts pr,rn */ 1697 { 0x005a, SETS1 | USESSP }, /* sts fpul,rn */ 1698 { 0x006a, SETS1 | USESSP }, /* sts fpscr,rn / sts dsr,rn */ 1699 { 0x0083, LOAD | USES1 }, /* pref @rn */ 1700 { 0x007a, SETS1 | USESSP }, /* sts a0,rn */ 1701 { 0x008a, SETS1 | USESSP }, /* sts x0,rn */ 1702 { 0x009a, SETS1 | USESSP }, /* sts x1,rn */ 1703 { 0x00aa, SETS1 | USESSP }, /* sts y0,rn */ 1704 { 0x00ba, SETS1 | USESSP } /* sts y1,rn */ 1705}; 1706 1707/* These sixteen instructions can be handled with one table entry below. */ 1708#if 0 1709 { 0x0002, SETS1 | USESSP }, /* stc sr,rn */ 1710 { 0x0012, SETS1 | USESSP }, /* stc gbr,rn */ 1711 { 0x0022, SETS1 | USESSP }, /* stc vbr,rn */ 1712 { 0x0032, SETS1 | USESSP }, /* stc ssr,rn */ 1713 { 0x0042, SETS1 | USESSP }, /* stc spc,rn */ 1714 { 0x0052, SETS1 | USESSP }, /* stc mod,rn */ 1715 { 0x0062, SETS1 | USESSP }, /* stc rs,rn */ 1716 { 0x0072, SETS1 | USESSP }, /* stc re,rn */ 1717 { 0x0082, SETS1 | USESSP }, /* stc r0_bank,rn */ 1718 { 0x0092, SETS1 | USESSP }, /* stc r1_bank,rn */ 1719 { 0x00a2, SETS1 | USESSP }, /* stc r2_bank,rn */ 1720 { 0x00b2, SETS1 | USESSP }, /* stc r3_bank,rn */ 1721 { 0x00c2, SETS1 | USESSP }, /* stc r4_bank,rn */ 1722 { 0x00d2, SETS1 | USESSP }, /* stc r5_bank,rn */ 1723 { 0x00e2, SETS1 | USESSP }, /* stc r6_bank,rn */ 1724 { 0x00f2, SETS1 | USESSP } /* stc r7_bank,rn */ 1725#endif 1726 1727static const struct sh_opcode sh_opcode02[] = 1728{ 1729 { 0x0002, SETS1 | USESSP }, /* stc <special_reg>,rn */ 1730 { 0x0004, STORE | USES1 | USES2 | USESR0 }, /* mov.b rm,@(r0,rn) */ 1731 { 0x0005, STORE | USES1 | USES2 | USESR0 }, /* mov.w rm,@(r0,rn) */ 1732 { 0x0006, STORE | USES1 | USES2 | USESR0 }, /* mov.l rm,@(r0,rn) */ 1733 { 0x0007, SETSSP | USES1 | USES2 }, /* mul.l rm,rn */ 1734 { 0x000c, LOAD | SETS1 | USES2 | USESR0 }, /* mov.b @(r0,rm),rn */ 1735 { 0x000d, LOAD | SETS1 | USES2 | USESR0 }, /* mov.w @(r0,rm),rn */ 1736 { 0x000e, LOAD | SETS1 | USES2 | USESR0 }, /* mov.l @(r0,rm),rn */ 1737 { 0x000f, LOAD|SETS1|SETS2|SETSSP|USES1|USES2|USESSP }, /* mac.l @rm+,@rn+ */ 1738}; 1739 1740static const struct sh_minor_opcode sh_opcode0[] = 1741{ 1742 { MAP (sh_opcode00), 0xffff }, 1743 { MAP (sh_opcode01), 0xf0ff }, 1744 { MAP (sh_opcode02), 0xf00f } 1745}; 1746 1747static const struct sh_opcode sh_opcode10[] = 1748{ 1749 { 0x1000, STORE | USES1 | USES2 } /* mov.l rm,@(disp,rn) */ 1750}; 1751 1752static const struct sh_minor_opcode sh_opcode1[] = 1753{ 1754 { MAP (sh_opcode10), 0xf000 } 1755}; 1756 1757static const struct sh_opcode sh_opcode20[] = 1758{ 1759 { 0x2000, STORE | USES1 | USES2 }, /* mov.b rm,@rn */ 1760 { 0x2001, STORE | USES1 | USES2 }, /* mov.w rm,@rn */ 1761 { 0x2002, STORE | USES1 | USES2 }, /* mov.l rm,@rn */ 1762 { 0x2004, STORE | SETS1 | USES1 | USES2 }, /* mov.b rm,@-rn */ 1763 { 0x2005, STORE | SETS1 | USES1 | USES2 }, /* mov.w rm,@-rn */ 1764 { 0x2006, STORE | SETS1 | USES1 | USES2 }, /* mov.l rm,@-rn */ 1765 { 0x2007, SETSSP | USES1 | USES2 | USESSP }, /* div0s */ 1766 { 0x2008, SETSSP | USES1 | USES2 }, /* tst rm,rn */ 1767 { 0x2009, SETS1 | USES1 | USES2 }, /* and rm,rn */ 1768 { 0x200a, SETS1 | USES1 | USES2 }, /* xor rm,rn */ 1769 { 0x200b, SETS1 | USES1 | USES2 }, /* or rm,rn */ 1770 { 0x200c, SETSSP | USES1 | USES2 }, /* cmp/str rm,rn */ 1771 { 0x200d, SETS1 | USES1 | USES2 }, /* xtrct rm,rn */ 1772 { 0x200e, SETSSP | USES1 | USES2 }, /* mulu.w rm,rn */ 1773 { 0x200f, SETSSP | USES1 | USES2 } /* muls.w rm,rn */ 1774}; 1775 1776static const struct sh_minor_opcode sh_opcode2[] = 1777{ 1778 { MAP (sh_opcode20), 0xf00f } 1779}; 1780 1781static const struct sh_opcode sh_opcode30[] = 1782{ 1783 { 0x3000, SETSSP | USES1 | USES2 }, /* cmp/eq rm,rn */ 1784 { 0x3002, SETSSP | USES1 | USES2 }, /* cmp/hs rm,rn */ 1785 { 0x3003, SETSSP | USES1 | USES2 }, /* cmp/ge rm,rn */ 1786 { 0x3004, SETSSP | USESSP | USES1 | USES2 }, /* div1 rm,rn */ 1787 { 0x3005, SETSSP | USES1 | USES2 }, /* dmulu.l rm,rn */ 1788 { 0x3006, SETSSP | USES1 | USES2 }, /* cmp/hi rm,rn */ 1789 { 0x3007, SETSSP | USES1 | USES2 }, /* cmp/gt rm,rn */ 1790 { 0x3008, SETS1 | USES1 | USES2 }, /* sub rm,rn */ 1791 { 0x300a, SETS1 | SETSSP | USES1 | USES2 | USESSP }, /* subc rm,rn */ 1792 { 0x300b, SETS1 | SETSSP | USES1 | USES2 }, /* subv rm,rn */ 1793 { 0x300c, SETS1 | USES1 | USES2 }, /* add rm,rn */ 1794 { 0x300d, SETSSP | USES1 | USES2 }, /* dmuls.l rm,rn */ 1795 { 0x300e, SETS1 | SETSSP | USES1 | USES2 | USESSP }, /* addc rm,rn */ 1796 { 0x300f, SETS1 | SETSSP | USES1 | USES2 } /* addv rm,rn */ 1797}; 1798 1799static const struct sh_minor_opcode sh_opcode3[] = 1800{ 1801 { MAP (sh_opcode30), 0xf00f } 1802}; 1803 1804static const struct sh_opcode sh_opcode40[] = 1805{ 1806 { 0x4000, SETS1 | SETSSP | USES1 }, /* shll rn */ 1807 { 0x4001, SETS1 | SETSSP | USES1 }, /* shlr rn */ 1808 { 0x4002, STORE | SETS1 | USES1 | USESSP }, /* sts.l mach,@-rn */ 1809 { 0x4004, SETS1 | SETSSP | USES1 }, /* rotl rn */ 1810 { 0x4005, SETS1 | SETSSP | USES1 }, /* rotr rn */ 1811 { 0x4006, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,mach */ 1812 { 0x4008, SETS1 | USES1 }, /* shll2 rn */ 1813 { 0x4009, SETS1 | USES1 }, /* shlr2 rn */ 1814 { 0x400a, SETSSP | USES1 }, /* lds rm,mach */ 1815 { 0x400b, BRANCH | DELAY | USES1 }, /* jsr @rn */ 1816 { 0x4010, SETS1 | SETSSP | USES1 }, /* dt rn */ 1817 { 0x4011, SETSSP | USES1 }, /* cmp/pz rn */ 1818 { 0x4012, STORE | SETS1 | USES1 | USESSP }, /* sts.l macl,@-rn */ 1819 { 0x4014, SETSSP | USES1 }, /* setrc rm */ 1820 { 0x4015, SETSSP | USES1 }, /* cmp/pl rn */ 1821 { 0x4016, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,macl */ 1822 { 0x4018, SETS1 | USES1 }, /* shll8 rn */ 1823 { 0x4019, SETS1 | USES1 }, /* shlr8 rn */ 1824 { 0x401a, SETSSP | USES1 }, /* lds rm,macl */ 1825 { 0x401b, LOAD | SETSSP | USES1 }, /* tas.b @rn */ 1826 { 0x4020, SETS1 | SETSSP | USES1 }, /* shal rn */ 1827 { 0x4021, SETS1 | SETSSP | USES1 }, /* shar rn */ 1828 { 0x4022, STORE | SETS1 | USES1 | USESSP }, /* sts.l pr,@-rn */ 1829 { 0x4024, SETS1 | SETSSP | USES1 | USESSP }, /* rotcl rn */ 1830 { 0x4025, SETS1 | SETSSP | USES1 | USESSP }, /* rotcr rn */ 1831 { 0x4026, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,pr */ 1832 { 0x4028, SETS1 | USES1 }, /* shll16 rn */ 1833 { 0x4029, SETS1 | USES1 }, /* shlr16 rn */ 1834 { 0x402a, SETSSP | USES1 }, /* lds rm,pr */ 1835 { 0x402b, BRANCH | DELAY | USES1 }, /* jmp @rn */ 1836 { 0x4052, STORE | SETS1 | USES1 | USESSP }, /* sts.l fpul,@-rn */ 1837 { 0x4056, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,fpul */ 1838 { 0x405a, SETSSP | USES1 }, /* lds.l rm,fpul */ 1839 { 0x4062, STORE | SETS1 | USES1 | USESSP }, /* sts.l fpscr / dsr,@-rn */ 1840 { 0x4066, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,fpscr / dsr */ 1841 { 0x406a, SETSSP | USES1 }, /* lds rm,fpscr / lds rm,dsr */ 1842 { 0x4072, STORE | SETS1 | USES1 | USESSP }, /* sts.l a0,@-rn */ 1843 { 0x4076, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,a0 */ 1844 { 0x407a, SETSSP | USES1 }, /* lds.l rm,a0 */ 1845 { 0x4082, STORE | SETS1 | USES1 | USESSP }, /* sts.l x0,@-rn */ 1846 { 0x4086, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,x0 */ 1847 { 0x408a, SETSSP | USES1 }, /* lds.l rm,x0 */ 1848 { 0x4092, STORE | SETS1 | USES1 | USESSP }, /* sts.l x1,@-rn */ 1849 { 0x4096, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,x1 */ 1850 { 0x409a, SETSSP | USES1 }, /* lds.l rm,x1 */ 1851 { 0x40a2, STORE | SETS1 | USES1 | USESSP }, /* sts.l y0,@-rn */ 1852 { 0x40a6, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,y0 */ 1853 { 0x40aa, SETSSP | USES1 }, /* lds.l rm,y0 */ 1854 { 0x40b2, STORE | SETS1 | USES1 | USESSP }, /* sts.l y1,@-rn */ 1855 { 0x40b6, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,y1 */ 1856 { 0x40ba, SETSSP | USES1 } /* lds.l rm,y1 */ 1857#if 0 /* These groups sixteen insns can be 1858 handled with one table entry each below. */ 1859 { 0x4003, STORE | SETS1 | USES1 | USESSP }, /* stc.l sr,@-rn */ 1860 { 0x4013, STORE | SETS1 | USES1 | USESSP }, /* stc.l gbr,@-rn */ 1861 { 0x4023, STORE | SETS1 | USES1 | USESSP }, /* stc.l vbr,@-rn */ 1862 { 0x4033, STORE | SETS1 | USES1 | USESSP }, /* stc.l ssr,@-rn */ 1863 { 0x4043, STORE | SETS1 | USES1 | USESSP }, /* stc.l spc,@-rn */ 1864 { 0x4053, STORE | SETS1 | USES1 | USESSP }, /* stc.l mod,@-rn */ 1865 { 0x4063, STORE | SETS1 | USES1 | USESSP }, /* stc.l rs,@-rn */ 1866 { 0x4073, STORE | SETS1 | USES1 | USESSP }, /* stc.l re,@-rn */ 1867 { 0x4083, STORE | SETS1 | USES1 | USESSP }, /* stc.l r0_bank,@-rn */ 1868 .. 1869 { 0x40f3, STORE | SETS1 | USES1 | USESSP }, /* stc.l r7_bank,@-rn */ 1870 1871 { 0x4007, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,sr */ 1872 { 0x4017, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,gbr */ 1873 { 0x4027, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,vbr */ 1874 { 0x4037, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,ssr */ 1875 { 0x4047, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,spc */ 1876 { 0x4057, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,mod */ 1877 { 0x4067, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,rs */ 1878 { 0x4077, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,re */ 1879 { 0x4087, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,r0_bank */ 1880 .. 1881 { 0x40f7, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,r7_bank */ 1882 1883 { 0x400e, SETSSP | USES1 }, /* ldc rm,sr */ 1884 { 0x401e, SETSSP | USES1 }, /* ldc rm,gbr */ 1885 { 0x402e, SETSSP | USES1 }, /* ldc rm,vbr */ 1886 { 0x403e, SETSSP | USES1 }, /* ldc rm,ssr */ 1887 { 0x404e, SETSSP | USES1 }, /* ldc rm,spc */ 1888 { 0x405e, SETSSP | USES1 }, /* ldc rm,mod */ 1889 { 0x406e, SETSSP | USES1 }, /* ldc rm,rs */ 1890 { 0x407e, SETSSP | USES1 } /* ldc rm,re */ 1891 { 0x408e, SETSSP | USES1 } /* ldc rm,r0_bank */ 1892 .. 1893 { 0x40fe, SETSSP | USES1 } /* ldc rm,r7_bank */ 1894#endif 1895}; 1896 1897static const struct sh_opcode sh_opcode41[] = 1898{ 1899 { 0x4003, STORE | SETS1 | USES1 | USESSP }, /* stc.l <special_reg>,@-rn */ 1900 { 0x4007, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,<special_reg> */ 1901 { 0x400c, SETS1 | USES1 | USES2 }, /* shad rm,rn */ 1902 { 0x400d, SETS1 | USES1 | USES2 }, /* shld rm,rn */ 1903 { 0x400e, SETSSP | USES1 }, /* ldc rm,<special_reg> */ 1904 { 0x400f, LOAD|SETS1|SETS2|SETSSP|USES1|USES2|USESSP }, /* mac.w @rm+,@rn+ */ 1905}; 1906 1907static const struct sh_minor_opcode sh_opcode4[] = 1908{ 1909 { MAP (sh_opcode40), 0xf0ff }, 1910 { MAP (sh_opcode41), 0xf00f } 1911}; 1912 1913static const struct sh_opcode sh_opcode50[] = 1914{ 1915 { 0x5000, LOAD | SETS1 | USES2 } /* mov.l @(disp,rm),rn */ 1916}; 1917 1918static const struct sh_minor_opcode sh_opcode5[] = 1919{ 1920 { MAP (sh_opcode50), 0xf000 } 1921}; 1922 1923static const struct sh_opcode sh_opcode60[] = 1924{ 1925 { 0x6000, LOAD | SETS1 | USES2 }, /* mov.b @rm,rn */ 1926 { 0x6001, LOAD | SETS1 | USES2 }, /* mov.w @rm,rn */ 1927 { 0x6002, LOAD | SETS1 | USES2 }, /* mov.l @rm,rn */ 1928 { 0x6003, SETS1 | USES2 }, /* mov rm,rn */ 1929 { 0x6004, LOAD | SETS1 | SETS2 | USES2 }, /* mov.b @rm+,rn */ 1930 { 0x6005, LOAD | SETS1 | SETS2 | USES2 }, /* mov.w @rm+,rn */ 1931 { 0x6006, LOAD | SETS1 | SETS2 | USES2 }, /* mov.l @rm+,rn */ 1932 { 0x6007, SETS1 | USES2 }, /* not rm,rn */ 1933 { 0x6008, SETS1 | USES2 }, /* swap.b rm,rn */ 1934 { 0x6009, SETS1 | USES2 }, /* swap.w rm,rn */ 1935 { 0x600a, SETS1 | SETSSP | USES2 | USESSP }, /* negc rm,rn */ 1936 { 0x600b, SETS1 | USES2 }, /* neg rm,rn */ 1937 { 0x600c, SETS1 | USES2 }, /* extu.b rm,rn */ 1938 { 0x600d, SETS1 | USES2 }, /* extu.w rm,rn */ 1939 { 0x600e, SETS1 | USES2 }, /* exts.b rm,rn */ 1940 { 0x600f, SETS1 | USES2 } /* exts.w rm,rn */ 1941}; 1942 1943static const struct sh_minor_opcode sh_opcode6[] = 1944{ 1945 { MAP (sh_opcode60), 0xf00f } 1946}; 1947 1948static const struct sh_opcode sh_opcode70[] = 1949{ 1950 { 0x7000, SETS1 | USES1 } /* add #imm,rn */ 1951}; 1952 1953static const struct sh_minor_opcode sh_opcode7[] = 1954{ 1955 { MAP (sh_opcode70), 0xf000 } 1956}; 1957 1958static const struct sh_opcode sh_opcode80[] = 1959{ 1960 { 0x8000, STORE | USES2 | USESR0 }, /* mov.b r0,@(disp,rn) */ 1961 { 0x8100, STORE | USES2 | USESR0 }, /* mov.w r0,@(disp,rn) */ 1962 { 0x8200, SETSSP }, /* setrc #imm */ 1963 { 0x8400, LOAD | SETSR0 | USES2 }, /* mov.b @(disp,rm),r0 */ 1964 { 0x8500, LOAD | SETSR0 | USES2 }, /* mov.w @(disp,rn),r0 */ 1965 { 0x8800, SETSSP | USESR0 }, /* cmp/eq #imm,r0 */ 1966 { 0x8900, BRANCH | USESSP }, /* bt label */ 1967 { 0x8b00, BRANCH | USESSP }, /* bf label */ 1968 { 0x8c00, SETSSP }, /* ldrs @(disp,pc) */ 1969 { 0x8d00, BRANCH | DELAY | USESSP }, /* bt/s label */ 1970 { 0x8e00, SETSSP }, /* ldre @(disp,pc) */ 1971 { 0x8f00, BRANCH | DELAY | USESSP } /* bf/s label */ 1972}; 1973 1974static const struct sh_minor_opcode sh_opcode8[] = 1975{ 1976 { MAP (sh_opcode80), 0xff00 } 1977}; 1978 1979static const struct sh_opcode sh_opcode90[] = 1980{ 1981 { 0x9000, LOAD | SETS1 } /* mov.w @(disp,pc),rn */ 1982}; 1983 1984static const struct sh_minor_opcode sh_opcode9[] = 1985{ 1986 { MAP (sh_opcode90), 0xf000 } 1987}; 1988 1989static const struct sh_opcode sh_opcodea0[] = 1990{ 1991 { 0xa000, BRANCH | DELAY } /* bra label */ 1992}; 1993 1994static const struct sh_minor_opcode sh_opcodea[] = 1995{ 1996 { MAP (sh_opcodea0), 0xf000 } 1997}; 1998 1999static const struct sh_opcode sh_opcodeb0[] = 2000{ 2001 { 0xb000, BRANCH | DELAY } /* bsr label */ 2002}; 2003 2004static const struct sh_minor_opcode sh_opcodeb[] = 2005{ 2006 { MAP (sh_opcodeb0), 0xf000 } 2007}; 2008 2009static const struct sh_opcode sh_opcodec0[] = 2010{ 2011 { 0xc000, STORE | USESR0 | USESSP }, /* mov.b r0,@(disp,gbr) */ 2012 { 0xc100, STORE | USESR0 | USESSP }, /* mov.w r0,@(disp,gbr) */ 2013 { 0xc200, STORE | USESR0 | USESSP }, /* mov.l r0,@(disp,gbr) */ 2014 { 0xc300, BRANCH | USESSP }, /* trapa #imm */ 2015 { 0xc400, LOAD | SETSR0 | USESSP }, /* mov.b @(disp,gbr),r0 */ 2016 { 0xc500, LOAD | SETSR0 | USESSP }, /* mov.w @(disp,gbr),r0 */ 2017 { 0xc600, LOAD | SETSR0 | USESSP }, /* mov.l @(disp,gbr),r0 */ 2018 { 0xc700, SETSR0 }, /* mova @(disp,pc),r0 */ 2019 { 0xc800, SETSSP | USESR0 }, /* tst #imm,r0 */ 2020 { 0xc900, SETSR0 | USESR0 }, /* and #imm,r0 */ 2021 { 0xca00, SETSR0 | USESR0 }, /* xor #imm,r0 */ 2022 { 0xcb00, SETSR0 | USESR0 }, /* or #imm,r0 */ 2023 { 0xcc00, LOAD | SETSSP | USESR0 | USESSP }, /* tst.b #imm,@(r0,gbr) */ 2024 { 0xcd00, LOAD | STORE | USESR0 | USESSP }, /* and.b #imm,@(r0,gbr) */ 2025 { 0xce00, LOAD | STORE | USESR0 | USESSP }, /* xor.b #imm,@(r0,gbr) */ 2026 { 0xcf00, LOAD | STORE | USESR0 | USESSP } /* or.b #imm,@(r0,gbr) */ 2027}; 2028 2029static const struct sh_minor_opcode sh_opcodec[] = 2030{ 2031 { MAP (sh_opcodec0), 0xff00 } 2032}; 2033 2034static const struct sh_opcode sh_opcoded0[] = 2035{ 2036 { 0xd000, LOAD | SETS1 } /* mov.l @(disp,pc),rn */ 2037}; 2038 2039static const struct sh_minor_opcode sh_opcoded[] = 2040{ 2041 { MAP (sh_opcoded0), 0xf000 } 2042}; 2043 2044static const struct sh_opcode sh_opcodee0[] = 2045{ 2046 { 0xe000, SETS1 } /* mov #imm,rn */ 2047}; 2048 2049static const struct sh_minor_opcode sh_opcodee[] = 2050{ 2051 { MAP (sh_opcodee0), 0xf000 } 2052}; 2053 2054static const struct sh_opcode sh_opcodef0[] = 2055{ 2056 { 0xf000, SETSF1 | USESF1 | USESF2 }, /* fadd fm,fn */ 2057 { 0xf001, SETSF1 | USESF1 | USESF2 }, /* fsub fm,fn */ 2058 { 0xf002, SETSF1 | USESF1 | USESF2 }, /* fmul fm,fn */ 2059 { 0xf003, SETSF1 | USESF1 | USESF2 }, /* fdiv fm,fn */ 2060 { 0xf004, SETSSP | USESF1 | USESF2 }, /* fcmp/eq fm,fn */ 2061 { 0xf005, SETSSP | USESF1 | USESF2 }, /* fcmp/gt fm,fn */ 2062 { 0xf006, LOAD | SETSF1 | USES2 | USESR0 }, /* fmov.s @(r0,rm),fn */ 2063 { 0xf007, STORE | USES1 | USESF2 | USESR0 }, /* fmov.s fm,@(r0,rn) */ 2064 { 0xf008, LOAD | SETSF1 | USES2 }, /* fmov.s @rm,fn */ 2065 { 0xf009, LOAD | SETS2 | SETSF1 | USES2 }, /* fmov.s @rm+,fn */ 2066 { 0xf00a, STORE | USES1 | USESF2 }, /* fmov.s fm,@rn */ 2067 { 0xf00b, STORE | SETS1 | USES1 | USESF2 }, /* fmov.s fm,@-rn */ 2068 { 0xf00c, SETSF1 | USESF2 }, /* fmov fm,fn */ 2069 { 0xf00e, SETSF1 | USESF1 | USESF2 | USESF0 } /* fmac f0,fm,fn */ 2070}; 2071 2072static const struct sh_opcode sh_opcodef1[] = 2073{ 2074 { 0xf00d, SETSF1 | USESSP }, /* fsts fpul,fn */ 2075 { 0xf01d, SETSSP | USESF1 }, /* flds fn,fpul */ 2076 { 0xf02d, SETSF1 | USESSP }, /* float fpul,fn */ 2077 { 0xf03d, SETSSP | USESF1 }, /* ftrc fn,fpul */ 2078 { 0xf04d, SETSF1 | USESF1 }, /* fneg fn */ 2079 { 0xf05d, SETSF1 | USESF1 }, /* fabs fn */ 2080 { 0xf06d, SETSF1 | USESF1 }, /* fsqrt fn */ 2081 { 0xf07d, SETSSP | USESF1 }, /* ftst/nan fn */ 2082 { 0xf08d, SETSF1 }, /* fldi0 fn */ 2083 { 0xf09d, SETSF1 } /* fldi1 fn */ 2084}; 2085 2086static const struct sh_minor_opcode sh_opcodef[] = 2087{ 2088 { MAP (sh_opcodef0), 0xf00f }, 2089 { MAP (sh_opcodef1), 0xf0ff } 2090}; 2091 2092static struct sh_major_opcode sh_opcodes[] = 2093{ 2094 { MAP (sh_opcode0) }, 2095 { MAP (sh_opcode1) }, 2096 { MAP (sh_opcode2) }, 2097 { MAP (sh_opcode3) }, 2098 { MAP (sh_opcode4) }, 2099 { MAP (sh_opcode5) }, 2100 { MAP (sh_opcode6) }, 2101 { MAP (sh_opcode7) }, 2102 { MAP (sh_opcode8) }, 2103 { MAP (sh_opcode9) }, 2104 { MAP (sh_opcodea) }, 2105 { MAP (sh_opcodeb) }, 2106 { MAP (sh_opcodec) }, 2107 { MAP (sh_opcoded) }, 2108 { MAP (sh_opcodee) }, 2109 { MAP (sh_opcodef) } 2110}; 2111 2112/* The double data transfer / parallel processing insns are not 2113 described here. This will cause sh_align_load_span to leave them alone. */ 2114 2115static const struct sh_opcode sh_dsp_opcodef0[] = 2116{ 2117 { 0xf400, USESAS | SETSAS | LOAD | SETSSP }, /* movs.x @-as,ds */ 2118 { 0xf401, USESAS | SETSAS | STORE | USESSP }, /* movs.x ds,@-as */ 2119 { 0xf404, USESAS | LOAD | SETSSP }, /* movs.x @as,ds */ 2120 { 0xf405, USESAS | STORE | USESSP }, /* movs.x ds,@as */ 2121 { 0xf408, USESAS | SETSAS | LOAD | SETSSP }, /* movs.x @as+,ds */ 2122 { 0xf409, USESAS | SETSAS | STORE | USESSP }, /* movs.x ds,@as+ */ 2123 { 0xf40c, USESAS | SETSAS | LOAD | SETSSP | USESR8 }, /* movs.x @as+r8,ds */ 2124 { 0xf40d, USESAS | SETSAS | STORE | USESSP | USESR8 } /* movs.x ds,@as+r8 */ 2125}; 2126 2127static const struct sh_minor_opcode sh_dsp_opcodef[] = 2128{ 2129 { MAP (sh_dsp_opcodef0), 0xfc0d } 2130}; 2131 2132/* Given an instruction, return a pointer to the corresponding 2133 sh_opcode structure. Return NULL if the instruction is not 2134 recognized. */ 2135 2136static const struct sh_opcode * 2137sh_insn_info (insn) 2138 unsigned int insn; 2139{ 2140 const struct sh_major_opcode *maj; 2141 const struct sh_minor_opcode *min, *minend; 2142 2143 maj = &sh_opcodes[(insn & 0xf000) >> 12]; 2144 min = maj->minor_opcodes; 2145 minend = min + maj->count; 2146 for (; min < minend; min++) 2147 { 2148 unsigned int l; 2149 const struct sh_opcode *op, *opend; 2150 2151 l = insn & min->mask; 2152 op = min->opcodes; 2153 opend = op + min->count; 2154 2155 /* Since the opcodes tables are sorted, we could use a binary 2156 search here if the count were above some cutoff value. */ 2157 for (; op < opend; op++) 2158 if (op->opcode == l) 2159 return op; 2160 } 2161 2162 return NULL; 2163} 2164 2165/* See whether an instruction uses or sets a general purpose register */ 2166 2167static bfd_boolean 2168sh_insn_uses_or_sets_reg (insn, op, reg) 2169 unsigned int insn; 2170 const struct sh_opcode *op; 2171 unsigned int reg; 2172{ 2173 if (sh_insn_uses_reg (insn, op, reg)) 2174 return TRUE; 2175 2176 return sh_insn_sets_reg (insn, op, reg); 2177} 2178 2179/* See whether an instruction uses a general purpose register. */ 2180 2181static bfd_boolean 2182sh_insn_uses_reg (insn, op, reg) 2183 unsigned int insn; 2184 const struct sh_opcode *op; 2185 unsigned int reg; 2186{ 2187 unsigned int f; 2188 2189 f = op->flags; 2190 2191 if ((f & USES1) != 0 2192 && USES1_REG (insn) == reg) 2193 return TRUE; 2194 if ((f & USES2) != 0 2195 && USES2_REG (insn) == reg) 2196 return TRUE; 2197 if ((f & USESR0) != 0 2198 && reg == 0) 2199 return TRUE; 2200 if ((f & USESAS) && reg == USESAS_REG (insn)) 2201 return TRUE; 2202 if ((f & USESR8) && reg == 8) 2203 return TRUE; 2204 2205 return FALSE; 2206} 2207 2208/* See whether an instruction sets a general purpose register. */ 2209 2210static bfd_boolean 2211sh_insn_sets_reg (insn, op, reg) 2212 unsigned int insn; 2213 const struct sh_opcode *op; 2214 unsigned int reg; 2215{ 2216 unsigned int f; 2217 2218 f = op->flags; 2219 2220 if ((f & SETS1) != 0 2221 && SETS1_REG (insn) == reg) 2222 return TRUE; 2223 if ((f & SETS2) != 0 2224 && SETS2_REG (insn) == reg) 2225 return TRUE; 2226 if ((f & SETSR0) != 0 2227 && reg == 0) 2228 return TRUE; 2229 if ((f & SETSAS) && reg == SETSAS_REG (insn)) 2230 return TRUE; 2231 2232 return FALSE; 2233} 2234 2235/* See whether an instruction uses or sets a floating point register */ 2236 2237static bfd_boolean 2238sh_insn_uses_or_sets_freg (insn, op, reg) 2239 unsigned int insn; 2240 const struct sh_opcode *op; 2241 unsigned int reg; 2242{ 2243 if (sh_insn_uses_freg (insn, op, reg)) 2244 return TRUE; 2245 2246 return sh_insn_sets_freg (insn, op, reg); 2247} 2248 2249/* See whether an instruction uses a floating point register. */ 2250 2251static bfd_boolean 2252sh_insn_uses_freg (insn, op, freg) 2253 unsigned int insn; 2254 const struct sh_opcode *op; 2255 unsigned int freg; 2256{ 2257 unsigned int f; 2258 2259 f = op->flags; 2260 2261 /* We can't tell if this is a double-precision insn, so just play safe 2262 and assume that it might be. So not only have we test FREG against 2263 itself, but also even FREG against FREG+1 - if the using insn uses 2264 just the low part of a double precision value - but also an odd 2265 FREG against FREG-1 - if the setting insn sets just the low part 2266 of a double precision value. 2267 So what this all boils down to is that we have to ignore the lowest 2268 bit of the register number. */ 2269 2270 if ((f & USESF1) != 0 2271 && (USESF1_REG (insn) & 0xe) == (freg & 0xe)) 2272 return TRUE; 2273 if ((f & USESF2) != 0 2274 && (USESF2_REG (insn) & 0xe) == (freg & 0xe)) 2275 return TRUE; 2276 if ((f & USESF0) != 0 2277 && freg == 0) 2278 return TRUE; 2279 2280 return FALSE; 2281} 2282 2283/* See whether an instruction sets a floating point register. */ 2284 2285static bfd_boolean 2286sh_insn_sets_freg (insn, op, freg) 2287 unsigned int insn; 2288 const struct sh_opcode *op; 2289 unsigned int freg; 2290{ 2291 unsigned int f; 2292 2293 f = op->flags; 2294 2295 /* We can't tell if this is a double-precision insn, so just play safe 2296 and assume that it might be. So not only have we test FREG against 2297 itself, but also even FREG against FREG+1 - if the using insn uses 2298 just the low part of a double precision value - but also an odd 2299 FREG against FREG-1 - if the setting insn sets just the low part 2300 of a double precision value. 2301 So what this all boils down to is that we have to ignore the lowest 2302 bit of the register number. */ 2303 2304 if ((f & SETSF1) != 0 2305 && (SETSF1_REG (insn) & 0xe) == (freg & 0xe)) 2306 return TRUE; 2307 2308 return FALSE; 2309} 2310 2311/* See whether instructions I1 and I2 conflict, assuming I1 comes 2312 before I2. OP1 and OP2 are the corresponding sh_opcode structures. 2313 This should return TRUE if there is a conflict, or FALSE if the 2314 instructions can be swapped safely. */ 2315 2316static bfd_boolean 2317sh_insns_conflict (i1, op1, i2, op2) 2318 unsigned int i1; 2319 const struct sh_opcode *op1; 2320 unsigned int i2; 2321 const struct sh_opcode *op2; 2322{ 2323 unsigned int f1, f2; 2324 2325 f1 = op1->flags; 2326 f2 = op2->flags; 2327 2328 /* Load of fpscr conflicts with floating point operations. 2329 FIXME: shouldn't test raw opcodes here. */ 2330 if (((i1 & 0xf0ff) == 0x4066 && (i2 & 0xf000) == 0xf000) 2331 || ((i2 & 0xf0ff) == 0x4066 && (i1 & 0xf000) == 0xf000)) 2332 return TRUE; 2333 2334 if ((f1 & (BRANCH | DELAY)) != 0 2335 || (f2 & (BRANCH | DELAY)) != 0) 2336 return TRUE; 2337 2338 if (((f1 | f2) & SETSSP) 2339 && (f1 & (SETSSP | USESSP)) 2340 && (f2 & (SETSSP | USESSP))) 2341 return TRUE; 2342 2343 if ((f1 & SETS1) != 0 2344 && sh_insn_uses_or_sets_reg (i2, op2, SETS1_REG (i1))) 2345 return TRUE; 2346 if ((f1 & SETS2) != 0 2347 && sh_insn_uses_or_sets_reg (i2, op2, SETS2_REG (i1))) 2348 return TRUE; 2349 if ((f1 & SETSR0) != 0 2350 && sh_insn_uses_or_sets_reg (i2, op2, 0)) 2351 return TRUE; 2352 if ((f1 & SETSAS) 2353 && sh_insn_uses_or_sets_reg (i2, op2, SETSAS_REG (i1))) 2354 return TRUE; 2355 if ((f1 & SETSF1) != 0 2356 && sh_insn_uses_or_sets_freg (i2, op2, SETSF1_REG (i1))) 2357 return TRUE; 2358 2359 if ((f2 & SETS1) != 0 2360 && sh_insn_uses_or_sets_reg (i1, op1, SETS1_REG (i2))) 2361 return TRUE; 2362 if ((f2 & SETS2) != 0 2363 && sh_insn_uses_or_sets_reg (i1, op1, SETS2_REG (i2))) 2364 return TRUE; 2365 if ((f2 & SETSR0) != 0 2366 && sh_insn_uses_or_sets_reg (i1, op1, 0)) 2367 return TRUE; 2368 if ((f2 & SETSAS) 2369 && sh_insn_uses_or_sets_reg (i1, op1, SETSAS_REG (i2))) 2370 return TRUE; 2371 if ((f2 & SETSF1) != 0 2372 && sh_insn_uses_or_sets_freg (i1, op1, SETSF1_REG (i2))) 2373 return TRUE; 2374 2375 /* The instructions do not conflict. */ 2376 return FALSE; 2377} 2378 2379/* I1 is a load instruction, and I2 is some other instruction. Return 2380 TRUE if I1 loads a register which I2 uses. */ 2381 2382static bfd_boolean 2383sh_load_use (i1, op1, i2, op2) 2384 unsigned int i1; 2385 const struct sh_opcode *op1; 2386 unsigned int i2; 2387 const struct sh_opcode *op2; 2388{ 2389 unsigned int f1; 2390 2391 f1 = op1->flags; 2392 2393 if ((f1 & LOAD) == 0) 2394 return FALSE; 2395 2396 /* If both SETS1 and SETSSP are set, that means a load to a special 2397 register using postincrement addressing mode, which we don't care 2398 about here. */ 2399 if ((f1 & SETS1) != 0 2400 && (f1 & SETSSP) == 0 2401 && sh_insn_uses_reg (i2, op2, (i1 & 0x0f00) >> 8)) 2402 return TRUE; 2403 2404 if ((f1 & SETSR0) != 0 2405 && sh_insn_uses_reg (i2, op2, 0)) 2406 return TRUE; 2407 2408 if ((f1 & SETSF1) != 0 2409 && sh_insn_uses_freg (i2, op2, (i1 & 0x0f00) >> 8)) 2410 return TRUE; 2411 2412 return FALSE; 2413} 2414 2415/* Try to align loads and stores within a span of memory. This is 2416 called by both the ELF and the COFF sh targets. ABFD and SEC are 2417 the BFD and section we are examining. CONTENTS is the contents of 2418 the section. SWAP is the routine to call to swap two instructions. 2419 RELOCS is a pointer to the internal relocation information, to be 2420 passed to SWAP. PLABEL is a pointer to the current label in a 2421 sorted list of labels; LABEL_END is the end of the list. START and 2422 STOP are the range of memory to examine. If a swap is made, 2423 *PSWAPPED is set to TRUE. */ 2424 2425#ifdef COFF_WITH_PE 2426static 2427#endif 2428bfd_boolean 2429_bfd_sh_align_load_span (abfd, sec, contents, swap, relocs, 2430 plabel, label_end, start, stop, pswapped) 2431 bfd *abfd; 2432 asection *sec; 2433 bfd_byte *contents; 2434 bfd_boolean (*swap) PARAMS ((bfd *, asection *, PTR, bfd_byte *, bfd_vma)); 2435 PTR relocs; 2436 bfd_vma **plabel; 2437 bfd_vma *label_end; 2438 bfd_vma start; 2439 bfd_vma stop; 2440 bfd_boolean *pswapped; 2441{ 2442 int dsp = (abfd->arch_info->mach == bfd_mach_sh_dsp 2443 || abfd->arch_info->mach == bfd_mach_sh3_dsp); 2444 bfd_vma i; 2445 2446 /* The SH4 has a Harvard architecture, hence aligning loads is not 2447 desirable. In fact, it is counter-productive, since it interferes 2448 with the schedules generated by the compiler. */ 2449 if (abfd->arch_info->mach == bfd_mach_sh4) 2450 return TRUE; 2451 2452 /* If we are linking sh[3]-dsp code, swap the FPU instructions for DSP 2453 instructions. */ 2454 if (dsp) 2455 { 2456 sh_opcodes[0xf].minor_opcodes = sh_dsp_opcodef; 2457 sh_opcodes[0xf].count = sizeof sh_dsp_opcodef / sizeof sh_dsp_opcodef; 2458 } 2459 2460 /* Instructions should be aligned on 2 byte boundaries. */ 2461 if ((start & 1) == 1) 2462 ++start; 2463 2464 /* Now look through the unaligned addresses. */ 2465 i = start; 2466 if ((i & 2) == 0) 2467 i += 2; 2468 for (; i < stop; i += 4) 2469 { 2470 unsigned int insn; 2471 const struct sh_opcode *op; 2472 unsigned int prev_insn = 0; 2473 const struct sh_opcode *prev_op = NULL; 2474 2475 insn = bfd_get_16 (abfd, contents + i); 2476 op = sh_insn_info (insn); 2477 if (op == NULL 2478 || (op->flags & (LOAD | STORE)) == 0) 2479 continue; 2480 2481 /* This is a load or store which is not on a four byte boundary. */ 2482 2483 while (*plabel < label_end && **plabel < i) 2484 ++*plabel; 2485 2486 if (i > start) 2487 { 2488 prev_insn = bfd_get_16 (abfd, contents + i - 2); 2489 /* If INSN is the field b of a parallel processing insn, it is not 2490 a load / store after all. Note that the test here might mistake 2491 the field_b of a pcopy insn for the starting code of a parallel 2492 processing insn; this might miss a swapping opportunity, but at 2493 least we're on the safe side. */ 2494 if (dsp && (prev_insn & 0xfc00) == 0xf800) 2495 continue; 2496 2497 /* Check if prev_insn is actually the field b of a parallel 2498 processing insn. Again, this can give a spurious match 2499 after a pcopy. */ 2500 if (dsp && i - 2 > start) 2501 { 2502 unsigned pprev_insn = bfd_get_16 (abfd, contents + i - 4); 2503 2504 if ((pprev_insn & 0xfc00) == 0xf800) 2505 prev_op = NULL; 2506 else 2507 prev_op = sh_insn_info (prev_insn); 2508 } 2509 else 2510 prev_op = sh_insn_info (prev_insn); 2511 2512 /* If the load/store instruction is in a delay slot, we 2513 can't swap. */ 2514 if (prev_op == NULL 2515 || (prev_op->flags & DELAY) != 0) 2516 continue; 2517 } 2518 if (i > start 2519 && (*plabel >= label_end || **plabel != i) 2520 && prev_op != NULL 2521 && (prev_op->flags & (LOAD | STORE)) == 0 2522 && ! sh_insns_conflict (prev_insn, prev_op, insn, op)) 2523 { 2524 bfd_boolean ok; 2525 2526 /* The load/store instruction does not have a label, and 2527 there is a previous instruction; PREV_INSN is not 2528 itself a load/store instruction, and PREV_INSN and 2529 INSN do not conflict. */ 2530 2531 ok = TRUE; 2532 2533 if (i >= start + 4) 2534 { 2535 unsigned int prev2_insn; 2536 const struct sh_opcode *prev2_op; 2537 2538 prev2_insn = bfd_get_16 (abfd, contents + i - 4); 2539 prev2_op = sh_insn_info (prev2_insn); 2540 2541 /* If the instruction before PREV_INSN has a delay 2542 slot--that is, PREV_INSN is in a delay slot--we 2543 can not swap. */ 2544 if (prev2_op == NULL 2545 || (prev2_op->flags & DELAY) != 0) 2546 ok = FALSE; 2547 2548 /* If the instruction before PREV_INSN is a load, 2549 and it sets a register which INSN uses, then 2550 putting INSN immediately after PREV_INSN will 2551 cause a pipeline bubble, so there is no point to 2552 making the swap. */ 2553 if (ok 2554 && (prev2_op->flags & LOAD) != 0 2555 && sh_load_use (prev2_insn, prev2_op, insn, op)) 2556 ok = FALSE; 2557 } 2558 2559 if (ok) 2560 { 2561 if (! (*swap) (abfd, sec, relocs, contents, i - 2)) 2562 return FALSE; 2563 *pswapped = TRUE; 2564 continue; 2565 } 2566 } 2567 2568 while (*plabel < label_end && **plabel < i + 2) 2569 ++*plabel; 2570 2571 if (i + 2 < stop 2572 && (*plabel >= label_end || **plabel != i + 2)) 2573 { 2574 unsigned int next_insn; 2575 const struct sh_opcode *next_op; 2576 2577 /* There is an instruction after the load/store 2578 instruction, and it does not have a label. */ 2579 next_insn = bfd_get_16 (abfd, contents + i + 2); 2580 next_op = sh_insn_info (next_insn); 2581 if (next_op != NULL 2582 && (next_op->flags & (LOAD | STORE)) == 0 2583 && ! sh_insns_conflict (insn, op, next_insn, next_op)) 2584 { 2585 bfd_boolean ok; 2586 2587 /* NEXT_INSN is not itself a load/store instruction, 2588 and it does not conflict with INSN. */ 2589 2590 ok = TRUE; 2591 2592 /* If PREV_INSN is a load, and it sets a register 2593 which NEXT_INSN uses, then putting NEXT_INSN 2594 immediately after PREV_INSN will cause a pipeline 2595 bubble, so there is no reason to make this swap. */ 2596 if (prev_op != NULL 2597 && (prev_op->flags & LOAD) != 0 2598 && sh_load_use (prev_insn, prev_op, next_insn, next_op)) 2599 ok = FALSE; 2600 2601 /* If INSN is a load, and it sets a register which 2602 the insn after NEXT_INSN uses, then doing the 2603 swap will cause a pipeline bubble, so there is no 2604 reason to make the swap. However, if the insn 2605 after NEXT_INSN is itself a load or store 2606 instruction, then it is misaligned, so 2607 optimistically hope that it will be swapped 2608 itself, and just live with the pipeline bubble if 2609 it isn't. */ 2610 if (ok 2611 && i + 4 < stop 2612 && (op->flags & LOAD) != 0) 2613 { 2614 unsigned int next2_insn; 2615 const struct sh_opcode *next2_op; 2616 2617 next2_insn = bfd_get_16 (abfd, contents + i + 4); 2618 next2_op = sh_insn_info (next2_insn); 2619 if ((next2_op->flags & (LOAD | STORE)) == 0 2620 && sh_load_use (insn, op, next2_insn, next2_op)) 2621 ok = FALSE; 2622 } 2623 2624 if (ok) 2625 { 2626 if (! (*swap) (abfd, sec, relocs, contents, i)) 2627 return FALSE; 2628 *pswapped = TRUE; 2629 continue; 2630 } 2631 } 2632 } 2633 } 2634 2635 return TRUE; 2636} 2637#endif /* not COFF_IMAGE_WITH_PE */ 2638 2639/* Look for loads and stores which we can align to four byte 2640 boundaries. See the longer comment above sh_relax_section for why 2641 this is desirable. This sets *PSWAPPED if some instruction was 2642 swapped. */ 2643 2644static bfd_boolean 2645sh_align_loads (abfd, sec, internal_relocs, contents, pswapped) 2646 bfd *abfd; 2647 asection *sec; 2648 struct internal_reloc *internal_relocs; 2649 bfd_byte *contents; 2650 bfd_boolean *pswapped; 2651{ 2652 struct internal_reloc *irel, *irelend; 2653 bfd_vma *labels = NULL; 2654 bfd_vma *label, *label_end; 2655 bfd_size_type amt; 2656 2657 *pswapped = FALSE; 2658 2659 irelend = internal_relocs + sec->reloc_count; 2660 2661 /* Get all the addresses with labels on them. */ 2662 amt = (bfd_size_type) sec->reloc_count * sizeof (bfd_vma); 2663 labels = (bfd_vma *) bfd_malloc (amt); 2664 if (labels == NULL) 2665 goto error_return; 2666 label_end = labels; 2667 for (irel = internal_relocs; irel < irelend; irel++) 2668 { 2669 if (irel->r_type == R_SH_LABEL) 2670 { 2671 *label_end = irel->r_vaddr - sec->vma; 2672 ++label_end; 2673 } 2674 } 2675 2676 /* Note that the assembler currently always outputs relocs in 2677 address order. If that ever changes, this code will need to sort 2678 the label values and the relocs. */ 2679 2680 label = labels; 2681 2682 for (irel = internal_relocs; irel < irelend; irel++) 2683 { 2684 bfd_vma start, stop; 2685 2686 if (irel->r_type != R_SH_CODE) 2687 continue; 2688 2689 start = irel->r_vaddr - sec->vma; 2690 2691 for (irel++; irel < irelend; irel++) 2692 if (irel->r_type == R_SH_DATA) 2693 break; 2694 if (irel < irelend) 2695 stop = irel->r_vaddr - sec->vma; 2696 else 2697 stop = sec->_cooked_size; 2698 2699 if (! _bfd_sh_align_load_span (abfd, sec, contents, sh_swap_insns, 2700 (PTR) internal_relocs, &label, 2701 label_end, start, stop, pswapped)) 2702 goto error_return; 2703 } 2704 2705 free (labels); 2706 2707 return TRUE; 2708 2709 error_return: 2710 if (labels != NULL) 2711 free (labels); 2712 return FALSE; 2713} 2714 2715/* Swap two SH instructions. */ 2716 2717static bfd_boolean 2718sh_swap_insns (abfd, sec, relocs, contents, addr) 2719 bfd *abfd; 2720 asection *sec; 2721 PTR relocs; 2722 bfd_byte *contents; 2723 bfd_vma addr; 2724{ 2725 struct internal_reloc *internal_relocs = (struct internal_reloc *) relocs; 2726 unsigned short i1, i2; 2727 struct internal_reloc *irel, *irelend; 2728 2729 /* Swap the instructions themselves. */ 2730 i1 = bfd_get_16 (abfd, contents + addr); 2731 i2 = bfd_get_16 (abfd, contents + addr + 2); 2732 bfd_put_16 (abfd, (bfd_vma) i2, contents + addr); 2733 bfd_put_16 (abfd, (bfd_vma) i1, contents + addr + 2); 2734 2735 /* Adjust all reloc addresses. */ 2736 irelend = internal_relocs + sec->reloc_count; 2737 for (irel = internal_relocs; irel < irelend; irel++) 2738 { 2739 int type, add; 2740 2741 /* There are a few special types of relocs that we don't want to 2742 adjust. These relocs do not apply to the instruction itself, 2743 but are only associated with the address. */ 2744 type = irel->r_type; 2745 if (type == R_SH_ALIGN 2746 || type == R_SH_CODE 2747 || type == R_SH_DATA 2748 || type == R_SH_LABEL) 2749 continue; 2750 2751 /* If an R_SH_USES reloc points to one of the addresses being 2752 swapped, we must adjust it. It would be incorrect to do this 2753 for a jump, though, since we want to execute both 2754 instructions after the jump. (We have avoided swapping 2755 around a label, so the jump will not wind up executing an 2756 instruction it shouldn't). */ 2757 if (type == R_SH_USES) 2758 { 2759 bfd_vma off; 2760 2761 off = irel->r_vaddr - sec->vma + 4 + irel->r_offset; 2762 if (off == addr) 2763 irel->r_offset += 2; 2764 else if (off == addr + 2) 2765 irel->r_offset -= 2; 2766 } 2767 2768 if (irel->r_vaddr - sec->vma == addr) 2769 { 2770 irel->r_vaddr += 2; 2771 add = -2; 2772 } 2773 else if (irel->r_vaddr - sec->vma == addr + 2) 2774 { 2775 irel->r_vaddr -= 2; 2776 add = 2; 2777 } 2778 else 2779 add = 0; 2780 2781 if (add != 0) 2782 { 2783 bfd_byte *loc; 2784 unsigned short insn, oinsn; 2785 bfd_boolean overflow; 2786 2787 loc = contents + irel->r_vaddr - sec->vma; 2788 overflow = FALSE; 2789 switch (type) 2790 { 2791 default: 2792 break; 2793 2794 case R_SH_PCDISP8BY2: 2795 case R_SH_PCRELIMM8BY2: 2796 insn = bfd_get_16 (abfd, loc); 2797 oinsn = insn; 2798 insn += add / 2; 2799 if ((oinsn & 0xff00) != (insn & 0xff00)) 2800 overflow = TRUE; 2801 bfd_put_16 (abfd, (bfd_vma) insn, loc); 2802 break; 2803 2804 case R_SH_PCDISP: 2805 insn = bfd_get_16 (abfd, loc); 2806 oinsn = insn; 2807 insn += add / 2; 2808 if ((oinsn & 0xf000) != (insn & 0xf000)) 2809 overflow = TRUE; 2810 bfd_put_16 (abfd, (bfd_vma) insn, loc); 2811 break; 2812 2813 case R_SH_PCRELIMM8BY4: 2814 /* This reloc ignores the least significant 3 bits of 2815 the program counter before adding in the offset. 2816 This means that if ADDR is at an even address, the 2817 swap will not affect the offset. If ADDR is an at an 2818 odd address, then the instruction will be crossing a 2819 four byte boundary, and must be adjusted. */ 2820 if ((addr & 3) != 0) 2821 { 2822 insn = bfd_get_16 (abfd, loc); 2823 oinsn = insn; 2824 insn += add / 2; 2825 if ((oinsn & 0xff00) != (insn & 0xff00)) 2826 overflow = TRUE; 2827 bfd_put_16 (abfd, (bfd_vma) insn, loc); 2828 } 2829 2830 break; 2831 } 2832 2833 if (overflow) 2834 { 2835 ((*_bfd_error_handler) 2836 ("%s: 0x%lx: fatal: reloc overflow while relaxing", 2837 bfd_archive_filename (abfd), (unsigned long) irel->r_vaddr)); 2838 bfd_set_error (bfd_error_bad_value); 2839 return FALSE; 2840 } 2841 } 2842 } 2843 2844 return TRUE; 2845} 2846 2847/* This is a modification of _bfd_coff_generic_relocate_section, which 2848 will handle SH relaxing. */ 2849 2850static bfd_boolean 2851sh_relocate_section (output_bfd, info, input_bfd, input_section, contents, 2852 relocs, syms, sections) 2853 bfd *output_bfd ATTRIBUTE_UNUSED; 2854 struct bfd_link_info *info; 2855 bfd *input_bfd; 2856 asection *input_section; 2857 bfd_byte *contents; 2858 struct internal_reloc *relocs; 2859 struct internal_syment *syms; 2860 asection **sections; 2861{ 2862 struct internal_reloc *rel; 2863 struct internal_reloc *relend; 2864 2865 rel = relocs; 2866 relend = rel + input_section->reloc_count; 2867 for (; rel < relend; rel++) 2868 { 2869 long symndx; 2870 struct coff_link_hash_entry *h; 2871 struct internal_syment *sym; 2872 bfd_vma addend; 2873 bfd_vma val; 2874 reloc_howto_type *howto; 2875 bfd_reloc_status_type rstat; 2876 2877 /* Almost all relocs have to do with relaxing. If any work must 2878 be done for them, it has been done in sh_relax_section. */ 2879 if (rel->r_type != R_SH_IMM32 2880#ifdef COFF_WITH_PE 2881 && rel->r_type != R_SH_IMM32CE 2882 && rel->r_type != R_SH_IMAGEBASE 2883#endif 2884 && rel->r_type != R_SH_PCDISP) 2885 continue; 2886 2887 symndx = rel->r_symndx; 2888 2889 if (symndx == -1) 2890 { 2891 h = NULL; 2892 sym = NULL; 2893 } 2894 else 2895 { 2896 if (symndx < 0 2897 || (unsigned long) symndx >= obj_raw_syment_count (input_bfd)) 2898 { 2899 (*_bfd_error_handler) 2900 ("%s: illegal symbol index %ld in relocs", 2901 bfd_archive_filename (input_bfd), symndx); 2902 bfd_set_error (bfd_error_bad_value); 2903 return FALSE; 2904 } 2905 h = obj_coff_sym_hashes (input_bfd)[symndx]; 2906 sym = syms + symndx; 2907 } 2908 2909 if (sym != NULL && sym->n_scnum != 0) 2910 addend = - sym->n_value; 2911 else 2912 addend = 0; 2913 2914 if (rel->r_type == R_SH_PCDISP) 2915 addend -= 4; 2916 2917 if (rel->r_type >= SH_COFF_HOWTO_COUNT) 2918 howto = NULL; 2919 else 2920 howto = &sh_coff_howtos[rel->r_type]; 2921 2922 if (howto == NULL) 2923 { 2924 bfd_set_error (bfd_error_bad_value); 2925 return FALSE; 2926 } 2927 2928#ifdef COFF_WITH_PE 2929 if (rel->r_type == R_SH_IMAGEBASE) 2930 addend -= pe_data (input_section->output_section->owner)->pe_opthdr.ImageBase; 2931#endif 2932 2933 val = 0; 2934 2935 if (h == NULL) 2936 { 2937 asection *sec; 2938 2939 /* There is nothing to do for an internal PCDISP reloc. */ 2940 if (rel->r_type == R_SH_PCDISP) 2941 continue; 2942 2943 if (symndx == -1) 2944 { 2945 sec = bfd_abs_section_ptr; 2946 val = 0; 2947 } 2948 else 2949 { 2950 sec = sections[symndx]; 2951 val = (sec->output_section->vma 2952 + sec->output_offset 2953 + sym->n_value 2954 - sec->vma); 2955 } 2956 } 2957 else 2958 { 2959 if (h->root.type == bfd_link_hash_defined 2960 || h->root.type == bfd_link_hash_defweak) 2961 { 2962 asection *sec; 2963 2964 sec = h->root.u.def.section; 2965 val = (h->root.u.def.value 2966 + sec->output_section->vma 2967 + sec->output_offset); 2968 } 2969 else if (! info->relocatable) 2970 { 2971 if (! ((*info->callbacks->undefined_symbol) 2972 (info, h->root.root.string, input_bfd, input_section, 2973 rel->r_vaddr - input_section->vma, TRUE))) 2974 return FALSE; 2975 } 2976 } 2977 2978 rstat = _bfd_final_link_relocate (howto, input_bfd, input_section, 2979 contents, 2980 rel->r_vaddr - input_section->vma, 2981 val, addend); 2982 2983 switch (rstat) 2984 { 2985 default: 2986 abort (); 2987 case bfd_reloc_ok: 2988 break; 2989 case bfd_reloc_overflow: 2990 { 2991 const char *name; 2992 char buf[SYMNMLEN + 1]; 2993 2994 if (symndx == -1) 2995 name = "*ABS*"; 2996 else if (h != NULL) 2997 name = h->root.root.string; 2998 else if (sym->_n._n_n._n_zeroes == 0 2999 && sym->_n._n_n._n_offset != 0) 3000 name = obj_coff_strings (input_bfd) + sym->_n._n_n._n_offset; 3001 else 3002 { 3003 strncpy (buf, sym->_n._n_name, SYMNMLEN); 3004 buf[SYMNMLEN] = '\0'; 3005 name = buf; 3006 } 3007 3008 if (! ((*info->callbacks->reloc_overflow) 3009 (info, name, howto->name, (bfd_vma) 0, input_bfd, 3010 input_section, rel->r_vaddr - input_section->vma))) 3011 return FALSE; 3012 } 3013 } 3014 } 3015 3016 return TRUE; 3017} 3018 3019/* This is a version of bfd_generic_get_relocated_section_contents 3020 which uses sh_relocate_section. */ 3021 3022static bfd_byte * 3023sh_coff_get_relocated_section_contents (output_bfd, link_info, link_order, 3024 data, relocatable, symbols) 3025 bfd *output_bfd; 3026 struct bfd_link_info *link_info; 3027 struct bfd_link_order *link_order; 3028 bfd_byte *data; 3029 bfd_boolean relocatable; 3030 asymbol **symbols; 3031{ 3032 asection *input_section = link_order->u.indirect.section; 3033 bfd *input_bfd = input_section->owner; 3034 asection **sections = NULL; 3035 struct internal_reloc *internal_relocs = NULL; 3036 struct internal_syment *internal_syms = NULL; 3037 3038 /* We only need to handle the case of relaxing, or of having a 3039 particular set of section contents, specially. */ 3040 if (relocatable 3041 || coff_section_data (input_bfd, input_section) == NULL 3042 || coff_section_data (input_bfd, input_section)->contents == NULL) 3043 return bfd_generic_get_relocated_section_contents (output_bfd, link_info, 3044 link_order, data, 3045 relocatable, 3046 symbols); 3047 3048 memcpy (data, coff_section_data (input_bfd, input_section)->contents, 3049 (size_t) input_section->_raw_size); 3050 3051 if ((input_section->flags & SEC_RELOC) != 0 3052 && input_section->reloc_count > 0) 3053 { 3054 bfd_size_type symesz = bfd_coff_symesz (input_bfd); 3055 bfd_byte *esym, *esymend; 3056 struct internal_syment *isymp; 3057 asection **secpp; 3058 bfd_size_type amt; 3059 3060 if (! _bfd_coff_get_external_symbols (input_bfd)) 3061 goto error_return; 3062 3063 internal_relocs = (_bfd_coff_read_internal_relocs 3064 (input_bfd, input_section, FALSE, (bfd_byte *) NULL, 3065 FALSE, (struct internal_reloc *) NULL)); 3066 if (internal_relocs == NULL) 3067 goto error_return; 3068 3069 amt = obj_raw_syment_count (input_bfd); 3070 amt *= sizeof (struct internal_syment); 3071 internal_syms = (struct internal_syment *) bfd_malloc (amt); 3072 if (internal_syms == NULL) 3073 goto error_return; 3074 3075 amt = obj_raw_syment_count (input_bfd); 3076 amt *= sizeof (asection *); 3077 sections = (asection **) bfd_malloc (amt); 3078 if (sections == NULL) 3079 goto error_return; 3080 3081 isymp = internal_syms; 3082 secpp = sections; 3083 esym = (bfd_byte *) obj_coff_external_syms (input_bfd); 3084 esymend = esym + obj_raw_syment_count (input_bfd) * symesz; 3085 while (esym < esymend) 3086 { 3087 bfd_coff_swap_sym_in (input_bfd, (PTR) esym, (PTR) isymp); 3088 3089 if (isymp->n_scnum != 0) 3090 *secpp = coff_section_from_bfd_index (input_bfd, isymp->n_scnum); 3091 else 3092 { 3093 if (isymp->n_value == 0) 3094 *secpp = bfd_und_section_ptr; 3095 else 3096 *secpp = bfd_com_section_ptr; 3097 } 3098 3099 esym += (isymp->n_numaux + 1) * symesz; 3100 secpp += isymp->n_numaux + 1; 3101 isymp += isymp->n_numaux + 1; 3102 } 3103 3104 if (! sh_relocate_section (output_bfd, link_info, input_bfd, 3105 input_section, data, internal_relocs, 3106 internal_syms, sections)) 3107 goto error_return; 3108 3109 free (sections); 3110 sections = NULL; 3111 free (internal_syms); 3112 internal_syms = NULL; 3113 free (internal_relocs); 3114 internal_relocs = NULL; 3115 } 3116 3117 return data; 3118 3119 error_return: 3120 if (internal_relocs != NULL) 3121 free (internal_relocs); 3122 if (internal_syms != NULL) 3123 free (internal_syms); 3124 if (sections != NULL) 3125 free (sections); 3126 return NULL; 3127} 3128 3129/* The target vectors. */ 3130 3131#ifndef TARGET_SHL_SYM 3132CREATE_BIG_COFF_TARGET_VEC (shcoff_vec, "coff-sh", BFD_IS_RELAXABLE, 0, '_', NULL, COFF_SWAP_TABLE) 3133#endif 3134 3135#ifdef TARGET_SHL_SYM 3136#define TARGET_SYM TARGET_SHL_SYM 3137#else 3138#define TARGET_SYM shlcoff_vec 3139#endif 3140 3141#ifndef TARGET_SHL_NAME 3142#define TARGET_SHL_NAME "coff-shl" 3143#endif 3144 3145#ifdef COFF_WITH_PE 3146CREATE_LITTLE_COFF_TARGET_VEC (TARGET_SYM, TARGET_SHL_NAME, BFD_IS_RELAXABLE, 3147 SEC_CODE | SEC_DATA, '_', NULL, COFF_SWAP_TABLE); 3148#else 3149CREATE_LITTLE_COFF_TARGET_VEC (TARGET_SYM, TARGET_SHL_NAME, BFD_IS_RELAXABLE, 3150 0, '_', NULL, COFF_SWAP_TABLE) 3151#endif 3152 3153#ifndef TARGET_SHL_SYM 3154static const bfd_target * coff_small_object_p PARAMS ((bfd *)); 3155static bfd_boolean coff_small_new_section_hook PARAMS ((bfd *, asection *)); 3156/* Some people want versions of the SH COFF target which do not align 3157 to 16 byte boundaries. We implement that by adding a couple of new 3158 target vectors. These are just like the ones above, but they 3159 change the default section alignment. To generate them in the 3160 assembler, use -small. To use them in the linker, use -b 3161 coff-sh{l}-small and -oformat coff-sh{l}-small. 3162 3163 Yes, this is a horrible hack. A general solution for setting 3164 section alignment in COFF is rather complex. ELF handles this 3165 correctly. */ 3166 3167/* Only recognize the small versions if the target was not defaulted. 3168 Otherwise we won't recognize the non default endianness. */ 3169 3170static const bfd_target * 3171coff_small_object_p (abfd) 3172 bfd *abfd; 3173{ 3174 if (abfd->target_defaulted) 3175 { 3176 bfd_set_error (bfd_error_wrong_format); 3177 return NULL; 3178 } 3179 return coff_object_p (abfd); 3180} 3181 3182/* Set the section alignment for the small versions. */ 3183 3184static bfd_boolean 3185coff_small_new_section_hook (abfd, section) 3186 bfd *abfd; 3187 asection *section; 3188{ 3189 if (! coff_new_section_hook (abfd, section)) 3190 return FALSE; 3191 3192 /* We must align to at least a four byte boundary, because longword 3193 accesses must be on a four byte boundary. */ 3194 if (section->alignment_power == COFF_DEFAULT_SECTION_ALIGNMENT_POWER) 3195 section->alignment_power = 2; 3196 3197 return TRUE; 3198} 3199 3200/* This is copied from bfd_coff_std_swap_table so that we can change 3201 the default section alignment power. */ 3202 3203static const bfd_coff_backend_data bfd_coff_small_swap_table = 3204{ 3205 coff_swap_aux_in, coff_swap_sym_in, coff_swap_lineno_in, 3206 coff_swap_aux_out, coff_swap_sym_out, 3207 coff_swap_lineno_out, coff_swap_reloc_out, 3208 coff_swap_filehdr_out, coff_swap_aouthdr_out, 3209 coff_swap_scnhdr_out, 3210 FILHSZ, AOUTSZ, SCNHSZ, SYMESZ, AUXESZ, RELSZ, LINESZ, FILNMLEN, 3211#ifdef COFF_LONG_FILENAMES 3212 TRUE, 3213#else 3214 FALSE, 3215#endif 3216#ifdef COFF_LONG_SECTION_NAMES 3217 TRUE, 3218#else 3219 FALSE, 3220#endif 3221 2, 3222#ifdef COFF_FORCE_SYMBOLS_IN_STRINGS 3223 TRUE, 3224#else 3225 FALSE, 3226#endif 3227#ifdef COFF_DEBUG_STRING_WIDE_PREFIX 3228 4, 3229#else 3230 2, 3231#endif 3232 coff_swap_filehdr_in, coff_swap_aouthdr_in, coff_swap_scnhdr_in, 3233 coff_swap_reloc_in, coff_bad_format_hook, coff_set_arch_mach_hook, 3234 coff_mkobject_hook, styp_to_sec_flags, coff_set_alignment_hook, 3235 coff_slurp_symbol_table, symname_in_debug_hook, coff_pointerize_aux_hook, 3236 coff_print_aux, coff_reloc16_extra_cases, coff_reloc16_estimate, 3237 coff_classify_symbol, coff_compute_section_file_positions, 3238 coff_start_final_link, coff_relocate_section, coff_rtype_to_howto, 3239 coff_adjust_symndx, coff_link_add_one_symbol, 3240 coff_link_output_has_begun, coff_final_link_postscript 3241}; 3242 3243#define coff_small_close_and_cleanup \ 3244 coff_close_and_cleanup 3245#define coff_small_bfd_free_cached_info \ 3246 coff_bfd_free_cached_info 3247#define coff_small_get_section_contents \ 3248 coff_get_section_contents 3249#define coff_small_get_section_contents_in_window \ 3250 coff_get_section_contents_in_window 3251 3252extern const bfd_target shlcoff_small_vec; 3253 3254const bfd_target shcoff_small_vec = 3255{ 3256 "coff-sh-small", /* name */ 3257 bfd_target_coff_flavour, 3258 BFD_ENDIAN_BIG, /* data byte order is big */ 3259 BFD_ENDIAN_BIG, /* header byte order is big */ 3260 3261 (HAS_RELOC | EXEC_P | /* object flags */ 3262 HAS_LINENO | HAS_DEBUG | 3263 HAS_SYMS | HAS_LOCALS | WP_TEXT | BFD_IS_RELAXABLE), 3264 3265 (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_RELOC), 3266 '_', /* leading symbol underscore */ 3267 '/', /* ar_pad_char */ 3268 15, /* ar_max_namelen */ 3269 bfd_getb64, bfd_getb_signed_64, bfd_putb64, 3270 bfd_getb32, bfd_getb_signed_32, bfd_putb32, 3271 bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* data */ 3272 bfd_getb64, bfd_getb_signed_64, bfd_putb64, 3273 bfd_getb32, bfd_getb_signed_32, bfd_putb32, 3274 bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* hdrs */ 3275 3276 {_bfd_dummy_target, coff_small_object_p, /* bfd_check_format */ 3277 bfd_generic_archive_p, _bfd_dummy_target}, 3278 {bfd_false, coff_mkobject, _bfd_generic_mkarchive, /* bfd_set_format */ 3279 bfd_false}, 3280 {bfd_false, coff_write_object_contents, /* bfd_write_contents */ 3281 _bfd_write_archive_contents, bfd_false}, 3282 3283 BFD_JUMP_TABLE_GENERIC (coff_small), 3284 BFD_JUMP_TABLE_COPY (coff), 3285 BFD_JUMP_TABLE_CORE (_bfd_nocore), 3286 BFD_JUMP_TABLE_ARCHIVE (_bfd_archive_coff), 3287 BFD_JUMP_TABLE_SYMBOLS (coff), 3288 BFD_JUMP_TABLE_RELOCS (coff), 3289 BFD_JUMP_TABLE_WRITE (coff), 3290 BFD_JUMP_TABLE_LINK (coff), 3291 BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic), 3292 3293 & shlcoff_small_vec, 3294 3295 (PTR) &bfd_coff_small_swap_table 3296}; 3297 3298const bfd_target shlcoff_small_vec = 3299{ 3300 "coff-shl-small", /* name */ 3301 bfd_target_coff_flavour, 3302 BFD_ENDIAN_LITTLE, /* data byte order is little */ 3303 BFD_ENDIAN_LITTLE, /* header byte order is little endian too*/ 3304 3305 (HAS_RELOC | EXEC_P | /* object flags */ 3306 HAS_LINENO | HAS_DEBUG | 3307 HAS_SYMS | HAS_LOCALS | WP_TEXT | BFD_IS_RELAXABLE), 3308 3309 (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_RELOC), 3310 '_', /* leading symbol underscore */ 3311 '/', /* ar_pad_char */ 3312 15, /* ar_max_namelen */ 3313 bfd_getl64, bfd_getl_signed_64, bfd_putl64, 3314 bfd_getl32, bfd_getl_signed_32, bfd_putl32, 3315 bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* data */ 3316 bfd_getl64, bfd_getl_signed_64, bfd_putl64, 3317 bfd_getl32, bfd_getl_signed_32, bfd_putl32, 3318 bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* hdrs */ 3319 3320 {_bfd_dummy_target, coff_small_object_p, /* bfd_check_format */ 3321 bfd_generic_archive_p, _bfd_dummy_target}, 3322 {bfd_false, coff_mkobject, _bfd_generic_mkarchive, /* bfd_set_format */ 3323 bfd_false}, 3324 {bfd_false, coff_write_object_contents, /* bfd_write_contents */ 3325 _bfd_write_archive_contents, bfd_false}, 3326 3327 BFD_JUMP_TABLE_GENERIC (coff_small), 3328 BFD_JUMP_TABLE_COPY (coff), 3329 BFD_JUMP_TABLE_CORE (_bfd_nocore), 3330 BFD_JUMP_TABLE_ARCHIVE (_bfd_archive_coff), 3331 BFD_JUMP_TABLE_SYMBOLS (coff), 3332 BFD_JUMP_TABLE_RELOCS (coff), 3333 BFD_JUMP_TABLE_WRITE (coff), 3334 BFD_JUMP_TABLE_LINK (coff), 3335 BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic), 3336 3337 & shcoff_small_vec, 3338 3339 (PTR) &bfd_coff_small_swap_table 3340}; 3341#endif 3342