1; Hitachi SH architecture description. -*- Scheme -*- 2; 3; Copyright 2000, 2001 Free Software Foundation, Inc. 4; 5; Contributed by Red Hat Inc; developed under contract from Hitachi 6; Semiconductor (America) Inc. 7; 8; This file is part of the GNU Binutils. 9; 10; This program is free software; you can redistribute it and/or modify 11; it under the terms of the GNU General Public License as published by 12; the Free Software Foundation; either version 2 of the License, or 13; (at your option) any later version. 14; 15; This program is distributed in the hope that it will be useful, 16; but WITHOUT ANY WARRANTY; without even the implied warranty of 17; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18; GNU General Public License for more details. 19; 20; You should have received a copy of the GNU General Public License 21; along with this program; if not, write to the Free Software 22; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. 23 24 25(include "simplify.inc") 26 27(define-arch 28 (name sh) 29 (comment "Hitachi SuperH (SH)") 30 (insn-lsb0? #t) 31 (machs sh2 sh3 sh3e sh4 sh5) 32 (isas compact media) 33) 34 35 36; Instruction sets. 37 38(define-isa 39 (name media) 40 (comment "SHmedia 32-bit instruction set") 41 (base-insn-bitsize 32) 42) 43 44(define-isa 45 (name compact) 46 (comment "SHcompact 16-bit instruction set") 47 (base-insn-bitsize 16) 48) 49 50 51; CPU family. 52 53(define-cpu 54 (name sh64) 55 (comment "SH 64-bit family") 56 (endian either) 57 (word-bitsize 32) 58) 59 60 61(define-mach 62 (name sh2) 63 (comment "SH-2 CPU core") 64 (cpu sh64) 65 (isas compact) 66) 67 68(define-mach 69 (name sh3) 70 (comment "SH-3 CPU core") 71 (cpu sh64) 72 (isas compact) 73) 74 75(define-mach 76 (name sh3e) 77 (comment "SH-3e CPU core") 78 (cpu sh64) 79 (isas compact) 80) 81 82(define-mach 83 (name sh4) 84 (comment "SH-4 CPU core") 85 (cpu sh64) 86 (isas compact) 87) 88 89(define-mach 90 (name sh5) 91 (comment "SH-5 CPU core") 92 (cpu sh64) 93 (isas compact media) 94) 95 96(define-model 97 (name sh5) 98 (comment "SH-5 reference implementation") 99 (mach sh5) 100 (unit u-exec "Execution unit" () 101 1 1 ; issue done 102 () () () ()) 103) 104 105; Hardware elements. 106 107(define-hardware 108 (name h-pc) 109 (comment "Program counter") 110 (attrs PC (ISA compact,media)) 111 (type pc UDI) 112 (get () (raw-reg h-pc)) 113 (set (newval) (sequence () 114 (set (raw-reg h-ism) (and newval 1)) 115 (set (raw-reg h-pc) (and newval (inv UDI 1))))) 116) 117 118(define-pmacro (-build-greg-name n) ((.sym r n) n)) 119 120(define-hardware 121 (name h-gr) 122 (comment "General purpose integer registers") 123 (attrs (ISA media,compact)) 124 (type register DI (64)) 125 (indices keyword "" (.map -build-greg-name (.iota 64))) 126 (get (index) 127 (if DI (eq index 63) 128 (const 0) 129 (raw-reg h-gr index))) 130 (set (index newval) 131 (if (ne index 63) 132 (set (raw-reg h-gr index) newval) 133 (nop))) 134) 135 136(define-hardware 137 (name h-grc) 138 (comment "General purpose integer registers (SHcompact view)") 139 (attrs VIRTUAL (ISA compact)) 140 (type register SI (16)) 141 (indices keyword "" (.map -build-greg-name (.iota 16))) 142 (get (index) 143 (and (raw-reg h-gr index) (zext DI #xFFFFFFFF))) 144 (set (index newval) 145 (set (raw-reg h-gr index) (ext DI newval))) 146) 147 148(define-pmacro (-build-creg-name n) ((.sym cr n) n)) 149 150(define-hardware 151 (name h-cr) 152 (comment "Control registers") 153 (attrs (ISA media)) 154 (type register DI (64)) 155 (indices keyword "" (.map -build-creg-name (.iota 64))) 156 (get (index) 157 (if DI (eq index 0) 158 (zext DI (reg h-sr)) 159 (raw-reg h-cr index))) 160 (set (index newval) 161 (if (eq index 0) 162 (set (reg h-sr) newval) 163 (set (raw-reg h-cr index) newval))) 164) 165 166(define-hardware 167 (name h-sr) 168 (comment "Status register") 169 (attrs (ISA compact,media)) 170 (type register SI) 171) 172 173(define-hardware 174 (name h-fpscr) 175 (comment "Floating point status and control register") 176 (attrs (ISA compact,media)) 177 (type register SI) 178) 179 180(define-hardware 181 (name h-frbit) 182 (comment "Floating point register file bit") 183 (attrs (ISA media,compact) VIRTUAL) 184 (type register BI) 185 (get () (and (srl (reg h-sr) 14) 1)) 186 (set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv (sll 1 14))) (sll SI newvalue 14)))) 187) 188 189(define-hardware 190 (name h-szbit) 191 (comment "Floating point transfer size bit") 192 (attrs (ISA media,compact) VIRTUAL) 193 (type register BI) 194 (get () (and (srl (reg h-sr) 13) 1)) 195 (set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv (sll 1 13))) (sll SI newvalue 13)))) 196) 197 198(define-hardware 199 (name h-prbit) 200 (comment "Floating point precision bit") 201 (attrs (ISA media,compact) VIRTUAL) 202 (type register BI) 203 (get () (and (srl (reg h-sr) 12) 1)) 204 (set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv (sll 1 12))) (sll SI newvalue 12)))) 205) 206 207(define-hardware 208 (name h-sbit) 209 (comment "Multiply-accumulate saturation flag") 210 (attrs (ISA compact) VIRTUAL) 211 (type register BI) 212 (get () (and (srl (reg h-sr) 1) 1)) 213 (set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv 2)) (sll SI newvalue 1)))) 214) 215 216(define-hardware 217 (name h-mbit) 218 (comment "Divide-step M flag") 219 (attrs (ISA compact) VIRTUAL) 220 (type register BI) 221 (get () (and (srl (reg h-sr) 9) 1)) 222 (set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv (sll 1 9))) (sll SI newvalue 9)))) 223) 224 225(define-hardware 226 (name h-qbit) 227 (comment "Divide-step Q flag") 228 (attrs (ISA compact) VIRTUAL) 229 (type register BI) 230 (get () (and (srl (reg h-sr) 8) 1)) 231 (set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv (sll 1 8))) (sll SI newvalue 8)))) 232) 233 234(define-pmacro (-build-freg-name n) ((.sym fr n) n)) 235 236(define-hardware 237 (name h-fr) 238 (comment "Single precision floating point registers") 239 (attrs (ISA media,compact)) 240 (type register SF (64)) 241 (indices keyword "" (.map -build-freg-name (.iota 64))) 242) 243 244 245(define-pmacro (-build-fpair-name n) ((.sym fp n) n)) 246 247(define-hardware 248 (name h-fp) 249 (comment "Single precision floating point register pairs") 250 (attrs (ISA media,compact)) 251 (type register DF (32)) 252 (indices keyword "" (.map -build-fpair-name (.iota 32))) 253) 254 255(define-pmacro (-build-fvec-name n) ((.sym fv n) n)) 256 257(define-hardware 258 (name h-fv) 259 (comment "Single precision floating point vectors") 260 (attrs VIRTUAL (ISA media,compact)) 261 (type register SF (16)) 262 (indices keyword "" (.map -build-fvec-name (.iota 16))) 263 ; Mask with $F to ensure 0 <= index < 15. 264 (get (index) (reg h-fr (mul (and UQI index 15) 4))) 265 (set (index newval) (set (reg h-fr (mul (and UQI index 15) 4)) newval)) 266) 267 268(define-hardware 269 (name h-fmtx) 270 (comment "Single precision floating point matrices") 271 (attrs VIRTUAL (ISA media)) 272 (type register SF (4)) 273 (indices keyword "" ((mtrx0 0) (mtrx1 1) (mtrx2 2) (mtrx3 3))) 274 ; Mask with $3 to ensure 0 <= index < 4. 275 (get (index) (reg h-fr (mul (and UQI index 3) 16))) 276 (set (index newval) (set (reg h-fr (mul (and UQI index 3) 16)) newval)) 277) 278 279(define-pmacro (-build-dreg-name n) ((.sym dr n) n)) 280 281(define-hardware 282 (name h-dr) 283 (comment "Double precision floating point registers") 284 (attrs (ISA media,compact) VIRTUAL) 285 (type register DF (32)) 286 (indices keyword "" (.map -build-dreg-name (.iota 64))) 287 (get (index) 288 (subword DF 289 (or 290 (sll DI (zext DI (subword SI (reg h-fr index) 0)) 32) 291 (zext DI (subword SI (reg h-fr (add index 1)) 0))) 0)) 292 (set (index newval) 293 (sequence () 294 (set (reg h-fr index) 295 (subword SF (subword SI newval 0) 0)) 296 (set (reg h-fr (add index 1)) 297 (subword SF (subword SI newval 1) 0)))) 298) 299 300(define-hardware 301 (name h-tr) 302 (comment "Branch target registers") 303 (attrs (ISA media)) 304 (type register DI (8)) 305 (indices keyword "" ((tr0 0) (tr1 1) (tr2 2) (tr3 3) (tr4 4) (tr5 5) (tr6 6) (tr7 7))) 306) 307 308(define-hardware 309 (name h-endian) 310 (comment "Current endian mode") 311 (attrs (ISA compact,media) VIRTUAL) 312 (type register BI) 313 (get () (c-call BI "sh64_endian")) 314 (set (newval) (error "cannot alter target byte order mid-program")) 315) 316 317(define-hardware 318 (name h-ism) 319 (comment "Current instruction set mode") 320 (attrs (ISA compact,media)) 321 (type register BI) 322 (get () (raw-reg h-ism)) 323 (set (newval) (error "cannot set ism directly")) 324) 325 326 327; Operands. 328 329(dnop endian "Endian mode" ((ISA compact,media)) h-endian f-nil) 330(dnop ism "Instruction set mode" ((ISA compact,media)) h-ism f-nil) 331 332; Universally useful macros. 333 334; A pmacro for use in semantic bodies of unimplemented insns. 335(define-pmacro (unimp mnemonic) (nop)) 336 337; Join 2 ints together in natural bit order. 338(define-pmacro (-join-si s1 s0) 339 (or (sll (zext DI s1) 32) 340 (zext DI s0))) 341 342; Join 4 half-ints together in natural bit order. 343(define-pmacro (-join-hi h3 h2 h1 h0) 344 (or (sll (zext DI h3) 48) 345 (or (sll (zext DI h2) 32) 346 (or (sll (zext DI h1) 16) 347 (zext DI h0))))) 348 349; Join 8 quarter-ints together in natural bit order. 350(define-pmacro (-join-qi b7 b6 b5 b4 b3 b2 b1 b0) 351 (or (sll (zext DI b7) 56) 352 (or (sll (zext DI b6) 48) 353 (or (sll (zext DI b5) 40) 354 (or (sll (zext DI b4) 32) 355 (or (sll (zext DI b3) 24) 356 (or (sll (zext DI b2) 16) 357 (or (sll (zext DI b1) 8) 358 (zext DI b0))))))))) 359 360 361; Include the two instruction set descriptions from their respective 362; source files. 363 364(if (keep-isa? (compact)) 365 (include "sh64-compact.cpu")) 366 367(if (keep-isa? (media)) 368 (include "sh64-media.cpu")) 369