1@section Relocations 2BFD maintains relocations in much the same way it maintains 3symbols: they are left alone until required, then read in 4en-masse and translated into an internal form. A common 5routine @code{bfd_perform_relocation} acts upon the 6canonical form to do the fixup. 7 8Relocations are maintained on a per section basis, 9while symbols are maintained on a per BFD basis. 10 11All that a back end has to do to fit the BFD interface is to create 12a @code{struct reloc_cache_entry} for each relocation 13in a particular section, and fill in the right bits of the structures. 14 15@menu 16* typedef arelent:: 17* howto manager:: 18@end menu 19 20 21@node typedef arelent, howto manager, Relocations, Relocations 22@subsection typedef arelent 23This is the structure of a relocation entry: 24 25 26@example 27 28typedef enum bfd_reloc_status 29@{ 30 /* No errors detected. */ 31 bfd_reloc_ok, 32 33 /* The relocation was performed, but there was an overflow. */ 34 bfd_reloc_overflow, 35 36 /* The address to relocate was not within the section supplied. */ 37 bfd_reloc_outofrange, 38 39 /* Used by special functions. */ 40 bfd_reloc_continue, 41 42 /* Unsupported relocation size requested. */ 43 bfd_reloc_notsupported, 44 45 /* Unused. */ 46 bfd_reloc_other, 47 48 /* The symbol to relocate against was undefined. */ 49 bfd_reloc_undefined, 50 51 /* The relocation was performed, but may not be ok - presently 52 generated only when linking i960 coff files with i960 b.out 53 symbols. If this type is returned, the error_message argument 54 to bfd_perform_relocation will be set. */ 55 bfd_reloc_dangerous 56 @} 57 bfd_reloc_status_type; 58 59 60typedef struct reloc_cache_entry 61@{ 62 /* A pointer into the canonical table of pointers. */ 63 struct bfd_symbol **sym_ptr_ptr; 64 65 /* offset in section. */ 66 bfd_size_type address; 67 68 /* addend for relocation value. */ 69 bfd_vma addend; 70 71 /* Pointer to how to perform the required relocation. */ 72 reloc_howto_type *howto; 73 74@} 75arelent; 76 77@end example 78@strong{Description}@* 79Here is a description of each of the fields within an @code{arelent}: 80 81@itemize @bullet 82 83@item 84@code{sym_ptr_ptr} 85@end itemize 86The symbol table pointer points to a pointer to the symbol 87associated with the relocation request. It is the pointer 88into the table returned by the back end's 89@code{canonicalize_symtab} action. @xref{Symbols}. The symbol is 90referenced through a pointer to a pointer so that tools like 91the linker can fix up all the symbols of the same name by 92modifying only one pointer. The relocation routine looks in 93the symbol and uses the base of the section the symbol is 94attached to and the value of the symbol as the initial 95relocation offset. If the symbol pointer is zero, then the 96section provided is looked up. 97 98@itemize @bullet 99 100@item 101@code{address} 102@end itemize 103The @code{address} field gives the offset in bytes from the base of 104the section data which owns the relocation record to the first 105byte of relocatable information. The actual data relocated 106will be relative to this point; for example, a relocation 107type which modifies the bottom two bytes of a four byte word 108would not touch the first byte pointed to in a big endian 109world. 110 111@itemize @bullet 112 113@item 114@code{addend} 115@end itemize 116The @code{addend} is a value provided by the back end to be added (!) 117to the relocation offset. Its interpretation is dependent upon 118the howto. For example, on the 68k the code: 119 120@example 121 char foo[]; 122 main() 123 @{ 124 return foo[0x12345678]; 125 @} 126@end example 127 128Could be compiled into: 129 130@example 131 linkw fp,#-4 132 moveb @@#12345678,d0 133 extbl d0 134 unlk fp 135 rts 136@end example 137 138This could create a reloc pointing to @code{foo}, but leave the 139offset in the data, something like: 140 141@example 142RELOCATION RECORDS FOR [.text]: 143offset type value 14400000006 32 _foo 145 14600000000 4e56 fffc ; linkw fp,#-4 14700000004 1039 1234 5678 ; moveb @@#12345678,d0 1480000000a 49c0 ; extbl d0 1490000000c 4e5e ; unlk fp 1500000000e 4e75 ; rts 151@end example 152 153Using coff and an 88k, some instructions don't have enough 154space in them to represent the full address range, and 155pointers have to be loaded in two parts. So you'd get something like: 156 157@example 158 or.u r13,r0,hi16(_foo+0x12345678) 159 ld.b r2,r13,lo16(_foo+0x12345678) 160 jmp r1 161@end example 162 163This should create two relocs, both pointing to @code{_foo}, and with 1640x12340000 in their addend field. The data would consist of: 165 166@example 167RELOCATION RECORDS FOR [.text]: 168offset type value 16900000002 HVRT16 _foo+0x12340000 17000000006 LVRT16 _foo+0x12340000 171 17200000000 5da05678 ; or.u r13,r0,0x5678 17300000004 1c4d5678 ; ld.b r2,r13,0x5678 17400000008 f400c001 ; jmp r1 175@end example 176 177The relocation routine digs out the value from the data, adds 178it to the addend to get the original offset, and then adds the 179value of @code{_foo}. Note that all 32 bits have to be kept around 180somewhere, to cope with carry from bit 15 to bit 16. 181 182One further example is the sparc and the a.out format. The 183sparc has a similar problem to the 88k, in that some 184instructions don't have room for an entire offset, but on the 185sparc the parts are created in odd sized lumps. The designers of 186the a.out format chose to not use the data within the section 187for storing part of the offset; all the offset is kept within 188the reloc. Anything in the data should be ignored. 189 190@example 191 save %sp,-112,%sp 192 sethi %hi(_foo+0x12345678),%g2 193 ldsb [%g2+%lo(_foo+0x12345678)],%i0 194 ret 195 restore 196@end example 197 198Both relocs contain a pointer to @code{foo}, and the offsets 199contain junk. 200 201@example 202RELOCATION RECORDS FOR [.text]: 203offset type value 20400000004 HI22 _foo+0x12345678 20500000008 LO10 _foo+0x12345678 206 20700000000 9de3bf90 ; save %sp,-112,%sp 20800000004 05000000 ; sethi %hi(_foo+0),%g2 20900000008 f048a000 ; ldsb [%g2+%lo(_foo+0)],%i0 2100000000c 81c7e008 ; ret 21100000010 81e80000 ; restore 212@end example 213 214@itemize @bullet 215 216@item 217@code{howto} 218@end itemize 219The @code{howto} field can be imagined as a 220relocation instruction. It is a pointer to a structure which 221contains information on what to do with all of the other 222information in the reloc record and data section. A back end 223would normally have a relocation instruction set and turn 224relocations into pointers to the correct structure on input - 225but it would be possible to create each howto field on demand. 226 227@subsubsection @code{enum complain_overflow} 228Indicates what sort of overflow checking should be done when 229performing a relocation. 230 231 232@example 233 234enum complain_overflow 235@{ 236 /* Do not complain on overflow. */ 237 complain_overflow_dont, 238 239 /* Complain if the value overflows when considered as a signed 240 number one bit larger than the field. ie. A bitfield of N bits 241 is allowed to represent -2**n to 2**n-1. */ 242 complain_overflow_bitfield, 243 244 /* Complain if the value overflows when considered as a signed 245 number. */ 246 complain_overflow_signed, 247 248 /* Complain if the value overflows when considered as an 249 unsigned number. */ 250 complain_overflow_unsigned 251@}; 252@end example 253@subsubsection @code{reloc_howto_type} 254The @code{reloc_howto_type} is a structure which contains all the 255information that libbfd needs to know to tie up a back end's data. 256 257 258@example 259struct bfd_symbol; /* Forward declaration. */ 260 261struct reloc_howto_struct 262@{ 263 /* The type field has mainly a documentary use - the back end can 264 do what it wants with it, though normally the back end's 265 external idea of what a reloc number is stored 266 in this field. For example, a PC relative word relocation 267 in a coff environment has the type 023 - because that's 268 what the outside world calls a R_PCRWORD reloc. */ 269 unsigned int type; 270 271 /* The value the final relocation is shifted right by. This drops 272 unwanted data from the relocation. */ 273 unsigned int rightshift; 274 275 /* The size of the item to be relocated. This is *not* a 276 power-of-two measure. To get the number of bytes operated 277 on by a type of relocation, use bfd_get_reloc_size. */ 278 int size; 279 280 /* The number of bits in the item to be relocated. This is used 281 when doing overflow checking. */ 282 unsigned int bitsize; 283 284 /* Notes that the relocation is relative to the location in the 285 data section of the addend. The relocation function will 286 subtract from the relocation value the address of the location 287 being relocated. */ 288 bfd_boolean pc_relative; 289 290 /* The bit position of the reloc value in the destination. 291 The relocated value is left shifted by this amount. */ 292 unsigned int bitpos; 293 294 /* What type of overflow error should be checked for when 295 relocating. */ 296 enum complain_overflow complain_on_overflow; 297 298 /* If this field is non null, then the supplied function is 299 called rather than the normal function. This allows really 300 strange relocation methods to be accommodated (e.g., i960 callj 301 instructions). */ 302 bfd_reloc_status_type (*special_function) 303 (bfd *, arelent *, struct bfd_symbol *, void *, asection *, 304 bfd *, char **); 305 306 /* The textual name of the relocation type. */ 307 char *name; 308 309 /* Some formats record a relocation addend in the section contents 310 rather than with the relocation. For ELF formats this is the 311 distinction between USE_REL and USE_RELA (though the code checks 312 for USE_REL == 1/0). The value of this field is TRUE if the 313 addend is recorded with the section contents; when performing a 314 partial link (ld -r) the section contents (the data) will be 315 modified. The value of this field is FALSE if addends are 316 recorded with the relocation (in arelent.addend); when performing 317 a partial link the relocation will be modified. 318 All relocations for all ELF USE_RELA targets should set this field 319 to FALSE (values of TRUE should be looked on with suspicion). 320 However, the converse is not true: not all relocations of all ELF 321 USE_REL targets set this field to TRUE. Why this is so is peculiar 322 to each particular target. For relocs that aren't used in partial 323 links (e.g. GOT stuff) it doesn't matter what this is set to. */ 324 bfd_boolean partial_inplace; 325 326 /* src_mask selects the part of the instruction (or data) to be used 327 in the relocation sum. If the target relocations don't have an 328 addend in the reloc, eg. ELF USE_REL, src_mask will normally equal 329 dst_mask to extract the addend from the section contents. If 330 relocations do have an addend in the reloc, eg. ELF USE_RELA, this 331 field should be zero. Non-zero values for ELF USE_RELA targets are 332 bogus as in those cases the value in the dst_mask part of the 333 section contents should be treated as garbage. */ 334 bfd_vma src_mask; 335 336 /* dst_mask selects which parts of the instruction (or data) are 337 replaced with a relocated value. */ 338 bfd_vma dst_mask; 339 340 /* When some formats create PC relative instructions, they leave 341 the value of the pc of the place being relocated in the offset 342 slot of the instruction, so that a PC relative relocation can 343 be made just by adding in an ordinary offset (e.g., sun3 a.out). 344 Some formats leave the displacement part of an instruction 345 empty (e.g., m88k bcs); this flag signals the fact. */ 346 bfd_boolean pcrel_offset; 347@}; 348 349@end example 350@findex The HOWTO Macro 351@subsubsection @code{The HOWTO Macro} 352@strong{Description}@* 353The HOWTO define is horrible and will go away. 354@example 355#define HOWTO(C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC) \ 356 @{ (unsigned) C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC @} 357@end example 358 359@strong{Description}@* 360And will be replaced with the totally magic way. But for the 361moment, we are compatible, so do it this way. 362@example 363#define NEWHOWTO(FUNCTION, NAME, SIZE, REL, IN) \ 364 HOWTO (0, 0, SIZE, 0, REL, 0, complain_overflow_dont, FUNCTION, \ 365 NAME, FALSE, 0, 0, IN) 366 367@end example 368 369@strong{Description}@* 370This is used to fill in an empty howto entry in an array. 371@example 372#define EMPTY_HOWTO(C) \ 373 HOWTO ((C), 0, 0, 0, FALSE, 0, complain_overflow_dont, NULL, \ 374 NULL, FALSE, 0, 0, FALSE) 375 376@end example 377 378@strong{Description}@* 379Helper routine to turn a symbol into a relocation value. 380@example 381#define HOWTO_PREPARE(relocation, symbol) \ 382 @{ \ 383 if (symbol != NULL) \ 384 @{ \ 385 if (bfd_is_com_section (symbol->section)) \ 386 @{ \ 387 relocation = 0; \ 388 @} \ 389 else \ 390 @{ \ 391 relocation = symbol->value; \ 392 @} \ 393 @} \ 394 @} 395 396@end example 397 398@findex bfd_get_reloc_size 399@subsubsection @code{bfd_get_reloc_size} 400@strong{Synopsis} 401@example 402unsigned int bfd_get_reloc_size (reloc_howto_type *); 403@end example 404@strong{Description}@* 405For a reloc_howto_type that operates on a fixed number of bytes, 406this returns the number of bytes operated on. 407 408@findex arelent_chain 409@subsubsection @code{arelent_chain} 410@strong{Description}@* 411How relocs are tied together in an @code{asection}: 412@example 413typedef struct relent_chain 414@{ 415 arelent relent; 416 struct relent_chain *next; 417@} 418arelent_chain; 419 420@end example 421 422@findex bfd_check_overflow 423@subsubsection @code{bfd_check_overflow} 424@strong{Synopsis} 425@example 426bfd_reloc_status_type bfd_check_overflow 427 (enum complain_overflow how, 428 unsigned int bitsize, 429 unsigned int rightshift, 430 unsigned int addrsize, 431 bfd_vma relocation); 432@end example 433@strong{Description}@* 434Perform overflow checking on @var{relocation} which has 435@var{bitsize} significant bits and will be shifted right by 436@var{rightshift} bits, on a machine with addresses containing 437@var{addrsize} significant bits. The result is either of 438@code{bfd_reloc_ok} or @code{bfd_reloc_overflow}. 439 440@findex bfd_perform_relocation 441@subsubsection @code{bfd_perform_relocation} 442@strong{Synopsis} 443@example 444bfd_reloc_status_type bfd_perform_relocation 445 (bfd *abfd, 446 arelent *reloc_entry, 447 void *data, 448 asection *input_section, 449 bfd *output_bfd, 450 char **error_message); 451@end example 452@strong{Description}@* 453If @var{output_bfd} is supplied to this function, the 454generated image will be relocatable; the relocations are 455copied to the output file after they have been changed to 456reflect the new state of the world. There are two ways of 457reflecting the results of partial linkage in an output file: 458by modifying the output data in place, and by modifying the 459relocation record. Some native formats (e.g., basic a.out and 460basic coff) have no way of specifying an addend in the 461relocation type, so the addend has to go in the output data. 462This is no big deal since in these formats the output data 463slot will always be big enough for the addend. Complex reloc 464types with addends were invented to solve just this problem. 465The @var{error_message} argument is set to an error message if 466this return @code{bfd_reloc_dangerous}. 467 468@findex bfd_install_relocation 469@subsubsection @code{bfd_install_relocation} 470@strong{Synopsis} 471@example 472bfd_reloc_status_type bfd_install_relocation 473 (bfd *abfd, 474 arelent *reloc_entry, 475 void *data, bfd_vma data_start, 476 asection *input_section, 477 char **error_message); 478@end example 479@strong{Description}@* 480This looks remarkably like @code{bfd_perform_relocation}, except it 481does not expect that the section contents have been filled in. 482I.e., it's suitable for use when creating, rather than applying 483a relocation. 484 485For now, this function should be considered reserved for the 486assembler. 487 488 489@node howto manager, , typedef arelent, Relocations 490@subsection The howto manager 491When an application wants to create a relocation, but doesn't 492know what the target machine might call it, it can find out by 493using this bit of code. 494 495@findex bfd_reloc_code_type 496@subsubsection @code{bfd_reloc_code_type} 497@strong{Description}@* 498The insides of a reloc code. The idea is that, eventually, there 499will be one enumerator for every type of relocation we ever do. 500Pass one of these values to @code{bfd_reloc_type_lookup}, and it'll 501return a howto pointer. 502 503This does mean that the application must determine the correct 504enumerator value; you can't get a howto pointer from a random set 505of attributes. 506 507Here are the possible values for @code{enum bfd_reloc_code_real}: 508 509@deffn {} BFD_RELOC_64 510@deffnx {} BFD_RELOC_32 511@deffnx {} BFD_RELOC_26 512@deffnx {} BFD_RELOC_24 513@deffnx {} BFD_RELOC_16 514@deffnx {} BFD_RELOC_14 515@deffnx {} BFD_RELOC_8 516Basic absolute relocations of N bits. 517@end deffn 518@deffn {} BFD_RELOC_64_PCREL 519@deffnx {} BFD_RELOC_32_PCREL 520@deffnx {} BFD_RELOC_24_PCREL 521@deffnx {} BFD_RELOC_16_PCREL 522@deffnx {} BFD_RELOC_12_PCREL 523@deffnx {} BFD_RELOC_8_PCREL 524PC-relative relocations. Sometimes these are relative to the address 525of the relocation itself; sometimes they are relative to the start of 526the section containing the relocation. It depends on the specific target. 527 528The 24-bit relocation is used in some Intel 960 configurations. 529@end deffn 530@deffn {} BFD_RELOC_32_SECREL 531Section relative relocations. Some targets need this for DWARF2. 532@end deffn 533@deffn {} BFD_RELOC_32_GOT_PCREL 534@deffnx {} BFD_RELOC_16_GOT_PCREL 535@deffnx {} BFD_RELOC_8_GOT_PCREL 536@deffnx {} BFD_RELOC_32_GOTOFF 537@deffnx {} BFD_RELOC_16_GOTOFF 538@deffnx {} BFD_RELOC_LO16_GOTOFF 539@deffnx {} BFD_RELOC_HI16_GOTOFF 540@deffnx {} BFD_RELOC_HI16_S_GOTOFF 541@deffnx {} BFD_RELOC_8_GOTOFF 542@deffnx {} BFD_RELOC_64_PLT_PCREL 543@deffnx {} BFD_RELOC_32_PLT_PCREL 544@deffnx {} BFD_RELOC_24_PLT_PCREL 545@deffnx {} BFD_RELOC_16_PLT_PCREL 546@deffnx {} BFD_RELOC_8_PLT_PCREL 547@deffnx {} BFD_RELOC_64_PLTOFF 548@deffnx {} BFD_RELOC_32_PLTOFF 549@deffnx {} BFD_RELOC_16_PLTOFF 550@deffnx {} BFD_RELOC_LO16_PLTOFF 551@deffnx {} BFD_RELOC_HI16_PLTOFF 552@deffnx {} BFD_RELOC_HI16_S_PLTOFF 553@deffnx {} BFD_RELOC_8_PLTOFF 554For ELF. 555@end deffn 556@deffn {} BFD_RELOC_68K_GLOB_DAT 557@deffnx {} BFD_RELOC_68K_JMP_SLOT 558@deffnx {} BFD_RELOC_68K_RELATIVE 559Relocations used by 68K ELF. 560@end deffn 561@deffn {} BFD_RELOC_32_BASEREL 562@deffnx {} BFD_RELOC_16_BASEREL 563@deffnx {} BFD_RELOC_LO16_BASEREL 564@deffnx {} BFD_RELOC_HI16_BASEREL 565@deffnx {} BFD_RELOC_HI16_S_BASEREL 566@deffnx {} BFD_RELOC_8_BASEREL 567@deffnx {} BFD_RELOC_RVA 568Linkage-table relative. 569@end deffn 570@deffn {} BFD_RELOC_8_FFnn 571Absolute 8-bit relocation, but used to form an address like 0xFFnn. 572@end deffn 573@deffn {} BFD_RELOC_32_PCREL_S2 574@deffnx {} BFD_RELOC_16_PCREL_S2 575@deffnx {} BFD_RELOC_23_PCREL_S2 576These PC-relative relocations are stored as word displacements -- 577i.e., byte displacements shifted right two bits. The 30-bit word 578displacement (<<32_PCREL_S2>> -- 32 bits, shifted 2) is used on the 579SPARC. (SPARC tools generally refer to this as <<WDISP30>>.) The 580signed 16-bit displacement is used on the MIPS, and the 23-bit 581displacement is used on the Alpha. 582@end deffn 583@deffn {} BFD_RELOC_HI22 584@deffnx {} BFD_RELOC_LO10 585High 22 bits and low 10 bits of 32-bit value, placed into lower bits of 586the target word. These are used on the SPARC. 587@end deffn 588@deffn {} BFD_RELOC_GPREL16 589@deffnx {} BFD_RELOC_GPREL32 590For systems that allocate a Global Pointer register, these are 591displacements off that register. These relocation types are 592handled specially, because the value the register will have is 593decided relatively late. 594@end deffn 595@deffn {} BFD_RELOC_I960_CALLJ 596Reloc types used for i960/b.out. 597@end deffn 598@deffn {} BFD_RELOC_NONE 599@deffnx {} BFD_RELOC_SPARC_WDISP22 600@deffnx {} BFD_RELOC_SPARC22 601@deffnx {} BFD_RELOC_SPARC13 602@deffnx {} BFD_RELOC_SPARC_GOT10 603@deffnx {} BFD_RELOC_SPARC_GOT13 604@deffnx {} BFD_RELOC_SPARC_GOT22 605@deffnx {} BFD_RELOC_SPARC_PC10 606@deffnx {} BFD_RELOC_SPARC_PC22 607@deffnx {} BFD_RELOC_SPARC_WPLT30 608@deffnx {} BFD_RELOC_SPARC_COPY 609@deffnx {} BFD_RELOC_SPARC_GLOB_DAT 610@deffnx {} BFD_RELOC_SPARC_JMP_SLOT 611@deffnx {} BFD_RELOC_SPARC_RELATIVE 612@deffnx {} BFD_RELOC_SPARC_UA16 613@deffnx {} BFD_RELOC_SPARC_UA32 614@deffnx {} BFD_RELOC_SPARC_UA64 615SPARC ELF relocations. There is probably some overlap with other 616relocation types already defined. 617@end deffn 618@deffn {} BFD_RELOC_SPARC_BASE13 619@deffnx {} BFD_RELOC_SPARC_BASE22 620I think these are specific to SPARC a.out (e.g., Sun 4). 621@end deffn 622@deffn {} BFD_RELOC_SPARC_64 623@deffnx {} BFD_RELOC_SPARC_10 624@deffnx {} BFD_RELOC_SPARC_11 625@deffnx {} BFD_RELOC_SPARC_OLO10 626@deffnx {} BFD_RELOC_SPARC_HH22 627@deffnx {} BFD_RELOC_SPARC_HM10 628@deffnx {} BFD_RELOC_SPARC_LM22 629@deffnx {} BFD_RELOC_SPARC_PC_HH22 630@deffnx {} BFD_RELOC_SPARC_PC_HM10 631@deffnx {} BFD_RELOC_SPARC_PC_LM22 632@deffnx {} BFD_RELOC_SPARC_WDISP16 633@deffnx {} BFD_RELOC_SPARC_WDISP19 634@deffnx {} BFD_RELOC_SPARC_7 635@deffnx {} BFD_RELOC_SPARC_6 636@deffnx {} BFD_RELOC_SPARC_5 637@deffnx {} BFD_RELOC_SPARC_DISP64 638@deffnx {} BFD_RELOC_SPARC_PLT32 639@deffnx {} BFD_RELOC_SPARC_PLT64 640@deffnx {} BFD_RELOC_SPARC_HIX22 641@deffnx {} BFD_RELOC_SPARC_LOX10 642@deffnx {} BFD_RELOC_SPARC_H44 643@deffnx {} BFD_RELOC_SPARC_M44 644@deffnx {} BFD_RELOC_SPARC_L44 645@deffnx {} BFD_RELOC_SPARC_REGISTER 646SPARC64 relocations 647@end deffn 648@deffn {} BFD_RELOC_SPARC_REV32 649SPARC little endian relocation 650@end deffn 651@deffn {} BFD_RELOC_SPARC_TLS_GD_HI22 652@deffnx {} BFD_RELOC_SPARC_TLS_GD_LO10 653@deffnx {} BFD_RELOC_SPARC_TLS_GD_ADD 654@deffnx {} BFD_RELOC_SPARC_TLS_GD_CALL 655@deffnx {} BFD_RELOC_SPARC_TLS_LDM_HI22 656@deffnx {} BFD_RELOC_SPARC_TLS_LDM_LO10 657@deffnx {} BFD_RELOC_SPARC_TLS_LDM_ADD 658@deffnx {} BFD_RELOC_SPARC_TLS_LDM_CALL 659@deffnx {} BFD_RELOC_SPARC_TLS_LDO_HIX22 660@deffnx {} BFD_RELOC_SPARC_TLS_LDO_LOX10 661@deffnx {} BFD_RELOC_SPARC_TLS_LDO_ADD 662@deffnx {} BFD_RELOC_SPARC_TLS_IE_HI22 663@deffnx {} BFD_RELOC_SPARC_TLS_IE_LO10 664@deffnx {} BFD_RELOC_SPARC_TLS_IE_LD 665@deffnx {} BFD_RELOC_SPARC_TLS_IE_LDX 666@deffnx {} BFD_RELOC_SPARC_TLS_IE_ADD 667@deffnx {} BFD_RELOC_SPARC_TLS_LE_HIX22 668@deffnx {} BFD_RELOC_SPARC_TLS_LE_LOX10 669@deffnx {} BFD_RELOC_SPARC_TLS_DTPMOD32 670@deffnx {} BFD_RELOC_SPARC_TLS_DTPMOD64 671@deffnx {} BFD_RELOC_SPARC_TLS_DTPOFF32 672@deffnx {} BFD_RELOC_SPARC_TLS_DTPOFF64 673@deffnx {} BFD_RELOC_SPARC_TLS_TPOFF32 674@deffnx {} BFD_RELOC_SPARC_TLS_TPOFF64 675SPARC TLS relocations 676@end deffn 677@deffn {} BFD_RELOC_ALPHA_GPDISP_HI16 678Alpha ECOFF and ELF relocations. Some of these treat the symbol or 679"addend" in some special way. 680For GPDISP_HI16 ("gpdisp") relocations, the symbol is ignored when 681writing; when reading, it will be the absolute section symbol. The 682addend is the displacement in bytes of the "lda" instruction from 683the "ldah" instruction (which is at the address of this reloc). 684@end deffn 685@deffn {} BFD_RELOC_ALPHA_GPDISP_LO16 686For GPDISP_LO16 ("ignore") relocations, the symbol is handled as 687with GPDISP_HI16 relocs. The addend is ignored when writing the 688relocations out, and is filled in with the file's GP value on 689reading, for convenience. 690@end deffn 691@deffn {} BFD_RELOC_ALPHA_GPDISP 692The ELF GPDISP relocation is exactly the same as the GPDISP_HI16 693relocation except that there is no accompanying GPDISP_LO16 694relocation. 695@end deffn 696@deffn {} BFD_RELOC_ALPHA_LITERAL 697@deffnx {} BFD_RELOC_ALPHA_ELF_LITERAL 698@deffnx {} BFD_RELOC_ALPHA_LITUSE 699The Alpha LITERAL/LITUSE relocs are produced by a symbol reference; 700the assembler turns it into a LDQ instruction to load the address of 701the symbol, and then fills in a register in the real instruction. 702 703The LITERAL reloc, at the LDQ instruction, refers to the .lita 704section symbol. The addend is ignored when writing, but is filled 705in with the file's GP value on reading, for convenience, as with the 706GPDISP_LO16 reloc. 707 708The ELF_LITERAL reloc is somewhere between 16_GOTOFF and GPDISP_LO16. 709It should refer to the symbol to be referenced, as with 16_GOTOFF, 710but it generates output not based on the position within the .got 711section, but relative to the GP value chosen for the file during the 712final link stage. 713 714The LITUSE reloc, on the instruction using the loaded address, gives 715information to the linker that it might be able to use to optimize 716away some literal section references. The symbol is ignored (read 717as the absolute section symbol), and the "addend" indicates the type 718of instruction using the register: 7191 - "memory" fmt insn 7202 - byte-manipulation (byte offset reg) 7213 - jsr (target of branch) 722@end deffn 723@deffn {} BFD_RELOC_ALPHA_HINT 724The HINT relocation indicates a value that should be filled into the 725"hint" field of a jmp/jsr/ret instruction, for possible branch- 726prediction logic which may be provided on some processors. 727@end deffn 728@deffn {} BFD_RELOC_ALPHA_LINKAGE 729The LINKAGE relocation outputs a linkage pair in the object file, 730which is filled by the linker. 731@end deffn 732@deffn {} BFD_RELOC_ALPHA_CODEADDR 733The CODEADDR relocation outputs a STO_CA in the object file, 734which is filled by the linker. 735@end deffn 736@deffn {} BFD_RELOC_ALPHA_GPREL_HI16 737@deffnx {} BFD_RELOC_ALPHA_GPREL_LO16 738The GPREL_HI/LO relocations together form a 32-bit offset from the 739GP register. 740@end deffn 741@deffn {} BFD_RELOC_ALPHA_BRSGP 742Like BFD_RELOC_23_PCREL_S2, except that the source and target must 743share a common GP, and the target address is adjusted for 744STO_ALPHA_STD_GPLOAD. 745@end deffn 746@deffn {} BFD_RELOC_ALPHA_TLSGD 747@deffnx {} BFD_RELOC_ALPHA_TLSLDM 748@deffnx {} BFD_RELOC_ALPHA_DTPMOD64 749@deffnx {} BFD_RELOC_ALPHA_GOTDTPREL16 750@deffnx {} BFD_RELOC_ALPHA_DTPREL64 751@deffnx {} BFD_RELOC_ALPHA_DTPREL_HI16 752@deffnx {} BFD_RELOC_ALPHA_DTPREL_LO16 753@deffnx {} BFD_RELOC_ALPHA_DTPREL16 754@deffnx {} BFD_RELOC_ALPHA_GOTTPREL16 755@deffnx {} BFD_RELOC_ALPHA_TPREL64 756@deffnx {} BFD_RELOC_ALPHA_TPREL_HI16 757@deffnx {} BFD_RELOC_ALPHA_TPREL_LO16 758@deffnx {} BFD_RELOC_ALPHA_TPREL16 759Alpha thread-local storage relocations. 760@end deffn 761@deffn {} BFD_RELOC_MIPS_JMP 762Bits 27..2 of the relocation address shifted right 2 bits; 763simple reloc otherwise. 764@end deffn 765@deffn {} BFD_RELOC_MIPS16_JMP 766The MIPS16 jump instruction. 767@end deffn 768@deffn {} BFD_RELOC_MIPS16_GPREL 769MIPS16 GP relative reloc. 770@end deffn 771@deffn {} BFD_RELOC_HI16 772High 16 bits of 32-bit value; simple reloc. 773@end deffn 774@deffn {} BFD_RELOC_HI16_S 775High 16 bits of 32-bit value but the low 16 bits will be sign 776extended and added to form the final result. If the low 16 777bits form a negative number, we need to add one to the high value 778to compensate for the borrow when the low bits are added. 779@end deffn 780@deffn {} BFD_RELOC_LO16 781Low 16 bits. 782@end deffn 783@deffn {} BFD_RELOC_HI16_PCREL 784High 16 bits of 32-bit pc-relative value 785@end deffn 786@deffn {} BFD_RELOC_HI16_S_PCREL 787High 16 bits of 32-bit pc-relative value, adjusted 788@end deffn 789@deffn {} BFD_RELOC_LO16_PCREL 790Low 16 bits of pc-relative value 791@end deffn 792@deffn {} BFD_RELOC_MIPS16_HI16 793MIPS16 high 16 bits of 32-bit value. 794@end deffn 795@deffn {} BFD_RELOC_MIPS16_HI16_S 796MIPS16 high 16 bits of 32-bit value but the low 16 bits will be sign 797extended and added to form the final result. If the low 16 798bits form a negative number, we need to add one to the high value 799to compensate for the borrow when the low bits are added. 800@end deffn 801@deffn {} BFD_RELOC_MIPS16_LO16 802MIPS16 low 16 bits. 803@end deffn 804@deffn {} BFD_RELOC_MIPS_LITERAL 805Relocation against a MIPS literal section. 806@end deffn 807@deffn {} BFD_RELOC_MIPS_GOT16 808@deffnx {} BFD_RELOC_MIPS_CALL16 809@deffnx {} BFD_RELOC_MIPS_GOT_HI16 810@deffnx {} BFD_RELOC_MIPS_GOT_LO16 811@deffnx {} BFD_RELOC_MIPS_CALL_HI16 812@deffnx {} BFD_RELOC_MIPS_CALL_LO16 813@deffnx {} BFD_RELOC_MIPS_SUB 814@deffnx {} BFD_RELOC_MIPS_GOT_PAGE 815@deffnx {} BFD_RELOC_MIPS_GOT_OFST 816@deffnx {} BFD_RELOC_MIPS_GOT_DISP 817@deffnx {} BFD_RELOC_MIPS_SHIFT5 818@deffnx {} BFD_RELOC_MIPS_SHIFT6 819@deffnx {} BFD_RELOC_MIPS_INSERT_A 820@deffnx {} BFD_RELOC_MIPS_INSERT_B 821@deffnx {} BFD_RELOC_MIPS_DELETE 822@deffnx {} BFD_RELOC_MIPS_HIGHEST 823@deffnx {} BFD_RELOC_MIPS_HIGHER 824@deffnx {} BFD_RELOC_MIPS_SCN_DISP 825@deffnx {} BFD_RELOC_MIPS_REL16 826@deffnx {} BFD_RELOC_MIPS_RELGOT 827@deffnx {} BFD_RELOC_MIPS_JALR 828@deffnx {} BFD_RELOC_MIPS_TLS_DTPMOD32 829@deffnx {} BFD_RELOC_MIPS_TLS_DTPREL32 830@deffnx {} BFD_RELOC_MIPS_TLS_DTPMOD64 831@deffnx {} BFD_RELOC_MIPS_TLS_DTPREL64 832@deffnx {} BFD_RELOC_MIPS_TLS_GD 833@deffnx {} BFD_RELOC_MIPS_TLS_LDM 834@deffnx {} BFD_RELOC_MIPS_TLS_DTPREL_HI16 835@deffnx {} BFD_RELOC_MIPS_TLS_DTPREL_LO16 836@deffnx {} BFD_RELOC_MIPS_TLS_GOTTPREL 837@deffnx {} BFD_RELOC_MIPS_TLS_TPREL32 838@deffnx {} BFD_RELOC_MIPS_TLS_TPREL64 839@deffnx {} BFD_RELOC_MIPS_TLS_TPREL_HI16 840@deffnx {} BFD_RELOC_MIPS_TLS_TPREL_LO16 841MIPS ELF relocations. 842@end deffn 843@deffn {} BFD_RELOC_MIPS_COPY 844@deffnx {} BFD_RELOC_MIPS_JUMP_SLOT 845MIPS ELF relocations (VxWorks extensions). 846@end deffn 847@deffn {} BFD_RELOC_FRV_LABEL16 848@deffnx {} BFD_RELOC_FRV_LABEL24 849@deffnx {} BFD_RELOC_FRV_LO16 850@deffnx {} BFD_RELOC_FRV_HI16 851@deffnx {} BFD_RELOC_FRV_GPREL12 852@deffnx {} BFD_RELOC_FRV_GPRELU12 853@deffnx {} BFD_RELOC_FRV_GPREL32 854@deffnx {} BFD_RELOC_FRV_GPRELHI 855@deffnx {} BFD_RELOC_FRV_GPRELLO 856@deffnx {} BFD_RELOC_FRV_GOT12 857@deffnx {} BFD_RELOC_FRV_GOTHI 858@deffnx {} BFD_RELOC_FRV_GOTLO 859@deffnx {} BFD_RELOC_FRV_FUNCDESC 860@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOT12 861@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTHI 862@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTLO 863@deffnx {} BFD_RELOC_FRV_FUNCDESC_VALUE 864@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTOFF12 865@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTOFFHI 866@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTOFFLO 867@deffnx {} BFD_RELOC_FRV_GOTOFF12 868@deffnx {} BFD_RELOC_FRV_GOTOFFHI 869@deffnx {} BFD_RELOC_FRV_GOTOFFLO 870@deffnx {} BFD_RELOC_FRV_GETTLSOFF 871@deffnx {} BFD_RELOC_FRV_TLSDESC_VALUE 872@deffnx {} BFD_RELOC_FRV_GOTTLSDESC12 873@deffnx {} BFD_RELOC_FRV_GOTTLSDESCHI 874@deffnx {} BFD_RELOC_FRV_GOTTLSDESCLO 875@deffnx {} BFD_RELOC_FRV_TLSMOFF12 876@deffnx {} BFD_RELOC_FRV_TLSMOFFHI 877@deffnx {} BFD_RELOC_FRV_TLSMOFFLO 878@deffnx {} BFD_RELOC_FRV_GOTTLSOFF12 879@deffnx {} BFD_RELOC_FRV_GOTTLSOFFHI 880@deffnx {} BFD_RELOC_FRV_GOTTLSOFFLO 881@deffnx {} BFD_RELOC_FRV_TLSOFF 882@deffnx {} BFD_RELOC_FRV_TLSDESC_RELAX 883@deffnx {} BFD_RELOC_FRV_GETTLSOFF_RELAX 884@deffnx {} BFD_RELOC_FRV_TLSOFF_RELAX 885@deffnx {} BFD_RELOC_FRV_TLSMOFF 886Fujitsu Frv Relocations. 887@end deffn 888@deffn {} BFD_RELOC_MN10300_GOTOFF24 889This is a 24bit GOT-relative reloc for the mn10300. 890@end deffn 891@deffn {} BFD_RELOC_MN10300_GOT32 892This is a 32bit GOT-relative reloc for the mn10300, offset by two bytes 893in the instruction. 894@end deffn 895@deffn {} BFD_RELOC_MN10300_GOT24 896This is a 24bit GOT-relative reloc for the mn10300, offset by two bytes 897in the instruction. 898@end deffn 899@deffn {} BFD_RELOC_MN10300_GOT16 900This is a 16bit GOT-relative reloc for the mn10300, offset by two bytes 901in the instruction. 902@end deffn 903@deffn {} BFD_RELOC_MN10300_COPY 904Copy symbol at runtime. 905@end deffn 906@deffn {} BFD_RELOC_MN10300_GLOB_DAT 907Create GOT entry. 908@end deffn 909@deffn {} BFD_RELOC_MN10300_JMP_SLOT 910Create PLT entry. 911@end deffn 912@deffn {} BFD_RELOC_MN10300_RELATIVE 913Adjust by program base. 914@end deffn 915@deffn {} BFD_RELOC_386_GOT32 916@deffnx {} BFD_RELOC_386_PLT32 917@deffnx {} BFD_RELOC_386_COPY 918@deffnx {} BFD_RELOC_386_GLOB_DAT 919@deffnx {} BFD_RELOC_386_JUMP_SLOT 920@deffnx {} BFD_RELOC_386_RELATIVE 921@deffnx {} BFD_RELOC_386_GOTOFF 922@deffnx {} BFD_RELOC_386_GOTPC 923@deffnx {} BFD_RELOC_386_TLS_TPOFF 924@deffnx {} BFD_RELOC_386_TLS_IE 925@deffnx {} BFD_RELOC_386_TLS_GOTIE 926@deffnx {} BFD_RELOC_386_TLS_LE 927@deffnx {} BFD_RELOC_386_TLS_GD 928@deffnx {} BFD_RELOC_386_TLS_LDM 929@deffnx {} BFD_RELOC_386_TLS_LDO_32 930@deffnx {} BFD_RELOC_386_TLS_IE_32 931@deffnx {} BFD_RELOC_386_TLS_LE_32 932@deffnx {} BFD_RELOC_386_TLS_DTPMOD32 933@deffnx {} BFD_RELOC_386_TLS_DTPOFF32 934@deffnx {} BFD_RELOC_386_TLS_TPOFF32 935@deffnx {} BFD_RELOC_386_TLS_GOTDESC 936@deffnx {} BFD_RELOC_386_TLS_DESC_CALL 937@deffnx {} BFD_RELOC_386_TLS_DESC 938i386/elf relocations 939@end deffn 940@deffn {} BFD_RELOC_X86_64_GOT32 941@deffnx {} BFD_RELOC_X86_64_PLT32 942@deffnx {} BFD_RELOC_X86_64_COPY 943@deffnx {} BFD_RELOC_X86_64_GLOB_DAT 944@deffnx {} BFD_RELOC_X86_64_JUMP_SLOT 945@deffnx {} BFD_RELOC_X86_64_RELATIVE 946@deffnx {} BFD_RELOC_X86_64_GOTPCREL 947@deffnx {} BFD_RELOC_X86_64_32S 948@deffnx {} BFD_RELOC_X86_64_DTPMOD64 949@deffnx {} BFD_RELOC_X86_64_DTPOFF64 950@deffnx {} BFD_RELOC_X86_64_TPOFF64 951@deffnx {} BFD_RELOC_X86_64_TLSGD 952@deffnx {} BFD_RELOC_X86_64_TLSLD 953@deffnx {} BFD_RELOC_X86_64_DTPOFF32 954@deffnx {} BFD_RELOC_X86_64_GOTTPOFF 955@deffnx {} BFD_RELOC_X86_64_TPOFF32 956@deffnx {} BFD_RELOC_X86_64_GOTOFF64 957@deffnx {} BFD_RELOC_X86_64_GOTPC32 958@deffnx {} BFD_RELOC_X86_64_GOT64 959@deffnx {} BFD_RELOC_X86_64_GOTPCREL64 960@deffnx {} BFD_RELOC_X86_64_GOTPC64 961@deffnx {} BFD_RELOC_X86_64_GOTPLT64 962@deffnx {} BFD_RELOC_X86_64_PLTOFF64 963@deffnx {} BFD_RELOC_X86_64_GOTPC32_TLSDESC 964@deffnx {} BFD_RELOC_X86_64_TLSDESC_CALL 965@deffnx {} BFD_RELOC_X86_64_TLSDESC 966x86-64/elf relocations 967@end deffn 968@deffn {} BFD_RELOC_NS32K_IMM_8 969@deffnx {} BFD_RELOC_NS32K_IMM_16 970@deffnx {} BFD_RELOC_NS32K_IMM_32 971@deffnx {} BFD_RELOC_NS32K_IMM_8_PCREL 972@deffnx {} BFD_RELOC_NS32K_IMM_16_PCREL 973@deffnx {} BFD_RELOC_NS32K_IMM_32_PCREL 974@deffnx {} BFD_RELOC_NS32K_DISP_8 975@deffnx {} BFD_RELOC_NS32K_DISP_16 976@deffnx {} BFD_RELOC_NS32K_DISP_32 977@deffnx {} BFD_RELOC_NS32K_DISP_8_PCREL 978@deffnx {} BFD_RELOC_NS32K_DISP_16_PCREL 979@deffnx {} BFD_RELOC_NS32K_DISP_32_PCREL 980ns32k relocations 981@end deffn 982@deffn {} BFD_RELOC_PDP11_DISP_8_PCREL 983@deffnx {} BFD_RELOC_PDP11_DISP_6_PCREL 984PDP11 relocations 985@end deffn 986@deffn {} BFD_RELOC_PJ_CODE_HI16 987@deffnx {} BFD_RELOC_PJ_CODE_LO16 988@deffnx {} BFD_RELOC_PJ_CODE_DIR16 989@deffnx {} BFD_RELOC_PJ_CODE_DIR32 990@deffnx {} BFD_RELOC_PJ_CODE_REL16 991@deffnx {} BFD_RELOC_PJ_CODE_REL32 992Picojava relocs. Not all of these appear in object files. 993@end deffn 994@deffn {} BFD_RELOC_PPC_B26 995@deffnx {} BFD_RELOC_PPC_BA26 996@deffnx {} BFD_RELOC_PPC_TOC16 997@deffnx {} BFD_RELOC_PPC_B16 998@deffnx {} BFD_RELOC_PPC_B16_BRTAKEN 999@deffnx {} BFD_RELOC_PPC_B16_BRNTAKEN 1000@deffnx {} BFD_RELOC_PPC_BA16 1001@deffnx {} BFD_RELOC_PPC_BA16_BRTAKEN 1002@deffnx {} BFD_RELOC_PPC_BA16_BRNTAKEN 1003@deffnx {} BFD_RELOC_PPC_COPY 1004@deffnx {} BFD_RELOC_PPC_GLOB_DAT 1005@deffnx {} BFD_RELOC_PPC_JMP_SLOT 1006@deffnx {} BFD_RELOC_PPC_RELATIVE 1007@deffnx {} BFD_RELOC_PPC_LOCAL24PC 1008@deffnx {} BFD_RELOC_PPC_EMB_NADDR32 1009@deffnx {} BFD_RELOC_PPC_EMB_NADDR16 1010@deffnx {} BFD_RELOC_PPC_EMB_NADDR16_LO 1011@deffnx {} BFD_RELOC_PPC_EMB_NADDR16_HI 1012@deffnx {} BFD_RELOC_PPC_EMB_NADDR16_HA 1013@deffnx {} BFD_RELOC_PPC_EMB_SDAI16 1014@deffnx {} BFD_RELOC_PPC_EMB_SDA2I16 1015@deffnx {} BFD_RELOC_PPC_EMB_SDA2REL 1016@deffnx {} BFD_RELOC_PPC_EMB_SDA21 1017@deffnx {} BFD_RELOC_PPC_EMB_MRKREF 1018@deffnx {} BFD_RELOC_PPC_EMB_RELSEC16 1019@deffnx {} BFD_RELOC_PPC_EMB_RELST_LO 1020@deffnx {} BFD_RELOC_PPC_EMB_RELST_HI 1021@deffnx {} BFD_RELOC_PPC_EMB_RELST_HA 1022@deffnx {} BFD_RELOC_PPC_EMB_BIT_FLD 1023@deffnx {} BFD_RELOC_PPC_EMB_RELSDA 1024@deffnx {} BFD_RELOC_PPC64_HIGHER 1025@deffnx {} BFD_RELOC_PPC64_HIGHER_S 1026@deffnx {} BFD_RELOC_PPC64_HIGHEST 1027@deffnx {} BFD_RELOC_PPC64_HIGHEST_S 1028@deffnx {} BFD_RELOC_PPC64_TOC16_LO 1029@deffnx {} BFD_RELOC_PPC64_TOC16_HI 1030@deffnx {} BFD_RELOC_PPC64_TOC16_HA 1031@deffnx {} BFD_RELOC_PPC64_TOC 1032@deffnx {} BFD_RELOC_PPC64_PLTGOT16 1033@deffnx {} BFD_RELOC_PPC64_PLTGOT16_LO 1034@deffnx {} BFD_RELOC_PPC64_PLTGOT16_HI 1035@deffnx {} BFD_RELOC_PPC64_PLTGOT16_HA 1036@deffnx {} BFD_RELOC_PPC64_ADDR16_DS 1037@deffnx {} BFD_RELOC_PPC64_ADDR16_LO_DS 1038@deffnx {} BFD_RELOC_PPC64_GOT16_DS 1039@deffnx {} BFD_RELOC_PPC64_GOT16_LO_DS 1040@deffnx {} BFD_RELOC_PPC64_PLT16_LO_DS 1041@deffnx {} BFD_RELOC_PPC64_SECTOFF_DS 1042@deffnx {} BFD_RELOC_PPC64_SECTOFF_LO_DS 1043@deffnx {} BFD_RELOC_PPC64_TOC16_DS 1044@deffnx {} BFD_RELOC_PPC64_TOC16_LO_DS 1045@deffnx {} BFD_RELOC_PPC64_PLTGOT16_DS 1046@deffnx {} BFD_RELOC_PPC64_PLTGOT16_LO_DS 1047Power(rs6000) and PowerPC relocations. 1048@end deffn 1049@deffn {} BFD_RELOC_PPC_TLS 1050@deffnx {} BFD_RELOC_PPC_DTPMOD 1051@deffnx {} BFD_RELOC_PPC_TPREL16 1052@deffnx {} BFD_RELOC_PPC_TPREL16_LO 1053@deffnx {} BFD_RELOC_PPC_TPREL16_HI 1054@deffnx {} BFD_RELOC_PPC_TPREL16_HA 1055@deffnx {} BFD_RELOC_PPC_TPREL 1056@deffnx {} BFD_RELOC_PPC_DTPREL16 1057@deffnx {} BFD_RELOC_PPC_DTPREL16_LO 1058@deffnx {} BFD_RELOC_PPC_DTPREL16_HI 1059@deffnx {} BFD_RELOC_PPC_DTPREL16_HA 1060@deffnx {} BFD_RELOC_PPC_DTPREL 1061@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16 1062@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16_LO 1063@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16_HI 1064@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16_HA 1065@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16 1066@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16_LO 1067@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16_HI 1068@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16_HA 1069@deffnx {} BFD_RELOC_PPC_GOT_TPREL16 1070@deffnx {} BFD_RELOC_PPC_GOT_TPREL16_LO 1071@deffnx {} BFD_RELOC_PPC_GOT_TPREL16_HI 1072@deffnx {} BFD_RELOC_PPC_GOT_TPREL16_HA 1073@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16 1074@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16_LO 1075@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16_HI 1076@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16_HA 1077@deffnx {} BFD_RELOC_PPC64_TPREL16_DS 1078@deffnx {} BFD_RELOC_PPC64_TPREL16_LO_DS 1079@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHER 1080@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHERA 1081@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHEST 1082@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHESTA 1083@deffnx {} BFD_RELOC_PPC64_DTPREL16_DS 1084@deffnx {} BFD_RELOC_PPC64_DTPREL16_LO_DS 1085@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHER 1086@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHERA 1087@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHEST 1088@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHESTA 1089PowerPC and PowerPC64 thread-local storage relocations. 1090@end deffn 1091@deffn {} BFD_RELOC_I370_D12 1092IBM 370/390 relocations 1093@end deffn 1094@deffn {} BFD_RELOC_CTOR 1095The type of reloc used to build a constructor table - at the moment 1096probably a 32 bit wide absolute relocation, but the target can choose. 1097It generally does map to one of the other relocation types. 1098@end deffn 1099@deffn {} BFD_RELOC_ARM_PCREL_BRANCH 1100ARM 26 bit pc-relative branch. The lowest two bits must be zero and are 1101not stored in the instruction. 1102@end deffn 1103@deffn {} BFD_RELOC_ARM_PCREL_BLX 1104ARM 26 bit pc-relative branch. The lowest bit must be zero and is 1105not stored in the instruction. The 2nd lowest bit comes from a 1 bit 1106field in the instruction. 1107@end deffn 1108@deffn {} BFD_RELOC_THUMB_PCREL_BLX 1109Thumb 22 bit pc-relative branch. The lowest bit must be zero and is 1110not stored in the instruction. The 2nd lowest bit comes from a 1 bit 1111field in the instruction. 1112@end deffn 1113@deffn {} BFD_RELOC_ARM_PCREL_CALL 1114ARM 26-bit pc-relative branch for an unconditional BL or BLX instruction. 1115@end deffn 1116@deffn {} BFD_RELOC_ARM_PCREL_JUMP 1117ARM 26-bit pc-relative branch for B or conditional BL instruction. 1118@end deffn 1119@deffn {} BFD_RELOC_THUMB_PCREL_BRANCH7 1120@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH9 1121@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH12 1122@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH20 1123@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH23 1124@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH25 1125Thumb 7-, 9-, 12-, 20-, 23-, and 25-bit pc-relative branches. 1126The lowest bit must be zero and is not stored in the instruction. 1127Note that the corresponding ELF R_ARM_THM_JUMPnn constant has an 1128"nn" one smaller in all cases. Note further that BRANCH23 1129corresponds to R_ARM_THM_CALL. 1130@end deffn 1131@deffn {} BFD_RELOC_ARM_OFFSET_IMM 113212-bit immediate offset, used in ARM-format ldr and str instructions. 1133@end deffn 1134@deffn {} BFD_RELOC_ARM_THUMB_OFFSET 11355-bit immediate offset, used in Thumb-format ldr and str instructions. 1136@end deffn 1137@deffn {} BFD_RELOC_ARM_TARGET1 1138Pc-relative or absolute relocation depending on target. Used for 1139entries in .init_array sections. 1140@end deffn 1141@deffn {} BFD_RELOC_ARM_ROSEGREL32 1142Read-only segment base relative address. 1143@end deffn 1144@deffn {} BFD_RELOC_ARM_SBREL32 1145Data segment base relative address. 1146@end deffn 1147@deffn {} BFD_RELOC_ARM_TARGET2 1148This reloc is used for references to RTTI data from exception handling 1149tables. The actual definition depends on the target. It may be a 1150pc-relative or some form of GOT-indirect relocation. 1151@end deffn 1152@deffn {} BFD_RELOC_ARM_PREL31 115331-bit PC relative address. 1154@end deffn 1155@deffn {} BFD_RELOC_ARM_JUMP_SLOT 1156@deffnx {} BFD_RELOC_ARM_GLOB_DAT 1157@deffnx {} BFD_RELOC_ARM_GOT32 1158@deffnx {} BFD_RELOC_ARM_PLT32 1159@deffnx {} BFD_RELOC_ARM_RELATIVE 1160@deffnx {} BFD_RELOC_ARM_GOTOFF 1161@deffnx {} BFD_RELOC_ARM_GOTPC 1162Relocations for setting up GOTs and PLTs for shared libraries. 1163@end deffn 1164@deffn {} BFD_RELOC_ARM_TLS_GD32 1165@deffnx {} BFD_RELOC_ARM_TLS_LDO32 1166@deffnx {} BFD_RELOC_ARM_TLS_LDM32 1167@deffnx {} BFD_RELOC_ARM_TLS_DTPOFF32 1168@deffnx {} BFD_RELOC_ARM_TLS_DTPMOD32 1169@deffnx {} BFD_RELOC_ARM_TLS_TPOFF32 1170@deffnx {} BFD_RELOC_ARM_TLS_IE32 1171@deffnx {} BFD_RELOC_ARM_TLS_LE32 1172ARM thread-local storage relocations. 1173@end deffn 1174@deffn {} BFD_RELOC_ARM_IMMEDIATE 1175@deffnx {} BFD_RELOC_ARM_ADRL_IMMEDIATE 1176@deffnx {} BFD_RELOC_ARM_T32_IMMEDIATE 1177@deffnx {} BFD_RELOC_ARM_T32_IMM12 1178@deffnx {} BFD_RELOC_ARM_T32_ADD_PC12 1179@deffnx {} BFD_RELOC_ARM_SHIFT_IMM 1180@deffnx {} BFD_RELOC_ARM_SMC 1181@deffnx {} BFD_RELOC_ARM_SWI 1182@deffnx {} BFD_RELOC_ARM_MULTI 1183@deffnx {} BFD_RELOC_ARM_CP_OFF_IMM 1184@deffnx {} BFD_RELOC_ARM_CP_OFF_IMM_S2 1185@deffnx {} BFD_RELOC_ARM_T32_CP_OFF_IMM 1186@deffnx {} BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 1187@deffnx {} BFD_RELOC_ARM_ADR_IMM 1188@deffnx {} BFD_RELOC_ARM_LDR_IMM 1189@deffnx {} BFD_RELOC_ARM_LITERAL 1190@deffnx {} BFD_RELOC_ARM_IN_POOL 1191@deffnx {} BFD_RELOC_ARM_OFFSET_IMM8 1192@deffnx {} BFD_RELOC_ARM_T32_OFFSET_U8 1193@deffnx {} BFD_RELOC_ARM_T32_OFFSET_IMM 1194@deffnx {} BFD_RELOC_ARM_HWLITERAL 1195@deffnx {} BFD_RELOC_ARM_THUMB_ADD 1196@deffnx {} BFD_RELOC_ARM_THUMB_IMM 1197@deffnx {} BFD_RELOC_ARM_THUMB_SHIFT 1198These relocs are only used within the ARM assembler. They are not 1199(at present) written to any object files. 1200@end deffn 1201@deffn {} BFD_RELOC_SH_PCDISP8BY2 1202@deffnx {} BFD_RELOC_SH_PCDISP12BY2 1203@deffnx {} BFD_RELOC_SH_IMM3 1204@deffnx {} BFD_RELOC_SH_IMM3U 1205@deffnx {} BFD_RELOC_SH_DISP12 1206@deffnx {} BFD_RELOC_SH_DISP12BY2 1207@deffnx {} BFD_RELOC_SH_DISP12BY4 1208@deffnx {} BFD_RELOC_SH_DISP12BY8 1209@deffnx {} BFD_RELOC_SH_DISP20 1210@deffnx {} BFD_RELOC_SH_DISP20BY8 1211@deffnx {} BFD_RELOC_SH_IMM4 1212@deffnx {} BFD_RELOC_SH_IMM4BY2 1213@deffnx {} BFD_RELOC_SH_IMM4BY4 1214@deffnx {} BFD_RELOC_SH_IMM8 1215@deffnx {} BFD_RELOC_SH_IMM8BY2 1216@deffnx {} BFD_RELOC_SH_IMM8BY4 1217@deffnx {} BFD_RELOC_SH_PCRELIMM8BY2 1218@deffnx {} BFD_RELOC_SH_PCRELIMM8BY4 1219@deffnx {} BFD_RELOC_SH_SWITCH16 1220@deffnx {} BFD_RELOC_SH_SWITCH32 1221@deffnx {} BFD_RELOC_SH_USES 1222@deffnx {} BFD_RELOC_SH_COUNT 1223@deffnx {} BFD_RELOC_SH_ALIGN 1224@deffnx {} BFD_RELOC_SH_CODE 1225@deffnx {} BFD_RELOC_SH_DATA 1226@deffnx {} BFD_RELOC_SH_LABEL 1227@deffnx {} BFD_RELOC_SH_LOOP_START 1228@deffnx {} BFD_RELOC_SH_LOOP_END 1229@deffnx {} BFD_RELOC_SH_COPY 1230@deffnx {} BFD_RELOC_SH_GLOB_DAT 1231@deffnx {} BFD_RELOC_SH_JMP_SLOT 1232@deffnx {} BFD_RELOC_SH_RELATIVE 1233@deffnx {} BFD_RELOC_SH_GOTPC 1234@deffnx {} BFD_RELOC_SH_GOT_LOW16 1235@deffnx {} BFD_RELOC_SH_GOT_MEDLOW16 1236@deffnx {} BFD_RELOC_SH_GOT_MEDHI16 1237@deffnx {} BFD_RELOC_SH_GOT_HI16 1238@deffnx {} BFD_RELOC_SH_GOTPLT_LOW16 1239@deffnx {} BFD_RELOC_SH_GOTPLT_MEDLOW16 1240@deffnx {} BFD_RELOC_SH_GOTPLT_MEDHI16 1241@deffnx {} BFD_RELOC_SH_GOTPLT_HI16 1242@deffnx {} BFD_RELOC_SH_PLT_LOW16 1243@deffnx {} BFD_RELOC_SH_PLT_MEDLOW16 1244@deffnx {} BFD_RELOC_SH_PLT_MEDHI16 1245@deffnx {} BFD_RELOC_SH_PLT_HI16 1246@deffnx {} BFD_RELOC_SH_GOTOFF_LOW16 1247@deffnx {} BFD_RELOC_SH_GOTOFF_MEDLOW16 1248@deffnx {} BFD_RELOC_SH_GOTOFF_MEDHI16 1249@deffnx {} BFD_RELOC_SH_GOTOFF_HI16 1250@deffnx {} BFD_RELOC_SH_GOTPC_LOW16 1251@deffnx {} BFD_RELOC_SH_GOTPC_MEDLOW16 1252@deffnx {} BFD_RELOC_SH_GOTPC_MEDHI16 1253@deffnx {} BFD_RELOC_SH_GOTPC_HI16 1254@deffnx {} BFD_RELOC_SH_COPY64 1255@deffnx {} BFD_RELOC_SH_GLOB_DAT64 1256@deffnx {} BFD_RELOC_SH_JMP_SLOT64 1257@deffnx {} BFD_RELOC_SH_RELATIVE64 1258@deffnx {} BFD_RELOC_SH_GOT10BY4 1259@deffnx {} BFD_RELOC_SH_GOT10BY8 1260@deffnx {} BFD_RELOC_SH_GOTPLT10BY4 1261@deffnx {} BFD_RELOC_SH_GOTPLT10BY8 1262@deffnx {} BFD_RELOC_SH_GOTPLT32 1263@deffnx {} BFD_RELOC_SH_SHMEDIA_CODE 1264@deffnx {} BFD_RELOC_SH_IMMU5 1265@deffnx {} BFD_RELOC_SH_IMMS6 1266@deffnx {} BFD_RELOC_SH_IMMS6BY32 1267@deffnx {} BFD_RELOC_SH_IMMU6 1268@deffnx {} BFD_RELOC_SH_IMMS10 1269@deffnx {} BFD_RELOC_SH_IMMS10BY2 1270@deffnx {} BFD_RELOC_SH_IMMS10BY4 1271@deffnx {} BFD_RELOC_SH_IMMS10BY8 1272@deffnx {} BFD_RELOC_SH_IMMS16 1273@deffnx {} BFD_RELOC_SH_IMMU16 1274@deffnx {} BFD_RELOC_SH_IMM_LOW16 1275@deffnx {} BFD_RELOC_SH_IMM_LOW16_PCREL 1276@deffnx {} BFD_RELOC_SH_IMM_MEDLOW16 1277@deffnx {} BFD_RELOC_SH_IMM_MEDLOW16_PCREL 1278@deffnx {} BFD_RELOC_SH_IMM_MEDHI16 1279@deffnx {} BFD_RELOC_SH_IMM_MEDHI16_PCREL 1280@deffnx {} BFD_RELOC_SH_IMM_HI16 1281@deffnx {} BFD_RELOC_SH_IMM_HI16_PCREL 1282@deffnx {} BFD_RELOC_SH_PT_16 1283@deffnx {} BFD_RELOC_SH_TLS_GD_32 1284@deffnx {} BFD_RELOC_SH_TLS_LD_32 1285@deffnx {} BFD_RELOC_SH_TLS_LDO_32 1286@deffnx {} BFD_RELOC_SH_TLS_IE_32 1287@deffnx {} BFD_RELOC_SH_TLS_LE_32 1288@deffnx {} BFD_RELOC_SH_TLS_DTPMOD32 1289@deffnx {} BFD_RELOC_SH_TLS_DTPOFF32 1290@deffnx {} BFD_RELOC_SH_TLS_TPOFF32 1291Renesas / SuperH SH relocs. Not all of these appear in object files. 1292@end deffn 1293@deffn {} BFD_RELOC_ARC_B22_PCREL 1294ARC Cores relocs. 1295ARC 22 bit pc-relative branch. The lowest two bits must be zero and are 1296not stored in the instruction. The high 20 bits are installed in bits 26 1297through 7 of the instruction. 1298@end deffn 1299@deffn {} BFD_RELOC_ARC_B26 1300ARC 26 bit absolute branch. The lowest two bits must be zero and are not 1301stored in the instruction. The high 24 bits are installed in bits 23 1302through 0. 1303@end deffn 1304@deffn {} BFD_RELOC_BFIN_16_IMM 1305ADI Blackfin 16 bit immediate absolute reloc. 1306@end deffn 1307@deffn {} BFD_RELOC_BFIN_16_HIGH 1308ADI Blackfin 16 bit immediate absolute reloc higher 16 bits. 1309@end deffn 1310@deffn {} BFD_RELOC_BFIN_4_PCREL 1311ADI Blackfin 'a' part of LSETUP. 1312@end deffn 1313@deffn {} BFD_RELOC_BFIN_5_PCREL 1314ADI Blackfin. 1315@end deffn 1316@deffn {} BFD_RELOC_BFIN_16_LOW 1317ADI Blackfin 16 bit immediate absolute reloc lower 16 bits. 1318@end deffn 1319@deffn {} BFD_RELOC_BFIN_10_PCREL 1320ADI Blackfin. 1321@end deffn 1322@deffn {} BFD_RELOC_BFIN_11_PCREL 1323ADI Blackfin 'b' part of LSETUP. 1324@end deffn 1325@deffn {} BFD_RELOC_BFIN_12_PCREL_JUMP 1326ADI Blackfin. 1327@end deffn 1328@deffn {} BFD_RELOC_BFIN_12_PCREL_JUMP_S 1329ADI Blackfin Short jump, pcrel. 1330@end deffn 1331@deffn {} BFD_RELOC_BFIN_24_PCREL_CALL_X 1332ADI Blackfin Call.x not implemented. 1333@end deffn 1334@deffn {} BFD_RELOC_BFIN_24_PCREL_JUMP_L 1335ADI Blackfin Long Jump pcrel. 1336@end deffn 1337@deffn {} BFD_RELOC_BFIN_GOT17M4 1338@deffnx {} BFD_RELOC_BFIN_GOTHI 1339@deffnx {} BFD_RELOC_BFIN_GOTLO 1340@deffnx {} BFD_RELOC_BFIN_FUNCDESC 1341@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOT17M4 1342@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTHI 1343@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTLO 1344@deffnx {} BFD_RELOC_BFIN_FUNCDESC_VALUE 1345@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTOFF17M4 1346@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTOFFHI 1347@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTOFFLO 1348@deffnx {} BFD_RELOC_BFIN_GOTOFF17M4 1349@deffnx {} BFD_RELOC_BFIN_GOTOFFHI 1350@deffnx {} BFD_RELOC_BFIN_GOTOFFLO 1351ADI Blackfin FD-PIC relocations. 1352@end deffn 1353@deffn {} BFD_RELOC_BFIN_GOT 1354ADI Blackfin GOT relocation. 1355@end deffn 1356@deffn {} BFD_RELOC_BFIN_PLTPC 1357ADI Blackfin PLTPC relocation. 1358@end deffn 1359@deffn {} BFD_ARELOC_BFIN_PUSH 1360ADI Blackfin arithmetic relocation. 1361@end deffn 1362@deffn {} BFD_ARELOC_BFIN_CONST 1363ADI Blackfin arithmetic relocation. 1364@end deffn 1365@deffn {} BFD_ARELOC_BFIN_ADD 1366ADI Blackfin arithmetic relocation. 1367@end deffn 1368@deffn {} BFD_ARELOC_BFIN_SUB 1369ADI Blackfin arithmetic relocation. 1370@end deffn 1371@deffn {} BFD_ARELOC_BFIN_MULT 1372ADI Blackfin arithmetic relocation. 1373@end deffn 1374@deffn {} BFD_ARELOC_BFIN_DIV 1375ADI Blackfin arithmetic relocation. 1376@end deffn 1377@deffn {} BFD_ARELOC_BFIN_MOD 1378ADI Blackfin arithmetic relocation. 1379@end deffn 1380@deffn {} BFD_ARELOC_BFIN_LSHIFT 1381ADI Blackfin arithmetic relocation. 1382@end deffn 1383@deffn {} BFD_ARELOC_BFIN_RSHIFT 1384ADI Blackfin arithmetic relocation. 1385@end deffn 1386@deffn {} BFD_ARELOC_BFIN_AND 1387ADI Blackfin arithmetic relocation. 1388@end deffn 1389@deffn {} BFD_ARELOC_BFIN_OR 1390ADI Blackfin arithmetic relocation. 1391@end deffn 1392@deffn {} BFD_ARELOC_BFIN_XOR 1393ADI Blackfin arithmetic relocation. 1394@end deffn 1395@deffn {} BFD_ARELOC_BFIN_LAND 1396ADI Blackfin arithmetic relocation. 1397@end deffn 1398@deffn {} BFD_ARELOC_BFIN_LOR 1399ADI Blackfin arithmetic relocation. 1400@end deffn 1401@deffn {} BFD_ARELOC_BFIN_LEN 1402ADI Blackfin arithmetic relocation. 1403@end deffn 1404@deffn {} BFD_ARELOC_BFIN_NEG 1405ADI Blackfin arithmetic relocation. 1406@end deffn 1407@deffn {} BFD_ARELOC_BFIN_COMP 1408ADI Blackfin arithmetic relocation. 1409@end deffn 1410@deffn {} BFD_ARELOC_BFIN_PAGE 1411ADI Blackfin arithmetic relocation. 1412@end deffn 1413@deffn {} BFD_ARELOC_BFIN_HWPAGE 1414ADI Blackfin arithmetic relocation. 1415@end deffn 1416@deffn {} BFD_ARELOC_BFIN_ADDR 1417ADI Blackfin arithmetic relocation. 1418@end deffn 1419@deffn {} BFD_RELOC_D10V_10_PCREL_R 1420Mitsubishi D10V relocs. 1421This is a 10-bit reloc with the right 2 bits 1422assumed to be 0. 1423@end deffn 1424@deffn {} BFD_RELOC_D10V_10_PCREL_L 1425Mitsubishi D10V relocs. 1426This is a 10-bit reloc with the right 2 bits 1427assumed to be 0. This is the same as the previous reloc 1428except it is in the left container, i.e., 1429shifted left 15 bits. 1430@end deffn 1431@deffn {} BFD_RELOC_D10V_18 1432This is an 18-bit reloc with the right 2 bits 1433assumed to be 0. 1434@end deffn 1435@deffn {} BFD_RELOC_D10V_18_PCREL 1436This is an 18-bit reloc with the right 2 bits 1437assumed to be 0. 1438@end deffn 1439@deffn {} BFD_RELOC_D30V_6 1440Mitsubishi D30V relocs. 1441This is a 6-bit absolute reloc. 1442@end deffn 1443@deffn {} BFD_RELOC_D30V_9_PCREL 1444This is a 6-bit pc-relative reloc with 1445the right 3 bits assumed to be 0. 1446@end deffn 1447@deffn {} BFD_RELOC_D30V_9_PCREL_R 1448This is a 6-bit pc-relative reloc with 1449the right 3 bits assumed to be 0. Same 1450as the previous reloc but on the right side 1451of the container. 1452@end deffn 1453@deffn {} BFD_RELOC_D30V_15 1454This is a 12-bit absolute reloc with the 1455right 3 bitsassumed to be 0. 1456@end deffn 1457@deffn {} BFD_RELOC_D30V_15_PCREL 1458This is a 12-bit pc-relative reloc with 1459the right 3 bits assumed to be 0. 1460@end deffn 1461@deffn {} BFD_RELOC_D30V_15_PCREL_R 1462This is a 12-bit pc-relative reloc with 1463the right 3 bits assumed to be 0. Same 1464as the previous reloc but on the right side 1465of the container. 1466@end deffn 1467@deffn {} BFD_RELOC_D30V_21 1468This is an 18-bit absolute reloc with 1469the right 3 bits assumed to be 0. 1470@end deffn 1471@deffn {} BFD_RELOC_D30V_21_PCREL 1472This is an 18-bit pc-relative reloc with 1473the right 3 bits assumed to be 0. 1474@end deffn 1475@deffn {} BFD_RELOC_D30V_21_PCREL_R 1476This is an 18-bit pc-relative reloc with 1477the right 3 bits assumed to be 0. Same 1478as the previous reloc but on the right side 1479of the container. 1480@end deffn 1481@deffn {} BFD_RELOC_D30V_32 1482This is a 32-bit absolute reloc. 1483@end deffn 1484@deffn {} BFD_RELOC_D30V_32_PCREL 1485This is a 32-bit pc-relative reloc. 1486@end deffn 1487@deffn {} BFD_RELOC_DLX_HI16_S 1488DLX relocs 1489@end deffn 1490@deffn {} BFD_RELOC_DLX_LO16 1491DLX relocs 1492@end deffn 1493@deffn {} BFD_RELOC_DLX_JMP26 1494DLX relocs 1495@end deffn 1496@deffn {} BFD_RELOC_M32C_HI8 1497@deffnx {} BFD_RELOC_M32C_RL_JUMP 1498@deffnx {} BFD_RELOC_M32C_RL_1ADDR 1499@deffnx {} BFD_RELOC_M32C_RL_2ADDR 1500Renesas M16C/M32C Relocations. 1501@end deffn 1502@deffn {} BFD_RELOC_M32R_24 1503Renesas M32R (formerly Mitsubishi M32R) relocs. 1504This is a 24 bit absolute address. 1505@end deffn 1506@deffn {} BFD_RELOC_M32R_10_PCREL 1507This is a 10-bit pc-relative reloc with the right 2 bits assumed to be 0. 1508@end deffn 1509@deffn {} BFD_RELOC_M32R_18_PCREL 1510This is an 18-bit reloc with the right 2 bits assumed to be 0. 1511@end deffn 1512@deffn {} BFD_RELOC_M32R_26_PCREL 1513This is a 26-bit reloc with the right 2 bits assumed to be 0. 1514@end deffn 1515@deffn {} BFD_RELOC_M32R_HI16_ULO 1516This is a 16-bit reloc containing the high 16 bits of an address 1517used when the lower 16 bits are treated as unsigned. 1518@end deffn 1519@deffn {} BFD_RELOC_M32R_HI16_SLO 1520This is a 16-bit reloc containing the high 16 bits of an address 1521used when the lower 16 bits are treated as signed. 1522@end deffn 1523@deffn {} BFD_RELOC_M32R_LO16 1524This is a 16-bit reloc containing the lower 16 bits of an address. 1525@end deffn 1526@deffn {} BFD_RELOC_M32R_SDA16 1527This is a 16-bit reloc containing the small data area offset for use in 1528add3, load, and store instructions. 1529@end deffn 1530@deffn {} BFD_RELOC_M32R_GOT24 1531@deffnx {} BFD_RELOC_M32R_26_PLTREL 1532@deffnx {} BFD_RELOC_M32R_COPY 1533@deffnx {} BFD_RELOC_M32R_GLOB_DAT 1534@deffnx {} BFD_RELOC_M32R_JMP_SLOT 1535@deffnx {} BFD_RELOC_M32R_RELATIVE 1536@deffnx {} BFD_RELOC_M32R_GOTOFF 1537@deffnx {} BFD_RELOC_M32R_GOTOFF_HI_ULO 1538@deffnx {} BFD_RELOC_M32R_GOTOFF_HI_SLO 1539@deffnx {} BFD_RELOC_M32R_GOTOFF_LO 1540@deffnx {} BFD_RELOC_M32R_GOTPC24 1541@deffnx {} BFD_RELOC_M32R_GOT16_HI_ULO 1542@deffnx {} BFD_RELOC_M32R_GOT16_HI_SLO 1543@deffnx {} BFD_RELOC_M32R_GOT16_LO 1544@deffnx {} BFD_RELOC_M32R_GOTPC_HI_ULO 1545@deffnx {} BFD_RELOC_M32R_GOTPC_HI_SLO 1546@deffnx {} BFD_RELOC_M32R_GOTPC_LO 1547For PIC. 1548@end deffn 1549@deffn {} BFD_RELOC_V850_9_PCREL 1550This is a 9-bit reloc 1551@end deffn 1552@deffn {} BFD_RELOC_V850_22_PCREL 1553This is a 22-bit reloc 1554@end deffn 1555@deffn {} BFD_RELOC_V850_SDA_16_16_OFFSET 1556This is a 16 bit offset from the short data area pointer. 1557@end deffn 1558@deffn {} BFD_RELOC_V850_SDA_15_16_OFFSET 1559This is a 16 bit offset (of which only 15 bits are used) from the 1560short data area pointer. 1561@end deffn 1562@deffn {} BFD_RELOC_V850_ZDA_16_16_OFFSET 1563This is a 16 bit offset from the zero data area pointer. 1564@end deffn 1565@deffn {} BFD_RELOC_V850_ZDA_15_16_OFFSET 1566This is a 16 bit offset (of which only 15 bits are used) from the 1567zero data area pointer. 1568@end deffn 1569@deffn {} BFD_RELOC_V850_TDA_6_8_OFFSET 1570This is an 8 bit offset (of which only 6 bits are used) from the 1571tiny data area pointer. 1572@end deffn 1573@deffn {} BFD_RELOC_V850_TDA_7_8_OFFSET 1574This is an 8bit offset (of which only 7 bits are used) from the tiny 1575data area pointer. 1576@end deffn 1577@deffn {} BFD_RELOC_V850_TDA_7_7_OFFSET 1578This is a 7 bit offset from the tiny data area pointer. 1579@end deffn 1580@deffn {} BFD_RELOC_V850_TDA_16_16_OFFSET 1581This is a 16 bit offset from the tiny data area pointer. 1582@end deffn 1583@deffn {} BFD_RELOC_V850_TDA_4_5_OFFSET 1584This is a 5 bit offset (of which only 4 bits are used) from the tiny 1585data area pointer. 1586@end deffn 1587@deffn {} BFD_RELOC_V850_TDA_4_4_OFFSET 1588This is a 4 bit offset from the tiny data area pointer. 1589@end deffn 1590@deffn {} BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET 1591This is a 16 bit offset from the short data area pointer, with the 1592bits placed non-contiguously in the instruction. 1593@end deffn 1594@deffn {} BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET 1595This is a 16 bit offset from the zero data area pointer, with the 1596bits placed non-contiguously in the instruction. 1597@end deffn 1598@deffn {} BFD_RELOC_V850_CALLT_6_7_OFFSET 1599This is a 6 bit offset from the call table base pointer. 1600@end deffn 1601@deffn {} BFD_RELOC_V850_CALLT_16_16_OFFSET 1602This is a 16 bit offset from the call table base pointer. 1603@end deffn 1604@deffn {} BFD_RELOC_V850_LONGCALL 1605Used for relaxing indirect function calls. 1606@end deffn 1607@deffn {} BFD_RELOC_V850_LONGJUMP 1608Used for relaxing indirect jumps. 1609@end deffn 1610@deffn {} BFD_RELOC_V850_ALIGN 1611Used to maintain alignment whilst relaxing. 1612@end deffn 1613@deffn {} BFD_RELOC_V850_LO16_SPLIT_OFFSET 1614This is a variation of BFD_RELOC_LO16 that can be used in v850e ld.bu 1615instructions. 1616@end deffn 1617@deffn {} BFD_RELOC_MN10300_32_PCREL 1618This is a 32bit pcrel reloc for the mn10300, offset by two bytes in the 1619instruction. 1620@end deffn 1621@deffn {} BFD_RELOC_MN10300_16_PCREL 1622This is a 16bit pcrel reloc for the mn10300, offset by two bytes in the 1623instruction. 1624@end deffn 1625@deffn {} BFD_RELOC_TIC30_LDP 1626This is a 8bit DP reloc for the tms320c30, where the most 1627significant 8 bits of a 24 bit word are placed into the least 1628significant 8 bits of the opcode. 1629@end deffn 1630@deffn {} BFD_RELOC_TIC54X_PARTLS7 1631This is a 7bit reloc for the tms320c54x, where the least 1632significant 7 bits of a 16 bit word are placed into the least 1633significant 7 bits of the opcode. 1634@end deffn 1635@deffn {} BFD_RELOC_TIC54X_PARTMS9 1636This is a 9bit DP reloc for the tms320c54x, where the most 1637significant 9 bits of a 16 bit word are placed into the least 1638significant 9 bits of the opcode. 1639@end deffn 1640@deffn {} BFD_RELOC_TIC54X_23 1641This is an extended address 23-bit reloc for the tms320c54x. 1642@end deffn 1643@deffn {} BFD_RELOC_TIC54X_16_OF_23 1644This is a 16-bit reloc for the tms320c54x, where the least 1645significant 16 bits of a 23-bit extended address are placed into 1646the opcode. 1647@end deffn 1648@deffn {} BFD_RELOC_TIC54X_MS7_OF_23 1649This is a reloc for the tms320c54x, where the most 1650significant 7 bits of a 23-bit extended address are placed into 1651the opcode. 1652@end deffn 1653@deffn {} BFD_RELOC_FR30_48 1654This is a 48 bit reloc for the FR30 that stores 32 bits. 1655@end deffn 1656@deffn {} BFD_RELOC_FR30_20 1657This is a 32 bit reloc for the FR30 that stores 20 bits split up into 1658two sections. 1659@end deffn 1660@deffn {} BFD_RELOC_FR30_6_IN_4 1661This is a 16 bit reloc for the FR30 that stores a 6 bit word offset in 16624 bits. 1663@end deffn 1664@deffn {} BFD_RELOC_FR30_8_IN_8 1665This is a 16 bit reloc for the FR30 that stores an 8 bit byte offset 1666into 8 bits. 1667@end deffn 1668@deffn {} BFD_RELOC_FR30_9_IN_8 1669This is a 16 bit reloc for the FR30 that stores a 9 bit short offset 1670into 8 bits. 1671@end deffn 1672@deffn {} BFD_RELOC_FR30_10_IN_8 1673This is a 16 bit reloc for the FR30 that stores a 10 bit word offset 1674into 8 bits. 1675@end deffn 1676@deffn {} BFD_RELOC_FR30_9_PCREL 1677This is a 16 bit reloc for the FR30 that stores a 9 bit pc relative 1678short offset into 8 bits. 1679@end deffn 1680@deffn {} BFD_RELOC_FR30_12_PCREL 1681This is a 16 bit reloc for the FR30 that stores a 12 bit pc relative 1682short offset into 11 bits. 1683@end deffn 1684@deffn {} BFD_RELOC_MCORE_PCREL_IMM8BY4 1685@deffnx {} BFD_RELOC_MCORE_PCREL_IMM11BY2 1686@deffnx {} BFD_RELOC_MCORE_PCREL_IMM4BY2 1687@deffnx {} BFD_RELOC_MCORE_PCREL_32 1688@deffnx {} BFD_RELOC_MCORE_PCREL_JSR_IMM11BY2 1689@deffnx {} BFD_RELOC_MCORE_RVA 1690Motorola Mcore relocations. 1691@end deffn 1692@deffn {} BFD_RELOC_MMIX_GETA 1693@deffnx {} BFD_RELOC_MMIX_GETA_1 1694@deffnx {} BFD_RELOC_MMIX_GETA_2 1695@deffnx {} BFD_RELOC_MMIX_GETA_3 1696These are relocations for the GETA instruction. 1697@end deffn 1698@deffn {} BFD_RELOC_MMIX_CBRANCH 1699@deffnx {} BFD_RELOC_MMIX_CBRANCH_J 1700@deffnx {} BFD_RELOC_MMIX_CBRANCH_1 1701@deffnx {} BFD_RELOC_MMIX_CBRANCH_2 1702@deffnx {} BFD_RELOC_MMIX_CBRANCH_3 1703These are relocations for a conditional branch instruction. 1704@end deffn 1705@deffn {} BFD_RELOC_MMIX_PUSHJ 1706@deffnx {} BFD_RELOC_MMIX_PUSHJ_1 1707@deffnx {} BFD_RELOC_MMIX_PUSHJ_2 1708@deffnx {} BFD_RELOC_MMIX_PUSHJ_3 1709@deffnx {} BFD_RELOC_MMIX_PUSHJ_STUBBABLE 1710These are relocations for the PUSHJ instruction. 1711@end deffn 1712@deffn {} BFD_RELOC_MMIX_JMP 1713@deffnx {} BFD_RELOC_MMIX_JMP_1 1714@deffnx {} BFD_RELOC_MMIX_JMP_2 1715@deffnx {} BFD_RELOC_MMIX_JMP_3 1716These are relocations for the JMP instruction. 1717@end deffn 1718@deffn {} BFD_RELOC_MMIX_ADDR19 1719This is a relocation for a relative address as in a GETA instruction or 1720a branch. 1721@end deffn 1722@deffn {} BFD_RELOC_MMIX_ADDR27 1723This is a relocation for a relative address as in a JMP instruction. 1724@end deffn 1725@deffn {} BFD_RELOC_MMIX_REG_OR_BYTE 1726This is a relocation for an instruction field that may be a general 1727register or a value 0..255. 1728@end deffn 1729@deffn {} BFD_RELOC_MMIX_REG 1730This is a relocation for an instruction field that may be a general 1731register. 1732@end deffn 1733@deffn {} BFD_RELOC_MMIX_BASE_PLUS_OFFSET 1734This is a relocation for two instruction fields holding a register and 1735an offset, the equivalent of the relocation. 1736@end deffn 1737@deffn {} BFD_RELOC_MMIX_LOCAL 1738This relocation is an assertion that the expression is not allocated as 1739a global register. It does not modify contents. 1740@end deffn 1741@deffn {} BFD_RELOC_AVR_7_PCREL 1742This is a 16 bit reloc for the AVR that stores 8 bit pc relative 1743short offset into 7 bits. 1744@end deffn 1745@deffn {} BFD_RELOC_AVR_13_PCREL 1746This is a 16 bit reloc for the AVR that stores 13 bit pc relative 1747short offset into 12 bits. 1748@end deffn 1749@deffn {} BFD_RELOC_AVR_16_PM 1750This is a 16 bit reloc for the AVR that stores 17 bit value (usually 1751program memory address) into 16 bits. 1752@end deffn 1753@deffn {} BFD_RELOC_AVR_LO8_LDI 1754This is a 16 bit reloc for the AVR that stores 8 bit value (usually 1755data memory address) into 8 bit immediate value of LDI insn. 1756@end deffn 1757@deffn {} BFD_RELOC_AVR_HI8_LDI 1758This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit 1759of data memory address) into 8 bit immediate value of LDI insn. 1760@end deffn 1761@deffn {} BFD_RELOC_AVR_HH8_LDI 1762This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit 1763of program memory address) into 8 bit immediate value of LDI insn. 1764@end deffn 1765@deffn {} BFD_RELOC_AVR_MS8_LDI 1766This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit 1767of 32 bit value) into 8 bit immediate value of LDI insn. 1768@end deffn 1769@deffn {} BFD_RELOC_AVR_LO8_LDI_NEG 1770This is a 16 bit reloc for the AVR that stores negated 8 bit value 1771(usually data memory address) into 8 bit immediate value of SUBI insn. 1772@end deffn 1773@deffn {} BFD_RELOC_AVR_HI8_LDI_NEG 1774This is a 16 bit reloc for the AVR that stores negated 8 bit value 1775(high 8 bit of data memory address) into 8 bit immediate value of 1776SUBI insn. 1777@end deffn 1778@deffn {} BFD_RELOC_AVR_HH8_LDI_NEG 1779This is a 16 bit reloc for the AVR that stores negated 8 bit value 1780(most high 8 bit of program memory address) into 8 bit immediate value 1781of LDI or SUBI insn. 1782@end deffn 1783@deffn {} BFD_RELOC_AVR_MS8_LDI_NEG 1784This is a 16 bit reloc for the AVR that stores negated 8 bit value (msb 1785of 32 bit value) into 8 bit immediate value of LDI insn. 1786@end deffn 1787@deffn {} BFD_RELOC_AVR_LO8_LDI_PM 1788This is a 16 bit reloc for the AVR that stores 8 bit value (usually 1789command address) into 8 bit immediate value of LDI insn. 1790@end deffn 1791@deffn {} BFD_RELOC_AVR_HI8_LDI_PM 1792This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit 1793of command address) into 8 bit immediate value of LDI insn. 1794@end deffn 1795@deffn {} BFD_RELOC_AVR_HH8_LDI_PM 1796This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit 1797of command address) into 8 bit immediate value of LDI insn. 1798@end deffn 1799@deffn {} BFD_RELOC_AVR_LO8_LDI_PM_NEG 1800This is a 16 bit reloc for the AVR that stores negated 8 bit value 1801(usually command address) into 8 bit immediate value of SUBI insn. 1802@end deffn 1803@deffn {} BFD_RELOC_AVR_HI8_LDI_PM_NEG 1804This is a 16 bit reloc for the AVR that stores negated 8 bit value 1805(high 8 bit of 16 bit command address) into 8 bit immediate value 1806of SUBI insn. 1807@end deffn 1808@deffn {} BFD_RELOC_AVR_HH8_LDI_PM_NEG 1809This is a 16 bit reloc for the AVR that stores negated 8 bit value 1810(high 6 bit of 22 bit command address) into 8 bit immediate 1811value of SUBI insn. 1812@end deffn 1813@deffn {} BFD_RELOC_AVR_CALL 1814This is a 32 bit reloc for the AVR that stores 23 bit value 1815into 22 bits. 1816@end deffn 1817@deffn {} BFD_RELOC_AVR_LDI 1818This is a 16 bit reloc for the AVR that stores all needed bits 1819for absolute addressing with ldi with overflow check to linktime 1820@end deffn 1821@deffn {} BFD_RELOC_AVR_6 1822This is a 6 bit reloc for the AVR that stores offset for ldd/std 1823instructions 1824@end deffn 1825@deffn {} BFD_RELOC_AVR_6_ADIW 1826This is a 6 bit reloc for the AVR that stores offset for adiw/sbiw 1827instructions 1828@end deffn 1829@deffn {} BFD_RELOC_390_12 1830Direct 12 bit. 1831@end deffn 1832@deffn {} BFD_RELOC_390_GOT12 183312 bit GOT offset. 1834@end deffn 1835@deffn {} BFD_RELOC_390_PLT32 183632 bit PC relative PLT address. 1837@end deffn 1838@deffn {} BFD_RELOC_390_COPY 1839Copy symbol at runtime. 1840@end deffn 1841@deffn {} BFD_RELOC_390_GLOB_DAT 1842Create GOT entry. 1843@end deffn 1844@deffn {} BFD_RELOC_390_JMP_SLOT 1845Create PLT entry. 1846@end deffn 1847@deffn {} BFD_RELOC_390_RELATIVE 1848Adjust by program base. 1849@end deffn 1850@deffn {} BFD_RELOC_390_GOTPC 185132 bit PC relative offset to GOT. 1852@end deffn 1853@deffn {} BFD_RELOC_390_GOT16 185416 bit GOT offset. 1855@end deffn 1856@deffn {} BFD_RELOC_390_PC16DBL 1857PC relative 16 bit shifted by 1. 1858@end deffn 1859@deffn {} BFD_RELOC_390_PLT16DBL 186016 bit PC rel. PLT shifted by 1. 1861@end deffn 1862@deffn {} BFD_RELOC_390_PC32DBL 1863PC relative 32 bit shifted by 1. 1864@end deffn 1865@deffn {} BFD_RELOC_390_PLT32DBL 186632 bit PC rel. PLT shifted by 1. 1867@end deffn 1868@deffn {} BFD_RELOC_390_GOTPCDBL 186932 bit PC rel. GOT shifted by 1. 1870@end deffn 1871@deffn {} BFD_RELOC_390_GOT64 187264 bit GOT offset. 1873@end deffn 1874@deffn {} BFD_RELOC_390_PLT64 187564 bit PC relative PLT address. 1876@end deffn 1877@deffn {} BFD_RELOC_390_GOTENT 187832 bit rel. offset to GOT entry. 1879@end deffn 1880@deffn {} BFD_RELOC_390_GOTOFF64 188164 bit offset to GOT. 1882@end deffn 1883@deffn {} BFD_RELOC_390_GOTPLT12 188412-bit offset to symbol-entry within GOT, with PLT handling. 1885@end deffn 1886@deffn {} BFD_RELOC_390_GOTPLT16 188716-bit offset to symbol-entry within GOT, with PLT handling. 1888@end deffn 1889@deffn {} BFD_RELOC_390_GOTPLT32 189032-bit offset to symbol-entry within GOT, with PLT handling. 1891@end deffn 1892@deffn {} BFD_RELOC_390_GOTPLT64 189364-bit offset to symbol-entry within GOT, with PLT handling. 1894@end deffn 1895@deffn {} BFD_RELOC_390_GOTPLTENT 189632-bit rel. offset to symbol-entry within GOT, with PLT handling. 1897@end deffn 1898@deffn {} BFD_RELOC_390_PLTOFF16 189916-bit rel. offset from the GOT to a PLT entry. 1900@end deffn 1901@deffn {} BFD_RELOC_390_PLTOFF32 190232-bit rel. offset from the GOT to a PLT entry. 1903@end deffn 1904@deffn {} BFD_RELOC_390_PLTOFF64 190564-bit rel. offset from the GOT to a PLT entry. 1906@end deffn 1907@deffn {} BFD_RELOC_390_TLS_LOAD 1908@deffnx {} BFD_RELOC_390_TLS_GDCALL 1909@deffnx {} BFD_RELOC_390_TLS_LDCALL 1910@deffnx {} BFD_RELOC_390_TLS_GD32 1911@deffnx {} BFD_RELOC_390_TLS_GD64 1912@deffnx {} BFD_RELOC_390_TLS_GOTIE12 1913@deffnx {} BFD_RELOC_390_TLS_GOTIE32 1914@deffnx {} BFD_RELOC_390_TLS_GOTIE64 1915@deffnx {} BFD_RELOC_390_TLS_LDM32 1916@deffnx {} BFD_RELOC_390_TLS_LDM64 1917@deffnx {} BFD_RELOC_390_TLS_IE32 1918@deffnx {} BFD_RELOC_390_TLS_IE64 1919@deffnx {} BFD_RELOC_390_TLS_IEENT 1920@deffnx {} BFD_RELOC_390_TLS_LE32 1921@deffnx {} BFD_RELOC_390_TLS_LE64 1922@deffnx {} BFD_RELOC_390_TLS_LDO32 1923@deffnx {} BFD_RELOC_390_TLS_LDO64 1924@deffnx {} BFD_RELOC_390_TLS_DTPMOD 1925@deffnx {} BFD_RELOC_390_TLS_DTPOFF 1926@deffnx {} BFD_RELOC_390_TLS_TPOFF 1927s390 tls relocations. 1928@end deffn 1929@deffn {} BFD_RELOC_390_20 1930@deffnx {} BFD_RELOC_390_GOT20 1931@deffnx {} BFD_RELOC_390_GOTPLT20 1932@deffnx {} BFD_RELOC_390_TLS_GOTIE20 1933Long displacement extension. 1934@end deffn 1935@deffn {} BFD_RELOC_IP2K_FR9 1936Scenix IP2K - 9-bit register number / data address 1937@end deffn 1938@deffn {} BFD_RELOC_IP2K_BANK 1939Scenix IP2K - 4-bit register/data bank number 1940@end deffn 1941@deffn {} BFD_RELOC_IP2K_ADDR16CJP 1942Scenix IP2K - low 13 bits of instruction word address 1943@end deffn 1944@deffn {} BFD_RELOC_IP2K_PAGE3 1945Scenix IP2K - high 3 bits of instruction word address 1946@end deffn 1947@deffn {} BFD_RELOC_IP2K_LO8DATA 1948@deffnx {} BFD_RELOC_IP2K_HI8DATA 1949@deffnx {} BFD_RELOC_IP2K_EX8DATA 1950Scenix IP2K - ext/low/high 8 bits of data address 1951@end deffn 1952@deffn {} BFD_RELOC_IP2K_LO8INSN 1953@deffnx {} BFD_RELOC_IP2K_HI8INSN 1954Scenix IP2K - low/high 8 bits of instruction word address 1955@end deffn 1956@deffn {} BFD_RELOC_IP2K_PC_SKIP 1957Scenix IP2K - even/odd PC modifier to modify snb pcl.0 1958@end deffn 1959@deffn {} BFD_RELOC_IP2K_TEXT 1960Scenix IP2K - 16 bit word address in text section. 1961@end deffn 1962@deffn {} BFD_RELOC_IP2K_FR_OFFSET 1963Scenix IP2K - 7-bit sp or dp offset 1964@end deffn 1965@deffn {} BFD_RELOC_VPE4KMATH_DATA 1966@deffnx {} BFD_RELOC_VPE4KMATH_INSN 1967Scenix VPE4K coprocessor - data/insn-space addressing 1968@end deffn 1969@deffn {} BFD_RELOC_VTABLE_INHERIT 1970@deffnx {} BFD_RELOC_VTABLE_ENTRY 1971These two relocations are used by the linker to determine which of 1972the entries in a C++ virtual function table are actually used. When 1973the --gc-sections option is given, the linker will zero out the entries 1974that are not used, so that the code for those functions need not be 1975included in the output. 1976 1977VTABLE_INHERIT is a zero-space relocation used to describe to the 1978linker the inheritance tree of a C++ virtual function table. The 1979relocation's symbol should be the parent class' vtable, and the 1980relocation should be located at the child vtable. 1981 1982VTABLE_ENTRY is a zero-space relocation that describes the use of a 1983virtual function table entry. The reloc's symbol should refer to the 1984table of the class mentioned in the code. Off of that base, an offset 1985describes the entry that is being used. For Rela hosts, this offset 1986is stored in the reloc's addend. For Rel hosts, we are forced to put 1987this offset in the reloc's section offset. 1988@end deffn 1989@deffn {} BFD_RELOC_IA64_IMM14 1990@deffnx {} BFD_RELOC_IA64_IMM22 1991@deffnx {} BFD_RELOC_IA64_IMM64 1992@deffnx {} BFD_RELOC_IA64_DIR32MSB 1993@deffnx {} BFD_RELOC_IA64_DIR32LSB 1994@deffnx {} BFD_RELOC_IA64_DIR64MSB 1995@deffnx {} BFD_RELOC_IA64_DIR64LSB 1996@deffnx {} BFD_RELOC_IA64_GPREL22 1997@deffnx {} BFD_RELOC_IA64_GPREL64I 1998@deffnx {} BFD_RELOC_IA64_GPREL32MSB 1999@deffnx {} BFD_RELOC_IA64_GPREL32LSB 2000@deffnx {} BFD_RELOC_IA64_GPREL64MSB 2001@deffnx {} BFD_RELOC_IA64_GPREL64LSB 2002@deffnx {} BFD_RELOC_IA64_LTOFF22 2003@deffnx {} BFD_RELOC_IA64_LTOFF64I 2004@deffnx {} BFD_RELOC_IA64_PLTOFF22 2005@deffnx {} BFD_RELOC_IA64_PLTOFF64I 2006@deffnx {} BFD_RELOC_IA64_PLTOFF64MSB 2007@deffnx {} BFD_RELOC_IA64_PLTOFF64LSB 2008@deffnx {} BFD_RELOC_IA64_FPTR64I 2009@deffnx {} BFD_RELOC_IA64_FPTR32MSB 2010@deffnx {} BFD_RELOC_IA64_FPTR32LSB 2011@deffnx {} BFD_RELOC_IA64_FPTR64MSB 2012@deffnx {} BFD_RELOC_IA64_FPTR64LSB 2013@deffnx {} BFD_RELOC_IA64_PCREL21B 2014@deffnx {} BFD_RELOC_IA64_PCREL21BI 2015@deffnx {} BFD_RELOC_IA64_PCREL21M 2016@deffnx {} BFD_RELOC_IA64_PCREL21F 2017@deffnx {} BFD_RELOC_IA64_PCREL22 2018@deffnx {} BFD_RELOC_IA64_PCREL60B 2019@deffnx {} BFD_RELOC_IA64_PCREL64I 2020@deffnx {} BFD_RELOC_IA64_PCREL32MSB 2021@deffnx {} BFD_RELOC_IA64_PCREL32LSB 2022@deffnx {} BFD_RELOC_IA64_PCREL64MSB 2023@deffnx {} BFD_RELOC_IA64_PCREL64LSB 2024@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR22 2025@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64I 2026@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR32MSB 2027@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR32LSB 2028@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64MSB 2029@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64LSB 2030@deffnx {} BFD_RELOC_IA64_SEGREL32MSB 2031@deffnx {} BFD_RELOC_IA64_SEGREL32LSB 2032@deffnx {} BFD_RELOC_IA64_SEGREL64MSB 2033@deffnx {} BFD_RELOC_IA64_SEGREL64LSB 2034@deffnx {} BFD_RELOC_IA64_SECREL32MSB 2035@deffnx {} BFD_RELOC_IA64_SECREL32LSB 2036@deffnx {} BFD_RELOC_IA64_SECREL64MSB 2037@deffnx {} BFD_RELOC_IA64_SECREL64LSB 2038@deffnx {} BFD_RELOC_IA64_REL32MSB 2039@deffnx {} BFD_RELOC_IA64_REL32LSB 2040@deffnx {} BFD_RELOC_IA64_REL64MSB 2041@deffnx {} BFD_RELOC_IA64_REL64LSB 2042@deffnx {} BFD_RELOC_IA64_LTV32MSB 2043@deffnx {} BFD_RELOC_IA64_LTV32LSB 2044@deffnx {} BFD_RELOC_IA64_LTV64MSB 2045@deffnx {} BFD_RELOC_IA64_LTV64LSB 2046@deffnx {} BFD_RELOC_IA64_IPLTMSB 2047@deffnx {} BFD_RELOC_IA64_IPLTLSB 2048@deffnx {} BFD_RELOC_IA64_COPY 2049@deffnx {} BFD_RELOC_IA64_LTOFF22X 2050@deffnx {} BFD_RELOC_IA64_LDXMOV 2051@deffnx {} BFD_RELOC_IA64_TPREL14 2052@deffnx {} BFD_RELOC_IA64_TPREL22 2053@deffnx {} BFD_RELOC_IA64_TPREL64I 2054@deffnx {} BFD_RELOC_IA64_TPREL64MSB 2055@deffnx {} BFD_RELOC_IA64_TPREL64LSB 2056@deffnx {} BFD_RELOC_IA64_LTOFF_TPREL22 2057@deffnx {} BFD_RELOC_IA64_DTPMOD64MSB 2058@deffnx {} BFD_RELOC_IA64_DTPMOD64LSB 2059@deffnx {} BFD_RELOC_IA64_LTOFF_DTPMOD22 2060@deffnx {} BFD_RELOC_IA64_DTPREL14 2061@deffnx {} BFD_RELOC_IA64_DTPREL22 2062@deffnx {} BFD_RELOC_IA64_DTPREL64I 2063@deffnx {} BFD_RELOC_IA64_DTPREL32MSB 2064@deffnx {} BFD_RELOC_IA64_DTPREL32LSB 2065@deffnx {} BFD_RELOC_IA64_DTPREL64MSB 2066@deffnx {} BFD_RELOC_IA64_DTPREL64LSB 2067@deffnx {} BFD_RELOC_IA64_LTOFF_DTPREL22 2068Intel IA64 Relocations. 2069@end deffn 2070@deffn {} BFD_RELOC_M68HC11_HI8 2071Motorola 68HC11 reloc. 2072This is the 8 bit high part of an absolute address. 2073@end deffn 2074@deffn {} BFD_RELOC_M68HC11_LO8 2075Motorola 68HC11 reloc. 2076This is the 8 bit low part of an absolute address. 2077@end deffn 2078@deffn {} BFD_RELOC_M68HC11_3B 2079Motorola 68HC11 reloc. 2080This is the 3 bit of a value. 2081@end deffn 2082@deffn {} BFD_RELOC_M68HC11_RL_JUMP 2083Motorola 68HC11 reloc. 2084This reloc marks the beginning of a jump/call instruction. 2085It is used for linker relaxation to correctly identify beginning 2086of instruction and change some branches to use PC-relative 2087addressing mode. 2088@end deffn 2089@deffn {} BFD_RELOC_M68HC11_RL_GROUP 2090Motorola 68HC11 reloc. 2091This reloc marks a group of several instructions that gcc generates 2092and for which the linker relaxation pass can modify and/or remove 2093some of them. 2094@end deffn 2095@deffn {} BFD_RELOC_M68HC11_LO16 2096Motorola 68HC11 reloc. 2097This is the 16-bit lower part of an address. It is used for 'call' 2098instruction to specify the symbol address without any special 2099transformation (due to memory bank window). 2100@end deffn 2101@deffn {} BFD_RELOC_M68HC11_PAGE 2102Motorola 68HC11 reloc. 2103This is a 8-bit reloc that specifies the page number of an address. 2104It is used by 'call' instruction to specify the page number of 2105the symbol. 2106@end deffn 2107@deffn {} BFD_RELOC_M68HC11_24 2108Motorola 68HC11 reloc. 2109This is a 24-bit reloc that represents the address with a 16-bit 2110value and a 8-bit page number. The symbol address is transformed 2111to follow the 16K memory bank of 68HC12 (seen as mapped in the window). 2112@end deffn 2113@deffn {} BFD_RELOC_M68HC12_5B 2114Motorola 68HC12 reloc. 2115This is the 5 bits of a value. 2116@end deffn 2117@deffn {} BFD_RELOC_16C_NUM08 2118@deffnx {} BFD_RELOC_16C_NUM08_C 2119@deffnx {} BFD_RELOC_16C_NUM16 2120@deffnx {} BFD_RELOC_16C_NUM16_C 2121@deffnx {} BFD_RELOC_16C_NUM32 2122@deffnx {} BFD_RELOC_16C_NUM32_C 2123@deffnx {} BFD_RELOC_16C_DISP04 2124@deffnx {} BFD_RELOC_16C_DISP04_C 2125@deffnx {} BFD_RELOC_16C_DISP08 2126@deffnx {} BFD_RELOC_16C_DISP08_C 2127@deffnx {} BFD_RELOC_16C_DISP16 2128@deffnx {} BFD_RELOC_16C_DISP16_C 2129@deffnx {} BFD_RELOC_16C_DISP24 2130@deffnx {} BFD_RELOC_16C_DISP24_C 2131@deffnx {} BFD_RELOC_16C_DISP24a 2132@deffnx {} BFD_RELOC_16C_DISP24a_C 2133@deffnx {} BFD_RELOC_16C_REG04 2134@deffnx {} BFD_RELOC_16C_REG04_C 2135@deffnx {} BFD_RELOC_16C_REG04a 2136@deffnx {} BFD_RELOC_16C_REG04a_C 2137@deffnx {} BFD_RELOC_16C_REG14 2138@deffnx {} BFD_RELOC_16C_REG14_C 2139@deffnx {} BFD_RELOC_16C_REG16 2140@deffnx {} BFD_RELOC_16C_REG16_C 2141@deffnx {} BFD_RELOC_16C_REG20 2142@deffnx {} BFD_RELOC_16C_REG20_C 2143@deffnx {} BFD_RELOC_16C_ABS20 2144@deffnx {} BFD_RELOC_16C_ABS20_C 2145@deffnx {} BFD_RELOC_16C_ABS24 2146@deffnx {} BFD_RELOC_16C_ABS24_C 2147@deffnx {} BFD_RELOC_16C_IMM04 2148@deffnx {} BFD_RELOC_16C_IMM04_C 2149@deffnx {} BFD_RELOC_16C_IMM16 2150@deffnx {} BFD_RELOC_16C_IMM16_C 2151@deffnx {} BFD_RELOC_16C_IMM20 2152@deffnx {} BFD_RELOC_16C_IMM20_C 2153@deffnx {} BFD_RELOC_16C_IMM24 2154@deffnx {} BFD_RELOC_16C_IMM24_C 2155@deffnx {} BFD_RELOC_16C_IMM32 2156@deffnx {} BFD_RELOC_16C_IMM32_C 2157NS CR16C Relocations. 2158@end deffn 2159@deffn {} BFD_RELOC_CRX_REL4 2160@deffnx {} BFD_RELOC_CRX_REL8 2161@deffnx {} BFD_RELOC_CRX_REL8_CMP 2162@deffnx {} BFD_RELOC_CRX_REL16 2163@deffnx {} BFD_RELOC_CRX_REL24 2164@deffnx {} BFD_RELOC_CRX_REL32 2165@deffnx {} BFD_RELOC_CRX_REGREL12 2166@deffnx {} BFD_RELOC_CRX_REGREL22 2167@deffnx {} BFD_RELOC_CRX_REGREL28 2168@deffnx {} BFD_RELOC_CRX_REGREL32 2169@deffnx {} BFD_RELOC_CRX_ABS16 2170@deffnx {} BFD_RELOC_CRX_ABS32 2171@deffnx {} BFD_RELOC_CRX_NUM8 2172@deffnx {} BFD_RELOC_CRX_NUM16 2173@deffnx {} BFD_RELOC_CRX_NUM32 2174@deffnx {} BFD_RELOC_CRX_IMM16 2175@deffnx {} BFD_RELOC_CRX_IMM32 2176@deffnx {} BFD_RELOC_CRX_SWITCH8 2177@deffnx {} BFD_RELOC_CRX_SWITCH16 2178@deffnx {} BFD_RELOC_CRX_SWITCH32 2179NS CRX Relocations. 2180@end deffn 2181@deffn {} BFD_RELOC_CRIS_BDISP8 2182@deffnx {} BFD_RELOC_CRIS_UNSIGNED_5 2183@deffnx {} BFD_RELOC_CRIS_SIGNED_6 2184@deffnx {} BFD_RELOC_CRIS_UNSIGNED_6 2185@deffnx {} BFD_RELOC_CRIS_SIGNED_8 2186@deffnx {} BFD_RELOC_CRIS_UNSIGNED_8 2187@deffnx {} BFD_RELOC_CRIS_SIGNED_16 2188@deffnx {} BFD_RELOC_CRIS_UNSIGNED_16 2189@deffnx {} BFD_RELOC_CRIS_LAPCQ_OFFSET 2190@deffnx {} BFD_RELOC_CRIS_UNSIGNED_4 2191These relocs are only used within the CRIS assembler. They are not 2192(at present) written to any object files. 2193@end deffn 2194@deffn {} BFD_RELOC_CRIS_COPY 2195@deffnx {} BFD_RELOC_CRIS_GLOB_DAT 2196@deffnx {} BFD_RELOC_CRIS_JUMP_SLOT 2197@deffnx {} BFD_RELOC_CRIS_RELATIVE 2198Relocs used in ELF shared libraries for CRIS. 2199@end deffn 2200@deffn {} BFD_RELOC_CRIS_32_GOT 220132-bit offset to symbol-entry within GOT. 2202@end deffn 2203@deffn {} BFD_RELOC_CRIS_16_GOT 220416-bit offset to symbol-entry within GOT. 2205@end deffn 2206@deffn {} BFD_RELOC_CRIS_32_GOTPLT 220732-bit offset to symbol-entry within GOT, with PLT handling. 2208@end deffn 2209@deffn {} BFD_RELOC_CRIS_16_GOTPLT 221016-bit offset to symbol-entry within GOT, with PLT handling. 2211@end deffn 2212@deffn {} BFD_RELOC_CRIS_32_GOTREL 221332-bit offset to symbol, relative to GOT. 2214@end deffn 2215@deffn {} BFD_RELOC_CRIS_32_PLT_GOTREL 221632-bit offset to symbol with PLT entry, relative to GOT. 2217@end deffn 2218@deffn {} BFD_RELOC_CRIS_32_PLT_PCREL 221932-bit offset to symbol with PLT entry, relative to this relocation. 2220@end deffn 2221@deffn {} BFD_RELOC_860_COPY 2222@deffnx {} BFD_RELOC_860_GLOB_DAT 2223@deffnx {} BFD_RELOC_860_JUMP_SLOT 2224@deffnx {} BFD_RELOC_860_RELATIVE 2225@deffnx {} BFD_RELOC_860_PC26 2226@deffnx {} BFD_RELOC_860_PLT26 2227@deffnx {} BFD_RELOC_860_PC16 2228@deffnx {} BFD_RELOC_860_LOW0 2229@deffnx {} BFD_RELOC_860_SPLIT0 2230@deffnx {} BFD_RELOC_860_LOW1 2231@deffnx {} BFD_RELOC_860_SPLIT1 2232@deffnx {} BFD_RELOC_860_LOW2 2233@deffnx {} BFD_RELOC_860_SPLIT2 2234@deffnx {} BFD_RELOC_860_LOW3 2235@deffnx {} BFD_RELOC_860_LOGOT0 2236@deffnx {} BFD_RELOC_860_SPGOT0 2237@deffnx {} BFD_RELOC_860_LOGOT1 2238@deffnx {} BFD_RELOC_860_SPGOT1 2239@deffnx {} BFD_RELOC_860_LOGOTOFF0 2240@deffnx {} BFD_RELOC_860_SPGOTOFF0 2241@deffnx {} BFD_RELOC_860_LOGOTOFF1 2242@deffnx {} BFD_RELOC_860_SPGOTOFF1 2243@deffnx {} BFD_RELOC_860_LOGOTOFF2 2244@deffnx {} BFD_RELOC_860_LOGOTOFF3 2245@deffnx {} BFD_RELOC_860_LOPC 2246@deffnx {} BFD_RELOC_860_HIGHADJ 2247@deffnx {} BFD_RELOC_860_HAGOT 2248@deffnx {} BFD_RELOC_860_HAGOTOFF 2249@deffnx {} BFD_RELOC_860_HAPC 2250@deffnx {} BFD_RELOC_860_HIGH 2251@deffnx {} BFD_RELOC_860_HIGOT 2252@deffnx {} BFD_RELOC_860_HIGOTOFF 2253Intel i860 Relocations. 2254@end deffn 2255@deffn {} BFD_RELOC_OPENRISC_ABS_26 2256@deffnx {} BFD_RELOC_OPENRISC_REL_26 2257OpenRISC Relocations. 2258@end deffn 2259@deffn {} BFD_RELOC_H8_DIR16A8 2260@deffnx {} BFD_RELOC_H8_DIR16R8 2261@deffnx {} BFD_RELOC_H8_DIR24A8 2262@deffnx {} BFD_RELOC_H8_DIR24R8 2263@deffnx {} BFD_RELOC_H8_DIR32A16 2264H8 elf Relocations. 2265@end deffn 2266@deffn {} BFD_RELOC_XSTORMY16_REL_12 2267@deffnx {} BFD_RELOC_XSTORMY16_12 2268@deffnx {} BFD_RELOC_XSTORMY16_24 2269@deffnx {} BFD_RELOC_XSTORMY16_FPTR16 2270Sony Xstormy16 Relocations. 2271@end deffn 2272@deffn {} BFD_RELOC_XC16X_PAG 2273@deffnx {} BFD_RELOC_XC16X_POF 2274@deffnx {} BFD_RELOC_XC16X_SEG 2275@deffnx {} BFD_RELOC_XC16X_SOF 2276Infineon Relocations. 2277@end deffn 2278@deffn {} BFD_RELOC_VAX_GLOB_DAT 2279@deffnx {} BFD_RELOC_VAX_JMP_SLOT 2280@deffnx {} BFD_RELOC_VAX_RELATIVE 2281Relocations used by VAX ELF. 2282@end deffn 2283@deffn {} BFD_RELOC_MT_PC16 2284Morpho MT - 16 bit immediate relocation. 2285@end deffn 2286@deffn {} BFD_RELOC_MT_HI16 2287Morpho MT - Hi 16 bits of an address. 2288@end deffn 2289@deffn {} BFD_RELOC_MT_LO16 2290Morpho MT - Low 16 bits of an address. 2291@end deffn 2292@deffn {} BFD_RELOC_MT_GNU_VTINHERIT 2293Morpho MT - Used to tell the linker which vtable entries are used. 2294@end deffn 2295@deffn {} BFD_RELOC_MT_GNU_VTENTRY 2296Morpho MT - Used to tell the linker which vtable entries are used. 2297@end deffn 2298@deffn {} BFD_RELOC_MT_PCINSN8 2299Morpho MT - 8 bit immediate relocation. 2300@end deffn 2301@deffn {} BFD_RELOC_MSP430_10_PCREL 2302@deffnx {} BFD_RELOC_MSP430_16_PCREL 2303@deffnx {} BFD_RELOC_MSP430_16 2304@deffnx {} BFD_RELOC_MSP430_16_PCREL_BYTE 2305@deffnx {} BFD_RELOC_MSP430_16_BYTE 2306@deffnx {} BFD_RELOC_MSP430_2X_PCREL 2307@deffnx {} BFD_RELOC_MSP430_RL_PCREL 2308msp430 specific relocation codes 2309@end deffn 2310@deffn {} BFD_RELOC_IQ2000_OFFSET_16 2311@deffnx {} BFD_RELOC_IQ2000_OFFSET_21 2312@deffnx {} BFD_RELOC_IQ2000_UHI16 2313IQ2000 Relocations. 2314@end deffn 2315@deffn {} BFD_RELOC_XTENSA_RTLD 2316Special Xtensa relocation used only by PLT entries in ELF shared 2317objects to indicate that the runtime linker should set the value 2318to one of its own internal functions or data structures. 2319@end deffn 2320@deffn {} BFD_RELOC_XTENSA_GLOB_DAT 2321@deffnx {} BFD_RELOC_XTENSA_JMP_SLOT 2322@deffnx {} BFD_RELOC_XTENSA_RELATIVE 2323Xtensa relocations for ELF shared objects. 2324@end deffn 2325@deffn {} BFD_RELOC_XTENSA_PLT 2326Xtensa relocation used in ELF object files for symbols that may require 2327PLT entries. Otherwise, this is just a generic 32-bit relocation. 2328@end deffn 2329@deffn {} BFD_RELOC_XTENSA_DIFF8 2330@deffnx {} BFD_RELOC_XTENSA_DIFF16 2331@deffnx {} BFD_RELOC_XTENSA_DIFF32 2332Xtensa relocations to mark the difference of two local symbols. 2333These are only needed to support linker relaxation and can be ignored 2334when not relaxing. The field is set to the value of the difference 2335assuming no relaxation. The relocation encodes the position of the 2336first symbol so the linker can determine whether to adjust the field 2337value. 2338@end deffn 2339@deffn {} BFD_RELOC_XTENSA_SLOT0_OP 2340@deffnx {} BFD_RELOC_XTENSA_SLOT1_OP 2341@deffnx {} BFD_RELOC_XTENSA_SLOT2_OP 2342@deffnx {} BFD_RELOC_XTENSA_SLOT3_OP 2343@deffnx {} BFD_RELOC_XTENSA_SLOT4_OP 2344@deffnx {} BFD_RELOC_XTENSA_SLOT5_OP 2345@deffnx {} BFD_RELOC_XTENSA_SLOT6_OP 2346@deffnx {} BFD_RELOC_XTENSA_SLOT7_OP 2347@deffnx {} BFD_RELOC_XTENSA_SLOT8_OP 2348@deffnx {} BFD_RELOC_XTENSA_SLOT9_OP 2349@deffnx {} BFD_RELOC_XTENSA_SLOT10_OP 2350@deffnx {} BFD_RELOC_XTENSA_SLOT11_OP 2351@deffnx {} BFD_RELOC_XTENSA_SLOT12_OP 2352@deffnx {} BFD_RELOC_XTENSA_SLOT13_OP 2353@deffnx {} BFD_RELOC_XTENSA_SLOT14_OP 2354Generic Xtensa relocations for instruction operands. Only the slot 2355number is encoded in the relocation. The relocation applies to the 2356last PC-relative immediate operand, or if there are no PC-relative 2357immediates, to the last immediate operand. 2358@end deffn 2359@deffn {} BFD_RELOC_XTENSA_SLOT0_ALT 2360@deffnx {} BFD_RELOC_XTENSA_SLOT1_ALT 2361@deffnx {} BFD_RELOC_XTENSA_SLOT2_ALT 2362@deffnx {} BFD_RELOC_XTENSA_SLOT3_ALT 2363@deffnx {} BFD_RELOC_XTENSA_SLOT4_ALT 2364@deffnx {} BFD_RELOC_XTENSA_SLOT5_ALT 2365@deffnx {} BFD_RELOC_XTENSA_SLOT6_ALT 2366@deffnx {} BFD_RELOC_XTENSA_SLOT7_ALT 2367@deffnx {} BFD_RELOC_XTENSA_SLOT8_ALT 2368@deffnx {} BFD_RELOC_XTENSA_SLOT9_ALT 2369@deffnx {} BFD_RELOC_XTENSA_SLOT10_ALT 2370@deffnx {} BFD_RELOC_XTENSA_SLOT11_ALT 2371@deffnx {} BFD_RELOC_XTENSA_SLOT12_ALT 2372@deffnx {} BFD_RELOC_XTENSA_SLOT13_ALT 2373@deffnx {} BFD_RELOC_XTENSA_SLOT14_ALT 2374Alternate Xtensa relocations. Only the slot is encoded in the 2375relocation. The meaning of these relocations is opcode-specific. 2376@end deffn 2377@deffn {} BFD_RELOC_XTENSA_OP0 2378@deffnx {} BFD_RELOC_XTENSA_OP1 2379@deffnx {} BFD_RELOC_XTENSA_OP2 2380Xtensa relocations for backward compatibility. These have all been 2381replaced by BFD_RELOC_XTENSA_SLOT0_OP. 2382@end deffn 2383@deffn {} BFD_RELOC_XTENSA_ASM_EXPAND 2384Xtensa relocation to mark that the assembler expanded the 2385instructions from an original target. The expansion size is 2386encoded in the reloc size. 2387@end deffn 2388@deffn {} BFD_RELOC_XTENSA_ASM_SIMPLIFY 2389Xtensa relocation to mark that the linker should simplify 2390assembler-expanded instructions. This is commonly used 2391internally by the linker after analysis of a 2392BFD_RELOC_XTENSA_ASM_EXPAND. 2393@end deffn 2394@deffn {} BFD_RELOC_Z80_DISP8 23958 bit signed offset in (ix+d) or (iy+d). 2396@end deffn 2397@deffn {} BFD_RELOC_Z8K_DISP7 2398DJNZ offset. 2399@end deffn 2400@deffn {} BFD_RELOC_Z8K_CALLR 2401CALR offset. 2402@end deffn 2403@deffn {} BFD_RELOC_Z8K_IMM4L 24044 bit value. 2405@end deffn 2406 2407@example 2408 2409typedef enum bfd_reloc_code_real bfd_reloc_code_real_type; 2410@end example 2411@findex bfd_reloc_type_lookup 2412@subsubsection @code{bfd_reloc_type_lookup} 2413@strong{Synopsis} 2414@example 2415reloc_howto_type *bfd_reloc_type_lookup 2416 (bfd *abfd, bfd_reloc_code_real_type code); 2417@end example 2418@strong{Description}@* 2419Return a pointer to a howto structure which, when 2420invoked, will perform the relocation @var{code} on data from the 2421architecture noted. 2422 2423@findex bfd_default_reloc_type_lookup 2424@subsubsection @code{bfd_default_reloc_type_lookup} 2425@strong{Synopsis} 2426@example 2427reloc_howto_type *bfd_default_reloc_type_lookup 2428 (bfd *abfd, bfd_reloc_code_real_type code); 2429@end example 2430@strong{Description}@* 2431Provides a default relocation lookup routine for any architecture. 2432 2433@findex bfd_get_reloc_code_name 2434@subsubsection @code{bfd_get_reloc_code_name} 2435@strong{Synopsis} 2436@example 2437const char *bfd_get_reloc_code_name (bfd_reloc_code_real_type code); 2438@end example 2439@strong{Description}@* 2440Provides a printable name for the supplied relocation code. 2441Useful mainly for printing error messages. 2442 2443@findex bfd_generic_relax_section 2444@subsubsection @code{bfd_generic_relax_section} 2445@strong{Synopsis} 2446@example 2447bfd_boolean bfd_generic_relax_section 2448 (bfd *abfd, 2449 asection *section, 2450 struct bfd_link_info *, 2451 bfd_boolean *); 2452@end example 2453@strong{Description}@* 2454Provides default handling for relaxing for back ends which 2455don't do relaxing. 2456 2457@findex bfd_generic_gc_sections 2458@subsubsection @code{bfd_generic_gc_sections} 2459@strong{Synopsis} 2460@example 2461bfd_boolean bfd_generic_gc_sections 2462 (bfd *, struct bfd_link_info *); 2463@end example 2464@strong{Description}@* 2465Provides default handling for relaxing for back ends which 2466don't do section gc -- i.e., does nothing. 2467 2468@findex bfd_generic_merge_sections 2469@subsubsection @code{bfd_generic_merge_sections} 2470@strong{Synopsis} 2471@example 2472bfd_boolean bfd_generic_merge_sections 2473 (bfd *, struct bfd_link_info *); 2474@end example 2475@strong{Description}@* 2476Provides default handling for SEC_MERGE section merging for back ends 2477which don't have SEC_MERGE support -- i.e., does nothing. 2478 2479@findex bfd_generic_get_relocated_section_contents 2480@subsubsection @code{bfd_generic_get_relocated_section_contents} 2481@strong{Synopsis} 2482@example 2483bfd_byte *bfd_generic_get_relocated_section_contents 2484 (bfd *abfd, 2485 struct bfd_link_info *link_info, 2486 struct bfd_link_order *link_order, 2487 bfd_byte *data, 2488 bfd_boolean relocatable, 2489 asymbol **symbols); 2490@end example 2491@strong{Description}@* 2492Provides default handling of relocation effort for back ends 2493which can't be bothered to do it efficiently. 2494 2495