1//===- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions -------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "ARMBaseInstrInfo.h"
10#include "ARMFeatures.h"
11#include "MCTargetDesc/ARMAddressingModes.h"
12#include "MCTargetDesc/ARMBaseInfo.h"
13#include "MCTargetDesc/ARMInstPrinter.h"
14#include "MCTargetDesc/ARMMCExpr.h"
15#include "MCTargetDesc/ARMMCTargetDesc.h"
16#include "TargetInfo/ARMTargetInfo.h"
17#include "Utils/ARMBaseInfo.h"
18#include "llvm/ADT/APFloat.h"
19#include "llvm/ADT/APInt.h"
20#include "llvm/ADT/STLExtras.h"
21#include "llvm/ADT/SmallSet.h"
22#include "llvm/ADT/SmallVector.h"
23#include "llvm/ADT/StringMap.h"
24#include "llvm/ADT/StringRef.h"
25#include "llvm/ADT/StringSet.h"
26#include "llvm/ADT/StringSwitch.h"
27#include "llvm/ADT/Triple.h"
28#include "llvm/ADT/Twine.h"
29#include "llvm/MC/MCContext.h"
30#include "llvm/MC/MCExpr.h"
31#include "llvm/MC/MCInst.h"
32#include "llvm/MC/MCInstrDesc.h"
33#include "llvm/MC/MCInstrInfo.h"
34#include "llvm/MC/MCParser/MCAsmLexer.h"
35#include "llvm/MC/MCParser/MCAsmParser.h"
36#include "llvm/MC/MCParser/MCAsmParserExtension.h"
37#include "llvm/MC/MCParser/MCAsmParserUtils.h"
38#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
39#include "llvm/MC/MCParser/MCTargetAsmParser.h"
40#include "llvm/MC/MCRegisterInfo.h"
41#include "llvm/MC/MCSection.h"
42#include "llvm/MC/MCStreamer.h"
43#include "llvm/MC/MCSubtargetInfo.h"
44#include "llvm/MC/MCSymbol.h"
45#include "llvm/MC/SubtargetFeature.h"
46#include "llvm/MC/TargetRegistry.h"
47#include "llvm/Support/ARMBuildAttributes.h"
48#include "llvm/Support/ARMEHABI.h"
49#include "llvm/Support/Casting.h"
50#include "llvm/Support/CommandLine.h"
51#include "llvm/Support/Compiler.h"
52#include "llvm/Support/ErrorHandling.h"
53#include "llvm/Support/MathExtras.h"
54#include "llvm/Support/SMLoc.h"
55#include "llvm/Support/TargetParser.h"
56#include "llvm/Support/raw_ostream.h"
57#include <algorithm>
58#include <cassert>
59#include <cstddef>
60#include <cstdint>
61#include <iterator>
62#include <limits>
63#include <memory>
64#include <string>
65#include <utility>
66#include <vector>
67
68#define DEBUG_TYPE "asm-parser"
69
70using namespace llvm;
71
72namespace llvm {
73extern const MCInstrDesc ARMInsts[];
74} // end namespace llvm
75
76namespace {
77
78enum class ImplicitItModeTy { Always, Never, ARMOnly, ThumbOnly };
79
80static cl::opt<ImplicitItModeTy> ImplicitItMode(
81    "arm-implicit-it", cl::init(ImplicitItModeTy::ARMOnly),
82    cl::desc("Allow conditional instructions outdside of an IT block"),
83    cl::values(clEnumValN(ImplicitItModeTy::Always, "always",
84                          "Accept in both ISAs, emit implicit ITs in Thumb"),
85               clEnumValN(ImplicitItModeTy::Never, "never",
86                          "Warn in ARM, reject in Thumb"),
87               clEnumValN(ImplicitItModeTy::ARMOnly, "arm",
88                          "Accept in ARM, reject in Thumb"),
89               clEnumValN(ImplicitItModeTy::ThumbOnly, "thumb",
90                          "Warn in ARM, emit implicit ITs in Thumb")));
91
92static cl::opt<bool> AddBuildAttributes("arm-add-build-attributes",
93                                        cl::init(false));
94
95enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
96
97static inline unsigned extractITMaskBit(unsigned Mask, unsigned Position) {
98  // Position==0 means we're not in an IT block at all. Position==1
99  // means we want the first state bit, which is always 0 (Then).
100  // Position==2 means we want the second state bit, stored at bit 3
101  // of Mask, and so on downwards. So (5 - Position) will shift the
102  // right bit down to bit 0, including the always-0 bit at bit 4 for
103  // the mandatory initial Then.
104  return (Mask >> (5 - Position) & 1);
105}
106
107class UnwindContext {
108  using Locs = SmallVector<SMLoc, 4>;
109
110  MCAsmParser &Parser;
111  Locs FnStartLocs;
112  Locs CantUnwindLocs;
113  Locs PersonalityLocs;
114  Locs PersonalityIndexLocs;
115  Locs HandlerDataLocs;
116  int FPReg;
117
118public:
119  UnwindContext(MCAsmParser &P) : Parser(P), FPReg(ARM::SP) {}
120
121  bool hasFnStart() const { return !FnStartLocs.empty(); }
122  bool cantUnwind() const { return !CantUnwindLocs.empty(); }
123  bool hasHandlerData() const { return !HandlerDataLocs.empty(); }
124
125  bool hasPersonality() const {
126    return !(PersonalityLocs.empty() && PersonalityIndexLocs.empty());
127  }
128
129  void recordFnStart(SMLoc L) { FnStartLocs.push_back(L); }
130  void recordCantUnwind(SMLoc L) { CantUnwindLocs.push_back(L); }
131  void recordPersonality(SMLoc L) { PersonalityLocs.push_back(L); }
132  void recordHandlerData(SMLoc L) { HandlerDataLocs.push_back(L); }
133  void recordPersonalityIndex(SMLoc L) { PersonalityIndexLocs.push_back(L); }
134
135  void saveFPReg(int Reg) { FPReg = Reg; }
136  int getFPReg() const { return FPReg; }
137
138  void emitFnStartLocNotes() const {
139    for (const SMLoc &Loc : FnStartLocs)
140      Parser.Note(Loc, ".fnstart was specified here");
141  }
142
143  void emitCantUnwindLocNotes() const {
144    for (const SMLoc &Loc : CantUnwindLocs)
145      Parser.Note(Loc, ".cantunwind was specified here");
146  }
147
148  void emitHandlerDataLocNotes() const {
149    for (const SMLoc &Loc : HandlerDataLocs)
150      Parser.Note(Loc, ".handlerdata was specified here");
151  }
152
153  void emitPersonalityLocNotes() const {
154    for (Locs::const_iterator PI = PersonalityLocs.begin(),
155                              PE = PersonalityLocs.end(),
156                              PII = PersonalityIndexLocs.begin(),
157                              PIE = PersonalityIndexLocs.end();
158         PI != PE || PII != PIE;) {
159      if (PI != PE && (PII == PIE || PI->getPointer() < PII->getPointer()))
160        Parser.Note(*PI++, ".personality was specified here");
161      else if (PII != PIE && (PI == PE || PII->getPointer() < PI->getPointer()))
162        Parser.Note(*PII++, ".personalityindex was specified here");
163      else
164        llvm_unreachable(".personality and .personalityindex cannot be "
165                         "at the same location");
166    }
167  }
168
169  void reset() {
170    FnStartLocs = Locs();
171    CantUnwindLocs = Locs();
172    PersonalityLocs = Locs();
173    HandlerDataLocs = Locs();
174    PersonalityIndexLocs = Locs();
175    FPReg = ARM::SP;
176  }
177};
178
179// Various sets of ARM instruction mnemonics which are used by the asm parser
180class ARMMnemonicSets {
181  StringSet<> CDE;
182  StringSet<> CDEWithVPTSuffix;
183public:
184  ARMMnemonicSets(const MCSubtargetInfo &STI);
185
186  /// Returns true iff a given mnemonic is a CDE instruction
187  bool isCDEInstr(StringRef Mnemonic) {
188    // Quick check before searching the set
189    if (!Mnemonic.startswith("cx") && !Mnemonic.startswith("vcx"))
190      return false;
191    return CDE.count(Mnemonic);
192  }
193
194  /// Returns true iff a given mnemonic is a VPT-predicable CDE instruction
195  /// (possibly with a predication suffix "e" or "t")
196  bool isVPTPredicableCDEInstr(StringRef Mnemonic) {
197    if (!Mnemonic.startswith("vcx"))
198      return false;
199    return CDEWithVPTSuffix.count(Mnemonic);
200  }
201
202  /// Returns true iff a given mnemonic is an IT-predicable CDE instruction
203  /// (possibly with a condition suffix)
204  bool isITPredicableCDEInstr(StringRef Mnemonic) {
205    if (!Mnemonic.startswith("cx"))
206      return false;
207    return Mnemonic.startswith("cx1a") || Mnemonic.startswith("cx1da") ||
208           Mnemonic.startswith("cx2a") || Mnemonic.startswith("cx2da") ||
209           Mnemonic.startswith("cx3a") || Mnemonic.startswith("cx3da");
210  }
211
212  /// Return true iff a given mnemonic is an integer CDE instruction with
213  /// dual-register destination
214  bool isCDEDualRegInstr(StringRef Mnemonic) {
215    if (!Mnemonic.startswith("cx"))
216      return false;
217    return Mnemonic == "cx1d" || Mnemonic == "cx1da" ||
218           Mnemonic == "cx2d" || Mnemonic == "cx2da" ||
219           Mnemonic == "cx3d" || Mnemonic == "cx3da";
220  }
221};
222
223ARMMnemonicSets::ARMMnemonicSets(const MCSubtargetInfo &STI) {
224  for (StringRef Mnemonic: { "cx1", "cx1a", "cx1d", "cx1da",
225                             "cx2", "cx2a", "cx2d", "cx2da",
226                             "cx3", "cx3a", "cx3d", "cx3da", })
227    CDE.insert(Mnemonic);
228  for (StringRef Mnemonic :
229       {"vcx1", "vcx1a", "vcx2", "vcx2a", "vcx3", "vcx3a"}) {
230    CDE.insert(Mnemonic);
231    CDEWithVPTSuffix.insert(Mnemonic);
232    CDEWithVPTSuffix.insert(std::string(Mnemonic) + "t");
233    CDEWithVPTSuffix.insert(std::string(Mnemonic) + "e");
234  }
235}
236
237class ARMAsmParser : public MCTargetAsmParser {
238  const MCRegisterInfo *MRI;
239  UnwindContext UC;
240  ARMMnemonicSets MS;
241
242  ARMTargetStreamer &getTargetStreamer() {
243    assert(getParser().getStreamer().getTargetStreamer() &&
244           "do not have a target streamer");
245    MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
246    return static_cast<ARMTargetStreamer &>(TS);
247  }
248
249  // Map of register aliases registers via the .req directive.
250  StringMap<unsigned> RegisterReqs;
251
252  bool NextSymbolIsThumb;
253
254  bool useImplicitITThumb() const {
255    return ImplicitItMode == ImplicitItModeTy::Always ||
256           ImplicitItMode == ImplicitItModeTy::ThumbOnly;
257  }
258
259  bool useImplicitITARM() const {
260    return ImplicitItMode == ImplicitItModeTy::Always ||
261           ImplicitItMode == ImplicitItModeTy::ARMOnly;
262  }
263
264  struct {
265    ARMCC::CondCodes Cond;    // Condition for IT block.
266    unsigned Mask:4;          // Condition mask for instructions.
267                              // Starting at first 1 (from lsb).
268                              //   '1'  condition as indicated in IT.
269                              //   '0'  inverse of condition (else).
270                              // Count of instructions in IT block is
271                              // 4 - trailingzeroes(mask)
272                              // Note that this does not have the same encoding
273                              // as in the IT instruction, which also depends
274                              // on the low bit of the condition code.
275
276    unsigned CurPosition;     // Current position in parsing of IT
277                              // block. In range [0,4], with 0 being the IT
278                              // instruction itself. Initialized according to
279                              // count of instructions in block.  ~0U if no
280                              // active IT block.
281
282    bool IsExplicit;          // true  - The IT instruction was present in the
283                              //         input, we should not modify it.
284                              // false - The IT instruction was added
285                              //         implicitly, we can extend it if that
286                              //         would be legal.
287  } ITState;
288
289  SmallVector<MCInst, 4> PendingConditionalInsts;
290
291  void flushPendingInstructions(MCStreamer &Out) override {
292    if (!inImplicitITBlock()) {
293      assert(PendingConditionalInsts.size() == 0);
294      return;
295    }
296
297    // Emit the IT instruction
298    MCInst ITInst;
299    ITInst.setOpcode(ARM::t2IT);
300    ITInst.addOperand(MCOperand::createImm(ITState.Cond));
301    ITInst.addOperand(MCOperand::createImm(ITState.Mask));
302    Out.emitInstruction(ITInst, getSTI());
303
304    // Emit the conditional instructions
305    assert(PendingConditionalInsts.size() <= 4);
306    for (const MCInst &Inst : PendingConditionalInsts) {
307      Out.emitInstruction(Inst, getSTI());
308    }
309    PendingConditionalInsts.clear();
310
311    // Clear the IT state
312    ITState.Mask = 0;
313    ITState.CurPosition = ~0U;
314  }
315
316  bool inITBlock() { return ITState.CurPosition != ~0U; }
317  bool inExplicitITBlock() { return inITBlock() && ITState.IsExplicit; }
318  bool inImplicitITBlock() { return inITBlock() && !ITState.IsExplicit; }
319
320  bool lastInITBlock() {
321    return ITState.CurPosition == 4 - countTrailingZeros(ITState.Mask);
322  }
323
324  void forwardITPosition() {
325    if (!inITBlock()) return;
326    // Move to the next instruction in the IT block, if there is one. If not,
327    // mark the block as done, except for implicit IT blocks, which we leave
328    // open until we find an instruction that can't be added to it.
329    unsigned TZ = countTrailingZeros(ITState.Mask);
330    if (++ITState.CurPosition == 5 - TZ && ITState.IsExplicit)
331      ITState.CurPosition = ~0U; // Done with the IT block after this.
332  }
333
334  // Rewind the state of the current IT block, removing the last slot from it.
335  void rewindImplicitITPosition() {
336    assert(inImplicitITBlock());
337    assert(ITState.CurPosition > 1);
338    ITState.CurPosition--;
339    unsigned TZ = countTrailingZeros(ITState.Mask);
340    unsigned NewMask = 0;
341    NewMask |= ITState.Mask & (0xC << TZ);
342    NewMask |= 0x2 << TZ;
343    ITState.Mask = NewMask;
344  }
345
346  // Rewind the state of the current IT block, removing the last slot from it.
347  // If we were at the first slot, this closes the IT block.
348  void discardImplicitITBlock() {
349    assert(inImplicitITBlock());
350    assert(ITState.CurPosition == 1);
351    ITState.CurPosition = ~0U;
352  }
353
354  // Return the low-subreg of a given Q register.
355  unsigned getDRegFromQReg(unsigned QReg) const {
356    return MRI->getSubReg(QReg, ARM::dsub_0);
357  }
358
359  // Get the condition code corresponding to the current IT block slot.
360  ARMCC::CondCodes currentITCond() {
361    unsigned MaskBit = extractITMaskBit(ITState.Mask, ITState.CurPosition);
362    return MaskBit ? ARMCC::getOppositeCondition(ITState.Cond) : ITState.Cond;
363  }
364
365  // Invert the condition of the current IT block slot without changing any
366  // other slots in the same block.
367  void invertCurrentITCondition() {
368    if (ITState.CurPosition == 1) {
369      ITState.Cond = ARMCC::getOppositeCondition(ITState.Cond);
370    } else {
371      ITState.Mask ^= 1 << (5 - ITState.CurPosition);
372    }
373  }
374
375  // Returns true if the current IT block is full (all 4 slots used).
376  bool isITBlockFull() {
377    return inITBlock() && (ITState.Mask & 1);
378  }
379
380  // Extend the current implicit IT block to have one more slot with the given
381  // condition code.
382  void extendImplicitITBlock(ARMCC::CondCodes Cond) {
383    assert(inImplicitITBlock());
384    assert(!isITBlockFull());
385    assert(Cond == ITState.Cond ||
386           Cond == ARMCC::getOppositeCondition(ITState.Cond));
387    unsigned TZ = countTrailingZeros(ITState.Mask);
388    unsigned NewMask = 0;
389    // Keep any existing condition bits.
390    NewMask |= ITState.Mask & (0xE << TZ);
391    // Insert the new condition bit.
392    NewMask |= (Cond != ITState.Cond) << TZ;
393    // Move the trailing 1 down one bit.
394    NewMask |= 1 << (TZ - 1);
395    ITState.Mask = NewMask;
396  }
397
398  // Create a new implicit IT block with a dummy condition code.
399  void startImplicitITBlock() {
400    assert(!inITBlock());
401    ITState.Cond = ARMCC::AL;
402    ITState.Mask = 8;
403    ITState.CurPosition = 1;
404    ITState.IsExplicit = false;
405  }
406
407  // Create a new explicit IT block with the given condition and mask.
408  // The mask should be in the format used in ARMOperand and
409  // MCOperand, with a 1 implying 'e', regardless of the low bit of
410  // the condition.
411  void startExplicitITBlock(ARMCC::CondCodes Cond, unsigned Mask) {
412    assert(!inITBlock());
413    ITState.Cond = Cond;
414    ITState.Mask = Mask;
415    ITState.CurPosition = 0;
416    ITState.IsExplicit = true;
417  }
418
419  struct {
420    unsigned Mask : 4;
421    unsigned CurPosition;
422  } VPTState;
423  bool inVPTBlock() { return VPTState.CurPosition != ~0U; }
424  void forwardVPTPosition() {
425    if (!inVPTBlock()) return;
426    unsigned TZ = countTrailingZeros(VPTState.Mask);
427    if (++VPTState.CurPosition == 5 - TZ)
428      VPTState.CurPosition = ~0U;
429  }
430
431  void Note(SMLoc L, const Twine &Msg, SMRange Range = std::nullopt) {
432    return getParser().Note(L, Msg, Range);
433  }
434
435  bool Warning(SMLoc L, const Twine &Msg, SMRange Range = std::nullopt) {
436    return getParser().Warning(L, Msg, Range);
437  }
438
439  bool Error(SMLoc L, const Twine &Msg, SMRange Range = std::nullopt) {
440    return getParser().Error(L, Msg, Range);
441  }
442
443  bool validatetLDMRegList(const MCInst &Inst, const OperandVector &Operands,
444                           unsigned ListNo, bool IsARPop = false);
445  bool validatetSTMRegList(const MCInst &Inst, const OperandVector &Operands,
446                           unsigned ListNo);
447
448  int tryParseRegister();
449  bool tryParseRegisterWithWriteBack(OperandVector &);
450  int tryParseShiftRegister(OperandVector &);
451  bool parseRegisterList(OperandVector &, bool EnforceOrder = true,
452                         bool AllowRAAC = false);
453  bool parseMemory(OperandVector &);
454  bool parseOperand(OperandVector &, StringRef Mnemonic);
455  bool parseImmExpr(int64_t &Out);
456  bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
457  bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
458                              unsigned &ShiftAmount);
459  bool parseLiteralValues(unsigned Size, SMLoc L);
460  bool parseDirectiveThumb(SMLoc L);
461  bool parseDirectiveARM(SMLoc L);
462  bool parseDirectiveThumbFunc(SMLoc L);
463  bool parseDirectiveCode(SMLoc L);
464  bool parseDirectiveSyntax(SMLoc L);
465  bool parseDirectiveReq(StringRef Name, SMLoc L);
466  bool parseDirectiveUnreq(SMLoc L);
467  bool parseDirectiveArch(SMLoc L);
468  bool parseDirectiveEabiAttr(SMLoc L);
469  bool parseDirectiveCPU(SMLoc L);
470  bool parseDirectiveFPU(SMLoc L);
471  bool parseDirectiveFnStart(SMLoc L);
472  bool parseDirectiveFnEnd(SMLoc L);
473  bool parseDirectiveCantUnwind(SMLoc L);
474  bool parseDirectivePersonality(SMLoc L);
475  bool parseDirectiveHandlerData(SMLoc L);
476  bool parseDirectiveSetFP(SMLoc L);
477  bool parseDirectivePad(SMLoc L);
478  bool parseDirectiveRegSave(SMLoc L, bool IsVector);
479  bool parseDirectiveInst(SMLoc L, char Suffix = '\0');
480  bool parseDirectiveLtorg(SMLoc L);
481  bool parseDirectiveEven(SMLoc L);
482  bool parseDirectivePersonalityIndex(SMLoc L);
483  bool parseDirectiveUnwindRaw(SMLoc L);
484  bool parseDirectiveTLSDescSeq(SMLoc L);
485  bool parseDirectiveMovSP(SMLoc L);
486  bool parseDirectiveObjectArch(SMLoc L);
487  bool parseDirectiveArchExtension(SMLoc L);
488  bool parseDirectiveAlign(SMLoc L);
489  bool parseDirectiveThumbSet(SMLoc L);
490
491  bool parseDirectiveSEHAllocStack(SMLoc L, bool Wide);
492  bool parseDirectiveSEHSaveRegs(SMLoc L, bool Wide);
493  bool parseDirectiveSEHSaveSP(SMLoc L);
494  bool parseDirectiveSEHSaveFRegs(SMLoc L);
495  bool parseDirectiveSEHSaveLR(SMLoc L);
496  bool parseDirectiveSEHPrologEnd(SMLoc L, bool Fragment);
497  bool parseDirectiveSEHNop(SMLoc L, bool Wide);
498  bool parseDirectiveSEHEpilogStart(SMLoc L, bool Condition);
499  bool parseDirectiveSEHEpilogEnd(SMLoc L);
500  bool parseDirectiveSEHCustom(SMLoc L);
501
502  bool isMnemonicVPTPredicable(StringRef Mnemonic, StringRef ExtraToken);
503  StringRef splitMnemonic(StringRef Mnemonic, StringRef ExtraToken,
504                          unsigned &PredicationCode,
505                          unsigned &VPTPredicationCode, bool &CarrySetting,
506                          unsigned &ProcessorIMod, StringRef &ITMask);
507  void getMnemonicAcceptInfo(StringRef Mnemonic, StringRef ExtraToken,
508                             StringRef FullInst, bool &CanAcceptCarrySet,
509                             bool &CanAcceptPredicationCode,
510                             bool &CanAcceptVPTPredicationCode);
511  bool enableArchExtFeature(StringRef Name, SMLoc &ExtLoc);
512
513  void tryConvertingToTwoOperandForm(StringRef Mnemonic, bool CarrySetting,
514                                     OperandVector &Operands);
515  bool CDEConvertDualRegOperand(StringRef Mnemonic, OperandVector &Operands);
516
517  bool isThumb() const {
518    // FIXME: Can tablegen auto-generate this?
519    return getSTI().getFeatureBits()[ARM::ModeThumb];
520  }
521
522  bool isThumbOne() const {
523    return isThumb() && !getSTI().getFeatureBits()[ARM::FeatureThumb2];
524  }
525
526  bool isThumbTwo() const {
527    return isThumb() && getSTI().getFeatureBits()[ARM::FeatureThumb2];
528  }
529
530  bool hasThumb() const {
531    return getSTI().getFeatureBits()[ARM::HasV4TOps];
532  }
533
534  bool hasThumb2() const {
535    return getSTI().getFeatureBits()[ARM::FeatureThumb2];
536  }
537
538  bool hasV6Ops() const {
539    return getSTI().getFeatureBits()[ARM::HasV6Ops];
540  }
541
542  bool hasV6T2Ops() const {
543    return getSTI().getFeatureBits()[ARM::HasV6T2Ops];
544  }
545
546  bool hasV6MOps() const {
547    return getSTI().getFeatureBits()[ARM::HasV6MOps];
548  }
549
550  bool hasV7Ops() const {
551    return getSTI().getFeatureBits()[ARM::HasV7Ops];
552  }
553
554  bool hasV8Ops() const {
555    return getSTI().getFeatureBits()[ARM::HasV8Ops];
556  }
557
558  bool hasV8MBaseline() const {
559    return getSTI().getFeatureBits()[ARM::HasV8MBaselineOps];
560  }
561
562  bool hasV8MMainline() const {
563    return getSTI().getFeatureBits()[ARM::HasV8MMainlineOps];
564  }
565  bool hasV8_1MMainline() const {
566    return getSTI().getFeatureBits()[ARM::HasV8_1MMainlineOps];
567  }
568  bool hasMVE() const {
569    return getSTI().getFeatureBits()[ARM::HasMVEIntegerOps];
570  }
571  bool hasMVEFloat() const {
572    return getSTI().getFeatureBits()[ARM::HasMVEFloatOps];
573  }
574  bool hasCDE() const {
575    return getSTI().getFeatureBits()[ARM::HasCDEOps];
576  }
577  bool has8MSecExt() const {
578    return getSTI().getFeatureBits()[ARM::Feature8MSecExt];
579  }
580
581  bool hasARM() const {
582    return !getSTI().getFeatureBits()[ARM::FeatureNoARM];
583  }
584
585  bool hasDSP() const {
586    return getSTI().getFeatureBits()[ARM::FeatureDSP];
587  }
588
589  bool hasD32() const {
590    return getSTI().getFeatureBits()[ARM::FeatureD32];
591  }
592
593  bool hasV8_1aOps() const {
594    return getSTI().getFeatureBits()[ARM::HasV8_1aOps];
595  }
596
597  bool hasRAS() const {
598    return getSTI().getFeatureBits()[ARM::FeatureRAS];
599  }
600
601  void SwitchMode() {
602    MCSubtargetInfo &STI = copySTI();
603    auto FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
604    setAvailableFeatures(FB);
605  }
606
607  void FixModeAfterArchChange(bool WasThumb, SMLoc Loc);
608
609  bool isMClass() const {
610    return getSTI().getFeatureBits()[ARM::FeatureMClass];
611  }
612
613  /// @name Auto-generated Match Functions
614  /// {
615
616#define GET_ASSEMBLER_HEADER
617#include "ARMGenAsmMatcher.inc"
618
619  /// }
620
621  OperandMatchResultTy parseITCondCode(OperandVector &);
622  OperandMatchResultTy parseCoprocNumOperand(OperandVector &);
623  OperandMatchResultTy parseCoprocRegOperand(OperandVector &);
624  OperandMatchResultTy parseCoprocOptionOperand(OperandVector &);
625  OperandMatchResultTy parseMemBarrierOptOperand(OperandVector &);
626  OperandMatchResultTy parseTraceSyncBarrierOptOperand(OperandVector &);
627  OperandMatchResultTy parseInstSyncBarrierOptOperand(OperandVector &);
628  OperandMatchResultTy parseProcIFlagsOperand(OperandVector &);
629  OperandMatchResultTy parseMSRMaskOperand(OperandVector &);
630  OperandMatchResultTy parseBankedRegOperand(OperandVector &);
631  OperandMatchResultTy parsePKHImm(OperandVector &O, StringRef Op, int Low,
632                                   int High);
633  OperandMatchResultTy parsePKHLSLImm(OperandVector &O) {
634    return parsePKHImm(O, "lsl", 0, 31);
635  }
636  OperandMatchResultTy parsePKHASRImm(OperandVector &O) {
637    return parsePKHImm(O, "asr", 1, 32);
638  }
639  OperandMatchResultTy parseSetEndImm(OperandVector &);
640  OperandMatchResultTy parseShifterImm(OperandVector &);
641  OperandMatchResultTy parseRotImm(OperandVector &);
642  OperandMatchResultTy parseModImm(OperandVector &);
643  OperandMatchResultTy parseBitfield(OperandVector &);
644  OperandMatchResultTy parsePostIdxReg(OperandVector &);
645  OperandMatchResultTy parseAM3Offset(OperandVector &);
646  OperandMatchResultTy parseFPImm(OperandVector &);
647  OperandMatchResultTy parseVectorList(OperandVector &);
648  OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index,
649                                       SMLoc &EndLoc);
650
651  // Asm Match Converter Methods
652  void cvtThumbMultiply(MCInst &Inst, const OperandVector &);
653  void cvtThumbBranches(MCInst &Inst, const OperandVector &);
654  void cvtMVEVMOVQtoDReg(MCInst &Inst, const OperandVector &);
655
656  bool validateInstruction(MCInst &Inst, const OperandVector &Ops);
657  bool processInstruction(MCInst &Inst, const OperandVector &Ops, MCStreamer &Out);
658  bool shouldOmitCCOutOperand(StringRef Mnemonic, OperandVector &Operands);
659  bool shouldOmitPredicateOperand(StringRef Mnemonic, OperandVector &Operands);
660  bool shouldOmitVectorPredicateOperand(StringRef Mnemonic, OperandVector &Operands);
661  bool isITBlockTerminator(MCInst &Inst) const;
662  void fixupGNULDRDAlias(StringRef Mnemonic, OperandVector &Operands);
663  bool validateLDRDSTRD(MCInst &Inst, const OperandVector &Operands,
664                        bool Load, bool ARMMode, bool Writeback);
665
666public:
667  enum ARMMatchResultTy {
668    Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
669    Match_RequiresNotITBlock,
670    Match_RequiresV6,
671    Match_RequiresThumb2,
672    Match_RequiresV8,
673    Match_RequiresFlagSetting,
674#define GET_OPERAND_DIAGNOSTIC_TYPES
675#include "ARMGenAsmMatcher.inc"
676
677  };
678
679  ARMAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
680               const MCInstrInfo &MII, const MCTargetOptions &Options)
681    : MCTargetAsmParser(Options, STI, MII), UC(Parser), MS(STI) {
682    MCAsmParserExtension::Initialize(Parser);
683
684    // Cache the MCRegisterInfo.
685    MRI = getContext().getRegisterInfo();
686
687    // Initialize the set of available features.
688    setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
689
690    // Add build attributes based on the selected target.
691    if (AddBuildAttributes)
692      getTargetStreamer().emitTargetAttributes(STI);
693
694    // Not in an ITBlock to start with.
695    ITState.CurPosition = ~0U;
696
697    VPTState.CurPosition = ~0U;
698
699    NextSymbolIsThumb = false;
700  }
701
702  // Implementation of the MCTargetAsmParser interface:
703  bool parseRegister(MCRegister &RegNo, SMLoc &StartLoc,
704                     SMLoc &EndLoc) override;
705  OperandMatchResultTy tryParseRegister(MCRegister &RegNo, SMLoc &StartLoc,
706                                        SMLoc &EndLoc) override;
707  bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
708                        SMLoc NameLoc, OperandVector &Operands) override;
709  bool ParseDirective(AsmToken DirectiveID) override;
710
711  unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
712                                      unsigned Kind) override;
713  unsigned checkTargetMatchPredicate(MCInst &Inst) override;
714
715  bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
716                               OperandVector &Operands, MCStreamer &Out,
717                               uint64_t &ErrorInfo,
718                               bool MatchingInlineAsm) override;
719  unsigned MatchInstruction(OperandVector &Operands, MCInst &Inst,
720                            SmallVectorImpl<NearMissInfo> &NearMisses,
721                            bool MatchingInlineAsm, bool &EmitInITBlock,
722                            MCStreamer &Out);
723
724  struct NearMissMessage {
725    SMLoc Loc;
726    SmallString<128> Message;
727  };
728
729  const char *getCustomOperandDiag(ARMMatchResultTy MatchError);
730
731  void FilterNearMisses(SmallVectorImpl<NearMissInfo> &NearMissesIn,
732                        SmallVectorImpl<NearMissMessage> &NearMissesOut,
733                        SMLoc IDLoc, OperandVector &Operands);
734  void ReportNearMisses(SmallVectorImpl<NearMissInfo> &NearMisses, SMLoc IDLoc,
735                        OperandVector &Operands);
736
737  void doBeforeLabelEmit(MCSymbol *Symbol, SMLoc IDLoc) override;
738
739  void onLabelParsed(MCSymbol *Symbol) override;
740};
741
742/// ARMOperand - Instances of this class represent a parsed ARM machine
743/// operand.
744class ARMOperand : public MCParsedAsmOperand {
745  enum KindTy {
746    k_CondCode,
747    k_VPTPred,
748    k_CCOut,
749    k_ITCondMask,
750    k_CoprocNum,
751    k_CoprocReg,
752    k_CoprocOption,
753    k_Immediate,
754    k_MemBarrierOpt,
755    k_InstSyncBarrierOpt,
756    k_TraceSyncBarrierOpt,
757    k_Memory,
758    k_PostIndexRegister,
759    k_MSRMask,
760    k_BankedReg,
761    k_ProcIFlags,
762    k_VectorIndex,
763    k_Register,
764    k_RegisterList,
765    k_RegisterListWithAPSR,
766    k_DPRRegisterList,
767    k_SPRRegisterList,
768    k_FPSRegisterListWithVPR,
769    k_FPDRegisterListWithVPR,
770    k_VectorList,
771    k_VectorListAllLanes,
772    k_VectorListIndexed,
773    k_ShiftedRegister,
774    k_ShiftedImmediate,
775    k_ShifterImmediate,
776    k_RotateImmediate,
777    k_ModifiedImmediate,
778    k_ConstantPoolImmediate,
779    k_BitfieldDescriptor,
780    k_Token,
781  } Kind;
782
783  SMLoc StartLoc, EndLoc, AlignmentLoc;
784  SmallVector<unsigned, 8> Registers;
785
786  struct CCOp {
787    ARMCC::CondCodes Val;
788  };
789
790  struct VCCOp {
791    ARMVCC::VPTCodes Val;
792  };
793
794  struct CopOp {
795    unsigned Val;
796  };
797
798  struct CoprocOptionOp {
799    unsigned Val;
800  };
801
802  struct ITMaskOp {
803    unsigned Mask:4;
804  };
805
806  struct MBOptOp {
807    ARM_MB::MemBOpt Val;
808  };
809
810  struct ISBOptOp {
811    ARM_ISB::InstSyncBOpt Val;
812  };
813
814  struct TSBOptOp {
815    ARM_TSB::TraceSyncBOpt Val;
816  };
817
818  struct IFlagsOp {
819    ARM_PROC::IFlags Val;
820  };
821
822  struct MMaskOp {
823    unsigned Val;
824  };
825
826  struct BankedRegOp {
827    unsigned Val;
828  };
829
830  struct TokOp {
831    const char *Data;
832    unsigned Length;
833  };
834
835  struct RegOp {
836    unsigned RegNum;
837  };
838
839  // A vector register list is a sequential list of 1 to 4 registers.
840  struct VectorListOp {
841    unsigned RegNum;
842    unsigned Count;
843    unsigned LaneIndex;
844    bool isDoubleSpaced;
845  };
846
847  struct VectorIndexOp {
848    unsigned Val;
849  };
850
851  struct ImmOp {
852    const MCExpr *Val;
853  };
854
855  /// Combined record for all forms of ARM address expressions.
856  struct MemoryOp {
857    unsigned BaseRegNum;
858    // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
859    // was specified.
860    const MCExpr *OffsetImm;  // Offset immediate value
861    unsigned OffsetRegNum;    // Offset register num, when OffsetImm == NULL
862    ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
863    unsigned ShiftImm;        // shift for OffsetReg.
864    unsigned Alignment;       // 0 = no alignment specified
865    // n = alignment in bytes (2, 4, 8, 16, or 32)
866    unsigned isNegative : 1;  // Negated OffsetReg? (~'U' bit)
867  };
868
869  struct PostIdxRegOp {
870    unsigned RegNum;
871    bool isAdd;
872    ARM_AM::ShiftOpc ShiftTy;
873    unsigned ShiftImm;
874  };
875
876  struct ShifterImmOp {
877    bool isASR;
878    unsigned Imm;
879  };
880
881  struct RegShiftedRegOp {
882    ARM_AM::ShiftOpc ShiftTy;
883    unsigned SrcReg;
884    unsigned ShiftReg;
885    unsigned ShiftImm;
886  };
887
888  struct RegShiftedImmOp {
889    ARM_AM::ShiftOpc ShiftTy;
890    unsigned SrcReg;
891    unsigned ShiftImm;
892  };
893
894  struct RotImmOp {
895    unsigned Imm;
896  };
897
898  struct ModImmOp {
899    unsigned Bits;
900    unsigned Rot;
901  };
902
903  struct BitfieldOp {
904    unsigned LSB;
905    unsigned Width;
906  };
907
908  union {
909    struct CCOp CC;
910    struct VCCOp VCC;
911    struct CopOp Cop;
912    struct CoprocOptionOp CoprocOption;
913    struct MBOptOp MBOpt;
914    struct ISBOptOp ISBOpt;
915    struct TSBOptOp TSBOpt;
916    struct ITMaskOp ITMask;
917    struct IFlagsOp IFlags;
918    struct MMaskOp MMask;
919    struct BankedRegOp BankedReg;
920    struct TokOp Tok;
921    struct RegOp Reg;
922    struct VectorListOp VectorList;
923    struct VectorIndexOp VectorIndex;
924    struct ImmOp Imm;
925    struct MemoryOp Memory;
926    struct PostIdxRegOp PostIdxReg;
927    struct ShifterImmOp ShifterImm;
928    struct RegShiftedRegOp RegShiftedReg;
929    struct RegShiftedImmOp RegShiftedImm;
930    struct RotImmOp RotImm;
931    struct ModImmOp ModImm;
932    struct BitfieldOp Bitfield;
933  };
934
935public:
936  ARMOperand(KindTy K) : Kind(K) {}
937
938  /// getStartLoc - Get the location of the first token of this operand.
939  SMLoc getStartLoc() const override { return StartLoc; }
940
941  /// getEndLoc - Get the location of the last token of this operand.
942  SMLoc getEndLoc() const override { return EndLoc; }
943
944  /// getLocRange - Get the range between the first and last token of this
945  /// operand.
946  SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
947
948  /// getAlignmentLoc - Get the location of the Alignment token of this operand.
949  SMLoc getAlignmentLoc() const {
950    assert(Kind == k_Memory && "Invalid access!");
951    return AlignmentLoc;
952  }
953
954  ARMCC::CondCodes getCondCode() const {
955    assert(Kind == k_CondCode && "Invalid access!");
956    return CC.Val;
957  }
958
959  ARMVCC::VPTCodes getVPTPred() const {
960    assert(isVPTPred() && "Invalid access!");
961    return VCC.Val;
962  }
963
964  unsigned getCoproc() const {
965    assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
966    return Cop.Val;
967  }
968
969  StringRef getToken() const {
970    assert(Kind == k_Token && "Invalid access!");
971    return StringRef(Tok.Data, Tok.Length);
972  }
973
974  unsigned getReg() const override {
975    assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
976    return Reg.RegNum;
977  }
978
979  const SmallVectorImpl<unsigned> &getRegList() const {
980    assert((Kind == k_RegisterList || Kind == k_RegisterListWithAPSR ||
981            Kind == k_DPRRegisterList || Kind == k_SPRRegisterList ||
982            Kind == k_FPSRegisterListWithVPR ||
983            Kind == k_FPDRegisterListWithVPR) &&
984           "Invalid access!");
985    return Registers;
986  }
987
988  const MCExpr *getImm() const {
989    assert(isImm() && "Invalid access!");
990    return Imm.Val;
991  }
992
993  const MCExpr *getConstantPoolImm() const {
994    assert(isConstantPoolImm() && "Invalid access!");
995    return Imm.Val;
996  }
997
998  unsigned getVectorIndex() const {
999    assert(Kind == k_VectorIndex && "Invalid access!");
1000    return VectorIndex.Val;
1001  }
1002
1003  ARM_MB::MemBOpt getMemBarrierOpt() const {
1004    assert(Kind == k_MemBarrierOpt && "Invalid access!");
1005    return MBOpt.Val;
1006  }
1007
1008  ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const {
1009    assert(Kind == k_InstSyncBarrierOpt && "Invalid access!");
1010    return ISBOpt.Val;
1011  }
1012
1013  ARM_TSB::TraceSyncBOpt getTraceSyncBarrierOpt() const {
1014    assert(Kind == k_TraceSyncBarrierOpt && "Invalid access!");
1015    return TSBOpt.Val;
1016  }
1017
1018  ARM_PROC::IFlags getProcIFlags() const {
1019    assert(Kind == k_ProcIFlags && "Invalid access!");
1020    return IFlags.Val;
1021  }
1022
1023  unsigned getMSRMask() const {
1024    assert(Kind == k_MSRMask && "Invalid access!");
1025    return MMask.Val;
1026  }
1027
1028  unsigned getBankedReg() const {
1029    assert(Kind == k_BankedReg && "Invalid access!");
1030    return BankedReg.Val;
1031  }
1032
1033  bool isCoprocNum() const { return Kind == k_CoprocNum; }
1034  bool isCoprocReg() const { return Kind == k_CoprocReg; }
1035  bool isCoprocOption() const { return Kind == k_CoprocOption; }
1036  bool isCondCode() const { return Kind == k_CondCode; }
1037  bool isVPTPred() const { return Kind == k_VPTPred; }
1038  bool isCCOut() const { return Kind == k_CCOut; }
1039  bool isITMask() const { return Kind == k_ITCondMask; }
1040  bool isITCondCode() const { return Kind == k_CondCode; }
1041  bool isImm() const override {
1042    return Kind == k_Immediate;
1043  }
1044
1045  bool isARMBranchTarget() const {
1046    if (!isImm()) return false;
1047
1048    if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()))
1049      return CE->getValue() % 4 == 0;
1050    return true;
1051  }
1052
1053
1054  bool isThumbBranchTarget() const {
1055    if (!isImm()) return false;
1056
1057    if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()))
1058      return CE->getValue() % 2 == 0;
1059    return true;
1060  }
1061
1062  // checks whether this operand is an unsigned offset which fits is a field
1063  // of specified width and scaled by a specific number of bits
1064  template<unsigned width, unsigned scale>
1065  bool isUnsignedOffset() const {
1066    if (!isImm()) return false;
1067    if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
1068    if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
1069      int64_t Val = CE->getValue();
1070      int64_t Align = 1LL << scale;
1071      int64_t Max = Align * ((1LL << width) - 1);
1072      return ((Val % Align) == 0) && (Val >= 0) && (Val <= Max);
1073    }
1074    return false;
1075  }
1076
1077  // checks whether this operand is an signed offset which fits is a field
1078  // of specified width and scaled by a specific number of bits
1079  template<unsigned width, unsigned scale>
1080  bool isSignedOffset() const {
1081    if (!isImm()) return false;
1082    if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
1083    if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
1084      int64_t Val = CE->getValue();
1085      int64_t Align = 1LL << scale;
1086      int64_t Max = Align * ((1LL << (width-1)) - 1);
1087      int64_t Min = -Align * (1LL << (width-1));
1088      return ((Val % Align) == 0) && (Val >= Min) && (Val <= Max);
1089    }
1090    return false;
1091  }
1092
1093  // checks whether this operand is an offset suitable for the LE /
1094  // LETP instructions in Arm v8.1M
1095  bool isLEOffset() const {
1096    if (!isImm()) return false;
1097    if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
1098    if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
1099      int64_t Val = CE->getValue();
1100      return Val < 0 && Val >= -4094 && (Val & 1) == 0;
1101    }
1102    return false;
1103  }
1104
1105  // checks whether this operand is a memory operand computed as an offset
1106  // applied to PC. the offset may have 8 bits of magnitude and is represented
1107  // with two bits of shift. textually it may be either [pc, #imm], #imm or
1108  // relocable expression...
1109  bool isThumbMemPC() const {
1110    int64_t Val = 0;
1111    if (isImm()) {
1112      if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
1113      const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val);
1114      if (!CE) return false;
1115      Val = CE->getValue();
1116    }
1117    else if (isGPRMem()) {
1118      if(!Memory.OffsetImm || Memory.OffsetRegNum) return false;
1119      if(Memory.BaseRegNum != ARM::PC) return false;
1120      if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm))
1121        Val = CE->getValue();
1122      else
1123        return false;
1124    }
1125    else return false;
1126    return ((Val % 4) == 0) && (Val >= 0) && (Val <= 1020);
1127  }
1128
1129  bool isFPImm() const {
1130    if (!isImm()) return false;
1131    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1132    if (!CE) return false;
1133    int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
1134    return Val != -1;
1135  }
1136
1137  template<int64_t N, int64_t M>
1138  bool isImmediate() const {
1139    if (!isImm()) return false;
1140    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1141    if (!CE) return false;
1142    int64_t Value = CE->getValue();
1143    return Value >= N && Value <= M;
1144  }
1145
1146  template<int64_t N, int64_t M>
1147  bool isImmediateS4() const {
1148    if (!isImm()) return false;
1149    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1150    if (!CE) return false;
1151    int64_t Value = CE->getValue();
1152    return ((Value & 3) == 0) && Value >= N && Value <= M;
1153  }
1154  template<int64_t N, int64_t M>
1155  bool isImmediateS2() const {
1156    if (!isImm()) return false;
1157    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1158    if (!CE) return false;
1159    int64_t Value = CE->getValue();
1160    return ((Value & 1) == 0) && Value >= N && Value <= M;
1161  }
1162  bool isFBits16() const {
1163    return isImmediate<0, 17>();
1164  }
1165  bool isFBits32() const {
1166    return isImmediate<1, 33>();
1167  }
1168  bool isImm8s4() const {
1169    return isImmediateS4<-1020, 1020>();
1170  }
1171  bool isImm7s4() const {
1172    return isImmediateS4<-508, 508>();
1173  }
1174  bool isImm7Shift0() const {
1175    return isImmediate<-127, 127>();
1176  }
1177  bool isImm7Shift1() const {
1178    return isImmediateS2<-255, 255>();
1179  }
1180  bool isImm7Shift2() const {
1181    return isImmediateS4<-511, 511>();
1182  }
1183  bool isImm7() const {
1184    return isImmediate<-127, 127>();
1185  }
1186  bool isImm0_1020s4() const {
1187    return isImmediateS4<0, 1020>();
1188  }
1189  bool isImm0_508s4() const {
1190    return isImmediateS4<0, 508>();
1191  }
1192  bool isImm0_508s4Neg() const {
1193    if (!isImm()) return false;
1194    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1195    if (!CE) return false;
1196    int64_t Value = -CE->getValue();
1197    // explicitly exclude zero. we want that to use the normal 0_508 version.
1198    return ((Value & 3) == 0) && Value > 0 && Value <= 508;
1199  }
1200
1201  bool isImm0_4095Neg() const {
1202    if (!isImm()) return false;
1203    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1204    if (!CE) return false;
1205    // isImm0_4095Neg is used with 32-bit immediates only.
1206    // 32-bit immediates are zero extended to 64-bit when parsed,
1207    // thus simple -CE->getValue() results in a big negative number,
1208    // not a small positive number as intended
1209    if ((CE->getValue() >> 32) > 0) return false;
1210    uint32_t Value = -static_cast<uint32_t>(CE->getValue());
1211    return Value > 0 && Value < 4096;
1212  }
1213
1214  bool isImm0_7() const {
1215    return isImmediate<0, 7>();
1216  }
1217
1218  bool isImm1_16() const {
1219    return isImmediate<1, 16>();
1220  }
1221
1222  bool isImm1_32() const {
1223    return isImmediate<1, 32>();
1224  }
1225
1226  bool isImm8_255() const {
1227    return isImmediate<8, 255>();
1228  }
1229
1230  bool isImm256_65535Expr() const {
1231    if (!isImm()) return false;
1232    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1233    // If it's not a constant expression, it'll generate a fixup and be
1234    // handled later.
1235    if (!CE) return true;
1236    int64_t Value = CE->getValue();
1237    return Value >= 256 && Value < 65536;
1238  }
1239
1240  bool isImm0_65535Expr() const {
1241    if (!isImm()) return false;
1242    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1243    // If it's not a constant expression, it'll generate a fixup and be
1244    // handled later.
1245    if (!CE) return true;
1246    int64_t Value = CE->getValue();
1247    return Value >= 0 && Value < 65536;
1248  }
1249
1250  bool isImm24bit() const {
1251    return isImmediate<0, 0xffffff + 1>();
1252  }
1253
1254  bool isImmThumbSR() const {
1255    return isImmediate<1, 33>();
1256  }
1257
1258  template<int shift>
1259  bool isExpImmValue(uint64_t Value) const {
1260    uint64_t mask = (1 << shift) - 1;
1261    if ((Value & mask) != 0 || (Value >> shift) > 0xff)
1262      return false;
1263    return true;
1264  }
1265
1266  template<int shift>
1267  bool isExpImm() const {
1268    if (!isImm()) return false;
1269    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1270    if (!CE) return false;
1271
1272    return isExpImmValue<shift>(CE->getValue());
1273  }
1274
1275  template<int shift, int size>
1276  bool isInvertedExpImm() const {
1277    if (!isImm()) return false;
1278    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1279    if (!CE) return false;
1280
1281    uint64_t OriginalValue = CE->getValue();
1282    uint64_t InvertedValue = OriginalValue ^ (((uint64_t)1 << size) - 1);
1283    return isExpImmValue<shift>(InvertedValue);
1284  }
1285
1286  bool isPKHLSLImm() const {
1287    return isImmediate<0, 32>();
1288  }
1289
1290  bool isPKHASRImm() const {
1291    return isImmediate<0, 33>();
1292  }
1293
1294  bool isAdrLabel() const {
1295    // If we have an immediate that's not a constant, treat it as a label
1296    // reference needing a fixup.
1297    if (isImm() && !isa<MCConstantExpr>(getImm()))
1298      return true;
1299
1300    // If it is a constant, it must fit into a modified immediate encoding.
1301    if (!isImm()) return false;
1302    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1303    if (!CE) return false;
1304    int64_t Value = CE->getValue();
1305    return (ARM_AM::getSOImmVal(Value) != -1 ||
1306            ARM_AM::getSOImmVal(-Value) != -1);
1307  }
1308
1309  bool isT2SOImm() const {
1310    // If we have an immediate that's not a constant, treat it as an expression
1311    // needing a fixup.
1312    if (isImm() && !isa<MCConstantExpr>(getImm())) {
1313      // We want to avoid matching :upper16: and :lower16: as we want these
1314      // expressions to match in isImm0_65535Expr()
1315      const ARMMCExpr *ARM16Expr = dyn_cast<ARMMCExpr>(getImm());
1316      return (!ARM16Expr || (ARM16Expr->getKind() != ARMMCExpr::VK_ARM_HI16 &&
1317                             ARM16Expr->getKind() != ARMMCExpr::VK_ARM_LO16));
1318    }
1319    if (!isImm()) return false;
1320    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1321    if (!CE) return false;
1322    int64_t Value = CE->getValue();
1323    return ARM_AM::getT2SOImmVal(Value) != -1;
1324  }
1325
1326  bool isT2SOImmNot() const {
1327    if (!isImm()) return false;
1328    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1329    if (!CE) return false;
1330    int64_t Value = CE->getValue();
1331    return ARM_AM::getT2SOImmVal(Value) == -1 &&
1332      ARM_AM::getT2SOImmVal(~Value) != -1;
1333  }
1334
1335  bool isT2SOImmNeg() const {
1336    if (!isImm()) return false;
1337    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1338    if (!CE) return false;
1339    int64_t Value = CE->getValue();
1340    // Only use this when not representable as a plain so_imm.
1341    return ARM_AM::getT2SOImmVal(Value) == -1 &&
1342      ARM_AM::getT2SOImmVal(-Value) != -1;
1343  }
1344
1345  bool isSetEndImm() const {
1346    if (!isImm()) return false;
1347    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1348    if (!CE) return false;
1349    int64_t Value = CE->getValue();
1350    return Value == 1 || Value == 0;
1351  }
1352
1353  bool isReg() const override { return Kind == k_Register; }
1354  bool isRegList() const { return Kind == k_RegisterList; }
1355  bool isRegListWithAPSR() const {
1356    return Kind == k_RegisterListWithAPSR || Kind == k_RegisterList;
1357  }
1358  bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
1359  bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
1360  bool isFPSRegListWithVPR() const { return Kind == k_FPSRegisterListWithVPR; }
1361  bool isFPDRegListWithVPR() const { return Kind == k_FPDRegisterListWithVPR; }
1362  bool isToken() const override { return Kind == k_Token; }
1363  bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
1364  bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; }
1365  bool isTraceSyncBarrierOpt() const { return Kind == k_TraceSyncBarrierOpt; }
1366  bool isMem() const override {
1367      return isGPRMem() || isMVEMem();
1368  }
1369  bool isMVEMem() const {
1370    if (Kind != k_Memory)
1371      return false;
1372    if (Memory.BaseRegNum &&
1373        !ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Memory.BaseRegNum) &&
1374        !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(Memory.BaseRegNum))
1375      return false;
1376    if (Memory.OffsetRegNum &&
1377        !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(
1378            Memory.OffsetRegNum))
1379      return false;
1380    return true;
1381  }
1382  bool isGPRMem() const {
1383    if (Kind != k_Memory)
1384      return false;
1385    if (Memory.BaseRegNum &&
1386        !ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Memory.BaseRegNum))
1387      return false;
1388    if (Memory.OffsetRegNum &&
1389        !ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Memory.OffsetRegNum))
1390      return false;
1391    return true;
1392  }
1393  bool isShifterImm() const { return Kind == k_ShifterImmediate; }
1394  bool isRegShiftedReg() const {
1395    return Kind == k_ShiftedRegister &&
1396           ARMMCRegisterClasses[ARM::GPRRegClassID].contains(
1397               RegShiftedReg.SrcReg) &&
1398           ARMMCRegisterClasses[ARM::GPRRegClassID].contains(
1399               RegShiftedReg.ShiftReg);
1400  }
1401  bool isRegShiftedImm() const {
1402    return Kind == k_ShiftedImmediate &&
1403           ARMMCRegisterClasses[ARM::GPRRegClassID].contains(
1404               RegShiftedImm.SrcReg);
1405  }
1406  bool isRotImm() const { return Kind == k_RotateImmediate; }
1407
1408  template<unsigned Min, unsigned Max>
1409  bool isPowerTwoInRange() const {
1410    if (!isImm()) return false;
1411    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1412    if (!CE) return false;
1413    int64_t Value = CE->getValue();
1414    return Value > 0 && llvm::popcount((uint64_t)Value) == 1 && Value >= Min &&
1415           Value <= Max;
1416  }
1417  bool isModImm() const { return Kind == k_ModifiedImmediate; }
1418
1419  bool isModImmNot() const {
1420    if (!isImm()) return false;
1421    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1422    if (!CE) return false;
1423    int64_t Value = CE->getValue();
1424    return ARM_AM::getSOImmVal(~Value) != -1;
1425  }
1426
1427  bool isModImmNeg() const {
1428    if (!isImm()) return false;
1429    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1430    if (!CE) return false;
1431    int64_t Value = CE->getValue();
1432    return ARM_AM::getSOImmVal(Value) == -1 &&
1433      ARM_AM::getSOImmVal(-Value) != -1;
1434  }
1435
1436  bool isThumbModImmNeg1_7() const {
1437    if (!isImm()) return false;
1438    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1439    if (!CE) return false;
1440    int32_t Value = -(int32_t)CE->getValue();
1441    return 0 < Value && Value < 8;
1442  }
1443
1444  bool isThumbModImmNeg8_255() const {
1445    if (!isImm()) return false;
1446    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1447    if (!CE) return false;
1448    int32_t Value = -(int32_t)CE->getValue();
1449    return 7 < Value && Value < 256;
1450  }
1451
1452  bool isConstantPoolImm() const { return Kind == k_ConstantPoolImmediate; }
1453  bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
1454  bool isPostIdxRegShifted() const {
1455    return Kind == k_PostIndexRegister &&
1456           ARMMCRegisterClasses[ARM::GPRRegClassID].contains(PostIdxReg.RegNum);
1457  }
1458  bool isPostIdxReg() const {
1459    return isPostIdxRegShifted() && PostIdxReg.ShiftTy == ARM_AM::no_shift;
1460  }
1461  bool isMemNoOffset(bool alignOK = false, unsigned Alignment = 0) const {
1462    if (!isGPRMem())
1463      return false;
1464    // No offset of any kind.
1465    return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
1466     (alignOK || Memory.Alignment == Alignment);
1467  }
1468  bool isMemNoOffsetT2(bool alignOK = false, unsigned Alignment = 0) const {
1469    if (!isGPRMem())
1470      return false;
1471
1472    if (!ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains(
1473            Memory.BaseRegNum))
1474      return false;
1475
1476    // No offset of any kind.
1477    return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
1478     (alignOK || Memory.Alignment == Alignment);
1479  }
1480  bool isMemNoOffsetT2NoSp(bool alignOK = false, unsigned Alignment = 0) const {
1481    if (!isGPRMem())
1482      return false;
1483
1484    if (!ARMMCRegisterClasses[ARM::rGPRRegClassID].contains(
1485            Memory.BaseRegNum))
1486      return false;
1487
1488    // No offset of any kind.
1489    return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
1490     (alignOK || Memory.Alignment == Alignment);
1491  }
1492  bool isMemNoOffsetT(bool alignOK = false, unsigned Alignment = 0) const {
1493    if (!isGPRMem())
1494      return false;
1495
1496    if (!ARMMCRegisterClasses[ARM::tGPRRegClassID].contains(
1497            Memory.BaseRegNum))
1498      return false;
1499
1500    // No offset of any kind.
1501    return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
1502     (alignOK || Memory.Alignment == Alignment);
1503  }
1504  bool isMemPCRelImm12() const {
1505    if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1506      return false;
1507    // Base register must be PC.
1508    if (Memory.BaseRegNum != ARM::PC)
1509      return false;
1510    // Immediate offset in range [-4095, 4095].
1511    if (!Memory.OffsetImm) return true;
1512    if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
1513      int64_t Val = CE->getValue();
1514      return (Val > -4096 && Val < 4096) ||
1515             (Val == std::numeric_limits<int32_t>::min());
1516    }
1517    return false;
1518  }
1519
1520  bool isAlignedMemory() const {
1521    return isMemNoOffset(true);
1522  }
1523
1524  bool isAlignedMemoryNone() const {
1525    return isMemNoOffset(false, 0);
1526  }
1527
1528  bool isDupAlignedMemoryNone() const {
1529    return isMemNoOffset(false, 0);
1530  }
1531
1532  bool isAlignedMemory16() const {
1533    if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1534      return true;
1535    return isMemNoOffset(false, 0);
1536  }
1537
1538  bool isDupAlignedMemory16() const {
1539    if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1540      return true;
1541    return isMemNoOffset(false, 0);
1542  }
1543
1544  bool isAlignedMemory32() const {
1545    if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1546      return true;
1547    return isMemNoOffset(false, 0);
1548  }
1549
1550  bool isDupAlignedMemory32() const {
1551    if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1552      return true;
1553    return isMemNoOffset(false, 0);
1554  }
1555
1556  bool isAlignedMemory64() const {
1557    if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1558      return true;
1559    return isMemNoOffset(false, 0);
1560  }
1561
1562  bool isDupAlignedMemory64() const {
1563    if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1564      return true;
1565    return isMemNoOffset(false, 0);
1566  }
1567
1568  bool isAlignedMemory64or128() const {
1569    if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1570      return true;
1571    if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1572      return true;
1573    return isMemNoOffset(false, 0);
1574  }
1575
1576  bool isDupAlignedMemory64or128() const {
1577    if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1578      return true;
1579    if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1580      return true;
1581    return isMemNoOffset(false, 0);
1582  }
1583
1584  bool isAlignedMemory64or128or256() const {
1585    if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1586      return true;
1587    if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1588      return true;
1589    if (isMemNoOffset(false, 32)) // alignment in bytes for 256-bits is 32.
1590      return true;
1591    return isMemNoOffset(false, 0);
1592  }
1593
1594  bool isAddrMode2() const {
1595    if (!isGPRMem() || Memory.Alignment != 0) return false;
1596    // Check for register offset.
1597    if (Memory.OffsetRegNum) return true;
1598    // Immediate offset in range [-4095, 4095].
1599    if (!Memory.OffsetImm) return true;
1600    if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
1601      int64_t Val = CE->getValue();
1602      return Val > -4096 && Val < 4096;
1603    }
1604    return false;
1605  }
1606
1607  bool isAM2OffsetImm() const {
1608    if (!isImm()) return false;
1609    // Immediate offset in range [-4095, 4095].
1610    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1611    if (!CE) return false;
1612    int64_t Val = CE->getValue();
1613    return (Val == std::numeric_limits<int32_t>::min()) ||
1614           (Val > -4096 && Val < 4096);
1615  }
1616
1617  bool isAddrMode3() const {
1618    // If we have an immediate that's not a constant, treat it as a label
1619    // reference needing a fixup. If it is a constant, it's something else
1620    // and we reject it.
1621    if (isImm() && !isa<MCConstantExpr>(getImm()))
1622      return true;
1623    if (!isGPRMem() || Memory.Alignment != 0) return false;
1624    // No shifts are legal for AM3.
1625    if (Memory.ShiftType != ARM_AM::no_shift) return false;
1626    // Check for register offset.
1627    if (Memory.OffsetRegNum) return true;
1628    // Immediate offset in range [-255, 255].
1629    if (!Memory.OffsetImm) return true;
1630    if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
1631      int64_t Val = CE->getValue();
1632      // The #-0 offset is encoded as std::numeric_limits<int32_t>::min(), and
1633      // we have to check for this too.
1634      return (Val > -256 && Val < 256) ||
1635             Val == std::numeric_limits<int32_t>::min();
1636    }
1637    return false;
1638  }
1639
1640  bool isAM3Offset() const {
1641    if (isPostIdxReg())
1642      return true;
1643    if (!isImm())
1644      return false;
1645    // Immediate offset in range [-255, 255].
1646    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1647    if (!CE) return false;
1648    int64_t Val = CE->getValue();
1649    // Special case, #-0 is std::numeric_limits<int32_t>::min().
1650    return (Val > -256 && Val < 256) ||
1651           Val == std::numeric_limits<int32_t>::min();
1652  }
1653
1654  bool isAddrMode5() const {
1655    // If we have an immediate that's not a constant, treat it as a label
1656    // reference needing a fixup. If it is a constant, it's something else
1657    // and we reject it.
1658    if (isImm() && !isa<MCConstantExpr>(getImm()))
1659      return true;
1660    if (!isGPRMem() || Memory.Alignment != 0) return false;
1661    // Check for register offset.
1662    if (Memory.OffsetRegNum) return false;
1663    // Immediate offset in range [-1020, 1020] and a multiple of 4.
1664    if (!Memory.OffsetImm) return true;
1665    if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
1666      int64_t Val = CE->getValue();
1667      return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
1668             Val == std::numeric_limits<int32_t>::min();
1669    }
1670    return false;
1671  }
1672
1673  bool isAddrMode5FP16() const {
1674    // If we have an immediate that's not a constant, treat it as a label
1675    // reference needing a fixup. If it is a constant, it's something else
1676    // and we reject it.
1677    if (isImm() && !isa<MCConstantExpr>(getImm()))
1678      return true;
1679    if (!isGPRMem() || Memory.Alignment != 0) return false;
1680    // Check for register offset.
1681    if (Memory.OffsetRegNum) return false;
1682    // Immediate offset in range [-510, 510] and a multiple of 2.
1683    if (!Memory.OffsetImm) return true;
1684    if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
1685      int64_t Val = CE->getValue();
1686      return (Val >= -510 && Val <= 510 && ((Val & 1) == 0)) ||
1687             Val == std::numeric_limits<int32_t>::min();
1688    }
1689    return false;
1690  }
1691
1692  bool isMemTBB() const {
1693    if (!isGPRMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1694        Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1695      return false;
1696    return true;
1697  }
1698
1699  bool isMemTBH() const {
1700    if (!isGPRMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1701        Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
1702        Memory.Alignment != 0 )
1703      return false;
1704    return true;
1705  }
1706
1707  bool isMemRegOffset() const {
1708    if (!isGPRMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
1709      return false;
1710    return true;
1711  }
1712
1713  bool isT2MemRegOffset() const {
1714    if (!isGPRMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1715        Memory.Alignment != 0 || Memory.BaseRegNum == ARM::PC)
1716      return false;
1717    // Only lsl #{0, 1, 2, 3} allowed.
1718    if (Memory.ShiftType == ARM_AM::no_shift)
1719      return true;
1720    if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
1721      return false;
1722    return true;
1723  }
1724
1725  bool isMemThumbRR() const {
1726    // Thumb reg+reg addressing is simple. Just two registers, a base and
1727    // an offset. No shifts, negations or any other complicating factors.
1728    if (!isGPRMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1729        Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1730      return false;
1731    return isARMLowRegister(Memory.BaseRegNum) &&
1732      (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
1733  }
1734
1735  bool isMemThumbRIs4() const {
1736    if (!isGPRMem() || Memory.OffsetRegNum != 0 ||
1737        !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1738      return false;
1739    // Immediate offset, multiple of 4 in range [0, 124].
1740    if (!Memory.OffsetImm) return true;
1741    if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
1742      int64_t Val = CE->getValue();
1743      return Val >= 0 && Val <= 124 && (Val % 4) == 0;
1744    }
1745    return false;
1746  }
1747
1748  bool isMemThumbRIs2() const {
1749    if (!isGPRMem() || Memory.OffsetRegNum != 0 ||
1750        !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1751      return false;
1752    // Immediate offset, multiple of 4 in range [0, 62].
1753    if (!Memory.OffsetImm) return true;
1754    if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
1755      int64_t Val = CE->getValue();
1756      return Val >= 0 && Val <= 62 && (Val % 2) == 0;
1757    }
1758    return false;
1759  }
1760
1761  bool isMemThumbRIs1() const {
1762    if (!isGPRMem() || Memory.OffsetRegNum != 0 ||
1763        !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1764      return false;
1765    // Immediate offset in range [0, 31].
1766    if (!Memory.OffsetImm) return true;
1767    if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
1768      int64_t Val = CE->getValue();
1769      return Val >= 0 && Val <= 31;
1770    }
1771    return false;
1772  }
1773
1774  bool isMemThumbSPI() const {
1775    if (!isGPRMem() || Memory.OffsetRegNum != 0 ||
1776        Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
1777      return false;
1778    // Immediate offset, multiple of 4 in range [0, 1020].
1779    if (!Memory.OffsetImm) return true;
1780    if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
1781      int64_t Val = CE->getValue();
1782      return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
1783    }
1784    return false;
1785  }
1786
1787  bool isMemImm8s4Offset() const {
1788    // If we have an immediate that's not a constant, treat it as a label
1789    // reference needing a fixup. If it is a constant, it's something else
1790    // and we reject it.
1791    if (isImm() && !isa<MCConstantExpr>(getImm()))
1792      return true;
1793    if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1794      return false;
1795    // Immediate offset a multiple of 4 in range [-1020, 1020].
1796    if (!Memory.OffsetImm) return true;
1797    if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
1798      int64_t Val = CE->getValue();
1799      // Special case, #-0 is std::numeric_limits<int32_t>::min().
1800      return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) ||
1801             Val == std::numeric_limits<int32_t>::min();
1802    }
1803    return false;
1804  }
1805
1806  bool isMemImm7s4Offset() const {
1807    // If we have an immediate that's not a constant, treat it as a label
1808    // reference needing a fixup. If it is a constant, it's something else
1809    // and we reject it.
1810    if (isImm() && !isa<MCConstantExpr>(getImm()))
1811      return true;
1812    if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0 ||
1813        !ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains(
1814            Memory.BaseRegNum))
1815      return false;
1816    // Immediate offset a multiple of 4 in range [-508, 508].
1817    if (!Memory.OffsetImm) return true;
1818    if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
1819      int64_t Val = CE->getValue();
1820      // Special case, #-0 is INT32_MIN.
1821      return (Val >= -508 && Val <= 508 && (Val & 3) == 0) || Val == INT32_MIN;
1822    }
1823    return false;
1824  }
1825
1826  bool isMemImm0_1020s4Offset() const {
1827    if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1828      return false;
1829    // Immediate offset a multiple of 4 in range [0, 1020].
1830    if (!Memory.OffsetImm) return true;
1831    if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
1832      int64_t Val = CE->getValue();
1833      return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1834    }
1835    return false;
1836  }
1837
1838  bool isMemImm8Offset() const {
1839    if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1840      return false;
1841    // Base reg of PC isn't allowed for these encodings.
1842    if (Memory.BaseRegNum == ARM::PC) return false;
1843    // Immediate offset in range [-255, 255].
1844    if (!Memory.OffsetImm) return true;
1845    if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
1846      int64_t Val = CE->getValue();
1847      return (Val == std::numeric_limits<int32_t>::min()) ||
1848             (Val > -256 && Val < 256);
1849    }
1850    return false;
1851  }
1852
1853  template<unsigned Bits, unsigned RegClassID>
1854  bool isMemImm7ShiftedOffset() const {
1855    if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0 ||
1856        !ARMMCRegisterClasses[RegClassID].contains(Memory.BaseRegNum))
1857      return false;
1858
1859    // Expect an immediate offset equal to an element of the range
1860    // [-127, 127], shifted left by Bits.
1861
1862    if (!Memory.OffsetImm) return true;
1863    if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
1864      int64_t Val = CE->getValue();
1865
1866      // INT32_MIN is a special-case value (indicating the encoding with
1867      // zero offset and the subtract bit set)
1868      if (Val == INT32_MIN)
1869        return true;
1870
1871      unsigned Divisor = 1U << Bits;
1872
1873      // Check that the low bits are zero
1874      if (Val % Divisor != 0)
1875        return false;
1876
1877      // Check that the remaining offset is within range.
1878      Val /= Divisor;
1879      return (Val >= -127 && Val <= 127);
1880    }
1881    return false;
1882  }
1883
1884  template <int shift> bool isMemRegRQOffset() const {
1885    if (!isMVEMem() || Memory.OffsetImm != nullptr || Memory.Alignment != 0)
1886      return false;
1887
1888    if (!ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains(
1889            Memory.BaseRegNum))
1890      return false;
1891    if (!ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(
1892            Memory.OffsetRegNum))
1893      return false;
1894
1895    if (shift == 0 && Memory.ShiftType != ARM_AM::no_shift)
1896      return false;
1897
1898    if (shift > 0 &&
1899        (Memory.ShiftType != ARM_AM::uxtw || Memory.ShiftImm != shift))
1900      return false;
1901
1902    return true;
1903  }
1904
1905  template <int shift> bool isMemRegQOffset() const {
1906    if (!isMVEMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1907      return false;
1908
1909    if (!ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(
1910            Memory.BaseRegNum))
1911      return false;
1912
1913    if (!Memory.OffsetImm)
1914      return true;
1915    static_assert(shift < 56,
1916                  "Such that we dont shift by a value higher than 62");
1917    if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
1918      int64_t Val = CE->getValue();
1919
1920      // The value must be a multiple of (1 << shift)
1921      if ((Val & ((1U << shift) - 1)) != 0)
1922        return false;
1923
1924      // And be in the right range, depending on the amount that it is shifted
1925      // by.  Shift 0, is equal to 7 unsigned bits, the sign bit is set
1926      // separately.
1927      int64_t Range = (1U << (7 + shift)) - 1;
1928      return (Val == INT32_MIN) || (Val > -Range && Val < Range);
1929    }
1930    return false;
1931  }
1932
1933  bool isMemPosImm8Offset() const {
1934    if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1935      return false;
1936    // Immediate offset in range [0, 255].
1937    if (!Memory.OffsetImm) return true;
1938    if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
1939      int64_t Val = CE->getValue();
1940      return Val >= 0 && Val < 256;
1941    }
1942    return false;
1943  }
1944
1945  bool isMemNegImm8Offset() const {
1946    if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1947      return false;
1948    // Base reg of PC isn't allowed for these encodings.
1949    if (Memory.BaseRegNum == ARM::PC) return false;
1950    // Immediate offset in range [-255, -1].
1951    if (!Memory.OffsetImm) return false;
1952    if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
1953      int64_t Val = CE->getValue();
1954      return (Val == std::numeric_limits<int32_t>::min()) ||
1955             (Val > -256 && Val < 0);
1956    }
1957    return false;
1958  }
1959
1960  bool isMemUImm12Offset() const {
1961    if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1962      return false;
1963    // Immediate offset in range [0, 4095].
1964    if (!Memory.OffsetImm) return true;
1965    if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
1966      int64_t Val = CE->getValue();
1967      return (Val >= 0 && Val < 4096);
1968    }
1969    return false;
1970  }
1971
1972  bool isMemImm12Offset() const {
1973    // If we have an immediate that's not a constant, treat it as a label
1974    // reference needing a fixup. If it is a constant, it's something else
1975    // and we reject it.
1976
1977    if (isImm() && !isa<MCConstantExpr>(getImm()))
1978      return true;
1979
1980    if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1981      return false;
1982    // Immediate offset in range [-4095, 4095].
1983    if (!Memory.OffsetImm) return true;
1984    if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
1985      int64_t Val = CE->getValue();
1986      return (Val > -4096 && Val < 4096) ||
1987             (Val == std::numeric_limits<int32_t>::min());
1988    }
1989    // If we have an immediate that's not a constant, treat it as a
1990    // symbolic expression needing a fixup.
1991    return true;
1992  }
1993
1994  bool isConstPoolAsmImm() const {
1995    // Delay processing of Constant Pool Immediate, this will turn into
1996    // a constant. Match no other operand
1997    return (isConstantPoolImm());
1998  }
1999
2000  bool isPostIdxImm8() const {
2001    if (!isImm()) return false;
2002    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2003    if (!CE) return false;
2004    int64_t Val = CE->getValue();
2005    return (Val > -256 && Val < 256) ||
2006           (Val == std::numeric_limits<int32_t>::min());
2007  }
2008
2009  bool isPostIdxImm8s4() const {
2010    if (!isImm()) return false;
2011    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2012    if (!CE) return false;
2013    int64_t Val = CE->getValue();
2014    return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
2015           (Val == std::numeric_limits<int32_t>::min());
2016  }
2017
2018  bool isMSRMask() const { return Kind == k_MSRMask; }
2019  bool isBankedReg() const { return Kind == k_BankedReg; }
2020  bool isProcIFlags() const { return Kind == k_ProcIFlags; }
2021
2022  // NEON operands.
2023  bool isSingleSpacedVectorList() const {
2024    return Kind == k_VectorList && !VectorList.isDoubleSpaced;
2025  }
2026
2027  bool isDoubleSpacedVectorList() const {
2028    return Kind == k_VectorList && VectorList.isDoubleSpaced;
2029  }
2030
2031  bool isVecListOneD() const {
2032    if (!isSingleSpacedVectorList()) return false;
2033    return VectorList.Count == 1;
2034  }
2035
2036  bool isVecListTwoMQ() const {
2037    return isSingleSpacedVectorList() && VectorList.Count == 2 &&
2038           ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(
2039               VectorList.RegNum);
2040  }
2041
2042  bool isVecListDPair() const {
2043    if (!isSingleSpacedVectorList()) return false;
2044    return (ARMMCRegisterClasses[ARM::DPairRegClassID]
2045              .contains(VectorList.RegNum));
2046  }
2047
2048  bool isVecListThreeD() const {
2049    if (!isSingleSpacedVectorList()) return false;
2050    return VectorList.Count == 3;
2051  }
2052
2053  bool isVecListFourD() const {
2054    if (!isSingleSpacedVectorList()) return false;
2055    return VectorList.Count == 4;
2056  }
2057
2058  bool isVecListDPairSpaced() const {
2059    if (Kind != k_VectorList) return false;
2060    if (isSingleSpacedVectorList()) return false;
2061    return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
2062              .contains(VectorList.RegNum));
2063  }
2064
2065  bool isVecListThreeQ() const {
2066    if (!isDoubleSpacedVectorList()) return false;
2067    return VectorList.Count == 3;
2068  }
2069
2070  bool isVecListFourQ() const {
2071    if (!isDoubleSpacedVectorList()) return false;
2072    return VectorList.Count == 4;
2073  }
2074
2075  bool isVecListFourMQ() const {
2076    return isSingleSpacedVectorList() && VectorList.Count == 4 &&
2077           ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(
2078               VectorList.RegNum);
2079  }
2080
2081  bool isSingleSpacedVectorAllLanes() const {
2082    return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
2083  }
2084
2085  bool isDoubleSpacedVectorAllLanes() const {
2086    return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
2087  }
2088
2089  bool isVecListOneDAllLanes() const {
2090    if (!isSingleSpacedVectorAllLanes()) return false;
2091    return VectorList.Count == 1;
2092  }
2093
2094  bool isVecListDPairAllLanes() const {
2095    if (!isSingleSpacedVectorAllLanes()) return false;
2096    return (ARMMCRegisterClasses[ARM::DPairRegClassID]
2097              .contains(VectorList.RegNum));
2098  }
2099
2100  bool isVecListDPairSpacedAllLanes() const {
2101    if (!isDoubleSpacedVectorAllLanes()) return false;
2102    return VectorList.Count == 2;
2103  }
2104
2105  bool isVecListThreeDAllLanes() const {
2106    if (!isSingleSpacedVectorAllLanes()) return false;
2107    return VectorList.Count == 3;
2108  }
2109
2110  bool isVecListThreeQAllLanes() const {
2111    if (!isDoubleSpacedVectorAllLanes()) return false;
2112    return VectorList.Count == 3;
2113  }
2114
2115  bool isVecListFourDAllLanes() const {
2116    if (!isSingleSpacedVectorAllLanes()) return false;
2117    return VectorList.Count == 4;
2118  }
2119
2120  bool isVecListFourQAllLanes() const {
2121    if (!isDoubleSpacedVectorAllLanes()) return false;
2122    return VectorList.Count == 4;
2123  }
2124
2125  bool isSingleSpacedVectorIndexed() const {
2126    return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
2127  }
2128
2129  bool isDoubleSpacedVectorIndexed() const {
2130    return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
2131  }
2132
2133  bool isVecListOneDByteIndexed() const {
2134    if (!isSingleSpacedVectorIndexed()) return false;
2135    return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
2136  }
2137
2138  bool isVecListOneDHWordIndexed() const {
2139    if (!isSingleSpacedVectorIndexed()) return false;
2140    return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
2141  }
2142
2143  bool isVecListOneDWordIndexed() const {
2144    if (!isSingleSpacedVectorIndexed()) return false;
2145    return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
2146  }
2147
2148  bool isVecListTwoDByteIndexed() const {
2149    if (!isSingleSpacedVectorIndexed()) return false;
2150    return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
2151  }
2152
2153  bool isVecListTwoDHWordIndexed() const {
2154    if (!isSingleSpacedVectorIndexed()) return false;
2155    return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
2156  }
2157
2158  bool isVecListTwoQWordIndexed() const {
2159    if (!isDoubleSpacedVectorIndexed()) return false;
2160    return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
2161  }
2162
2163  bool isVecListTwoQHWordIndexed() const {
2164    if (!isDoubleSpacedVectorIndexed()) return false;
2165    return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
2166  }
2167
2168  bool isVecListTwoDWordIndexed() const {
2169    if (!isSingleSpacedVectorIndexed()) return false;
2170    return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
2171  }
2172
2173  bool isVecListThreeDByteIndexed() const {
2174    if (!isSingleSpacedVectorIndexed()) return false;
2175    return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
2176  }
2177
2178  bool isVecListThreeDHWordIndexed() const {
2179    if (!isSingleSpacedVectorIndexed()) return false;
2180    return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
2181  }
2182
2183  bool isVecListThreeQWordIndexed() const {
2184    if (!isDoubleSpacedVectorIndexed()) return false;
2185    return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
2186  }
2187
2188  bool isVecListThreeQHWordIndexed() const {
2189    if (!isDoubleSpacedVectorIndexed()) return false;
2190    return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
2191  }
2192
2193  bool isVecListThreeDWordIndexed() const {
2194    if (!isSingleSpacedVectorIndexed()) return false;
2195    return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
2196  }
2197
2198  bool isVecListFourDByteIndexed() const {
2199    if (!isSingleSpacedVectorIndexed()) return false;
2200    return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
2201  }
2202
2203  bool isVecListFourDHWordIndexed() const {
2204    if (!isSingleSpacedVectorIndexed()) return false;
2205    return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
2206  }
2207
2208  bool isVecListFourQWordIndexed() const {
2209    if (!isDoubleSpacedVectorIndexed()) return false;
2210    return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
2211  }
2212
2213  bool isVecListFourQHWordIndexed() const {
2214    if (!isDoubleSpacedVectorIndexed()) return false;
2215    return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
2216  }
2217
2218  bool isVecListFourDWordIndexed() const {
2219    if (!isSingleSpacedVectorIndexed()) return false;
2220    return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
2221  }
2222
2223  bool isVectorIndex() const { return Kind == k_VectorIndex; }
2224
2225  template <unsigned NumLanes>
2226  bool isVectorIndexInRange() const {
2227    if (Kind != k_VectorIndex) return false;
2228    return VectorIndex.Val < NumLanes;
2229  }
2230
2231  bool isVectorIndex8()  const { return isVectorIndexInRange<8>(); }
2232  bool isVectorIndex16() const { return isVectorIndexInRange<4>(); }
2233  bool isVectorIndex32() const { return isVectorIndexInRange<2>(); }
2234  bool isVectorIndex64() const { return isVectorIndexInRange<1>(); }
2235
2236  template<int PermittedValue, int OtherPermittedValue>
2237  bool isMVEPairVectorIndex() const {
2238    if (Kind != k_VectorIndex) return false;
2239    return VectorIndex.Val == PermittedValue ||
2240           VectorIndex.Val == OtherPermittedValue;
2241  }
2242
2243  bool isNEONi8splat() const {
2244    if (!isImm()) return false;
2245    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2246    // Must be a constant.
2247    if (!CE) return false;
2248    int64_t Value = CE->getValue();
2249    // i8 value splatted across 8 bytes. The immediate is just the 8 byte
2250    // value.
2251    return Value >= 0 && Value < 256;
2252  }
2253
2254  bool isNEONi16splat() const {
2255    if (isNEONByteReplicate(2))
2256      return false; // Leave that for bytes replication and forbid by default.
2257    if (!isImm())
2258      return false;
2259    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2260    // Must be a constant.
2261    if (!CE) return false;
2262    unsigned Value = CE->getValue();
2263    return ARM_AM::isNEONi16splat(Value);
2264  }
2265
2266  bool isNEONi16splatNot() const {
2267    if (!isImm())
2268      return false;
2269    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2270    // Must be a constant.
2271    if (!CE) return false;
2272    unsigned Value = CE->getValue();
2273    return ARM_AM::isNEONi16splat(~Value & 0xffff);
2274  }
2275
2276  bool isNEONi32splat() const {
2277    if (isNEONByteReplicate(4))
2278      return false; // Leave that for bytes replication and forbid by default.
2279    if (!isImm())
2280      return false;
2281    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2282    // Must be a constant.
2283    if (!CE) return false;
2284    unsigned Value = CE->getValue();
2285    return ARM_AM::isNEONi32splat(Value);
2286  }
2287
2288  bool isNEONi32splatNot() const {
2289    if (!isImm())
2290      return false;
2291    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2292    // Must be a constant.
2293    if (!CE) return false;
2294    unsigned Value = CE->getValue();
2295    return ARM_AM::isNEONi32splat(~Value);
2296  }
2297
2298  static bool isValidNEONi32vmovImm(int64_t Value) {
2299    // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
2300    // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
2301    return ((Value & 0xffffffffffffff00) == 0) ||
2302           ((Value & 0xffffffffffff00ff) == 0) ||
2303           ((Value & 0xffffffffff00ffff) == 0) ||
2304           ((Value & 0xffffffff00ffffff) == 0) ||
2305           ((Value & 0xffffffffffff00ff) == 0xff) ||
2306           ((Value & 0xffffffffff00ffff) == 0xffff);
2307  }
2308
2309  bool isNEONReplicate(unsigned Width, unsigned NumElems, bool Inv) const {
2310    assert((Width == 8 || Width == 16 || Width == 32) &&
2311           "Invalid element width");
2312    assert(NumElems * Width <= 64 && "Invalid result width");
2313
2314    if (!isImm())
2315      return false;
2316    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2317    // Must be a constant.
2318    if (!CE)
2319      return false;
2320    int64_t Value = CE->getValue();
2321    if (!Value)
2322      return false; // Don't bother with zero.
2323    if (Inv)
2324      Value = ~Value;
2325
2326    uint64_t Mask = (1ull << Width) - 1;
2327    uint64_t Elem = Value & Mask;
2328    if (Width == 16 && (Elem & 0x00ff) != 0 && (Elem & 0xff00) != 0)
2329      return false;
2330    if (Width == 32 && !isValidNEONi32vmovImm(Elem))
2331      return false;
2332
2333    for (unsigned i = 1; i < NumElems; ++i) {
2334      Value >>= Width;
2335      if ((Value & Mask) != Elem)
2336        return false;
2337    }
2338    return true;
2339  }
2340
2341  bool isNEONByteReplicate(unsigned NumBytes) const {
2342    return isNEONReplicate(8, NumBytes, false);
2343  }
2344
2345  static void checkNeonReplicateArgs(unsigned FromW, unsigned ToW) {
2346    assert((FromW == 8 || FromW == 16 || FromW == 32) &&
2347           "Invalid source width");
2348    assert((ToW == 16 || ToW == 32 || ToW == 64) &&
2349           "Invalid destination width");
2350    assert(FromW < ToW && "ToW is not less than FromW");
2351  }
2352
2353  template<unsigned FromW, unsigned ToW>
2354  bool isNEONmovReplicate() const {
2355    checkNeonReplicateArgs(FromW, ToW);
2356    if (ToW == 64 && isNEONi64splat())
2357      return false;
2358    return isNEONReplicate(FromW, ToW / FromW, false);
2359  }
2360
2361  template<unsigned FromW, unsigned ToW>
2362  bool isNEONinvReplicate() const {
2363    checkNeonReplicateArgs(FromW, ToW);
2364    return isNEONReplicate(FromW, ToW / FromW, true);
2365  }
2366
2367  bool isNEONi32vmov() const {
2368    if (isNEONByteReplicate(4))
2369      return false; // Let it to be classified as byte-replicate case.
2370    if (!isImm())
2371      return false;
2372    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2373    // Must be a constant.
2374    if (!CE)
2375      return false;
2376    return isValidNEONi32vmovImm(CE->getValue());
2377  }
2378
2379  bool isNEONi32vmovNeg() const {
2380    if (!isImm()) return false;
2381    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2382    // Must be a constant.
2383    if (!CE) return false;
2384    return isValidNEONi32vmovImm(~CE->getValue());
2385  }
2386
2387  bool isNEONi64splat() const {
2388    if (!isImm()) return false;
2389    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2390    // Must be a constant.
2391    if (!CE) return false;
2392    uint64_t Value = CE->getValue();
2393    // i64 value with each byte being either 0 or 0xff.
2394    for (unsigned i = 0; i < 8; ++i, Value >>= 8)
2395      if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
2396    return true;
2397  }
2398
2399  template<int64_t Angle, int64_t Remainder>
2400  bool isComplexRotation() const {
2401    if (!isImm()) return false;
2402
2403    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2404    if (!CE) return false;
2405    uint64_t Value = CE->getValue();
2406
2407    return (Value % Angle == Remainder && Value <= 270);
2408  }
2409
2410  bool isMVELongShift() const {
2411    if (!isImm()) return false;
2412    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2413    // Must be a constant.
2414    if (!CE) return false;
2415    uint64_t Value = CE->getValue();
2416    return Value >= 1 && Value <= 32;
2417  }
2418
2419  bool isMveSaturateOp() const {
2420    if (!isImm()) return false;
2421    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2422    if (!CE) return false;
2423    uint64_t Value = CE->getValue();
2424    return Value == 48 || Value == 64;
2425  }
2426
2427  bool isITCondCodeNoAL() const {
2428    if (!isITCondCode()) return false;
2429    ARMCC::CondCodes CC = getCondCode();
2430    return CC != ARMCC::AL;
2431  }
2432
2433  bool isITCondCodeRestrictedI() const {
2434    if (!isITCondCode())
2435      return false;
2436    ARMCC::CondCodes CC = getCondCode();
2437    return CC == ARMCC::EQ || CC == ARMCC::NE;
2438  }
2439
2440  bool isITCondCodeRestrictedS() const {
2441    if (!isITCondCode())
2442      return false;
2443    ARMCC::CondCodes CC = getCondCode();
2444    return CC == ARMCC::LT || CC == ARMCC::GT || CC == ARMCC::LE ||
2445           CC == ARMCC::GE;
2446  }
2447
2448  bool isITCondCodeRestrictedU() const {
2449    if (!isITCondCode())
2450      return false;
2451    ARMCC::CondCodes CC = getCondCode();
2452    return CC == ARMCC::HS || CC == ARMCC::HI;
2453  }
2454
2455  bool isITCondCodeRestrictedFP() const {
2456    if (!isITCondCode())
2457      return false;
2458    ARMCC::CondCodes CC = getCondCode();
2459    return CC == ARMCC::EQ || CC == ARMCC::NE || CC == ARMCC::LT ||
2460           CC == ARMCC::GT || CC == ARMCC::LE || CC == ARMCC::GE;
2461  }
2462
2463  void addExpr(MCInst &Inst, const MCExpr *Expr) const {
2464    // Add as immediates when possible.  Null MCExpr = 0.
2465    if (!Expr)
2466      Inst.addOperand(MCOperand::createImm(0));
2467    else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
2468      Inst.addOperand(MCOperand::createImm(CE->getValue()));
2469    else
2470      Inst.addOperand(MCOperand::createExpr(Expr));
2471  }
2472
2473  void addARMBranchTargetOperands(MCInst &Inst, unsigned N) const {
2474    assert(N == 1 && "Invalid number of operands!");
2475    addExpr(Inst, getImm());
2476  }
2477
2478  void addThumbBranchTargetOperands(MCInst &Inst, unsigned N) const {
2479    assert(N == 1 && "Invalid number of operands!");
2480    addExpr(Inst, getImm());
2481  }
2482
2483  void addCondCodeOperands(MCInst &Inst, unsigned N) const {
2484    assert(N == 2 && "Invalid number of operands!");
2485    Inst.addOperand(MCOperand::createImm(unsigned(getCondCode())));
2486    unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
2487    Inst.addOperand(MCOperand::createReg(RegNum));
2488  }
2489
2490  void addVPTPredNOperands(MCInst &Inst, unsigned N) const {
2491    assert(N == 3 && "Invalid number of operands!");
2492    Inst.addOperand(MCOperand::createImm(unsigned(getVPTPred())));
2493    unsigned RegNum = getVPTPred() == ARMVCC::None ? 0: ARM::P0;
2494    Inst.addOperand(MCOperand::createReg(RegNum));
2495    Inst.addOperand(MCOperand::createReg(0));
2496  }
2497
2498  void addVPTPredROperands(MCInst &Inst, unsigned N) const {
2499    assert(N == 4 && "Invalid number of operands!");
2500    addVPTPredNOperands(Inst, N-1);
2501    unsigned RegNum;
2502    if (getVPTPred() == ARMVCC::None) {
2503      RegNum = 0;
2504    } else {
2505      unsigned NextOpIndex = Inst.getNumOperands();
2506      const MCInstrDesc &MCID =
2507          ARMInsts[ARM::INSTRUCTION_LIST_END - 1 - Inst.getOpcode()];
2508      int TiedOp = MCID.getOperandConstraint(NextOpIndex, MCOI::TIED_TO);
2509      assert(TiedOp >= 0 &&
2510             "Inactive register in vpred_r is not tied to an output!");
2511      RegNum = Inst.getOperand(TiedOp).getReg();
2512    }
2513    Inst.addOperand(MCOperand::createReg(RegNum));
2514  }
2515
2516  void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
2517    assert(N == 1 && "Invalid number of operands!");
2518    Inst.addOperand(MCOperand::createImm(getCoproc()));
2519  }
2520
2521  void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
2522    assert(N == 1 && "Invalid number of operands!");
2523    Inst.addOperand(MCOperand::createImm(getCoproc()));
2524  }
2525
2526  void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
2527    assert(N == 1 && "Invalid number of operands!");
2528    Inst.addOperand(MCOperand::createImm(CoprocOption.Val));
2529  }
2530
2531  void addITMaskOperands(MCInst &Inst, unsigned N) const {
2532    assert(N == 1 && "Invalid number of operands!");
2533    Inst.addOperand(MCOperand::createImm(ITMask.Mask));
2534  }
2535
2536  void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
2537    assert(N == 1 && "Invalid number of operands!");
2538    Inst.addOperand(MCOperand::createImm(unsigned(getCondCode())));
2539  }
2540
2541  void addITCondCodeInvOperands(MCInst &Inst, unsigned N) const {
2542    assert(N == 1 && "Invalid number of operands!");
2543    Inst.addOperand(MCOperand::createImm(unsigned(ARMCC::getOppositeCondition(getCondCode()))));
2544  }
2545
2546  void addCCOutOperands(MCInst &Inst, unsigned N) const {
2547    assert(N == 1 && "Invalid number of operands!");
2548    Inst.addOperand(MCOperand::createReg(getReg()));
2549  }
2550
2551  void addRegOperands(MCInst &Inst, unsigned N) const {
2552    assert(N == 1 && "Invalid number of operands!");
2553    Inst.addOperand(MCOperand::createReg(getReg()));
2554  }
2555
2556  void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
2557    assert(N == 3 && "Invalid number of operands!");
2558    assert(isRegShiftedReg() &&
2559           "addRegShiftedRegOperands() on non-RegShiftedReg!");
2560    Inst.addOperand(MCOperand::createReg(RegShiftedReg.SrcReg));
2561    Inst.addOperand(MCOperand::createReg(RegShiftedReg.ShiftReg));
2562    Inst.addOperand(MCOperand::createImm(
2563      ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
2564  }
2565
2566  void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
2567    assert(N == 2 && "Invalid number of operands!");
2568    assert(isRegShiftedImm() &&
2569           "addRegShiftedImmOperands() on non-RegShiftedImm!");
2570    Inst.addOperand(MCOperand::createReg(RegShiftedImm.SrcReg));
2571    // Shift of #32 is encoded as 0 where permitted
2572    unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
2573    Inst.addOperand(MCOperand::createImm(
2574      ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
2575  }
2576
2577  void addShifterImmOperands(MCInst &Inst, unsigned N) const {
2578    assert(N == 1 && "Invalid number of operands!");
2579    Inst.addOperand(MCOperand::createImm((ShifterImm.isASR << 5) |
2580                                         ShifterImm.Imm));
2581  }
2582
2583  void addRegListOperands(MCInst &Inst, unsigned N) const {
2584    assert(N == 1 && "Invalid number of operands!");
2585    const SmallVectorImpl<unsigned> &RegList = getRegList();
2586    for (unsigned Reg : RegList)
2587      Inst.addOperand(MCOperand::createReg(Reg));
2588  }
2589
2590  void addRegListWithAPSROperands(MCInst &Inst, unsigned N) const {
2591    assert(N == 1 && "Invalid number of operands!");
2592    const SmallVectorImpl<unsigned> &RegList = getRegList();
2593    for (unsigned Reg : RegList)
2594      Inst.addOperand(MCOperand::createReg(Reg));
2595  }
2596
2597  void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
2598    addRegListOperands(Inst, N);
2599  }
2600
2601  void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
2602    addRegListOperands(Inst, N);
2603  }
2604
2605  void addFPSRegListWithVPROperands(MCInst &Inst, unsigned N) const {
2606    addRegListOperands(Inst, N);
2607  }
2608
2609  void addFPDRegListWithVPROperands(MCInst &Inst, unsigned N) const {
2610    addRegListOperands(Inst, N);
2611  }
2612
2613  void addRotImmOperands(MCInst &Inst, unsigned N) const {
2614    assert(N == 1 && "Invalid number of operands!");
2615    // Encoded as val>>3. The printer handles display as 8, 16, 24.
2616    Inst.addOperand(MCOperand::createImm(RotImm.Imm >> 3));
2617  }
2618
2619  void addModImmOperands(MCInst &Inst, unsigned N) const {
2620    assert(N == 1 && "Invalid number of operands!");
2621
2622    // Support for fixups (MCFixup)
2623    if (isImm())
2624      return addImmOperands(Inst, N);
2625
2626    Inst.addOperand(MCOperand::createImm(ModImm.Bits | (ModImm.Rot << 7)));
2627  }
2628
2629  void addModImmNotOperands(MCInst &Inst, unsigned N) const {
2630    assert(N == 1 && "Invalid number of operands!");
2631    const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2632    uint32_t Enc = ARM_AM::getSOImmVal(~CE->getValue());
2633    Inst.addOperand(MCOperand::createImm(Enc));
2634  }
2635
2636  void addModImmNegOperands(MCInst &Inst, unsigned N) const {
2637    assert(N == 1 && "Invalid number of operands!");
2638    const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2639    uint32_t Enc = ARM_AM::getSOImmVal(-CE->getValue());
2640    Inst.addOperand(MCOperand::createImm(Enc));
2641  }
2642
2643  void addThumbModImmNeg8_255Operands(MCInst &Inst, unsigned N) const {
2644    assert(N == 1 && "Invalid number of operands!");
2645    const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2646    uint32_t Val = -CE->getValue();
2647    Inst.addOperand(MCOperand::createImm(Val));
2648  }
2649
2650  void addThumbModImmNeg1_7Operands(MCInst &Inst, unsigned N) const {
2651    assert(N == 1 && "Invalid number of operands!");
2652    const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2653    uint32_t Val = -CE->getValue();
2654    Inst.addOperand(MCOperand::createImm(Val));
2655  }
2656
2657  void addBitfieldOperands(MCInst &Inst, unsigned N) const {
2658    assert(N == 1 && "Invalid number of operands!");
2659    // Munge the lsb/width into a bitfield mask.
2660    unsigned lsb = Bitfield.LSB;
2661    unsigned width = Bitfield.Width;
2662    // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
2663    uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
2664                      (32 - (lsb + width)));
2665    Inst.addOperand(MCOperand::createImm(Mask));
2666  }
2667
2668  void addImmOperands(MCInst &Inst, unsigned N) const {
2669    assert(N == 1 && "Invalid number of operands!");
2670    addExpr(Inst, getImm());
2671  }
2672
2673  void addFBits16Operands(MCInst &Inst, unsigned N) const {
2674    assert(N == 1 && "Invalid number of operands!");
2675    const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2676    Inst.addOperand(MCOperand::createImm(16 - CE->getValue()));
2677  }
2678
2679  void addFBits32Operands(MCInst &Inst, unsigned N) const {
2680    assert(N == 1 && "Invalid number of operands!");
2681    const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2682    Inst.addOperand(MCOperand::createImm(32 - CE->getValue()));
2683  }
2684
2685  void addFPImmOperands(MCInst &Inst, unsigned N) const {
2686    assert(N == 1 && "Invalid number of operands!");
2687    const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2688    int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
2689    Inst.addOperand(MCOperand::createImm(Val));
2690  }
2691
2692  void addImm8s4Operands(MCInst &Inst, unsigned N) const {
2693    assert(N == 1 && "Invalid number of operands!");
2694    // FIXME: We really want to scale the value here, but the LDRD/STRD
2695    // instruction don't encode operands that way yet.
2696    const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2697    Inst.addOperand(MCOperand::createImm(CE->getValue()));
2698  }
2699
2700  void addImm7s4Operands(MCInst &Inst, unsigned N) const {
2701    assert(N == 1 && "Invalid number of operands!");
2702    // FIXME: We really want to scale the value here, but the VSTR/VLDR_VSYSR
2703    // instruction don't encode operands that way yet.
2704    const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2705    Inst.addOperand(MCOperand::createImm(CE->getValue()));
2706  }
2707
2708  void addImm7Shift0Operands(MCInst &Inst, unsigned N) const {
2709    assert(N == 1 && "Invalid number of operands!");
2710    const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2711    Inst.addOperand(MCOperand::createImm(CE->getValue()));
2712  }
2713
2714  void addImm7Shift1Operands(MCInst &Inst, unsigned N) const {
2715    assert(N == 1 && "Invalid number of operands!");
2716    const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2717    Inst.addOperand(MCOperand::createImm(CE->getValue()));
2718  }
2719
2720  void addImm7Shift2Operands(MCInst &Inst, unsigned N) const {
2721    assert(N == 1 && "Invalid number of operands!");
2722    const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2723    Inst.addOperand(MCOperand::createImm(CE->getValue()));
2724  }
2725
2726  void addImm7Operands(MCInst &Inst, unsigned N) const {
2727    assert(N == 1 && "Invalid number of operands!");
2728    const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2729    Inst.addOperand(MCOperand::createImm(CE->getValue()));
2730  }
2731
2732  void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
2733    assert(N == 1 && "Invalid number of operands!");
2734    // The immediate is scaled by four in the encoding and is stored
2735    // in the MCInst as such. Lop off the low two bits here.
2736    const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2737    Inst.addOperand(MCOperand::createImm(CE->getValue() / 4));
2738  }
2739
2740  void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
2741    assert(N == 1 && "Invalid number of operands!");
2742    // The immediate is scaled by four in the encoding and is stored
2743    // in the MCInst as such. Lop off the low two bits here.
2744    const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2745    Inst.addOperand(MCOperand::createImm(-(CE->getValue() / 4)));
2746  }
2747
2748  void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
2749    assert(N == 1 && "Invalid number of operands!");
2750    // The immediate is scaled by four in the encoding and is stored
2751    // in the MCInst as such. Lop off the low two bits here.
2752    const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2753    Inst.addOperand(MCOperand::createImm(CE->getValue() / 4));
2754  }
2755
2756  void addImm1_16Operands(MCInst &Inst, unsigned N) const {
2757    assert(N == 1 && "Invalid number of operands!");
2758    // The constant encodes as the immediate-1, and we store in the instruction
2759    // the bits as encoded, so subtract off one here.
2760    const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2761    Inst.addOperand(MCOperand::createImm(CE->getValue() - 1));
2762  }
2763
2764  void addImm1_32Operands(MCInst &Inst, unsigned N) const {
2765    assert(N == 1 && "Invalid number of operands!");
2766    // The constant encodes as the immediate-1, and we store in the instruction
2767    // the bits as encoded, so subtract off one here.
2768    const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2769    Inst.addOperand(MCOperand::createImm(CE->getValue() - 1));
2770  }
2771
2772  void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
2773    assert(N == 1 && "Invalid number of operands!");
2774    // The constant encodes as the immediate, except for 32, which encodes as
2775    // zero.
2776    const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2777    unsigned Imm = CE->getValue();
2778    Inst.addOperand(MCOperand::createImm((Imm == 32 ? 0 : Imm)));
2779  }
2780
2781  void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
2782    assert(N == 1 && "Invalid number of operands!");
2783    // An ASR value of 32 encodes as 0, so that's how we want to add it to
2784    // the instruction as well.
2785    const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2786    int Val = CE->getValue();
2787    Inst.addOperand(MCOperand::createImm(Val == 32 ? 0 : Val));
2788  }
2789
2790  void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
2791    assert(N == 1 && "Invalid number of operands!");
2792    // The operand is actually a t2_so_imm, but we have its bitwise
2793    // negation in the assembly source, so twiddle it here.
2794    const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2795    Inst.addOperand(MCOperand::createImm(~(uint32_t)CE->getValue()));
2796  }
2797
2798  void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
2799    assert(N == 1 && "Invalid number of operands!");
2800    // The operand is actually a t2_so_imm, but we have its
2801    // negation in the assembly source, so twiddle it here.
2802    const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2803    Inst.addOperand(MCOperand::createImm(-(uint32_t)CE->getValue()));
2804  }
2805
2806  void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
2807    assert(N == 1 && "Invalid number of operands!");
2808    // The operand is actually an imm0_4095, but we have its
2809    // negation in the assembly source, so twiddle it here.
2810    const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2811    Inst.addOperand(MCOperand::createImm(-(uint32_t)CE->getValue()));
2812  }
2813
2814  void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const {
2815    if(const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) {
2816      Inst.addOperand(MCOperand::createImm(CE->getValue() >> 2));
2817      return;
2818    }
2819    const MCSymbolRefExpr *SR = cast<MCSymbolRefExpr>(Imm.Val);
2820    Inst.addOperand(MCOperand::createExpr(SR));
2821  }
2822
2823  void addThumbMemPCOperands(MCInst &Inst, unsigned N) const {
2824    assert(N == 1 && "Invalid number of operands!");
2825    if (isImm()) {
2826      const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2827      if (CE) {
2828        Inst.addOperand(MCOperand::createImm(CE->getValue()));
2829        return;
2830      }
2831      const MCSymbolRefExpr *SR = cast<MCSymbolRefExpr>(Imm.Val);
2832      Inst.addOperand(MCOperand::createExpr(SR));
2833      return;
2834    }
2835
2836    assert(isGPRMem()  && "Unknown value type!");
2837    assert(isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!");
2838    if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm))
2839      Inst.addOperand(MCOperand::createImm(CE->getValue()));
2840    else
2841      Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm));
2842  }
2843
2844  void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
2845    assert(N == 1 && "Invalid number of operands!");
2846    Inst.addOperand(MCOperand::createImm(unsigned(getMemBarrierOpt())));
2847  }
2848
2849  void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
2850    assert(N == 1 && "Invalid number of operands!");
2851    Inst.addOperand(MCOperand::createImm(unsigned(getInstSyncBarrierOpt())));
2852  }
2853
2854  void addTraceSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
2855    assert(N == 1 && "Invalid number of operands!");
2856    Inst.addOperand(MCOperand::createImm(unsigned(getTraceSyncBarrierOpt())));
2857  }
2858
2859  void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
2860    assert(N == 1 && "Invalid number of operands!");
2861    Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2862  }
2863
2864  void addMemNoOffsetT2Operands(MCInst &Inst, unsigned N) const {
2865    assert(N == 1 && "Invalid number of operands!");
2866    Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2867  }
2868
2869  void addMemNoOffsetT2NoSpOperands(MCInst &Inst, unsigned N) const {
2870    assert(N == 1 && "Invalid number of operands!");
2871    Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2872  }
2873
2874  void addMemNoOffsetTOperands(MCInst &Inst, unsigned N) const {
2875    assert(N == 1 && "Invalid number of operands!");
2876    Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2877  }
2878
2879  void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
2880    assert(N == 1 && "Invalid number of operands!");
2881    if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm))
2882      Inst.addOperand(MCOperand::createImm(CE->getValue()));
2883    else
2884      Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm));
2885  }
2886
2887  void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
2888    assert(N == 1 && "Invalid number of operands!");
2889    assert(isImm() && "Not an immediate!");
2890
2891    // If we have an immediate that's not a constant, treat it as a label
2892    // reference needing a fixup.
2893    if (!isa<MCConstantExpr>(getImm())) {
2894      Inst.addOperand(MCOperand::createExpr(getImm()));
2895      return;
2896    }
2897
2898    const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2899    int Val = CE->getValue();
2900    Inst.addOperand(MCOperand::createImm(Val));
2901  }
2902
2903  void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
2904    assert(N == 2 && "Invalid number of operands!");
2905    Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2906    Inst.addOperand(MCOperand::createImm(Memory.Alignment));
2907  }
2908
2909  void addDupAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
2910    addAlignedMemoryOperands(Inst, N);
2911  }
2912
2913  void addAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
2914    addAlignedMemoryOperands(Inst, N);
2915  }
2916
2917  void addAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2918    addAlignedMemoryOperands(Inst, N);
2919  }
2920
2921  void addDupAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2922    addAlignedMemoryOperands(Inst, N);
2923  }
2924
2925  void addAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2926    addAlignedMemoryOperands(Inst, N);
2927  }
2928
2929  void addDupAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2930    addAlignedMemoryOperands(Inst, N);
2931  }
2932
2933  void addAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2934    addAlignedMemoryOperands(Inst, N);
2935  }
2936
2937  void addDupAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2938    addAlignedMemoryOperands(Inst, N);
2939  }
2940
2941  void addAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2942    addAlignedMemoryOperands(Inst, N);
2943  }
2944
2945  void addDupAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2946    addAlignedMemoryOperands(Inst, N);
2947  }
2948
2949  void addAlignedMemory64or128or256Operands(MCInst &Inst, unsigned N) const {
2950    addAlignedMemoryOperands(Inst, N);
2951  }
2952
2953  void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
2954    assert(N == 3 && "Invalid number of operands!");
2955    Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2956    Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2957    if (!Memory.OffsetRegNum) {
2958      if (!Memory.OffsetImm)
2959        Inst.addOperand(MCOperand::createImm(0));
2960      else if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
2961        int32_t Val = CE->getValue();
2962        ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2963        // Special case for #-0
2964        if (Val == std::numeric_limits<int32_t>::min())
2965          Val = 0;
2966        if (Val < 0)
2967          Val = -Val;
2968        Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2969        Inst.addOperand(MCOperand::createImm(Val));
2970      } else
2971        Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm));
2972    } else {
2973      // For register offset, we encode the shift type and negation flag
2974      // here.
2975      int32_t Val =
2976          ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2977                            Memory.ShiftImm, Memory.ShiftType);
2978      Inst.addOperand(MCOperand::createImm(Val));
2979    }
2980  }
2981
2982  void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
2983    assert(N == 2 && "Invalid number of operands!");
2984    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2985    assert(CE && "non-constant AM2OffsetImm operand!");
2986    int32_t Val = CE->getValue();
2987    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2988    // Special case for #-0
2989    if (Val == std::numeric_limits<int32_t>::min()) Val = 0;
2990    if (Val < 0) Val = -Val;
2991    Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2992    Inst.addOperand(MCOperand::createReg(0));
2993    Inst.addOperand(MCOperand::createImm(Val));
2994  }
2995
2996  void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
2997    assert(N == 3 && "Invalid number of operands!");
2998    // If we have an immediate that's not a constant, treat it as a label
2999    // reference needing a fixup. If it is a constant, it's something else
3000    // and we reject it.
3001    if (isImm()) {
3002      Inst.addOperand(MCOperand::createExpr(getImm()));
3003      Inst.addOperand(MCOperand::createReg(0));
3004      Inst.addOperand(MCOperand::createImm(0));
3005      return;
3006    }
3007
3008    Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3009    Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
3010    if (!Memory.OffsetRegNum) {
3011      if (!Memory.OffsetImm)
3012        Inst.addOperand(MCOperand::createImm(0));
3013      else if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
3014        int32_t Val = CE->getValue();
3015        ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
3016        // Special case for #-0
3017        if (Val == std::numeric_limits<int32_t>::min())
3018          Val = 0;
3019        if (Val < 0)
3020          Val = -Val;
3021        Val = ARM_AM::getAM3Opc(AddSub, Val);
3022        Inst.addOperand(MCOperand::createImm(Val));
3023      } else
3024        Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm));
3025    } else {
3026      // For register offset, we encode the shift type and negation flag
3027      // here.
3028      int32_t Val =
3029          ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
3030      Inst.addOperand(MCOperand::createImm(Val));
3031    }
3032  }
3033
3034  void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
3035    assert(N == 2 && "Invalid number of operands!");
3036    if (Kind == k_PostIndexRegister) {
3037      int32_t Val =
3038        ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
3039      Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
3040      Inst.addOperand(MCOperand::createImm(Val));
3041      return;
3042    }
3043
3044    // Constant offset.
3045    const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
3046    int32_t Val = CE->getValue();
3047    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
3048    // Special case for #-0
3049    if (Val == std::numeric_limits<int32_t>::min()) Val = 0;
3050    if (Val < 0) Val = -Val;
3051    Val = ARM_AM::getAM3Opc(AddSub, Val);
3052    Inst.addOperand(MCOperand::createReg(0));
3053    Inst.addOperand(MCOperand::createImm(Val));
3054  }
3055
3056  void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
3057    assert(N == 2 && "Invalid number of operands!");
3058    // If we have an immediate that's not a constant, treat it as a label
3059    // reference needing a fixup. If it is a constant, it's something else
3060    // and we reject it.
3061    if (isImm()) {
3062      Inst.addOperand(MCOperand::createExpr(getImm()));
3063      Inst.addOperand(MCOperand::createImm(0));
3064      return;
3065    }
3066
3067    Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3068    if (!Memory.OffsetImm)
3069      Inst.addOperand(MCOperand::createImm(0));
3070    else if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
3071      // The lower two bits are always zero and as such are not encoded.
3072      int32_t Val = CE->getValue() / 4;
3073      ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
3074      // Special case for #-0
3075      if (Val == std::numeric_limits<int32_t>::min())
3076        Val = 0;
3077      if (Val < 0)
3078        Val = -Val;
3079      Val = ARM_AM::getAM5Opc(AddSub, Val);
3080      Inst.addOperand(MCOperand::createImm(Val));
3081    } else
3082      Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm));
3083  }
3084
3085  void addAddrMode5FP16Operands(MCInst &Inst, unsigned N) const {
3086    assert(N == 2 && "Invalid number of operands!");
3087    // If we have an immediate that's not a constant, treat it as a label
3088    // reference needing a fixup. If it is a constant, it's something else
3089    // and we reject it.
3090    if (isImm()) {
3091      Inst.addOperand(MCOperand::createExpr(getImm()));
3092      Inst.addOperand(MCOperand::createImm(0));
3093      return;
3094    }
3095
3096    Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3097    // The lower bit is always zero and as such is not encoded.
3098    if (!Memory.OffsetImm)
3099      Inst.addOperand(MCOperand::createImm(0));
3100    else if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
3101      int32_t Val = CE->getValue() / 2;
3102      ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
3103      // Special case for #-0
3104      if (Val == std::numeric_limits<int32_t>::min())
3105        Val = 0;
3106      if (Val < 0)
3107        Val = -Val;
3108      Val = ARM_AM::getAM5FP16Opc(AddSub, Val);
3109      Inst.addOperand(MCOperand::createImm(Val));
3110    } else
3111      Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm));
3112  }
3113
3114  void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
3115    assert(N == 2 && "Invalid number of operands!");
3116    // If we have an immediate that's not a constant, treat it as a label
3117    // reference needing a fixup. If it is a constant, it's something else
3118    // and we reject it.
3119    if (isImm()) {
3120      Inst.addOperand(MCOperand::createExpr(getImm()));
3121      Inst.addOperand(MCOperand::createImm(0));
3122      return;
3123    }
3124
3125    Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3126    addExpr(Inst, Memory.OffsetImm);
3127  }
3128
3129  void addMemImm7s4OffsetOperands(MCInst &Inst, unsigned N) const {
3130    assert(N == 2 && "Invalid number of operands!");
3131    // If we have an immediate that's not a constant, treat it as a label
3132    // reference needing a fixup. If it is a constant, it's something else
3133    // and we reject it.
3134    if (isImm()) {
3135      Inst.addOperand(MCOperand::createExpr(getImm()));
3136      Inst.addOperand(MCOperand::createImm(0));
3137      return;
3138    }
3139
3140    Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3141    addExpr(Inst, Memory.OffsetImm);
3142  }
3143
3144  void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
3145    assert(N == 2 && "Invalid number of operands!");
3146    Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3147    if (!Memory.OffsetImm)
3148      Inst.addOperand(MCOperand::createImm(0));
3149    else if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm))
3150      // The lower two bits are always zero and as such are not encoded.
3151      Inst.addOperand(MCOperand::createImm(CE->getValue() / 4));
3152    else
3153      Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm));
3154  }
3155
3156  void addMemImmOffsetOperands(MCInst &Inst, unsigned N) const {
3157    assert(N == 2 && "Invalid number of operands!");
3158    Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3159    addExpr(Inst, Memory.OffsetImm);
3160  }
3161
3162  void addMemRegRQOffsetOperands(MCInst &Inst, unsigned N) const {
3163    assert(N == 2 && "Invalid number of operands!");
3164    Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3165    Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
3166  }
3167
3168  void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
3169    assert(N == 2 && "Invalid number of operands!");
3170    // If this is an immediate, it's a label reference.
3171    if (isImm()) {
3172      addExpr(Inst, getImm());
3173      Inst.addOperand(MCOperand::createImm(0));
3174      return;
3175    }
3176
3177    // Otherwise, it's a normal memory reg+offset.
3178    Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3179    addExpr(Inst, Memory.OffsetImm);
3180  }
3181
3182  void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
3183    assert(N == 2 && "Invalid number of operands!");
3184    // If this is an immediate, it's a label reference.
3185    if (isImm()) {
3186      addExpr(Inst, getImm());
3187      Inst.addOperand(MCOperand::createImm(0));
3188      return;
3189    }
3190
3191    // Otherwise, it's a normal memory reg+offset.
3192    Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3193    addExpr(Inst, Memory.OffsetImm);
3194  }
3195
3196  void addConstPoolAsmImmOperands(MCInst &Inst, unsigned N) const {
3197    assert(N == 1 && "Invalid number of operands!");
3198    // This is container for the immediate that we will create the constant
3199    // pool from
3200    addExpr(Inst, getConstantPoolImm());
3201  }
3202
3203  void addMemTBBOperands(MCInst &Inst, unsigned N) const {
3204    assert(N == 2 && "Invalid number of operands!");
3205    Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3206    Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
3207  }
3208
3209  void addMemTBHOperands(MCInst &Inst, unsigned N) const {
3210    assert(N == 2 && "Invalid number of operands!");
3211    Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3212    Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
3213  }
3214
3215  void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
3216    assert(N == 3 && "Invalid number of operands!");
3217    unsigned Val =
3218      ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
3219                        Memory.ShiftImm, Memory.ShiftType);
3220    Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3221    Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
3222    Inst.addOperand(MCOperand::createImm(Val));
3223  }
3224
3225  void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
3226    assert(N == 3 && "Invalid number of operands!");
3227    Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3228    Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
3229    Inst.addOperand(MCOperand::createImm(Memory.ShiftImm));
3230  }
3231
3232  void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
3233    assert(N == 2 && "Invalid number of operands!");
3234    Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3235    Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
3236  }
3237
3238  void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
3239    assert(N == 2 && "Invalid number of operands!");
3240    Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3241    if (!Memory.OffsetImm)
3242      Inst.addOperand(MCOperand::createImm(0));
3243    else if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm))
3244      // The lower two bits are always zero and as such are not encoded.
3245      Inst.addOperand(MCOperand::createImm(CE->getValue() / 4));
3246    else
3247      Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm));
3248  }
3249
3250  void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
3251    assert(N == 2 && "Invalid number of operands!");
3252    Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3253    if (!Memory.OffsetImm)
3254      Inst.addOperand(MCOperand::createImm(0));
3255    else if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm))
3256      Inst.addOperand(MCOperand::createImm(CE->getValue() / 2));
3257    else
3258      Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm));
3259  }
3260
3261  void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
3262    assert(N == 2 && "Invalid number of operands!");
3263    Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3264    addExpr(Inst, Memory.OffsetImm);
3265  }
3266
3267  void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
3268    assert(N == 2 && "Invalid number of operands!");
3269    Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3270    if (!Memory.OffsetImm)
3271      Inst.addOperand(MCOperand::createImm(0));
3272    else if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm))
3273      // The lower two bits are always zero and as such are not encoded.
3274      Inst.addOperand(MCOperand::createImm(CE->getValue() / 4));
3275    else
3276      Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm));
3277  }
3278
3279  void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
3280    assert(N == 1 && "Invalid number of operands!");
3281    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
3282    assert(CE && "non-constant post-idx-imm8 operand!");
3283    int Imm = CE->getValue();
3284    bool isAdd = Imm >= 0;
3285    if (Imm == std::numeric_limits<int32_t>::min()) Imm = 0;
3286    Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
3287    Inst.addOperand(MCOperand::createImm(Imm));
3288  }
3289
3290  void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
3291    assert(N == 1 && "Invalid number of operands!");
3292    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
3293    assert(CE && "non-constant post-idx-imm8s4 operand!");
3294    int Imm = CE->getValue();
3295    bool isAdd = Imm >= 0;
3296    if (Imm == std::numeric_limits<int32_t>::min()) Imm = 0;
3297    // Immediate is scaled by 4.
3298    Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
3299    Inst.addOperand(MCOperand::createImm(Imm));
3300  }
3301
3302  void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
3303    assert(N == 2 && "Invalid number of operands!");
3304    Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
3305    Inst.addOperand(MCOperand::createImm(PostIdxReg.isAdd));
3306  }
3307
3308  void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
3309    assert(N == 2 && "Invalid number of operands!");
3310    Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
3311    // The sign, shift type, and shift amount are encoded in a single operand
3312    // using the AM2 encoding helpers.
3313    ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
3314    unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
3315                                     PostIdxReg.ShiftTy);
3316    Inst.addOperand(MCOperand::createImm(Imm));
3317  }
3318
3319  void addPowerTwoOperands(MCInst &Inst, unsigned N) const {
3320    assert(N == 1 && "Invalid number of operands!");
3321    const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3322    Inst.addOperand(MCOperand::createImm(CE->getValue()));
3323  }
3324
3325  void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
3326    assert(N == 1 && "Invalid number of operands!");
3327    Inst.addOperand(MCOperand::createImm(unsigned(getMSRMask())));
3328  }
3329
3330  void addBankedRegOperands(MCInst &Inst, unsigned N) const {
3331    assert(N == 1 && "Invalid number of operands!");
3332    Inst.addOperand(MCOperand::createImm(unsigned(getBankedReg())));
3333  }
3334
3335  void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
3336    assert(N == 1 && "Invalid number of operands!");
3337    Inst.addOperand(MCOperand::createImm(unsigned(getProcIFlags())));
3338  }
3339
3340  void addVecListOperands(MCInst &Inst, unsigned N) const {
3341    assert(N == 1 && "Invalid number of operands!");
3342    Inst.addOperand(MCOperand::createReg(VectorList.RegNum));
3343  }
3344
3345  void addMVEVecListOperands(MCInst &Inst, unsigned N) const {
3346    assert(N == 1 && "Invalid number of operands!");
3347
3348    // When we come here, the VectorList field will identify a range
3349    // of q-registers by its base register and length, and it will
3350    // have already been error-checked to be the expected length of
3351    // range and contain only q-regs in the range q0-q7. So we can
3352    // count on the base register being in the range q0-q6 (for 2
3353    // regs) or q0-q4 (for 4)
3354    //
3355    // The MVE instructions taking a register range of this kind will
3356    // need an operand in the MQQPR or MQQQQPR class, representing the
3357    // entire range as a unit. So we must translate into that class,
3358    // by finding the index of the base register in the MQPR reg
3359    // class, and returning the super-register at the corresponding
3360    // index in the target class.
3361
3362    const MCRegisterClass *RC_in = &ARMMCRegisterClasses[ARM::MQPRRegClassID];
3363    const MCRegisterClass *RC_out =
3364        (VectorList.Count == 2) ? &ARMMCRegisterClasses[ARM::MQQPRRegClassID]
3365                                : &ARMMCRegisterClasses[ARM::MQQQQPRRegClassID];
3366
3367    unsigned I, E = RC_out->getNumRegs();
3368    for (I = 0; I < E; I++)
3369      if (RC_in->getRegister(I) == VectorList.RegNum)
3370        break;
3371    assert(I < E && "Invalid vector list start register!");
3372
3373    Inst.addOperand(MCOperand::createReg(RC_out->getRegister(I)));
3374  }
3375
3376  void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
3377    assert(N == 2 && "Invalid number of operands!");
3378    Inst.addOperand(MCOperand::createReg(VectorList.RegNum));
3379    Inst.addOperand(MCOperand::createImm(VectorList.LaneIndex));
3380  }
3381
3382  void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
3383    assert(N == 1 && "Invalid number of operands!");
3384    Inst.addOperand(MCOperand::createImm(getVectorIndex()));
3385  }
3386
3387  void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
3388    assert(N == 1 && "Invalid number of operands!");
3389    Inst.addOperand(MCOperand::createImm(getVectorIndex()));
3390  }
3391
3392  void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
3393    assert(N == 1 && "Invalid number of operands!");
3394    Inst.addOperand(MCOperand::createImm(getVectorIndex()));
3395  }
3396
3397  void addVectorIndex64Operands(MCInst &Inst, unsigned N) const {
3398    assert(N == 1 && "Invalid number of operands!");
3399    Inst.addOperand(MCOperand::createImm(getVectorIndex()));
3400  }
3401
3402  void addMVEVectorIndexOperands(MCInst &Inst, unsigned N) const {
3403    assert(N == 1 && "Invalid number of operands!");
3404    Inst.addOperand(MCOperand::createImm(getVectorIndex()));
3405  }
3406
3407  void addMVEPairVectorIndexOperands(MCInst &Inst, unsigned N) const {
3408    assert(N == 1 && "Invalid number of operands!");
3409    Inst.addOperand(MCOperand::createImm(getVectorIndex()));
3410  }
3411
3412  void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
3413    assert(N == 1 && "Invalid number of operands!");
3414    // The immediate encodes the type of constant as well as the value.
3415    // Mask in that this is an i8 splat.
3416    const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3417    Inst.addOperand(MCOperand::createImm(CE->getValue() | 0xe00));
3418  }
3419
3420  void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
3421    assert(N == 1 && "Invalid number of operands!");
3422    // The immediate encodes the type of constant as well as the value.
3423    const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3424    unsigned Value = CE->getValue();
3425    Value = ARM_AM::encodeNEONi16splat(Value);
3426    Inst.addOperand(MCOperand::createImm(Value));
3427  }
3428
3429  void addNEONi16splatNotOperands(MCInst &Inst, unsigned N) const {
3430    assert(N == 1 && "Invalid number of operands!");
3431    // The immediate encodes the type of constant as well as the value.
3432    const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3433    unsigned Value = CE->getValue();
3434    Value = ARM_AM::encodeNEONi16splat(~Value & 0xffff);
3435    Inst.addOperand(MCOperand::createImm(Value));
3436  }
3437
3438  void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
3439    assert(N == 1 && "Invalid number of operands!");
3440    // The immediate encodes the type of constant as well as the value.
3441    const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3442    unsigned Value = CE->getValue();
3443    Value = ARM_AM::encodeNEONi32splat(Value);
3444    Inst.addOperand(MCOperand::createImm(Value));
3445  }
3446
3447  void addNEONi32splatNotOperands(MCInst &Inst, unsigned N) const {
3448    assert(N == 1 && "Invalid number of operands!");
3449    // The immediate encodes the type of constant as well as the value.
3450    const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3451    unsigned Value = CE->getValue();
3452    Value = ARM_AM::encodeNEONi32splat(~Value);
3453    Inst.addOperand(MCOperand::createImm(Value));
3454  }
3455
3456  void addNEONi8ReplicateOperands(MCInst &Inst, bool Inv) const {
3457    // The immediate encodes the type of constant as well as the value.
3458    const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3459    assert((Inst.getOpcode() == ARM::VMOVv8i8 ||
3460            Inst.getOpcode() == ARM::VMOVv16i8) &&
3461          "All instructions that wants to replicate non-zero byte "
3462          "always must be replaced with VMOVv8i8 or VMOVv16i8.");
3463    unsigned Value = CE->getValue();
3464    if (Inv)
3465      Value = ~Value;
3466    unsigned B = Value & 0xff;
3467    B |= 0xe00; // cmode = 0b1110
3468    Inst.addOperand(MCOperand::createImm(B));
3469  }
3470
3471  void addNEONinvi8ReplicateOperands(MCInst &Inst, unsigned N) const {
3472    assert(N == 1 && "Invalid number of operands!");
3473    addNEONi8ReplicateOperands(Inst, true);
3474  }
3475
3476  static unsigned encodeNeonVMOVImmediate(unsigned Value) {
3477    if (Value >= 256 && Value <= 0xffff)
3478      Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
3479    else if (Value > 0xffff && Value <= 0xffffff)
3480      Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
3481    else if (Value > 0xffffff)
3482      Value = (Value >> 24) | 0x600;
3483    return Value;
3484  }
3485
3486  void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
3487    assert(N == 1 && "Invalid number of operands!");
3488    // The immediate encodes the type of constant as well as the value.
3489    const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3490    unsigned Value = encodeNeonVMOVImmediate(CE->getValue());
3491    Inst.addOperand(MCOperand::createImm(Value));
3492  }
3493
3494  void addNEONvmovi8ReplicateOperands(MCInst &Inst, unsigned N) const {
3495    assert(N == 1 && "Invalid number of operands!");
3496    addNEONi8ReplicateOperands(Inst, false);
3497  }
3498
3499  void addNEONvmovi16ReplicateOperands(MCInst &Inst, unsigned N) const {
3500    assert(N == 1 && "Invalid number of operands!");
3501    const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3502    assert((Inst.getOpcode() == ARM::VMOVv4i16 ||
3503            Inst.getOpcode() == ARM::VMOVv8i16 ||
3504            Inst.getOpcode() == ARM::VMVNv4i16 ||
3505            Inst.getOpcode() == ARM::VMVNv8i16) &&
3506          "All instructions that want to replicate non-zero half-word "
3507          "always must be replaced with V{MOV,MVN}v{4,8}i16.");
3508    uint64_t Value = CE->getValue();
3509    unsigned Elem = Value & 0xffff;
3510    if (Elem >= 256)
3511      Elem = (Elem >> 8) | 0x200;
3512    Inst.addOperand(MCOperand::createImm(Elem));
3513  }
3514
3515  void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
3516    assert(N == 1 && "Invalid number of operands!");
3517    // The immediate encodes the type of constant as well as the value.
3518    const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3519    unsigned Value = encodeNeonVMOVImmediate(~CE->getValue());
3520    Inst.addOperand(MCOperand::createImm(Value));
3521  }
3522
3523  void addNEONvmovi32ReplicateOperands(MCInst &Inst, unsigned N) const {
3524    assert(N == 1 && "Invalid number of operands!");
3525    const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3526    assert((Inst.getOpcode() == ARM::VMOVv2i32 ||
3527            Inst.getOpcode() == ARM::VMOVv4i32 ||
3528            Inst.getOpcode() == ARM::VMVNv2i32 ||
3529            Inst.getOpcode() == ARM::VMVNv4i32) &&
3530          "All instructions that want to replicate non-zero word "
3531          "always must be replaced with V{MOV,MVN}v{2,4}i32.");
3532    uint64_t Value = CE->getValue();
3533    unsigned Elem = encodeNeonVMOVImmediate(Value & 0xffffffff);
3534    Inst.addOperand(MCOperand::createImm(Elem));
3535  }
3536
3537  void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
3538    assert(N == 1 && "Invalid number of operands!");
3539    // The immediate encodes the type of constant as well as the value.
3540    const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3541    uint64_t Value = CE->getValue();
3542    unsigned Imm = 0;
3543    for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
3544      Imm |= (Value & 1) << i;
3545    }
3546    Inst.addOperand(MCOperand::createImm(Imm | 0x1e00));
3547  }
3548
3549  void addComplexRotationEvenOperands(MCInst &Inst, unsigned N) const {
3550    assert(N == 1 && "Invalid number of operands!");
3551    const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3552    Inst.addOperand(MCOperand::createImm(CE->getValue() / 90));
3553  }
3554
3555  void addComplexRotationOddOperands(MCInst &Inst, unsigned N) const {
3556    assert(N == 1 && "Invalid number of operands!");
3557    const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3558    Inst.addOperand(MCOperand::createImm((CE->getValue() - 90) / 180));
3559  }
3560
3561  void addMveSaturateOperands(MCInst &Inst, unsigned N) const {
3562    assert(N == 1 && "Invalid number of operands!");
3563    const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3564    unsigned Imm = CE->getValue();
3565    assert((Imm == 48 || Imm == 64) && "Invalid saturate operand");
3566    Inst.addOperand(MCOperand::createImm(Imm == 48 ? 1 : 0));
3567  }
3568
3569  void print(raw_ostream &OS) const override;
3570
3571  static std::unique_ptr<ARMOperand> CreateITMask(unsigned Mask, SMLoc S) {
3572    auto Op = std::make_unique<ARMOperand>(k_ITCondMask);
3573    Op->ITMask.Mask = Mask;
3574    Op->StartLoc = S;
3575    Op->EndLoc = S;
3576    return Op;
3577  }
3578
3579  static std::unique_ptr<ARMOperand> CreateCondCode(ARMCC::CondCodes CC,
3580                                                    SMLoc S) {
3581    auto Op = std::make_unique<ARMOperand>(k_CondCode);
3582    Op->CC.Val = CC;
3583    Op->StartLoc = S;
3584    Op->EndLoc = S;
3585    return Op;
3586  }
3587
3588  static std::unique_ptr<ARMOperand> CreateVPTPred(ARMVCC::VPTCodes CC,
3589                                                   SMLoc S) {
3590    auto Op = std::make_unique<ARMOperand>(k_VPTPred);
3591    Op->VCC.Val = CC;
3592    Op->StartLoc = S;
3593    Op->EndLoc = S;
3594    return Op;
3595  }
3596
3597  static std::unique_ptr<ARMOperand> CreateCoprocNum(unsigned CopVal, SMLoc S) {
3598    auto Op = std::make_unique<ARMOperand>(k_CoprocNum);
3599    Op->Cop.Val = CopVal;
3600    Op->StartLoc = S;
3601    Op->EndLoc = S;
3602    return Op;
3603  }
3604
3605  static std::unique_ptr<ARMOperand> CreateCoprocReg(unsigned CopVal, SMLoc S) {
3606    auto Op = std::make_unique<ARMOperand>(k_CoprocReg);
3607    Op->Cop.Val = CopVal;
3608    Op->StartLoc = S;
3609    Op->EndLoc = S;
3610    return Op;
3611  }
3612
3613  static std::unique_ptr<ARMOperand> CreateCoprocOption(unsigned Val, SMLoc S,
3614                                                        SMLoc E) {
3615    auto Op = std::make_unique<ARMOperand>(k_CoprocOption);
3616    Op->Cop.Val = Val;
3617    Op->StartLoc = S;
3618    Op->EndLoc = E;
3619    return Op;
3620  }
3621
3622  static std::unique_ptr<ARMOperand> CreateCCOut(unsigned RegNum, SMLoc S) {
3623    auto Op = std::make_unique<ARMOperand>(k_CCOut);
3624    Op->Reg.RegNum = RegNum;
3625    Op->StartLoc = S;
3626    Op->EndLoc = S;
3627    return Op;
3628  }
3629
3630  static std::unique_ptr<ARMOperand> CreateToken(StringRef Str, SMLoc S) {
3631    auto Op = std::make_unique<ARMOperand>(k_Token);
3632    Op->Tok.Data = Str.data();
3633    Op->Tok.Length = Str.size();
3634    Op->StartLoc = S;
3635    Op->EndLoc = S;
3636    return Op;
3637  }
3638
3639  static std::unique_ptr<ARMOperand> CreateReg(unsigned RegNum, SMLoc S,
3640                                               SMLoc E) {
3641    auto Op = std::make_unique<ARMOperand>(k_Register);
3642    Op->Reg.RegNum = RegNum;
3643    Op->StartLoc = S;
3644    Op->EndLoc = E;
3645    return Op;
3646  }
3647
3648  static std::unique_ptr<ARMOperand>
3649  CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
3650                        unsigned ShiftReg, unsigned ShiftImm, SMLoc S,
3651                        SMLoc E) {
3652    auto Op = std::make_unique<ARMOperand>(k_ShiftedRegister);
3653    Op->RegShiftedReg.ShiftTy = ShTy;
3654    Op->RegShiftedReg.SrcReg = SrcReg;
3655    Op->RegShiftedReg.ShiftReg = ShiftReg;
3656    Op->RegShiftedReg.ShiftImm = ShiftImm;
3657    Op->StartLoc = S;
3658    Op->EndLoc = E;
3659    return Op;
3660  }
3661
3662  static std::unique_ptr<ARMOperand>
3663  CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
3664                         unsigned ShiftImm, SMLoc S, SMLoc E) {
3665    auto Op = std::make_unique<ARMOperand>(k_ShiftedImmediate);
3666    Op->RegShiftedImm.ShiftTy = ShTy;
3667    Op->RegShiftedImm.SrcReg = SrcReg;
3668    Op->RegShiftedImm.ShiftImm = ShiftImm;
3669    Op->StartLoc = S;
3670    Op->EndLoc = E;
3671    return Op;
3672  }
3673
3674  static std::unique_ptr<ARMOperand> CreateShifterImm(bool isASR, unsigned Imm,
3675                                                      SMLoc S, SMLoc E) {
3676    auto Op = std::make_unique<ARMOperand>(k_ShifterImmediate);
3677    Op->ShifterImm.isASR = isASR;
3678    Op->ShifterImm.Imm = Imm;
3679    Op->StartLoc = S;
3680    Op->EndLoc = E;
3681    return Op;
3682  }
3683
3684  static std::unique_ptr<ARMOperand> CreateRotImm(unsigned Imm, SMLoc S,
3685                                                  SMLoc E) {
3686    auto Op = std::make_unique<ARMOperand>(k_RotateImmediate);
3687    Op->RotImm.Imm = Imm;
3688    Op->StartLoc = S;
3689    Op->EndLoc = E;
3690    return Op;
3691  }
3692
3693  static std::unique_ptr<ARMOperand> CreateModImm(unsigned Bits, unsigned Rot,
3694                                                  SMLoc S, SMLoc E) {
3695    auto Op = std::make_unique<ARMOperand>(k_ModifiedImmediate);
3696    Op->ModImm.Bits = Bits;
3697    Op->ModImm.Rot = Rot;
3698    Op->StartLoc = S;
3699    Op->EndLoc = E;
3700    return Op;
3701  }
3702
3703  static std::unique_ptr<ARMOperand>
3704  CreateConstantPoolImm(const MCExpr *Val, SMLoc S, SMLoc E) {
3705    auto Op = std::make_unique<ARMOperand>(k_ConstantPoolImmediate);
3706    Op->Imm.Val = Val;
3707    Op->StartLoc = S;
3708    Op->EndLoc = E;
3709    return Op;
3710  }
3711
3712  static std::unique_ptr<ARMOperand>
3713  CreateBitfield(unsigned LSB, unsigned Width, SMLoc S, SMLoc E) {
3714    auto Op = std::make_unique<ARMOperand>(k_BitfieldDescriptor);
3715    Op->Bitfield.LSB = LSB;
3716    Op->Bitfield.Width = Width;
3717    Op->StartLoc = S;
3718    Op->EndLoc = E;
3719    return Op;
3720  }
3721
3722  static std::unique_ptr<ARMOperand>
3723  CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned>> &Regs,
3724                SMLoc StartLoc, SMLoc EndLoc) {
3725    assert(Regs.size() > 0 && "RegList contains no registers?");
3726    KindTy Kind = k_RegisterList;
3727
3728    if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(
3729            Regs.front().second)) {
3730      if (Regs.back().second == ARM::VPR)
3731        Kind = k_FPDRegisterListWithVPR;
3732      else
3733        Kind = k_DPRRegisterList;
3734    } else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(
3735                   Regs.front().second)) {
3736      if (Regs.back().second == ARM::VPR)
3737        Kind = k_FPSRegisterListWithVPR;
3738      else
3739        Kind = k_SPRRegisterList;
3740    }
3741
3742    if (Kind == k_RegisterList && Regs.back().second == ARM::APSR)
3743      Kind = k_RegisterListWithAPSR;
3744
3745    assert(llvm::is_sorted(Regs) && "Register list must be sorted by encoding");
3746
3747    auto Op = std::make_unique<ARMOperand>(Kind);
3748    for (const auto &P : Regs)
3749      Op->Registers.push_back(P.second);
3750
3751    Op->StartLoc = StartLoc;
3752    Op->EndLoc = EndLoc;
3753    return Op;
3754  }
3755
3756  static std::unique_ptr<ARMOperand> CreateVectorList(unsigned RegNum,
3757                                                      unsigned Count,
3758                                                      bool isDoubleSpaced,
3759                                                      SMLoc S, SMLoc E) {
3760    auto Op = std::make_unique<ARMOperand>(k_VectorList);
3761    Op->VectorList.RegNum = RegNum;
3762    Op->VectorList.Count = Count;
3763    Op->VectorList.isDoubleSpaced = isDoubleSpaced;
3764    Op->StartLoc = S;
3765    Op->EndLoc = E;
3766    return Op;
3767  }
3768
3769  static std::unique_ptr<ARMOperand>
3770  CreateVectorListAllLanes(unsigned RegNum, unsigned Count, bool isDoubleSpaced,
3771                           SMLoc S, SMLoc E) {
3772    auto Op = std::make_unique<ARMOperand>(k_VectorListAllLanes);
3773    Op->VectorList.RegNum = RegNum;
3774    Op->VectorList.Count = Count;
3775    Op->VectorList.isDoubleSpaced = isDoubleSpaced;
3776    Op->StartLoc = S;
3777    Op->EndLoc = E;
3778    return Op;
3779  }
3780
3781  static std::unique_ptr<ARMOperand>
3782  CreateVectorListIndexed(unsigned RegNum, unsigned Count, unsigned Index,
3783                          bool isDoubleSpaced, SMLoc S, SMLoc E) {
3784    auto Op = std::make_unique<ARMOperand>(k_VectorListIndexed);
3785    Op->VectorList.RegNum = RegNum;
3786    Op->VectorList.Count = Count;
3787    Op->VectorList.LaneIndex = Index;
3788    Op->VectorList.isDoubleSpaced = isDoubleSpaced;
3789    Op->StartLoc = S;
3790    Op->EndLoc = E;
3791    return Op;
3792  }
3793
3794  static std::unique_ptr<ARMOperand>
3795  CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E, MCContext &Ctx) {
3796    auto Op = std::make_unique<ARMOperand>(k_VectorIndex);
3797    Op->VectorIndex.Val = Idx;
3798    Op->StartLoc = S;
3799    Op->EndLoc = E;
3800    return Op;
3801  }
3802
3803  static std::unique_ptr<ARMOperand> CreateImm(const MCExpr *Val, SMLoc S,
3804                                               SMLoc E) {
3805    auto Op = std::make_unique<ARMOperand>(k_Immediate);
3806    Op->Imm.Val = Val;
3807    Op->StartLoc = S;
3808    Op->EndLoc = E;
3809    return Op;
3810  }
3811
3812  static std::unique_ptr<ARMOperand>
3813  CreateMem(unsigned BaseRegNum, const MCExpr *OffsetImm, unsigned OffsetRegNum,
3814            ARM_AM::ShiftOpc ShiftType, unsigned ShiftImm, unsigned Alignment,
3815            bool isNegative, SMLoc S, SMLoc E, SMLoc AlignmentLoc = SMLoc()) {
3816    auto Op = std::make_unique<ARMOperand>(k_Memory);
3817    Op->Memory.BaseRegNum = BaseRegNum;
3818    Op->Memory.OffsetImm = OffsetImm;
3819    Op->Memory.OffsetRegNum = OffsetRegNum;
3820    Op->Memory.ShiftType = ShiftType;
3821    Op->Memory.ShiftImm = ShiftImm;
3822    Op->Memory.Alignment = Alignment;
3823    Op->Memory.isNegative = isNegative;
3824    Op->StartLoc = S;
3825    Op->EndLoc = E;
3826    Op->AlignmentLoc = AlignmentLoc;
3827    return Op;
3828  }
3829
3830  static std::unique_ptr<ARMOperand>
3831  CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy,
3832                   unsigned ShiftImm, SMLoc S, SMLoc E) {
3833    auto Op = std::make_unique<ARMOperand>(k_PostIndexRegister);
3834    Op->PostIdxReg.RegNum = RegNum;
3835    Op->PostIdxReg.isAdd = isAdd;
3836    Op->PostIdxReg.ShiftTy = ShiftTy;
3837    Op->PostIdxReg.ShiftImm = ShiftImm;
3838    Op->StartLoc = S;
3839    Op->EndLoc = E;
3840    return Op;
3841  }
3842
3843  static std::unique_ptr<ARMOperand> CreateMemBarrierOpt(ARM_MB::MemBOpt Opt,
3844                                                         SMLoc S) {
3845    auto Op = std::make_unique<ARMOperand>(k_MemBarrierOpt);
3846    Op->MBOpt.Val = Opt;
3847    Op->StartLoc = S;
3848    Op->EndLoc = S;
3849    return Op;
3850  }
3851
3852  static std::unique_ptr<ARMOperand>
3853  CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt, SMLoc S) {
3854    auto Op = std::make_unique<ARMOperand>(k_InstSyncBarrierOpt);
3855    Op->ISBOpt.Val = Opt;
3856    Op->StartLoc = S;
3857    Op->EndLoc = S;
3858    return Op;
3859  }
3860
3861  static std::unique_ptr<ARMOperand>
3862  CreateTraceSyncBarrierOpt(ARM_TSB::TraceSyncBOpt Opt, SMLoc S) {
3863    auto Op = std::make_unique<ARMOperand>(k_TraceSyncBarrierOpt);
3864    Op->TSBOpt.Val = Opt;
3865    Op->StartLoc = S;
3866    Op->EndLoc = S;
3867    return Op;
3868  }
3869
3870  static std::unique_ptr<ARMOperand> CreateProcIFlags(ARM_PROC::IFlags IFlags,
3871                                                      SMLoc S) {
3872    auto Op = std::make_unique<ARMOperand>(k_ProcIFlags);
3873    Op->IFlags.Val = IFlags;
3874    Op->StartLoc = S;
3875    Op->EndLoc = S;
3876    return Op;
3877  }
3878
3879  static std::unique_ptr<ARMOperand> CreateMSRMask(unsigned MMask, SMLoc S) {
3880    auto Op = std::make_unique<ARMOperand>(k_MSRMask);
3881    Op->MMask.Val = MMask;
3882    Op->StartLoc = S;
3883    Op->EndLoc = S;
3884    return Op;
3885  }
3886
3887  static std::unique_ptr<ARMOperand> CreateBankedReg(unsigned Reg, SMLoc S) {
3888    auto Op = std::make_unique<ARMOperand>(k_BankedReg);
3889    Op->BankedReg.Val = Reg;
3890    Op->StartLoc = S;
3891    Op->EndLoc = S;
3892    return Op;
3893  }
3894};
3895
3896} // end anonymous namespace.
3897
3898void ARMOperand::print(raw_ostream &OS) const {
3899  auto RegName = [](MCRegister Reg) {
3900    if (Reg)
3901      return ARMInstPrinter::getRegisterName(Reg);
3902    else
3903      return "noreg";
3904  };
3905
3906  switch (Kind) {
3907  case k_CondCode:
3908    OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
3909    break;
3910  case k_VPTPred:
3911    OS << "<ARMVCC::" << ARMVPTPredToString(getVPTPred()) << ">";
3912    break;
3913  case k_CCOut:
3914    OS << "<ccout " << RegName(getReg()) << ">";
3915    break;
3916  case k_ITCondMask: {
3917    static const char *const MaskStr[] = {
3918      "(invalid)", "(tttt)", "(ttt)", "(ttte)",
3919      "(tt)",      "(ttet)", "(tte)", "(ttee)",
3920      "(t)",       "(tett)", "(tet)", "(tete)",
3921      "(te)",      "(teet)", "(tee)", "(teee)",
3922    };
3923    assert((ITMask.Mask & 0xf) == ITMask.Mask);
3924    OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
3925    break;
3926  }
3927  case k_CoprocNum:
3928    OS << "<coprocessor number: " << getCoproc() << ">";
3929    break;
3930  case k_CoprocReg:
3931    OS << "<coprocessor register: " << getCoproc() << ">";
3932    break;
3933  case k_CoprocOption:
3934    OS << "<coprocessor option: " << CoprocOption.Val << ">";
3935    break;
3936  case k_MSRMask:
3937    OS << "<mask: " << getMSRMask() << ">";
3938    break;
3939  case k_BankedReg:
3940    OS << "<banked reg: " << getBankedReg() << ">";
3941    break;
3942  case k_Immediate:
3943    OS << *getImm();
3944    break;
3945  case k_MemBarrierOpt:
3946    OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt(), false) << ">";
3947    break;
3948  case k_InstSyncBarrierOpt:
3949    OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">";
3950    break;
3951  case k_TraceSyncBarrierOpt:
3952    OS << "<ARM_TSB::" << TraceSyncBOptToString(getTraceSyncBarrierOpt()) << ">";
3953    break;
3954  case k_Memory:
3955    OS << "<memory";
3956    if (Memory.BaseRegNum)
3957      OS << " base:" << RegName(Memory.BaseRegNum);
3958    if (Memory.OffsetImm)
3959      OS << " offset-imm:" << *Memory.OffsetImm;
3960    if (Memory.OffsetRegNum)
3961      OS << " offset-reg:" << (Memory.isNegative ? "-" : "")
3962         << RegName(Memory.OffsetRegNum);
3963    if (Memory.ShiftType != ARM_AM::no_shift) {
3964      OS << " shift-type:" << ARM_AM::getShiftOpcStr(Memory.ShiftType);
3965      OS << " shift-imm:" << Memory.ShiftImm;
3966    }
3967    if (Memory.Alignment)
3968      OS << " alignment:" << Memory.Alignment;
3969    OS << ">";
3970    break;
3971  case k_PostIndexRegister:
3972    OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
3973       << RegName(PostIdxReg.RegNum);
3974    if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
3975      OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
3976         << PostIdxReg.ShiftImm;
3977    OS << ">";
3978    break;
3979  case k_ProcIFlags: {
3980    OS << "<ARM_PROC::";
3981    unsigned IFlags = getProcIFlags();
3982    for (int i=2; i >= 0; --i)
3983      if (IFlags & (1 << i))
3984        OS << ARM_PROC::IFlagsToString(1 << i);
3985    OS << ">";
3986    break;
3987  }
3988  case k_Register:
3989    OS << "<register " << RegName(getReg()) << ">";
3990    break;
3991  case k_ShifterImmediate:
3992    OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
3993       << " #" << ShifterImm.Imm << ">";
3994    break;
3995  case k_ShiftedRegister:
3996    OS << "<so_reg_reg " << RegName(RegShiftedReg.SrcReg) << " "
3997       << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy) << " "
3998       << RegName(RegShiftedReg.ShiftReg) << ">";
3999    break;
4000  case k_ShiftedImmediate:
4001    OS << "<so_reg_imm " << RegName(RegShiftedImm.SrcReg) << " "
4002       << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy) << " #"
4003       << RegShiftedImm.ShiftImm << ">";
4004    break;
4005  case k_RotateImmediate:
4006    OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
4007    break;
4008  case k_ModifiedImmediate:
4009    OS << "<mod_imm #" << ModImm.Bits << ", #"
4010       <<  ModImm.Rot << ")>";
4011    break;
4012  case k_ConstantPoolImmediate:
4013    OS << "<constant_pool_imm #" << *getConstantPoolImm();
4014    break;
4015  case k_BitfieldDescriptor:
4016    OS << "<bitfield " << "lsb: " << Bitfield.LSB
4017       << ", width: " << Bitfield.Width << ">";
4018    break;
4019  case k_RegisterList:
4020  case k_RegisterListWithAPSR:
4021  case k_DPRRegisterList:
4022  case k_SPRRegisterList:
4023  case k_FPSRegisterListWithVPR:
4024  case k_FPDRegisterListWithVPR: {
4025    OS << "<register_list ";
4026
4027    const SmallVectorImpl<unsigned> &RegList = getRegList();
4028    for (SmallVectorImpl<unsigned>::const_iterator
4029           I = RegList.begin(), E = RegList.end(); I != E; ) {
4030      OS << RegName(*I);
4031      if (++I < E) OS << ", ";
4032    }
4033
4034    OS << ">";
4035    break;
4036  }
4037  case k_VectorList:
4038    OS << "<vector_list " << VectorList.Count << " * "
4039       << RegName(VectorList.RegNum) << ">";
4040    break;
4041  case k_VectorListAllLanes:
4042    OS << "<vector_list(all lanes) " << VectorList.Count << " * "
4043       << RegName(VectorList.RegNum) << ">";
4044    break;
4045  case k_VectorListIndexed:
4046    OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
4047       << VectorList.Count << " * " << RegName(VectorList.RegNum) << ">";
4048    break;
4049  case k_Token:
4050    OS << "'" << getToken() << "'";
4051    break;
4052  case k_VectorIndex:
4053    OS << "<vectorindex " << getVectorIndex() << ">";
4054    break;
4055  }
4056}
4057
4058/// @name Auto-generated Match Functions
4059/// {
4060
4061static unsigned MatchRegisterName(StringRef Name);
4062
4063/// }
4064
4065bool ARMAsmParser::parseRegister(MCRegister &RegNo, SMLoc &StartLoc,
4066                                 SMLoc &EndLoc) {
4067  const AsmToken &Tok = getParser().getTok();
4068  StartLoc = Tok.getLoc();
4069  EndLoc = Tok.getEndLoc();
4070  RegNo = tryParseRegister();
4071
4072  return (RegNo == (unsigned)-1);
4073}
4074
4075OperandMatchResultTy ARMAsmParser::tryParseRegister(MCRegister &RegNo,
4076                                                    SMLoc &StartLoc,
4077                                                    SMLoc &EndLoc) {
4078  if (parseRegister(RegNo, StartLoc, EndLoc))
4079    return MatchOperand_NoMatch;
4080  return MatchOperand_Success;
4081}
4082
4083/// Try to parse a register name.  The token must be an Identifier when called,
4084/// and if it is a register name the token is eaten and the register number is
4085/// returned.  Otherwise return -1.
4086int ARMAsmParser::tryParseRegister() {
4087  MCAsmParser &Parser = getParser();
4088  const AsmToken &Tok = Parser.getTok();
4089  if (Tok.isNot(AsmToken::Identifier)) return -1;
4090
4091  std::string lowerCase = Tok.getString().lower();
4092  unsigned RegNum = MatchRegisterName(lowerCase);
4093  if (!RegNum) {
4094    RegNum = StringSwitch<unsigned>(lowerCase)
4095      .Case("r13", ARM::SP)
4096      .Case("r14", ARM::LR)
4097      .Case("r15", ARM::PC)
4098      .Case("ip", ARM::R12)
4099      // Additional register name aliases for 'gas' compatibility.
4100      .Case("a1", ARM::R0)
4101      .Case("a2", ARM::R1)
4102      .Case("a3", ARM::R2)
4103      .Case("a4", ARM::R3)
4104      .Case("v1", ARM::R4)
4105      .Case("v2", ARM::R5)
4106      .Case("v3", ARM::R6)
4107      .Case("v4", ARM::R7)
4108      .Case("v5", ARM::R8)
4109      .Case("v6", ARM::R9)
4110      .Case("v7", ARM::R10)
4111      .Case("v8", ARM::R11)
4112      .Case("sb", ARM::R9)
4113      .Case("sl", ARM::R10)
4114      .Case("fp", ARM::R11)
4115      .Default(0);
4116  }
4117  if (!RegNum) {
4118    // Check for aliases registered via .req. Canonicalize to lower case.
4119    // That's more consistent since register names are case insensitive, and
4120    // it's how the original entry was passed in from MC/MCParser/AsmParser.
4121    StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
4122    // If no match, return failure.
4123    if (Entry == RegisterReqs.end())
4124      return -1;
4125    Parser.Lex(); // Eat identifier token.
4126    return Entry->getValue();
4127  }
4128
4129  // Some FPUs only have 16 D registers, so D16-D31 are invalid
4130  if (!hasD32() && RegNum >= ARM::D16 && RegNum <= ARM::D31)
4131    return -1;
4132
4133  Parser.Lex(); // Eat identifier token.
4134
4135  return RegNum;
4136}
4137
4138// Try to parse a shifter  (e.g., "lsl <amt>"). On success, return 0.
4139// If a recoverable error occurs, return 1. If an irrecoverable error
4140// occurs, return -1. An irrecoverable error is one where tokens have been
4141// consumed in the process of trying to parse the shifter (i.e., when it is
4142// indeed a shifter operand, but malformed).
4143int ARMAsmParser::tryParseShiftRegister(OperandVector &Operands) {
4144  MCAsmParser &Parser = getParser();
4145  SMLoc S = Parser.getTok().getLoc();
4146  const AsmToken &Tok = Parser.getTok();
4147  if (Tok.isNot(AsmToken::Identifier))
4148    return -1;
4149
4150  std::string lowerCase = Tok.getString().lower();
4151  ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
4152      .Case("asl", ARM_AM::lsl)
4153      .Case("lsl", ARM_AM::lsl)
4154      .Case("lsr", ARM_AM::lsr)
4155      .Case("asr", ARM_AM::asr)
4156      .Case("ror", ARM_AM::ror)
4157      .Case("rrx", ARM_AM::rrx)
4158      .Default(ARM_AM::no_shift);
4159
4160  if (ShiftTy == ARM_AM::no_shift)
4161    return 1;
4162
4163  Parser.Lex(); // Eat the operator.
4164
4165  // The source register for the shift has already been added to the
4166  // operand list, so we need to pop it off and combine it into the shifted
4167  // register operand instead.
4168  std::unique_ptr<ARMOperand> PrevOp(
4169      (ARMOperand *)Operands.pop_back_val().release());
4170  if (!PrevOp->isReg())
4171    return Error(PrevOp->getStartLoc(), "shift must be of a register");
4172  int SrcReg = PrevOp->getReg();
4173
4174  SMLoc EndLoc;
4175  int64_t Imm = 0;
4176  int ShiftReg = 0;
4177  if (ShiftTy == ARM_AM::rrx) {
4178    // RRX Doesn't have an explicit shift amount. The encoder expects
4179    // the shift register to be the same as the source register. Seems odd,
4180    // but OK.
4181    ShiftReg = SrcReg;
4182  } else {
4183    // Figure out if this is shifted by a constant or a register (for non-RRX).
4184    if (Parser.getTok().is(AsmToken::Hash) ||
4185        Parser.getTok().is(AsmToken::Dollar)) {
4186      Parser.Lex(); // Eat hash.
4187      SMLoc ImmLoc = Parser.getTok().getLoc();
4188      const MCExpr *ShiftExpr = nullptr;
4189      if (getParser().parseExpression(ShiftExpr, EndLoc)) {
4190        Error(ImmLoc, "invalid immediate shift value");
4191        return -1;
4192      }
4193      // The expression must be evaluatable as an immediate.
4194      const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
4195      if (!CE) {
4196        Error(ImmLoc, "invalid immediate shift value");
4197        return -1;
4198      }
4199      // Range check the immediate.
4200      // lsl, ror: 0 <= imm <= 31
4201      // lsr, asr: 0 <= imm <= 32
4202      Imm = CE->getValue();
4203      if (Imm < 0 ||
4204          ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
4205          ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
4206        Error(ImmLoc, "immediate shift value out of range");
4207        return -1;
4208      }
4209      // shift by zero is a nop. Always send it through as lsl.
4210      // ('as' compatibility)
4211      if (Imm == 0)
4212        ShiftTy = ARM_AM::lsl;
4213    } else if (Parser.getTok().is(AsmToken::Identifier)) {
4214      SMLoc L = Parser.getTok().getLoc();
4215      EndLoc = Parser.getTok().getEndLoc();
4216      ShiftReg = tryParseRegister();
4217      if (ShiftReg == -1) {
4218        Error(L, "expected immediate or register in shift operand");
4219        return -1;
4220      }
4221    } else {
4222      Error(Parser.getTok().getLoc(),
4223            "expected immediate or register in shift operand");
4224      return -1;
4225    }
4226  }
4227
4228  if (ShiftReg && ShiftTy != ARM_AM::rrx)
4229    Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
4230                                                         ShiftReg, Imm,
4231                                                         S, EndLoc));
4232  else
4233    Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
4234                                                          S, EndLoc));
4235
4236  return 0;
4237}
4238
4239/// Try to parse a register name.  The token must be an Identifier when called.
4240/// If it's a register, an AsmOperand is created. Another AsmOperand is created
4241/// if there is a "writeback". 'true' if it's not a register.
4242///
4243/// TODO this is likely to change to allow different register types and or to
4244/// parse for a specific register type.
4245bool ARMAsmParser::tryParseRegisterWithWriteBack(OperandVector &Operands) {
4246  MCAsmParser &Parser = getParser();
4247  SMLoc RegStartLoc = Parser.getTok().getLoc();
4248  SMLoc RegEndLoc = Parser.getTok().getEndLoc();
4249  int RegNo = tryParseRegister();
4250  if (RegNo == -1)
4251    return true;
4252
4253  Operands.push_back(ARMOperand::CreateReg(RegNo, RegStartLoc, RegEndLoc));
4254
4255  const AsmToken &ExclaimTok = Parser.getTok();
4256  if (ExclaimTok.is(AsmToken::Exclaim)) {
4257    Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
4258                                               ExclaimTok.getLoc()));
4259    Parser.Lex(); // Eat exclaim token
4260    return false;
4261  }
4262
4263  // Also check for an index operand. This is only legal for vector registers,
4264  // but that'll get caught OK in operand matching, so we don't need to
4265  // explicitly filter everything else out here.
4266  if (Parser.getTok().is(AsmToken::LBrac)) {
4267    SMLoc SIdx = Parser.getTok().getLoc();
4268    Parser.Lex(); // Eat left bracket token.
4269
4270    const MCExpr *ImmVal;
4271    if (getParser().parseExpression(ImmVal))
4272      return true;
4273    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
4274    if (!MCE)
4275      return TokError("immediate value expected for vector index");
4276
4277    if (Parser.getTok().isNot(AsmToken::RBrac))
4278      return Error(Parser.getTok().getLoc(), "']' expected");
4279
4280    SMLoc E = Parser.getTok().getEndLoc();
4281    Parser.Lex(); // Eat right bracket token.
4282
4283    Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
4284                                                     SIdx, E,
4285                                                     getContext()));
4286  }
4287
4288  return false;
4289}
4290
4291/// MatchCoprocessorOperandName - Try to parse an coprocessor related
4292/// instruction with a symbolic operand name.
4293/// We accept "crN" syntax for GAS compatibility.
4294/// <operand-name> ::= <prefix><number>
4295/// If CoprocOp is 'c', then:
4296///   <prefix> ::= c | cr
4297/// If CoprocOp is 'p', then :
4298///   <prefix> ::= p
4299/// <number> ::= integer in range [0, 15]
4300static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
4301  // Use the same layout as the tablegen'erated register name matcher. Ugly,
4302  // but efficient.
4303  if (Name.size() < 2 || Name[0] != CoprocOp)
4304    return -1;
4305  Name = (Name[1] == 'r') ? Name.drop_front(2) : Name.drop_front();
4306
4307  switch (Name.size()) {
4308  default: return -1;
4309  case 1:
4310    switch (Name[0]) {
4311    default:  return -1;
4312    case '0': return 0;
4313    case '1': return 1;
4314    case '2': return 2;
4315    case '3': return 3;
4316    case '4': return 4;
4317    case '5': return 5;
4318    case '6': return 6;
4319    case '7': return 7;
4320    case '8': return 8;
4321    case '9': return 9;
4322    }
4323  case 2:
4324    if (Name[0] != '1')
4325      return -1;
4326    switch (Name[1]) {
4327    default:  return -1;
4328    // CP10 and CP11 are VFP/NEON and so vector instructions should be used.
4329    // However, old cores (v5/v6) did use them in that way.
4330    case '0': return 10;
4331    case '1': return 11;
4332    case '2': return 12;
4333    case '3': return 13;
4334    case '4': return 14;
4335    case '5': return 15;
4336    }
4337  }
4338}
4339
4340/// parseITCondCode - Try to parse a condition code for an IT instruction.
4341OperandMatchResultTy
4342ARMAsmParser::parseITCondCode(OperandVector &Operands) {
4343  MCAsmParser &Parser = getParser();
4344  SMLoc S = Parser.getTok().getLoc();
4345  const AsmToken &Tok = Parser.getTok();
4346  if (!Tok.is(AsmToken::Identifier))
4347    return MatchOperand_NoMatch;
4348  unsigned CC = ARMCondCodeFromString(Tok.getString());
4349  if (CC == ~0U)
4350    return MatchOperand_NoMatch;
4351  Parser.Lex(); // Eat the token.
4352
4353  Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
4354
4355  return MatchOperand_Success;
4356}
4357
4358/// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
4359/// token must be an Identifier when called, and if it is a coprocessor
4360/// number, the token is eaten and the operand is added to the operand list.
4361OperandMatchResultTy
4362ARMAsmParser::parseCoprocNumOperand(OperandVector &Operands) {
4363  MCAsmParser &Parser = getParser();
4364  SMLoc S = Parser.getTok().getLoc();
4365  const AsmToken &Tok = Parser.getTok();
4366  if (Tok.isNot(AsmToken::Identifier))
4367    return MatchOperand_NoMatch;
4368
4369  int Num = MatchCoprocessorOperandName(Tok.getString().lower(), 'p');
4370  if (Num == -1)
4371    return MatchOperand_NoMatch;
4372  if (!isValidCoprocessorNumber(Num, getSTI().getFeatureBits()))
4373    return MatchOperand_NoMatch;
4374
4375  Parser.Lex(); // Eat identifier token.
4376  Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
4377  return MatchOperand_Success;
4378}
4379
4380/// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
4381/// token must be an Identifier when called, and if it is a coprocessor
4382/// number, the token is eaten and the operand is added to the operand list.
4383OperandMatchResultTy
4384ARMAsmParser::parseCoprocRegOperand(OperandVector &Operands) {
4385  MCAsmParser &Parser = getParser();
4386  SMLoc S = Parser.getTok().getLoc();
4387  const AsmToken &Tok = Parser.getTok();
4388  if (Tok.isNot(AsmToken::Identifier))
4389    return MatchOperand_NoMatch;
4390
4391  int Reg = MatchCoprocessorOperandName(Tok.getString().lower(), 'c');
4392  if (Reg == -1)
4393    return MatchOperand_NoMatch;
4394
4395  Parser.Lex(); // Eat identifier token.
4396  Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
4397  return MatchOperand_Success;
4398}
4399
4400/// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
4401/// coproc_option : '{' imm0_255 '}'
4402OperandMatchResultTy
4403ARMAsmParser::parseCoprocOptionOperand(OperandVector &Operands) {
4404  MCAsmParser &Parser = getParser();
4405  SMLoc S = Parser.getTok().getLoc();
4406
4407  // If this isn't a '{', this isn't a coprocessor immediate operand.
4408  if (Parser.getTok().isNot(AsmToken::LCurly))
4409    return MatchOperand_NoMatch;
4410  Parser.Lex(); // Eat the '{'
4411
4412  const MCExpr *Expr;
4413  SMLoc Loc = Parser.getTok().getLoc();
4414  if (getParser().parseExpression(Expr)) {
4415    Error(Loc, "illegal expression");
4416    return MatchOperand_ParseFail;
4417  }
4418  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4419  if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
4420    Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
4421    return MatchOperand_ParseFail;
4422  }
4423  int Val = CE->getValue();
4424
4425  // Check for and consume the closing '}'
4426  if (Parser.getTok().isNot(AsmToken::RCurly))
4427    return MatchOperand_ParseFail;
4428  SMLoc E = Parser.getTok().getEndLoc();
4429  Parser.Lex(); // Eat the '}'
4430
4431  Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
4432  return MatchOperand_Success;
4433}
4434
4435// For register list parsing, we need to map from raw GPR register numbering
4436// to the enumeration values. The enumeration values aren't sorted by
4437// register number due to our using "sp", "lr" and "pc" as canonical names.
4438static unsigned getNextRegister(unsigned Reg) {
4439  // If this is a GPR, we need to do it manually, otherwise we can rely
4440  // on the sort ordering of the enumeration since the other reg-classes
4441  // are sane.
4442  if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
4443    return Reg + 1;
4444  switch(Reg) {
4445  default: llvm_unreachable("Invalid GPR number!");
4446  case ARM::R0:  return ARM::R1;  case ARM::R1:  return ARM::R2;
4447  case ARM::R2:  return ARM::R3;  case ARM::R3:  return ARM::R4;
4448  case ARM::R4:  return ARM::R5;  case ARM::R5:  return ARM::R6;
4449  case ARM::R6:  return ARM::R7;  case ARM::R7:  return ARM::R8;
4450  case ARM::R8:  return ARM::R9;  case ARM::R9:  return ARM::R10;
4451  case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
4452  case ARM::R12: return ARM::SP;  case ARM::SP:  return ARM::LR;
4453  case ARM::LR:  return ARM::PC;  case ARM::PC:  return ARM::R0;
4454  }
4455}
4456
4457// Insert an <Encoding, Register> pair in an ordered vector. Return true on
4458// success, or false, if duplicate encoding found.
4459static bool
4460insertNoDuplicates(SmallVectorImpl<std::pair<unsigned, unsigned>> &Regs,
4461                   unsigned Enc, unsigned Reg) {
4462  Regs.emplace_back(Enc, Reg);
4463  for (auto I = Regs.rbegin(), J = I + 1, E = Regs.rend(); J != E; ++I, ++J) {
4464    if (J->first == Enc) {
4465      Regs.erase(J.base());
4466      return false;
4467    }
4468    if (J->first < Enc)
4469      break;
4470    std::swap(*I, *J);
4471  }
4472  return true;
4473}
4474
4475/// Parse a register list.
4476bool ARMAsmParser::parseRegisterList(OperandVector &Operands, bool EnforceOrder,
4477                                     bool AllowRAAC) {
4478  MCAsmParser &Parser = getParser();
4479  if (Parser.getTok().isNot(AsmToken::LCurly))
4480    return TokError("Token is not a Left Curly Brace");
4481  SMLoc S = Parser.getTok().getLoc();
4482  Parser.Lex(); // Eat '{' token.
4483  SMLoc RegLoc = Parser.getTok().getLoc();
4484
4485  // Check the first register in the list to see what register class
4486  // this is a list of.
4487  int Reg = tryParseRegister();
4488  if (Reg == -1)
4489    return Error(RegLoc, "register expected");
4490  if (!AllowRAAC && Reg == ARM::RA_AUTH_CODE)
4491    return Error(RegLoc, "pseudo-register not allowed");
4492  // The reglist instructions have at most 16 registers, so reserve
4493  // space for that many.
4494  int EReg = 0;
4495  SmallVector<std::pair<unsigned, unsigned>, 16> Registers;
4496
4497  // Allow Q regs and just interpret them as the two D sub-registers.
4498  if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
4499    Reg = getDRegFromQReg(Reg);
4500    EReg = MRI->getEncodingValue(Reg);
4501    Registers.emplace_back(EReg, Reg);
4502    ++Reg;
4503  }
4504  const MCRegisterClass *RC;
4505  if (Reg == ARM::RA_AUTH_CODE ||
4506      ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
4507    RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
4508  else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
4509    RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
4510  else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
4511    RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
4512  else if (ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID].contains(Reg))
4513    RC = &ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID];
4514  else
4515    return Error(RegLoc, "invalid register in register list");
4516
4517  // Store the register.
4518  EReg = MRI->getEncodingValue(Reg);
4519  Registers.emplace_back(EReg, Reg);
4520
4521  // This starts immediately after the first register token in the list,
4522  // so we can see either a comma or a minus (range separator) as a legal
4523  // next token.
4524  while (Parser.getTok().is(AsmToken::Comma) ||
4525         Parser.getTok().is(AsmToken::Minus)) {
4526    if (Parser.getTok().is(AsmToken::Minus)) {
4527      if (Reg == ARM::RA_AUTH_CODE)
4528        return Error(RegLoc, "pseudo-register not allowed");
4529      Parser.Lex(); // Eat the minus.
4530      SMLoc AfterMinusLoc = Parser.getTok().getLoc();
4531      int EndReg = tryParseRegister();
4532      if (EndReg == -1)
4533        return Error(AfterMinusLoc, "register expected");
4534      if (EndReg == ARM::RA_AUTH_CODE)
4535        return Error(AfterMinusLoc, "pseudo-register not allowed");
4536      // Allow Q regs and just interpret them as the two D sub-registers.
4537      if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
4538        EndReg = getDRegFromQReg(EndReg) + 1;
4539      // If the register is the same as the start reg, there's nothing
4540      // more to do.
4541      if (Reg == EndReg)
4542        continue;
4543      // The register must be in the same register class as the first.
4544      if (!RC->contains(Reg))
4545        return Error(AfterMinusLoc, "invalid register in register list");
4546      // Ranges must go from low to high.
4547      if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
4548        return Error(AfterMinusLoc, "bad range in register list");
4549
4550      // Add all the registers in the range to the register list.
4551      while (Reg != EndReg) {
4552        Reg = getNextRegister(Reg);
4553        EReg = MRI->getEncodingValue(Reg);
4554        if (!insertNoDuplicates(Registers, EReg, Reg)) {
4555          Warning(AfterMinusLoc, StringRef("duplicated register (") +
4556                                     ARMInstPrinter::getRegisterName(Reg) +
4557                                     ") in register list");
4558        }
4559      }
4560      continue;
4561    }
4562    Parser.Lex(); // Eat the comma.
4563    RegLoc = Parser.getTok().getLoc();
4564    int OldReg = Reg;
4565    const AsmToken RegTok = Parser.getTok();
4566    Reg = tryParseRegister();
4567    if (Reg == -1)
4568      return Error(RegLoc, "register expected");
4569    if (!AllowRAAC && Reg == ARM::RA_AUTH_CODE)
4570      return Error(RegLoc, "pseudo-register not allowed");
4571    // Allow Q regs and just interpret them as the two D sub-registers.
4572    bool isQReg = false;
4573    if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
4574      Reg = getDRegFromQReg(Reg);
4575      isQReg = true;
4576    }
4577    if (Reg != ARM::RA_AUTH_CODE && !RC->contains(Reg) &&
4578        RC->getID() == ARMMCRegisterClasses[ARM::GPRRegClassID].getID() &&
4579        ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID].contains(Reg)) {
4580      // switch the register classes, as GPRwithAPSRnospRegClassID is a partial
4581      // subset of GPRRegClassId except it contains APSR as well.
4582      RC = &ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID];
4583    }
4584    if (Reg == ARM::VPR &&
4585        (RC == &ARMMCRegisterClasses[ARM::SPRRegClassID] ||
4586         RC == &ARMMCRegisterClasses[ARM::DPRRegClassID] ||
4587         RC == &ARMMCRegisterClasses[ARM::FPWithVPRRegClassID])) {
4588      RC = &ARMMCRegisterClasses[ARM::FPWithVPRRegClassID];
4589      EReg = MRI->getEncodingValue(Reg);
4590      if (!insertNoDuplicates(Registers, EReg, Reg)) {
4591        Warning(RegLoc, "duplicated register (" + RegTok.getString() +
4592                            ") in register list");
4593      }
4594      continue;
4595    }
4596    // The register must be in the same register class as the first.
4597    if ((Reg == ARM::RA_AUTH_CODE &&
4598         RC != &ARMMCRegisterClasses[ARM::GPRRegClassID]) ||
4599        (Reg != ARM::RA_AUTH_CODE && !RC->contains(Reg)))
4600      return Error(RegLoc, "invalid register in register list");
4601    // In most cases, the list must be monotonically increasing. An
4602    // exception is CLRM, which is order-independent anyway, so
4603    // there's no potential for confusion if you write clrm {r2,r1}
4604    // instead of clrm {r1,r2}.
4605    if (EnforceOrder &&
4606        MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
4607      if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
4608        Warning(RegLoc, "register list not in ascending order");
4609      else if (!ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID].contains(Reg))
4610        return Error(RegLoc, "register list not in ascending order");
4611    }
4612    // VFP register lists must also be contiguous.
4613    if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
4614        RC != &ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID] &&
4615        Reg != OldReg + 1)
4616      return Error(RegLoc, "non-contiguous register range");
4617    EReg = MRI->getEncodingValue(Reg);
4618    if (!insertNoDuplicates(Registers, EReg, Reg)) {
4619      Warning(RegLoc, "duplicated register (" + RegTok.getString() +
4620                          ") in register list");
4621    }
4622    if (isQReg) {
4623      EReg = MRI->getEncodingValue(++Reg);
4624      Registers.emplace_back(EReg, Reg);
4625    }
4626  }
4627
4628  if (Parser.getTok().isNot(AsmToken::RCurly))
4629    return Error(Parser.getTok().getLoc(), "'}' expected");
4630  SMLoc E = Parser.getTok().getEndLoc();
4631  Parser.Lex(); // Eat '}' token.
4632
4633  // Push the register list operand.
4634  Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
4635
4636  // The ARM system instruction variants for LDM/STM have a '^' token here.
4637  if (Parser.getTok().is(AsmToken::Caret)) {
4638    Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
4639    Parser.Lex(); // Eat '^' token.
4640  }
4641
4642  return false;
4643}
4644
4645// Helper function to parse the lane index for vector lists.
4646OperandMatchResultTy ARMAsmParser::
4647parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) {
4648  MCAsmParser &Parser = getParser();
4649  Index = 0; // Always return a defined index value.
4650  if (Parser.getTok().is(AsmToken::LBrac)) {
4651    Parser.Lex(); // Eat the '['.
4652    if (Parser.getTok().is(AsmToken::RBrac)) {
4653      // "Dn[]" is the 'all lanes' syntax.
4654      LaneKind = AllLanes;
4655      EndLoc = Parser.getTok().getEndLoc();
4656      Parser.Lex(); // Eat the ']'.
4657      return MatchOperand_Success;
4658    }
4659
4660    // There's an optional '#' token here. Normally there wouldn't be, but
4661    // inline assemble puts one in, and it's friendly to accept that.
4662    if (Parser.getTok().is(AsmToken::Hash))
4663      Parser.Lex(); // Eat '#' or '$'.
4664
4665    const MCExpr *LaneIndex;
4666    SMLoc Loc = Parser.getTok().getLoc();
4667    if (getParser().parseExpression(LaneIndex)) {
4668      Error(Loc, "illegal expression");
4669      return MatchOperand_ParseFail;
4670    }
4671    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
4672    if (!CE) {
4673      Error(Loc, "lane index must be empty or an integer");
4674      return MatchOperand_ParseFail;
4675    }
4676    if (Parser.getTok().isNot(AsmToken::RBrac)) {
4677      Error(Parser.getTok().getLoc(), "']' expected");
4678      return MatchOperand_ParseFail;
4679    }
4680    EndLoc = Parser.getTok().getEndLoc();
4681    Parser.Lex(); // Eat the ']'.
4682    int64_t Val = CE->getValue();
4683
4684    // FIXME: Make this range check context sensitive for .8, .16, .32.
4685    if (Val < 0 || Val > 7) {
4686      Error(Parser.getTok().getLoc(), "lane index out of range");
4687      return MatchOperand_ParseFail;
4688    }
4689    Index = Val;
4690    LaneKind = IndexedLane;
4691    return MatchOperand_Success;
4692  }
4693  LaneKind = NoLanes;
4694  return MatchOperand_Success;
4695}
4696
4697// parse a vector register list
4698OperandMatchResultTy
4699ARMAsmParser::parseVectorList(OperandVector &Operands) {
4700  MCAsmParser &Parser = getParser();
4701  VectorLaneTy LaneKind;
4702  unsigned LaneIndex;
4703  SMLoc S = Parser.getTok().getLoc();
4704  // As an extension (to match gas), support a plain D register or Q register
4705  // (without encosing curly braces) as a single or double entry list,
4706  // respectively.
4707  if (!hasMVE() && Parser.getTok().is(AsmToken::Identifier)) {
4708    SMLoc E = Parser.getTok().getEndLoc();
4709    int Reg = tryParseRegister();
4710    if (Reg == -1)
4711      return MatchOperand_NoMatch;
4712    if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
4713      OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
4714      if (Res != MatchOperand_Success)
4715        return Res;
4716      switch (LaneKind) {
4717      case NoLanes:
4718        Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
4719        break;
4720      case AllLanes:
4721        Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
4722                                                                S, E));
4723        break;
4724      case IndexedLane:
4725        Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
4726                                                               LaneIndex,
4727                                                               false, S, E));
4728        break;
4729      }
4730      return MatchOperand_Success;
4731    }
4732    if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
4733      Reg = getDRegFromQReg(Reg);
4734      OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
4735      if (Res != MatchOperand_Success)
4736        return Res;
4737      switch (LaneKind) {
4738      case NoLanes:
4739        Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
4740                                   &ARMMCRegisterClasses[ARM::DPairRegClassID]);
4741        Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
4742        break;
4743      case AllLanes:
4744        Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
4745                                   &ARMMCRegisterClasses[ARM::DPairRegClassID]);
4746        Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
4747                                                                S, E));
4748        break;
4749      case IndexedLane:
4750        Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
4751                                                               LaneIndex,
4752                                                               false, S, E));
4753        break;
4754      }
4755      return MatchOperand_Success;
4756    }
4757    Error(S, "vector register expected");
4758    return MatchOperand_ParseFail;
4759  }
4760
4761  if (Parser.getTok().isNot(AsmToken::LCurly))
4762    return MatchOperand_NoMatch;
4763
4764  Parser.Lex(); // Eat '{' token.
4765  SMLoc RegLoc = Parser.getTok().getLoc();
4766
4767  int Reg = tryParseRegister();
4768  if (Reg == -1) {
4769    Error(RegLoc, "register expected");
4770    return MatchOperand_ParseFail;
4771  }
4772  unsigned Count = 1;
4773  int Spacing = 0;
4774  unsigned FirstReg = Reg;
4775
4776  if (hasMVE() && !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(Reg)) {
4777      Error(Parser.getTok().getLoc(), "vector register in range Q0-Q7 expected");
4778      return MatchOperand_ParseFail;
4779  }
4780  // The list is of D registers, but we also allow Q regs and just interpret
4781  // them as the two D sub-registers.
4782  else if (!hasMVE() && ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
4783    FirstReg = Reg = getDRegFromQReg(Reg);
4784    Spacing = 1; // double-spacing requires explicit D registers, otherwise
4785                 // it's ambiguous with four-register single spaced.
4786    ++Reg;
4787    ++Count;
4788  }
4789
4790  SMLoc E;
4791  if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success)
4792    return MatchOperand_ParseFail;
4793
4794  while (Parser.getTok().is(AsmToken::Comma) ||
4795         Parser.getTok().is(AsmToken::Minus)) {
4796    if (Parser.getTok().is(AsmToken::Minus)) {
4797      if (!Spacing)
4798        Spacing = 1; // Register range implies a single spaced list.
4799      else if (Spacing == 2) {
4800        Error(Parser.getTok().getLoc(),
4801              "sequential registers in double spaced list");
4802        return MatchOperand_ParseFail;
4803      }
4804      Parser.Lex(); // Eat the minus.
4805      SMLoc AfterMinusLoc = Parser.getTok().getLoc();
4806      int EndReg = tryParseRegister();
4807      if (EndReg == -1) {
4808        Error(AfterMinusLoc, "register expected");
4809        return MatchOperand_ParseFail;
4810      }
4811      // Allow Q regs and just interpret them as the two D sub-registers.
4812      if (!hasMVE() && ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
4813        EndReg = getDRegFromQReg(EndReg) + 1;
4814      // If the register is the same as the start reg, there's nothing
4815      // more to do.
4816      if (Reg == EndReg)
4817        continue;
4818      // The register must be in the same register class as the first.
4819      if ((hasMVE() &&
4820           !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(EndReg)) ||
4821          (!hasMVE() &&
4822           !ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg))) {
4823        Error(AfterMinusLoc, "invalid register in register list");
4824        return MatchOperand_ParseFail;
4825      }
4826      // Ranges must go from low to high.
4827      if (Reg > EndReg) {
4828        Error(AfterMinusLoc, "bad range in register list");
4829        return MatchOperand_ParseFail;
4830      }
4831      // Parse the lane specifier if present.
4832      VectorLaneTy NextLaneKind;
4833      unsigned NextLaneIndex;
4834      if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
4835          MatchOperand_Success)
4836        return MatchOperand_ParseFail;
4837      if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
4838        Error(AfterMinusLoc, "mismatched lane index in register list");
4839        return MatchOperand_ParseFail;
4840      }
4841
4842      // Add all the registers in the range to the register list.
4843      Count += EndReg - Reg;
4844      Reg = EndReg;
4845      continue;
4846    }
4847    Parser.Lex(); // Eat the comma.
4848    RegLoc = Parser.getTok().getLoc();
4849    int OldReg = Reg;
4850    Reg = tryParseRegister();
4851    if (Reg == -1) {
4852      Error(RegLoc, "register expected");
4853      return MatchOperand_ParseFail;
4854    }
4855
4856    if (hasMVE()) {
4857      if (!ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(Reg)) {
4858        Error(RegLoc, "vector register in range Q0-Q7 expected");
4859        return MatchOperand_ParseFail;
4860      }
4861      Spacing = 1;
4862    }
4863    // vector register lists must be contiguous.
4864    // It's OK to use the enumeration values directly here rather, as the
4865    // VFP register classes have the enum sorted properly.
4866    //
4867    // The list is of D registers, but we also allow Q regs and just interpret
4868    // them as the two D sub-registers.
4869    else if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
4870      if (!Spacing)
4871        Spacing = 1; // Register range implies a single spaced list.
4872      else if (Spacing == 2) {
4873        Error(RegLoc,
4874              "invalid register in double-spaced list (must be 'D' register')");
4875        return MatchOperand_ParseFail;
4876      }
4877      Reg = getDRegFromQReg(Reg);
4878      if (Reg != OldReg + 1) {
4879        Error(RegLoc, "non-contiguous register range");
4880        return MatchOperand_ParseFail;
4881      }
4882      ++Reg;
4883      Count += 2;
4884      // Parse the lane specifier if present.
4885      VectorLaneTy NextLaneKind;
4886      unsigned NextLaneIndex;
4887      SMLoc LaneLoc = Parser.getTok().getLoc();
4888      if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
4889          MatchOperand_Success)
4890        return MatchOperand_ParseFail;
4891      if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
4892        Error(LaneLoc, "mismatched lane index in register list");
4893        return MatchOperand_ParseFail;
4894      }
4895      continue;
4896    }
4897    // Normal D register.
4898    // Figure out the register spacing (single or double) of the list if
4899    // we don't know it already.
4900    if (!Spacing)
4901      Spacing = 1 + (Reg == OldReg + 2);
4902
4903    // Just check that it's contiguous and keep going.
4904    if (Reg != OldReg + Spacing) {
4905      Error(RegLoc, "non-contiguous register range");
4906      return MatchOperand_ParseFail;
4907    }
4908    ++Count;
4909    // Parse the lane specifier if present.
4910    VectorLaneTy NextLaneKind;
4911    unsigned NextLaneIndex;
4912    SMLoc EndLoc = Parser.getTok().getLoc();
4913    if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success)
4914      return MatchOperand_ParseFail;
4915    if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
4916      Error(EndLoc, "mismatched lane index in register list");
4917      return MatchOperand_ParseFail;
4918    }
4919  }
4920
4921  if (Parser.getTok().isNot(AsmToken::RCurly)) {
4922    Error(Parser.getTok().getLoc(), "'}' expected");
4923    return MatchOperand_ParseFail;
4924  }
4925  E = Parser.getTok().getEndLoc();
4926  Parser.Lex(); // Eat '}' token.
4927
4928  switch (LaneKind) {
4929  case NoLanes:
4930  case AllLanes: {
4931    // Two-register operands have been converted to the
4932    // composite register classes.
4933    if (Count == 2 && !hasMVE()) {
4934      const MCRegisterClass *RC = (Spacing == 1) ?
4935        &ARMMCRegisterClasses[ARM::DPairRegClassID] :
4936        &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
4937      FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
4938    }
4939    auto Create = (LaneKind == NoLanes ? ARMOperand::CreateVectorList :
4940                   ARMOperand::CreateVectorListAllLanes);
4941    Operands.push_back(Create(FirstReg, Count, (Spacing == 2), S, E));
4942    break;
4943  }
4944  case IndexedLane:
4945    Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
4946                                                           LaneIndex,
4947                                                           (Spacing == 2),
4948                                                           S, E));
4949    break;
4950  }
4951  return MatchOperand_Success;
4952}
4953
4954/// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
4955OperandMatchResultTy
4956ARMAsmParser::parseMemBarrierOptOperand(OperandVector &Operands) {
4957  MCAsmParser &Parser = getParser();
4958  SMLoc S = Parser.getTok().getLoc();
4959  const AsmToken &Tok = Parser.getTok();
4960  unsigned Opt;
4961
4962  if (Tok.is(AsmToken::Identifier)) {
4963    StringRef OptStr = Tok.getString();
4964
4965    Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower())
4966      .Case("sy",    ARM_MB::SY)
4967      .Case("st",    ARM_MB::ST)
4968      .Case("ld",    ARM_MB::LD)
4969      .Case("sh",    ARM_MB::ISH)
4970      .Case("ish",   ARM_MB::ISH)
4971      .Case("shst",  ARM_MB::ISHST)
4972      .Case("ishst", ARM_MB::ISHST)
4973      .Case("ishld", ARM_MB::ISHLD)
4974      .Case("nsh",   ARM_MB::NSH)
4975      .Case("un",    ARM_MB::NSH)
4976      .Case("nshst", ARM_MB::NSHST)
4977      .Case("nshld", ARM_MB::NSHLD)
4978      .Case("unst",  ARM_MB::NSHST)
4979      .Case("osh",   ARM_MB::OSH)
4980      .Case("oshst", ARM_MB::OSHST)
4981      .Case("oshld", ARM_MB::OSHLD)
4982      .Default(~0U);
4983
4984    // ishld, oshld, nshld and ld are only available from ARMv8.
4985    if (!hasV8Ops() && (Opt == ARM_MB::ISHLD || Opt == ARM_MB::OSHLD ||
4986                        Opt == ARM_MB::NSHLD || Opt == ARM_MB::LD))
4987      Opt = ~0U;
4988
4989    if (Opt == ~0U)
4990      return MatchOperand_NoMatch;
4991
4992    Parser.Lex(); // Eat identifier token.
4993  } else if (Tok.is(AsmToken::Hash) ||
4994             Tok.is(AsmToken::Dollar) ||
4995             Tok.is(AsmToken::Integer)) {
4996    if (Parser.getTok().isNot(AsmToken::Integer))
4997      Parser.Lex(); // Eat '#' or '$'.
4998    SMLoc Loc = Parser.getTok().getLoc();
4999
5000    const MCExpr *MemBarrierID;
5001    if (getParser().parseExpression(MemBarrierID)) {
5002      Error(Loc, "illegal expression");
5003      return MatchOperand_ParseFail;
5004    }
5005
5006    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID);
5007    if (!CE) {
5008      Error(Loc, "constant expression expected");
5009      return MatchOperand_ParseFail;
5010    }
5011
5012    int Val = CE->getValue();
5013    if (Val & ~0xf) {
5014      Error(Loc, "immediate value out of range");
5015      return MatchOperand_ParseFail;
5016    }
5017
5018    Opt = ARM_MB::RESERVED_0 + Val;
5019  } else
5020    return MatchOperand_ParseFail;
5021
5022  Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
5023  return MatchOperand_Success;
5024}
5025
5026OperandMatchResultTy
5027ARMAsmParser::parseTraceSyncBarrierOptOperand(OperandVector &Operands) {
5028  MCAsmParser &Parser = getParser();
5029  SMLoc S = Parser.getTok().getLoc();
5030  const AsmToken &Tok = Parser.getTok();
5031
5032  if (Tok.isNot(AsmToken::Identifier))
5033     return MatchOperand_NoMatch;
5034
5035  if (!Tok.getString().equals_insensitive("csync"))
5036    return MatchOperand_NoMatch;
5037
5038  Parser.Lex(); // Eat identifier token.
5039
5040  Operands.push_back(ARMOperand::CreateTraceSyncBarrierOpt(ARM_TSB::CSYNC, S));
5041  return MatchOperand_Success;
5042}
5043
5044/// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options.
5045OperandMatchResultTy
5046ARMAsmParser::parseInstSyncBarrierOptOperand(OperandVector &Operands) {
5047  MCAsmParser &Parser = getParser();
5048  SMLoc S = Parser.getTok().getLoc();
5049  const AsmToken &Tok = Parser.getTok();
5050  unsigned Opt;
5051
5052  if (Tok.is(AsmToken::Identifier)) {
5053    StringRef OptStr = Tok.getString();
5054
5055    if (OptStr.equals_insensitive("sy"))
5056      Opt = ARM_ISB::SY;
5057    else
5058      return MatchOperand_NoMatch;
5059
5060    Parser.Lex(); // Eat identifier token.
5061  } else if (Tok.is(AsmToken::Hash) ||
5062             Tok.is(AsmToken::Dollar) ||
5063             Tok.is(AsmToken::Integer)) {
5064    if (Parser.getTok().isNot(AsmToken::Integer))
5065      Parser.Lex(); // Eat '#' or '$'.
5066    SMLoc Loc = Parser.getTok().getLoc();
5067
5068    const MCExpr *ISBarrierID;
5069    if (getParser().parseExpression(ISBarrierID)) {
5070      Error(Loc, "illegal expression");
5071      return MatchOperand_ParseFail;
5072    }
5073
5074    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID);
5075    if (!CE) {
5076      Error(Loc, "constant expression expected");
5077      return MatchOperand_ParseFail;
5078    }
5079
5080    int Val = CE->getValue();
5081    if (Val & ~0xf) {
5082      Error(Loc, "immediate value out of range");
5083      return MatchOperand_ParseFail;
5084    }
5085
5086    Opt = ARM_ISB::RESERVED_0 + Val;
5087  } else
5088    return MatchOperand_ParseFail;
5089
5090  Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt(
5091          (ARM_ISB::InstSyncBOpt)Opt, S));
5092  return MatchOperand_Success;
5093}
5094
5095
5096/// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
5097OperandMatchResultTy
5098ARMAsmParser::parseProcIFlagsOperand(OperandVector &Operands) {
5099  MCAsmParser &Parser = getParser();
5100  SMLoc S = Parser.getTok().getLoc();
5101  const AsmToken &Tok = Parser.getTok();
5102  if (!Tok.is(AsmToken::Identifier))
5103    return MatchOperand_NoMatch;
5104  StringRef IFlagsStr = Tok.getString();
5105
5106  // An iflags string of "none" is interpreted to mean that none of the AIF
5107  // bits are set.  Not a terribly useful instruction, but a valid encoding.
5108  unsigned IFlags = 0;
5109  if (IFlagsStr != "none") {
5110        for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
5111      unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1).lower())
5112        .Case("a", ARM_PROC::A)
5113        .Case("i", ARM_PROC::I)
5114        .Case("f", ARM_PROC::F)
5115        .Default(~0U);
5116
5117      // If some specific iflag is already set, it means that some letter is
5118      // present more than once, this is not acceptable.
5119      if (Flag == ~0U || (IFlags & Flag))
5120        return MatchOperand_NoMatch;
5121
5122      IFlags |= Flag;
5123    }
5124  }
5125
5126  Parser.Lex(); // Eat identifier token.
5127  Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
5128  return MatchOperand_Success;
5129}
5130
5131/// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
5132OperandMatchResultTy
5133ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) {
5134  MCAsmParser &Parser = getParser();
5135  SMLoc S = Parser.getTok().getLoc();
5136  const AsmToken &Tok = Parser.getTok();
5137
5138  if (Tok.is(AsmToken::Integer)) {
5139    int64_t Val = Tok.getIntVal();
5140    if (Val > 255 || Val < 0) {
5141      return MatchOperand_NoMatch;
5142    }
5143    unsigned SYSmvalue = Val & 0xFF;
5144    Parser.Lex();
5145    Operands.push_back(ARMOperand::CreateMSRMask(SYSmvalue, S));
5146    return MatchOperand_Success;
5147  }
5148
5149  if (!Tok.is(AsmToken::Identifier))
5150    return MatchOperand_NoMatch;
5151  StringRef Mask = Tok.getString();
5152
5153  if (isMClass()) {
5154    auto TheReg = ARMSysReg::lookupMClassSysRegByName(Mask.lower());
5155    if (!TheReg || !TheReg->hasRequiredFeatures(getSTI().getFeatureBits()))
5156      return MatchOperand_NoMatch;
5157
5158    unsigned SYSmvalue = TheReg->Encoding & 0xFFF;
5159
5160    Parser.Lex(); // Eat identifier token.
5161    Operands.push_back(ARMOperand::CreateMSRMask(SYSmvalue, S));
5162    return MatchOperand_Success;
5163  }
5164
5165  // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
5166  size_t Start = 0, Next = Mask.find('_');
5167  StringRef Flags = "";
5168  std::string SpecReg = Mask.slice(Start, Next).lower();
5169  if (Next != StringRef::npos)
5170    Flags = Mask.slice(Next+1, Mask.size());
5171
5172  // FlagsVal contains the complete mask:
5173  // 3-0: Mask
5174  // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
5175  unsigned FlagsVal = 0;
5176
5177  if (SpecReg == "apsr") {
5178    FlagsVal = StringSwitch<unsigned>(Flags)
5179    .Case("nzcvq",  0x8) // same as CPSR_f
5180    .Case("g",      0x4) // same as CPSR_s
5181    .Case("nzcvqg", 0xc) // same as CPSR_fs
5182    .Default(~0U);
5183
5184    if (FlagsVal == ~0U) {
5185      if (!Flags.empty())
5186        return MatchOperand_NoMatch;
5187      else
5188        FlagsVal = 8; // No flag
5189    }
5190  } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
5191    // cpsr_all is an alias for cpsr_fc, as is plain cpsr.
5192    if (Flags == "all" || Flags == "")
5193      Flags = "fc";
5194    for (int i = 0, e = Flags.size(); i != e; ++i) {
5195      unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
5196      .Case("c", 1)
5197      .Case("x", 2)
5198      .Case("s", 4)
5199      .Case("f", 8)
5200      .Default(~0U);
5201
5202      // If some specific flag is already set, it means that some letter is
5203      // present more than once, this is not acceptable.
5204      if (Flag == ~0U || (FlagsVal & Flag))
5205        return MatchOperand_NoMatch;
5206      FlagsVal |= Flag;
5207    }
5208  } else // No match for special register.
5209    return MatchOperand_NoMatch;
5210
5211  // Special register without flags is NOT equivalent to "fc" flags.
5212  // NOTE: This is a divergence from gas' behavior.  Uncommenting the following
5213  // two lines would enable gas compatibility at the expense of breaking
5214  // round-tripping.
5215  //
5216  // if (!FlagsVal)
5217  //  FlagsVal = 0x9;
5218
5219  // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
5220  if (SpecReg == "spsr")
5221    FlagsVal |= 16;
5222
5223  Parser.Lex(); // Eat identifier token.
5224  Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
5225  return MatchOperand_Success;
5226}
5227
5228/// parseBankedRegOperand - Try to parse a banked register (e.g. "lr_irq") for
5229/// use in the MRS/MSR instructions added to support virtualization.
5230OperandMatchResultTy
5231ARMAsmParser::parseBankedRegOperand(OperandVector &Operands) {
5232  MCAsmParser &Parser = getParser();
5233  SMLoc S = Parser.getTok().getLoc();
5234  const AsmToken &Tok = Parser.getTok();
5235  if (!Tok.is(AsmToken::Identifier))
5236    return MatchOperand_NoMatch;
5237  StringRef RegName = Tok.getString();
5238
5239  auto TheReg = ARMBankedReg::lookupBankedRegByName(RegName.lower());
5240  if (!TheReg)
5241    return MatchOperand_NoMatch;
5242  unsigned Encoding = TheReg->Encoding;
5243
5244  Parser.Lex(); // Eat identifier token.
5245  Operands.push_back(ARMOperand::CreateBankedReg(Encoding, S));
5246  return MatchOperand_Success;
5247}
5248
5249OperandMatchResultTy
5250ARMAsmParser::parsePKHImm(OperandVector &Operands, StringRef Op, int Low,
5251                          int High) {
5252  MCAsmParser &Parser = getParser();
5253  const AsmToken &Tok = Parser.getTok();
5254  if (Tok.isNot(AsmToken::Identifier)) {
5255    Error(Parser.getTok().getLoc(), Op + " operand expected.");
5256    return MatchOperand_ParseFail;
5257  }
5258  StringRef ShiftName = Tok.getString();
5259  std::string LowerOp = Op.lower();
5260  std::string UpperOp = Op.upper();
5261  if (ShiftName != LowerOp && ShiftName != UpperOp) {
5262    Error(Parser.getTok().getLoc(), Op + " operand expected.");
5263    return MatchOperand_ParseFail;
5264  }
5265  Parser.Lex(); // Eat shift type token.
5266
5267  // There must be a '#' and a shift amount.
5268  if (Parser.getTok().isNot(AsmToken::Hash) &&
5269      Parser.getTok().isNot(AsmToken::Dollar)) {
5270    Error(Parser.getTok().getLoc(), "'#' expected");
5271    return MatchOperand_ParseFail;
5272  }
5273  Parser.Lex(); // Eat hash token.
5274
5275  const MCExpr *ShiftAmount;
5276  SMLoc Loc = Parser.getTok().getLoc();
5277  SMLoc EndLoc;
5278  if (getParser().parseExpression(ShiftAmount, EndLoc)) {
5279    Error(Loc, "illegal expression");
5280    return MatchOperand_ParseFail;
5281  }
5282  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
5283  if (!CE) {
5284    Error(Loc, "constant expression expected");
5285    return MatchOperand_ParseFail;
5286  }
5287  int Val = CE->getValue();
5288  if (Val < Low || Val > High) {
5289    Error(Loc, "immediate value out of range");
5290    return MatchOperand_ParseFail;
5291  }
5292
5293  Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc));
5294
5295  return MatchOperand_Success;
5296}
5297
5298OperandMatchResultTy
5299ARMAsmParser::parseSetEndImm(OperandVector &Operands) {
5300  MCAsmParser &Parser = getParser();
5301  const AsmToken &Tok = Parser.getTok();
5302  SMLoc S = Tok.getLoc();
5303  if (Tok.isNot(AsmToken::Identifier)) {
5304    Error(S, "'be' or 'le' operand expected");
5305    return MatchOperand_ParseFail;
5306  }
5307  int Val = StringSwitch<int>(Tok.getString().lower())
5308    .Case("be", 1)
5309    .Case("le", 0)
5310    .Default(-1);
5311  Parser.Lex(); // Eat the token.
5312
5313  if (Val == -1) {
5314    Error(S, "'be' or 'le' operand expected");
5315    return MatchOperand_ParseFail;
5316  }
5317  Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::create(Val,
5318                                                                  getContext()),
5319                                           S, Tok.getEndLoc()));
5320  return MatchOperand_Success;
5321}
5322
5323/// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
5324/// instructions. Legal values are:
5325///     lsl #n  'n' in [0,31]
5326///     asr #n  'n' in [1,32]
5327///             n == 32 encoded as n == 0.
5328OperandMatchResultTy
5329ARMAsmParser::parseShifterImm(OperandVector &Operands) {
5330  MCAsmParser &Parser = getParser();
5331  const AsmToken &Tok = Parser.getTok();
5332  SMLoc S = Tok.getLoc();
5333  if (Tok.isNot(AsmToken::Identifier)) {
5334    Error(S, "shift operator 'asr' or 'lsl' expected");
5335    return MatchOperand_ParseFail;
5336  }
5337  StringRef ShiftName = Tok.getString();
5338  bool isASR;
5339  if (ShiftName == "lsl" || ShiftName == "LSL")
5340    isASR = false;
5341  else if (ShiftName == "asr" || ShiftName == "ASR")
5342    isASR = true;
5343  else {
5344    Error(S, "shift operator 'asr' or 'lsl' expected");
5345    return MatchOperand_ParseFail;
5346  }
5347  Parser.Lex(); // Eat the operator.
5348
5349  // A '#' and a shift amount.
5350  if (Parser.getTok().isNot(AsmToken::Hash) &&
5351      Parser.getTok().isNot(AsmToken::Dollar)) {
5352    Error(Parser.getTok().getLoc(), "'#' expected");
5353    return MatchOperand_ParseFail;
5354  }
5355  Parser.Lex(); // Eat hash token.
5356  SMLoc ExLoc = Parser.getTok().getLoc();
5357
5358  const MCExpr *ShiftAmount;
5359  SMLoc EndLoc;
5360  if (getParser().parseExpression(ShiftAmount, EndLoc)) {
5361    Error(ExLoc, "malformed shift expression");
5362    return MatchOperand_ParseFail;
5363  }
5364  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
5365  if (!CE) {
5366    Error(ExLoc, "shift amount must be an immediate");
5367    return MatchOperand_ParseFail;
5368  }
5369
5370  int64_t Val = CE->getValue();
5371  if (isASR) {
5372    // Shift amount must be in [1,32]
5373    if (Val < 1 || Val > 32) {
5374      Error(ExLoc, "'asr' shift amount must be in range [1,32]");
5375      return MatchOperand_ParseFail;
5376    }
5377    // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
5378    if (isThumb() && Val == 32) {
5379      Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode");
5380      return MatchOperand_ParseFail;
5381    }
5382    if (Val == 32) Val = 0;
5383  } else {
5384    // Shift amount must be in [1,32]
5385    if (Val < 0 || Val > 31) {
5386      Error(ExLoc, "'lsr' shift amount must be in range [0,31]");
5387      return MatchOperand_ParseFail;
5388    }
5389  }
5390
5391  Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc));
5392
5393  return MatchOperand_Success;
5394}
5395
5396/// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
5397/// of instructions. Legal values are:
5398///     ror #n  'n' in {0, 8, 16, 24}
5399OperandMatchResultTy
5400ARMAsmParser::parseRotImm(OperandVector &Operands) {
5401  MCAsmParser &Parser = getParser();
5402  const AsmToken &Tok = Parser.getTok();
5403  SMLoc S = Tok.getLoc();
5404  if (Tok.isNot(AsmToken::Identifier))
5405    return MatchOperand_NoMatch;
5406  StringRef ShiftName = Tok.getString();
5407  if (ShiftName != "ror" && ShiftName != "ROR")
5408    return MatchOperand_NoMatch;
5409  Parser.Lex(); // Eat the operator.
5410
5411  // A '#' and a rotate amount.
5412  if (Parser.getTok().isNot(AsmToken::Hash) &&
5413      Parser.getTok().isNot(AsmToken::Dollar)) {
5414    Error(Parser.getTok().getLoc(), "'#' expected");
5415    return MatchOperand_ParseFail;
5416  }
5417  Parser.Lex(); // Eat hash token.
5418  SMLoc ExLoc = Parser.getTok().getLoc();
5419
5420  const MCExpr *ShiftAmount;
5421  SMLoc EndLoc;
5422  if (getParser().parseExpression(ShiftAmount, EndLoc)) {
5423    Error(ExLoc, "malformed rotate expression");
5424    return MatchOperand_ParseFail;
5425  }
5426  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
5427  if (!CE) {
5428    Error(ExLoc, "rotate amount must be an immediate");
5429    return MatchOperand_ParseFail;
5430  }
5431
5432  int64_t Val = CE->getValue();
5433  // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
5434  // normally, zero is represented in asm by omitting the rotate operand
5435  // entirely.
5436  if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
5437    Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24");
5438    return MatchOperand_ParseFail;
5439  }
5440
5441  Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc));
5442
5443  return MatchOperand_Success;
5444}
5445
5446OperandMatchResultTy
5447ARMAsmParser::parseModImm(OperandVector &Operands) {
5448  MCAsmParser &Parser = getParser();
5449  MCAsmLexer &Lexer = getLexer();
5450  int64_t Imm1, Imm2;
5451
5452  SMLoc S = Parser.getTok().getLoc();
5453
5454  // 1) A mod_imm operand can appear in the place of a register name:
5455  //   add r0, #mod_imm
5456  //   add r0, r0, #mod_imm
5457  // to correctly handle the latter, we bail out as soon as we see an
5458  // identifier.
5459  //
5460  // 2) Similarly, we do not want to parse into complex operands:
5461  //   mov r0, #mod_imm
5462  //   mov r0, :lower16:(_foo)
5463  if (Parser.getTok().is(AsmToken::Identifier) ||
5464      Parser.getTok().is(AsmToken::Colon))
5465    return MatchOperand_NoMatch;
5466
5467  // Hash (dollar) is optional as per the ARMARM
5468  if (Parser.getTok().is(AsmToken::Hash) ||
5469      Parser.getTok().is(AsmToken::Dollar)) {
5470    // Avoid parsing into complex operands (#:)
5471    if (Lexer.peekTok().is(AsmToken::Colon))
5472      return MatchOperand_NoMatch;
5473
5474    // Eat the hash (dollar)
5475    Parser.Lex();
5476  }
5477
5478  SMLoc Sx1, Ex1;
5479  Sx1 = Parser.getTok().getLoc();
5480  const MCExpr *Imm1Exp;
5481  if (getParser().parseExpression(Imm1Exp, Ex1)) {
5482    Error(Sx1, "malformed expression");
5483    return MatchOperand_ParseFail;
5484  }
5485
5486  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm1Exp);
5487
5488  if (CE) {
5489    // Immediate must fit within 32-bits
5490    Imm1 = CE->getValue();
5491    int Enc = ARM_AM::getSOImmVal(Imm1);
5492    if (Enc != -1 && Parser.getTok().is(AsmToken::EndOfStatement)) {
5493      // We have a match!
5494      Operands.push_back(ARMOperand::CreateModImm((Enc & 0xFF),
5495                                                  (Enc & 0xF00) >> 7,
5496                                                  Sx1, Ex1));
5497      return MatchOperand_Success;
5498    }
5499
5500    // We have parsed an immediate which is not for us, fallback to a plain
5501    // immediate. This can happen for instruction aliases. For an example,
5502    // ARMInstrInfo.td defines the alias [mov <-> mvn] which can transform
5503    // a mov (mvn) with a mod_imm_neg/mod_imm_not operand into the opposite
5504    // instruction with a mod_imm operand. The alias is defined such that the
5505    // parser method is shared, that's why we have to do this here.
5506    if (Parser.getTok().is(AsmToken::EndOfStatement)) {
5507      Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1));
5508      return MatchOperand_Success;
5509    }
5510  } else {
5511    // Operands like #(l1 - l2) can only be evaluated at a later stage (via an
5512    // MCFixup). Fallback to a plain immediate.
5513    Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1));
5514    return MatchOperand_Success;
5515  }
5516
5517  // From this point onward, we expect the input to be a (#bits, #rot) pair
5518  if (Parser.getTok().isNot(AsmToken::Comma)) {
5519    Error(Sx1, "expected modified immediate operand: #[0, 255], #even[0-30]");
5520    return MatchOperand_ParseFail;
5521  }
5522
5523  if (Imm1 & ~0xFF) {
5524    Error(Sx1, "immediate operand must a number in the range [0, 255]");
5525    return MatchOperand_ParseFail;
5526  }
5527
5528  // Eat the comma
5529  Parser.Lex();
5530
5531  // Repeat for #rot
5532  SMLoc Sx2, Ex2;
5533  Sx2 = Parser.getTok().getLoc();
5534
5535  // Eat the optional hash (dollar)
5536  if (Parser.getTok().is(AsmToken::Hash) ||
5537      Parser.getTok().is(AsmToken::Dollar))
5538    Parser.Lex();
5539
5540  const MCExpr *Imm2Exp;
5541  if (getParser().parseExpression(Imm2Exp, Ex2)) {
5542    Error(Sx2, "malformed expression");
5543    return MatchOperand_ParseFail;
5544  }
5545
5546  CE = dyn_cast<MCConstantExpr>(Imm2Exp);
5547
5548  if (CE) {
5549    Imm2 = CE->getValue();
5550    if (!(Imm2 & ~0x1E)) {
5551      // We have a match!
5552      Operands.push_back(ARMOperand::CreateModImm(Imm1, Imm2, S, Ex2));
5553      return MatchOperand_Success;
5554    }
5555    Error(Sx2, "immediate operand must an even number in the range [0, 30]");
5556    return MatchOperand_ParseFail;
5557  } else {
5558    Error(Sx2, "constant expression expected");
5559    return MatchOperand_ParseFail;
5560  }
5561}
5562
5563OperandMatchResultTy
5564ARMAsmParser::parseBitfield(OperandVector &Operands) {
5565  MCAsmParser &Parser = getParser();
5566  SMLoc S = Parser.getTok().getLoc();
5567  // The bitfield descriptor is really two operands, the LSB and the width.
5568  if (Parser.getTok().isNot(AsmToken::Hash) &&
5569      Parser.getTok().isNot(AsmToken::Dollar)) {
5570    Error(Parser.getTok().getLoc(), "'#' expected");
5571    return MatchOperand_ParseFail;
5572  }
5573  Parser.Lex(); // Eat hash token.
5574
5575  const MCExpr *LSBExpr;
5576  SMLoc E = Parser.getTok().getLoc();
5577  if (getParser().parseExpression(LSBExpr)) {
5578    Error(E, "malformed immediate expression");
5579    return MatchOperand_ParseFail;
5580  }
5581  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
5582  if (!CE) {
5583    Error(E, "'lsb' operand must be an immediate");
5584    return MatchOperand_ParseFail;
5585  }
5586
5587  int64_t LSB = CE->getValue();
5588  // The LSB must be in the range [0,31]
5589  if (LSB < 0 || LSB > 31) {
5590    Error(E, "'lsb' operand must be in the range [0,31]");
5591    return MatchOperand_ParseFail;
5592  }
5593  E = Parser.getTok().getLoc();
5594
5595  // Expect another immediate operand.
5596  if (Parser.getTok().isNot(AsmToken::Comma)) {
5597    Error(Parser.getTok().getLoc(), "too few operands");
5598    return MatchOperand_ParseFail;
5599  }
5600  Parser.Lex(); // Eat hash token.
5601  if (Parser.getTok().isNot(AsmToken::Hash) &&
5602      Parser.getTok().isNot(AsmToken::Dollar)) {
5603    Error(Parser.getTok().getLoc(), "'#' expected");
5604    return MatchOperand_ParseFail;
5605  }
5606  Parser.Lex(); // Eat hash token.
5607
5608  const MCExpr *WidthExpr;
5609  SMLoc EndLoc;
5610  if (getParser().parseExpression(WidthExpr, EndLoc)) {
5611    Error(E, "malformed immediate expression");
5612    return MatchOperand_ParseFail;
5613  }
5614  CE = dyn_cast<MCConstantExpr>(WidthExpr);
5615  if (!CE) {
5616    Error(E, "'width' operand must be an immediate");
5617    return MatchOperand_ParseFail;
5618  }
5619
5620  int64_t Width = CE->getValue();
5621  // The LSB must be in the range [1,32-lsb]
5622  if (Width < 1 || Width > 32 - LSB) {
5623    Error(E, "'width' operand must be in the range [1,32-lsb]");
5624    return MatchOperand_ParseFail;
5625  }
5626
5627  Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc));
5628
5629  return MatchOperand_Success;
5630}
5631
5632OperandMatchResultTy
5633ARMAsmParser::parsePostIdxReg(OperandVector &Operands) {
5634  // Check for a post-index addressing register operand. Specifically:
5635  // postidx_reg := '+' register {, shift}
5636  //              | '-' register {, shift}
5637  //              | register {, shift}
5638
5639  // This method must return MatchOperand_NoMatch without consuming any tokens
5640  // in the case where there is no match, as other alternatives take other
5641  // parse methods.
5642  MCAsmParser &Parser = getParser();
5643  AsmToken Tok = Parser.getTok();
5644  SMLoc S = Tok.getLoc();
5645  bool haveEaten = false;
5646  bool isAdd = true;
5647  if (Tok.is(AsmToken::Plus)) {
5648    Parser.Lex(); // Eat the '+' token.
5649    haveEaten = true;
5650  } else if (Tok.is(AsmToken::Minus)) {
5651    Parser.Lex(); // Eat the '-' token.
5652    isAdd = false;
5653    haveEaten = true;
5654  }
5655
5656  SMLoc E = Parser.getTok().getEndLoc();
5657  int Reg = tryParseRegister();
5658  if (Reg == -1) {
5659    if (!haveEaten)
5660      return MatchOperand_NoMatch;
5661    Error(Parser.getTok().getLoc(), "register expected");
5662    return MatchOperand_ParseFail;
5663  }
5664
5665  ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
5666  unsigned ShiftImm = 0;
5667  if (Parser.getTok().is(AsmToken::Comma)) {
5668    Parser.Lex(); // Eat the ','.
5669    if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
5670      return MatchOperand_ParseFail;
5671
5672    // FIXME: Only approximates end...may include intervening whitespace.
5673    E = Parser.getTok().getLoc();
5674  }
5675
5676  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
5677                                                  ShiftImm, S, E));
5678
5679  return MatchOperand_Success;
5680}
5681
5682OperandMatchResultTy
5683ARMAsmParser::parseAM3Offset(OperandVector &Operands) {
5684  // Check for a post-index addressing register operand. Specifically:
5685  // am3offset := '+' register
5686  //              | '-' register
5687  //              | register
5688  //              | # imm
5689  //              | # + imm
5690  //              | # - imm
5691
5692  // This method must return MatchOperand_NoMatch without consuming any tokens
5693  // in the case where there is no match, as other alternatives take other
5694  // parse methods.
5695  MCAsmParser &Parser = getParser();
5696  AsmToken Tok = Parser.getTok();
5697  SMLoc S = Tok.getLoc();
5698
5699  // Do immediates first, as we always parse those if we have a '#'.
5700  if (Parser.getTok().is(AsmToken::Hash) ||
5701      Parser.getTok().is(AsmToken::Dollar)) {
5702    Parser.Lex(); // Eat '#' or '$'.
5703    // Explicitly look for a '-', as we need to encode negative zero
5704    // differently.
5705    bool isNegative = Parser.getTok().is(AsmToken::Minus);
5706    const MCExpr *Offset;
5707    SMLoc E;
5708    if (getParser().parseExpression(Offset, E))
5709      return MatchOperand_ParseFail;
5710    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
5711    if (!CE) {
5712      Error(S, "constant expression expected");
5713      return MatchOperand_ParseFail;
5714    }
5715    // Negative zero is encoded as the flag value
5716    // std::numeric_limits<int32_t>::min().
5717    int32_t Val = CE->getValue();
5718    if (isNegative && Val == 0)
5719      Val = std::numeric_limits<int32_t>::min();
5720
5721    Operands.push_back(
5722      ARMOperand::CreateImm(MCConstantExpr::create(Val, getContext()), S, E));
5723
5724    return MatchOperand_Success;
5725  }
5726
5727  bool haveEaten = false;
5728  bool isAdd = true;
5729  if (Tok.is(AsmToken::Plus)) {
5730    Parser.Lex(); // Eat the '+' token.
5731    haveEaten = true;
5732  } else if (Tok.is(AsmToken::Minus)) {
5733    Parser.Lex(); // Eat the '-' token.
5734    isAdd = false;
5735    haveEaten = true;
5736  }
5737
5738  Tok = Parser.getTok();
5739  int Reg = tryParseRegister();
5740  if (Reg == -1) {
5741    if (!haveEaten)
5742      return MatchOperand_NoMatch;
5743    Error(Tok.getLoc(), "register expected");
5744    return MatchOperand_ParseFail;
5745  }
5746
5747  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
5748                                                  0, S, Tok.getEndLoc()));
5749
5750  return MatchOperand_Success;
5751}
5752
5753/// Convert parsed operands to MCInst.  Needed here because this instruction
5754/// only has two register operands, but multiplication is commutative so
5755/// assemblers should accept both "mul rD, rN, rD" and "mul rD, rD, rN".
5756void ARMAsmParser::cvtThumbMultiply(MCInst &Inst,
5757                                    const OperandVector &Operands) {
5758  ((ARMOperand &)*Operands[3]).addRegOperands(Inst, 1);
5759  ((ARMOperand &)*Operands[1]).addCCOutOperands(Inst, 1);
5760  // If we have a three-operand form, make sure to set Rn to be the operand
5761  // that isn't the same as Rd.
5762  unsigned RegOp = 4;
5763  if (Operands.size() == 6 &&
5764      ((ARMOperand &)*Operands[4]).getReg() ==
5765          ((ARMOperand &)*Operands[3]).getReg())
5766    RegOp = 5;
5767  ((ARMOperand &)*Operands[RegOp]).addRegOperands(Inst, 1);
5768  Inst.addOperand(Inst.getOperand(0));
5769  ((ARMOperand &)*Operands[2]).addCondCodeOperands(Inst, 2);
5770}
5771
5772void ARMAsmParser::cvtThumbBranches(MCInst &Inst,
5773                                    const OperandVector &Operands) {
5774  int CondOp = -1, ImmOp = -1;
5775  switch(Inst.getOpcode()) {
5776    case ARM::tB:
5777    case ARM::tBcc:  CondOp = 1; ImmOp = 2; break;
5778
5779    case ARM::t2B:
5780    case ARM::t2Bcc: CondOp = 1; ImmOp = 3; break;
5781
5782    default: llvm_unreachable("Unexpected instruction in cvtThumbBranches");
5783  }
5784  // first decide whether or not the branch should be conditional
5785  // by looking at it's location relative to an IT block
5786  if(inITBlock()) {
5787    // inside an IT block we cannot have any conditional branches. any
5788    // such instructions needs to be converted to unconditional form
5789    switch(Inst.getOpcode()) {
5790      case ARM::tBcc: Inst.setOpcode(ARM::tB); break;
5791      case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break;
5792    }
5793  } else {
5794    // outside IT blocks we can only have unconditional branches with AL
5795    // condition code or conditional branches with non-AL condition code
5796    unsigned Cond = static_cast<ARMOperand &>(*Operands[CondOp]).getCondCode();
5797    switch(Inst.getOpcode()) {
5798      case ARM::tB:
5799      case ARM::tBcc:
5800        Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc);
5801        break;
5802      case ARM::t2B:
5803      case ARM::t2Bcc:
5804        Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc);
5805        break;
5806    }
5807  }
5808
5809  // now decide on encoding size based on branch target range
5810  switch(Inst.getOpcode()) {
5811    // classify tB as either t2B or t1B based on range of immediate operand
5812    case ARM::tB: {
5813      ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]);
5814      if (!op.isSignedOffset<11, 1>() && isThumb() && hasV8MBaseline())
5815        Inst.setOpcode(ARM::t2B);
5816      break;
5817    }
5818    // classify tBcc as either t2Bcc or t1Bcc based on range of immediate operand
5819    case ARM::tBcc: {
5820      ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]);
5821      if (!op.isSignedOffset<8, 1>() && isThumb() && hasV8MBaseline())
5822        Inst.setOpcode(ARM::t2Bcc);
5823      break;
5824    }
5825  }
5826  ((ARMOperand &)*Operands[ImmOp]).addImmOperands(Inst, 1);
5827  ((ARMOperand &)*Operands[CondOp]).addCondCodeOperands(Inst, 2);
5828}
5829
5830void ARMAsmParser::cvtMVEVMOVQtoDReg(
5831  MCInst &Inst, const OperandVector &Operands) {
5832
5833  // mnemonic, condition code, Rt, Rt2, Qd, idx, Qd again, idx2
5834  assert(Operands.size() == 8);
5835
5836  ((ARMOperand &)*Operands[2]).addRegOperands(Inst, 1); // Rt
5837  ((ARMOperand &)*Operands[3]).addRegOperands(Inst, 1); // Rt2
5838  ((ARMOperand &)*Operands[4]).addRegOperands(Inst, 1); // Qd
5839  ((ARMOperand &)*Operands[5]).addMVEPairVectorIndexOperands(Inst, 1); // idx
5840  // skip second copy of Qd in Operands[6]
5841  ((ARMOperand &)*Operands[7]).addMVEPairVectorIndexOperands(Inst, 1); // idx2
5842  ((ARMOperand &)*Operands[1]).addCondCodeOperands(Inst, 2); // condition code
5843}
5844
5845/// Parse an ARM memory expression, return false if successful else return true
5846/// or an error.  The first token must be a '[' when called.
5847bool ARMAsmParser::parseMemory(OperandVector &Operands) {
5848  MCAsmParser &Parser = getParser();
5849  SMLoc S, E;
5850  if (Parser.getTok().isNot(AsmToken::LBrac))
5851    return TokError("Token is not a Left Bracket");
5852  S = Parser.getTok().getLoc();
5853  Parser.Lex(); // Eat left bracket token.
5854
5855  const AsmToken &BaseRegTok = Parser.getTok();
5856  int BaseRegNum = tryParseRegister();
5857  if (BaseRegNum == -1)
5858    return Error(BaseRegTok.getLoc(), "register expected");
5859
5860  // The next token must either be a comma, a colon or a closing bracket.
5861  const AsmToken &Tok = Parser.getTok();
5862  if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) &&
5863      !Tok.is(AsmToken::RBrac))
5864    return Error(Tok.getLoc(), "malformed memory operand");
5865
5866  if (Tok.is(AsmToken::RBrac)) {
5867    E = Tok.getEndLoc();
5868    Parser.Lex(); // Eat right bracket token.
5869
5870    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0,
5871                                             ARM_AM::no_shift, 0, 0, false,
5872                                             S, E));
5873
5874    // If there's a pre-indexing writeback marker, '!', just add it as a token
5875    // operand. It's rather odd, but syntactically valid.
5876    if (Parser.getTok().is(AsmToken::Exclaim)) {
5877      Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
5878      Parser.Lex(); // Eat the '!'.
5879    }
5880
5881    return false;
5882  }
5883
5884  assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) &&
5885         "Lost colon or comma in memory operand?!");
5886  if (Tok.is(AsmToken::Comma)) {
5887    Parser.Lex(); // Eat the comma.
5888  }
5889
5890  // If we have a ':', it's an alignment specifier.
5891  if (Parser.getTok().is(AsmToken::Colon)) {
5892    Parser.Lex(); // Eat the ':'.
5893    E = Parser.getTok().getLoc();
5894    SMLoc AlignmentLoc = Tok.getLoc();
5895
5896    const MCExpr *Expr;
5897    if (getParser().parseExpression(Expr))
5898     return true;
5899
5900    // The expression has to be a constant. Memory references with relocations
5901    // don't come through here, as they use the <label> forms of the relevant
5902    // instructions.
5903    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
5904    if (!CE)
5905      return Error (E, "constant expression expected");
5906
5907    unsigned Align = 0;
5908    switch (CE->getValue()) {
5909    default:
5910      return Error(E,
5911                   "alignment specifier must be 16, 32, 64, 128, or 256 bits");
5912    case 16:  Align = 2; break;
5913    case 32:  Align = 4; break;
5914    case 64:  Align = 8; break;
5915    case 128: Align = 16; break;
5916    case 256: Align = 32; break;
5917    }
5918
5919    // Now we should have the closing ']'
5920    if (Parser.getTok().isNot(AsmToken::RBrac))
5921      return Error(Parser.getTok().getLoc(), "']' expected");
5922    E = Parser.getTok().getEndLoc();
5923    Parser.Lex(); // Eat right bracket token.
5924
5925    // Don't worry about range checking the value here. That's handled by
5926    // the is*() predicates.
5927    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0,
5928                                             ARM_AM::no_shift, 0, Align,
5929                                             false, S, E, AlignmentLoc));
5930
5931    // If there's a pre-indexing writeback marker, '!', just add it as a token
5932    // operand.
5933    if (Parser.getTok().is(AsmToken::Exclaim)) {
5934      Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
5935      Parser.Lex(); // Eat the '!'.
5936    }
5937
5938    return false;
5939  }
5940
5941  // If we have a '#' or '$', it's an immediate offset, else assume it's a
5942  // register offset. Be friendly and also accept a plain integer or expression
5943  // (without a leading hash) for gas compatibility.
5944  if (Parser.getTok().is(AsmToken::Hash) ||
5945      Parser.getTok().is(AsmToken::Dollar) ||
5946      Parser.getTok().is(AsmToken::LParen) ||
5947      Parser.getTok().is(AsmToken::Integer)) {
5948    if (Parser.getTok().is(AsmToken::Hash) ||
5949        Parser.getTok().is(AsmToken::Dollar))
5950      Parser.Lex(); // Eat '#' or '$'
5951    E = Parser.getTok().getLoc();
5952
5953    bool isNegative = getParser().getTok().is(AsmToken::Minus);
5954    const MCExpr *Offset, *AdjustedOffset;
5955    if (getParser().parseExpression(Offset))
5956     return true;
5957
5958    if (const auto *CE = dyn_cast<MCConstantExpr>(Offset)) {
5959      // If the constant was #-0, represent it as
5960      // std::numeric_limits<int32_t>::min().
5961      int32_t Val = CE->getValue();
5962      if (isNegative && Val == 0)
5963        CE = MCConstantExpr::create(std::numeric_limits<int32_t>::min(),
5964                                    getContext());
5965      // Don't worry about range checking the value here. That's handled by
5966      // the is*() predicates.
5967      AdjustedOffset = CE;
5968    } else
5969      AdjustedOffset = Offset;
5970    Operands.push_back(ARMOperand::CreateMem(
5971        BaseRegNum, AdjustedOffset, 0, ARM_AM::no_shift, 0, 0, false, S, E));
5972
5973    // Now we should have the closing ']'
5974    if (Parser.getTok().isNot(AsmToken::RBrac))
5975      return Error(Parser.getTok().getLoc(), "']' expected");
5976    E = Parser.getTok().getEndLoc();
5977    Parser.Lex(); // Eat right bracket token.
5978
5979    // If there's a pre-indexing writeback marker, '!', just add it as a token
5980    // operand.
5981    if (Parser.getTok().is(AsmToken::Exclaim)) {
5982      Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
5983      Parser.Lex(); // Eat the '!'.
5984    }
5985
5986    return false;
5987  }
5988
5989  // The register offset is optionally preceded by a '+' or '-'
5990  bool isNegative = false;
5991  if (Parser.getTok().is(AsmToken::Minus)) {
5992    isNegative = true;
5993    Parser.Lex(); // Eat the '-'.
5994  } else if (Parser.getTok().is(AsmToken::Plus)) {
5995    // Nothing to do.
5996    Parser.Lex(); // Eat the '+'.
5997  }
5998
5999  E = Parser.getTok().getLoc();
6000  int OffsetRegNum = tryParseRegister();
6001  if (OffsetRegNum == -1)
6002    return Error(E, "register expected");
6003
6004  // If there's a shift operator, handle it.
6005  ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
6006  unsigned ShiftImm = 0;
6007  if (Parser.getTok().is(AsmToken::Comma)) {
6008    Parser.Lex(); // Eat the ','.
6009    if (parseMemRegOffsetShift(ShiftType, ShiftImm))
6010      return true;
6011  }
6012
6013  // Now we should have the closing ']'
6014  if (Parser.getTok().isNot(AsmToken::RBrac))
6015    return Error(Parser.getTok().getLoc(), "']' expected");
6016  E = Parser.getTok().getEndLoc();
6017  Parser.Lex(); // Eat right bracket token.
6018
6019  Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, OffsetRegNum,
6020                                           ShiftType, ShiftImm, 0, isNegative,
6021                                           S, E));
6022
6023  // If there's a pre-indexing writeback marker, '!', just add it as a token
6024  // operand.
6025  if (Parser.getTok().is(AsmToken::Exclaim)) {
6026    Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
6027    Parser.Lex(); // Eat the '!'.
6028  }
6029
6030  return false;
6031}
6032
6033/// parseMemRegOffsetShift - one of these two:
6034///   ( lsl | lsr | asr | ror ) , # shift_amount
6035///   rrx
6036/// return true if it parses a shift otherwise it returns false.
6037bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
6038                                          unsigned &Amount) {
6039  MCAsmParser &Parser = getParser();
6040  SMLoc Loc = Parser.getTok().getLoc();
6041  const AsmToken &Tok = Parser.getTok();
6042  if (Tok.isNot(AsmToken::Identifier))
6043    return Error(Loc, "illegal shift operator");
6044  StringRef ShiftName = Tok.getString();
6045  if (ShiftName == "lsl" || ShiftName == "LSL" ||
6046      ShiftName == "asl" || ShiftName == "ASL")
6047    St = ARM_AM::lsl;
6048  else if (ShiftName == "lsr" || ShiftName == "LSR")
6049    St = ARM_AM::lsr;
6050  else if (ShiftName == "asr" || ShiftName == "ASR")
6051    St = ARM_AM::asr;
6052  else if (ShiftName == "ror" || ShiftName == "ROR")
6053    St = ARM_AM::ror;
6054  else if (ShiftName == "rrx" || ShiftName == "RRX")
6055    St = ARM_AM::rrx;
6056  else if (ShiftName == "uxtw" || ShiftName == "UXTW")
6057    St = ARM_AM::uxtw;
6058  else
6059    return Error(Loc, "illegal shift operator");
6060  Parser.Lex(); // Eat shift type token.
6061
6062  // rrx stands alone.
6063  Amount = 0;
6064  if (St != ARM_AM::rrx) {
6065    Loc = Parser.getTok().getLoc();
6066    // A '#' and a shift amount.
6067    const AsmToken &HashTok = Parser.getTok();
6068    if (HashTok.isNot(AsmToken::Hash) &&
6069        HashTok.isNot(AsmToken::Dollar))
6070      return Error(HashTok.getLoc(), "'#' expected");
6071    Parser.Lex(); // Eat hash token.
6072
6073    const MCExpr *Expr;
6074    if (getParser().parseExpression(Expr))
6075      return true;
6076    // Range check the immediate.
6077    // lsl, ror: 0 <= imm <= 31
6078    // lsr, asr: 0 <= imm <= 32
6079    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
6080    if (!CE)
6081      return Error(Loc, "shift amount must be an immediate");
6082    int64_t Imm = CE->getValue();
6083    if (Imm < 0 ||
6084        ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
6085        ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
6086      return Error(Loc, "immediate shift value out of range");
6087    // If <ShiftTy> #0, turn it into a no_shift.
6088    if (Imm == 0)
6089      St = ARM_AM::lsl;
6090    // For consistency, treat lsr #32 and asr #32 as having immediate value 0.
6091    if (Imm == 32)
6092      Imm = 0;
6093    Amount = Imm;
6094  }
6095
6096  return false;
6097}
6098
6099/// parseFPImm - A floating point immediate expression operand.
6100OperandMatchResultTy
6101ARMAsmParser::parseFPImm(OperandVector &Operands) {
6102  MCAsmParser &Parser = getParser();
6103  // Anything that can accept a floating point constant as an operand
6104  // needs to go through here, as the regular parseExpression is
6105  // integer only.
6106  //
6107  // This routine still creates a generic Immediate operand, containing
6108  // a bitcast of the 64-bit floating point value. The various operands
6109  // that accept floats can check whether the value is valid for them
6110  // via the standard is*() predicates.
6111
6112  SMLoc S = Parser.getTok().getLoc();
6113
6114  if (Parser.getTok().isNot(AsmToken::Hash) &&
6115      Parser.getTok().isNot(AsmToken::Dollar))
6116    return MatchOperand_NoMatch;
6117
6118  // Disambiguate the VMOV forms that can accept an FP immediate.
6119  // vmov.f32 <sreg>, #imm
6120  // vmov.f64 <dreg>, #imm
6121  // vmov.f32 <dreg>, #imm  @ vector f32x2
6122  // vmov.f32 <qreg>, #imm  @ vector f32x4
6123  //
6124  // There are also the NEON VMOV instructions which expect an
6125  // integer constant. Make sure we don't try to parse an FPImm
6126  // for these:
6127  // vmov.i{8|16|32|64} <dreg|qreg>, #imm
6128  ARMOperand &TyOp = static_cast<ARMOperand &>(*Operands[2]);
6129  bool isVmovf = TyOp.isToken() &&
6130                 (TyOp.getToken() == ".f32" || TyOp.getToken() == ".f64" ||
6131                  TyOp.getToken() == ".f16");
6132  ARMOperand &Mnemonic = static_cast<ARMOperand &>(*Operands[0]);
6133  bool isFconst = Mnemonic.isToken() && (Mnemonic.getToken() == "fconstd" ||
6134                                         Mnemonic.getToken() == "fconsts");
6135  if (!(isVmovf || isFconst))
6136    return MatchOperand_NoMatch;
6137
6138  Parser.Lex(); // Eat '#' or '$'.
6139
6140  // Handle negation, as that still comes through as a separate token.
6141  bool isNegative = false;
6142  if (Parser.getTok().is(AsmToken::Minus)) {
6143    isNegative = true;
6144    Parser.Lex();
6145  }
6146  const AsmToken &Tok = Parser.getTok();
6147  SMLoc Loc = Tok.getLoc();
6148  if (Tok.is(AsmToken::Real) && isVmovf) {
6149    APFloat RealVal(APFloat::IEEEsingle(), Tok.getString());
6150    uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
6151    // If we had a '-' in front, toggle the sign bit.
6152    IntVal ^= (uint64_t)isNegative << 31;
6153    Parser.Lex(); // Eat the token.
6154    Operands.push_back(ARMOperand::CreateImm(
6155          MCConstantExpr::create(IntVal, getContext()),
6156          S, Parser.getTok().getLoc()));
6157    return MatchOperand_Success;
6158  }
6159  // Also handle plain integers. Instructions which allow floating point
6160  // immediates also allow a raw encoded 8-bit value.
6161  if (Tok.is(AsmToken::Integer) && isFconst) {
6162    int64_t Val = Tok.getIntVal();
6163    Parser.Lex(); // Eat the token.
6164    if (Val > 255 || Val < 0) {
6165      Error(Loc, "encoded floating point value out of range");
6166      return MatchOperand_ParseFail;
6167    }
6168    float RealVal = ARM_AM::getFPImmFloat(Val);
6169    Val = APFloat(RealVal).bitcastToAPInt().getZExtValue();
6170
6171    Operands.push_back(ARMOperand::CreateImm(
6172        MCConstantExpr::create(Val, getContext()), S,
6173        Parser.getTok().getLoc()));
6174    return MatchOperand_Success;
6175  }
6176
6177  Error(Loc, "invalid floating point immediate");
6178  return MatchOperand_ParseFail;
6179}
6180
6181/// Parse a arm instruction operand.  For now this parses the operand regardless
6182/// of the mnemonic.
6183bool ARMAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
6184  MCAsmParser &Parser = getParser();
6185  SMLoc S, E;
6186
6187  // Check if the current operand has a custom associated parser, if so, try to
6188  // custom parse the operand, or fallback to the general approach.
6189  OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
6190  if (ResTy == MatchOperand_Success)
6191    return false;
6192  // If there wasn't a custom match, try the generic matcher below. Otherwise,
6193  // there was a match, but an error occurred, in which case, just return that
6194  // the operand parsing failed.
6195  if (ResTy == MatchOperand_ParseFail)
6196    return true;
6197
6198  switch (getLexer().getKind()) {
6199  default:
6200    Error(Parser.getTok().getLoc(), "unexpected token in operand");
6201    return true;
6202  case AsmToken::Identifier: {
6203    // If we've seen a branch mnemonic, the next operand must be a label.  This
6204    // is true even if the label is a register name.  So "br r1" means branch to
6205    // label "r1".
6206    bool ExpectLabel = Mnemonic == "b" || Mnemonic == "bl";
6207    if (!ExpectLabel) {
6208      if (!tryParseRegisterWithWriteBack(Operands))
6209        return false;
6210      int Res = tryParseShiftRegister(Operands);
6211      if (Res == 0) // success
6212        return false;
6213      else if (Res == -1) // irrecoverable error
6214        return true;
6215      // If this is VMRS, check for the apsr_nzcv operand.
6216      if (Mnemonic == "vmrs" &&
6217          Parser.getTok().getString().equals_insensitive("apsr_nzcv")) {
6218        S = Parser.getTok().getLoc();
6219        Parser.Lex();
6220        Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S));
6221        return false;
6222      }
6223    }
6224
6225    // Fall though for the Identifier case that is not a register or a
6226    // special name.
6227    [[fallthrough]];
6228  }
6229  case AsmToken::LParen:  // parenthesized expressions like (_strcmp-4)
6230  case AsmToken::Integer: // things like 1f and 2b as a branch targets
6231  case AsmToken::String:  // quoted label names.
6232  case AsmToken::Dot: {   // . as a branch target
6233    // This was not a register so parse other operands that start with an
6234    // identifier (like labels) as expressions and create them as immediates.
6235    const MCExpr *IdVal;
6236    S = Parser.getTok().getLoc();
6237    if (getParser().parseExpression(IdVal))
6238      return true;
6239    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
6240    Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
6241    return false;
6242  }
6243  case AsmToken::LBrac:
6244    return parseMemory(Operands);
6245  case AsmToken::LCurly:
6246    return parseRegisterList(Operands, !Mnemonic.startswith("clr"));
6247  case AsmToken::Dollar:
6248  case AsmToken::Hash: {
6249    // #42 -> immediate
6250    // $ 42 -> immediate
6251    // $foo -> symbol name
6252    // $42 -> symbol name
6253    S = Parser.getTok().getLoc();
6254
6255    // Favor the interpretation of $-prefixed operands as symbol names.
6256    // Cases where immediates are explicitly expected are handled by their
6257    // specific ParseMethod implementations.
6258    auto AdjacentToken = getLexer().peekTok(/*ShouldSkipSpace=*/false);
6259    bool ExpectIdentifier = Parser.getTok().is(AsmToken::Dollar) &&
6260                            (AdjacentToken.is(AsmToken::Identifier) ||
6261                             AdjacentToken.is(AsmToken::Integer));
6262    if (!ExpectIdentifier) {
6263      // Token is not part of identifier. Drop leading $ or # before parsing
6264      // expression.
6265      Parser.Lex();
6266    }
6267
6268    if (Parser.getTok().isNot(AsmToken::Colon)) {
6269      bool IsNegative = Parser.getTok().is(AsmToken::Minus);
6270      const MCExpr *ImmVal;
6271      if (getParser().parseExpression(ImmVal))
6272        return true;
6273      const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
6274      if (CE) {
6275        int32_t Val = CE->getValue();
6276        if (IsNegative && Val == 0)
6277          ImmVal = MCConstantExpr::create(std::numeric_limits<int32_t>::min(),
6278                                          getContext());
6279      }
6280      E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
6281      Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
6282
6283      // There can be a trailing '!' on operands that we want as a separate
6284      // '!' Token operand. Handle that here. For example, the compatibility
6285      // alias for 'srsdb sp!, #imm' is 'srsdb #imm!'.
6286      if (Parser.getTok().is(AsmToken::Exclaim)) {
6287        Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(),
6288                                                   Parser.getTok().getLoc()));
6289        Parser.Lex(); // Eat exclaim token
6290      }
6291      return false;
6292    }
6293    // w/ a ':' after the '#', it's just like a plain ':'.
6294    [[fallthrough]];
6295  }
6296  case AsmToken::Colon: {
6297    S = Parser.getTok().getLoc();
6298    // ":lower16:" and ":upper16:" expression prefixes
6299    // FIXME: Check it's an expression prefix,
6300    // e.g. (FOO - :lower16:BAR) isn't legal.
6301    ARMMCExpr::VariantKind RefKind;
6302    if (parsePrefix(RefKind))
6303      return true;
6304
6305    const MCExpr *SubExprVal;
6306    if (getParser().parseExpression(SubExprVal))
6307      return true;
6308
6309    const MCExpr *ExprVal = ARMMCExpr::create(RefKind, SubExprVal,
6310                                              getContext());
6311    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
6312    Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
6313    return false;
6314  }
6315  case AsmToken::Equal: {
6316    S = Parser.getTok().getLoc();
6317    if (Mnemonic != "ldr") // only parse for ldr pseudo (e.g. ldr r0, =val)
6318      return Error(S, "unexpected token in operand");
6319    Parser.Lex(); // Eat '='
6320    const MCExpr *SubExprVal;
6321    if (getParser().parseExpression(SubExprVal))
6322      return true;
6323    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
6324
6325    // execute-only: we assume that assembly programmers know what they are
6326    // doing and allow literal pool creation here
6327    Operands.push_back(ARMOperand::CreateConstantPoolImm(SubExprVal, S, E));
6328    return false;
6329  }
6330  }
6331}
6332
6333bool ARMAsmParser::parseImmExpr(int64_t &Out) {
6334  const MCExpr *Expr = nullptr;
6335  SMLoc L = getParser().getTok().getLoc();
6336  if (check(getParser().parseExpression(Expr), L, "expected expression"))
6337    return true;
6338  const MCConstantExpr *Value = dyn_cast_or_null<MCConstantExpr>(Expr);
6339  if (check(!Value, L, "expected constant expression"))
6340    return true;
6341  Out = Value->getValue();
6342  return false;
6343}
6344
6345// parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
6346//  :lower16: and :upper16:.
6347bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
6348  MCAsmParser &Parser = getParser();
6349  RefKind = ARMMCExpr::VK_ARM_None;
6350
6351  // consume an optional '#' (GNU compatibility)
6352  if (getLexer().is(AsmToken::Hash))
6353    Parser.Lex();
6354
6355  // :lower16: and :upper16: modifiers
6356  assert(getLexer().is(AsmToken::Colon) && "expected a :");
6357  Parser.Lex(); // Eat ':'
6358
6359  if (getLexer().isNot(AsmToken::Identifier)) {
6360    Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
6361    return true;
6362  }
6363
6364  enum {
6365    COFF = (1 << MCContext::IsCOFF),
6366    ELF = (1 << MCContext::IsELF),
6367    MACHO = (1 << MCContext::IsMachO),
6368    WASM = (1 << MCContext::IsWasm),
6369  };
6370  static const struct PrefixEntry {
6371    const char *Spelling;
6372    ARMMCExpr::VariantKind VariantKind;
6373    uint8_t SupportedFormats;
6374  } PrefixEntries[] = {
6375    { "lower16", ARMMCExpr::VK_ARM_LO16, COFF | ELF | MACHO },
6376    { "upper16", ARMMCExpr::VK_ARM_HI16, COFF | ELF | MACHO },
6377  };
6378
6379  StringRef IDVal = Parser.getTok().getIdentifier();
6380
6381  const auto &Prefix =
6382      llvm::find_if(PrefixEntries, [&IDVal](const PrefixEntry &PE) {
6383        return PE.Spelling == IDVal;
6384      });
6385  if (Prefix == std::end(PrefixEntries)) {
6386    Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
6387    return true;
6388  }
6389
6390  uint8_t CurrentFormat;
6391  switch (getContext().getObjectFileType()) {
6392  case MCContext::IsMachO:
6393    CurrentFormat = MACHO;
6394    break;
6395  case MCContext::IsELF:
6396    CurrentFormat = ELF;
6397    break;
6398  case MCContext::IsCOFF:
6399    CurrentFormat = COFF;
6400    break;
6401  case MCContext::IsWasm:
6402    CurrentFormat = WASM;
6403    break;
6404  case MCContext::IsGOFF:
6405  case MCContext::IsSPIRV:
6406  case MCContext::IsXCOFF:
6407  case MCContext::IsDXContainer:
6408    llvm_unreachable("unexpected object format");
6409    break;
6410  }
6411
6412  if (~Prefix->SupportedFormats & CurrentFormat) {
6413    Error(Parser.getTok().getLoc(),
6414          "cannot represent relocation in the current file format");
6415    return true;
6416  }
6417
6418  RefKind = Prefix->VariantKind;
6419  Parser.Lex();
6420
6421  if (getLexer().isNot(AsmToken::Colon)) {
6422    Error(Parser.getTok().getLoc(), "unexpected token after prefix");
6423    return true;
6424  }
6425  Parser.Lex(); // Eat the last ':'
6426
6427  return false;
6428}
6429
6430/// Given a mnemonic, split out possible predication code and carry
6431/// setting letters to form a canonical mnemonic and flags.
6432//
6433// FIXME: Would be nice to autogen this.
6434// FIXME: This is a bit of a maze of special cases.
6435StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
6436                                      StringRef ExtraToken,
6437                                      unsigned &PredicationCode,
6438                                      unsigned &VPTPredicationCode,
6439                                      bool &CarrySetting,
6440                                      unsigned &ProcessorIMod,
6441                                      StringRef &ITMask) {
6442  PredicationCode = ARMCC::AL;
6443  VPTPredicationCode = ARMVCC::None;
6444  CarrySetting = false;
6445  ProcessorIMod = 0;
6446
6447  // Ignore some mnemonics we know aren't predicated forms.
6448  //
6449  // FIXME: Would be nice to autogen this.
6450  if ((Mnemonic == "movs" && isThumb()) ||
6451      Mnemonic == "teq"   || Mnemonic == "vceq"   || Mnemonic == "svc"   ||
6452      Mnemonic == "mls"   || Mnemonic == "smmls"  || Mnemonic == "vcls"  ||
6453      Mnemonic == "vmls"  || Mnemonic == "vnmls"  || Mnemonic == "vacge" ||
6454      Mnemonic == "vcge"  || Mnemonic == "vclt"   || Mnemonic == "vacgt" ||
6455      Mnemonic == "vaclt" || Mnemonic == "vacle"  || Mnemonic == "hlt" ||
6456      Mnemonic == "vcgt"  || Mnemonic == "vcle"   || Mnemonic == "smlal" ||
6457      Mnemonic == "umaal" || Mnemonic == "umlal"  || Mnemonic == "vabal" ||
6458      Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
6459      Mnemonic == "fmuls" || Mnemonic == "vmaxnm" || Mnemonic == "vminnm" ||
6460      Mnemonic == "vcvta" || Mnemonic == "vcvtn"  || Mnemonic == "vcvtp" ||
6461      Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" ||
6462      Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic == "hvc" ||
6463      Mnemonic.startswith("vsel") || Mnemonic == "vins" || Mnemonic == "vmovx" ||
6464      Mnemonic == "bxns"  || Mnemonic == "blxns" ||
6465      Mnemonic == "vdot"  || Mnemonic == "vmmla" ||
6466      Mnemonic == "vudot" || Mnemonic == "vsdot" ||
6467      Mnemonic == "vcmla" || Mnemonic == "vcadd" ||
6468      Mnemonic == "vfmal" || Mnemonic == "vfmsl" ||
6469      Mnemonic == "wls"   || Mnemonic == "le"    || Mnemonic == "dls" ||
6470      Mnemonic == "csel"  || Mnemonic == "csinc" ||
6471      Mnemonic == "csinv" || Mnemonic == "csneg" || Mnemonic == "cinc" ||
6472      Mnemonic == "cinv"  || Mnemonic == "cneg"  || Mnemonic == "cset" ||
6473      Mnemonic == "csetm" ||
6474      Mnemonic == "aut"   || Mnemonic == "pac" || Mnemonic == "pacbti" ||
6475      Mnemonic == "bti")
6476    return Mnemonic;
6477
6478  // First, split out any predication code. Ignore mnemonics we know aren't
6479  // predicated but do have a carry-set and so weren't caught above.
6480  if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
6481      Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
6482      Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
6483      Mnemonic != "sbcs" && Mnemonic != "rscs" &&
6484      !(hasMVE() &&
6485        (Mnemonic == "vmine" ||
6486         Mnemonic == "vshle" || Mnemonic == "vshlt" || Mnemonic == "vshllt" ||
6487         Mnemonic == "vrshle" || Mnemonic == "vrshlt" ||
6488         Mnemonic == "vmvne" || Mnemonic == "vorne" ||
6489         Mnemonic == "vnege" || Mnemonic == "vnegt" ||
6490         Mnemonic == "vmule" || Mnemonic == "vmult" ||
6491         Mnemonic == "vrintne" ||
6492         Mnemonic == "vcmult" || Mnemonic == "vcmule" ||
6493         Mnemonic == "vpsele" || Mnemonic == "vpselt" ||
6494         Mnemonic.startswith("vq")))) {
6495    unsigned CC = ARMCondCodeFromString(Mnemonic.substr(Mnemonic.size()-2));
6496    if (CC != ~0U) {
6497      Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
6498      PredicationCode = CC;
6499    }
6500  }
6501
6502  // Next, determine if we have a carry setting bit. We explicitly ignore all
6503  // the instructions we know end in 's'.
6504  if (Mnemonic.endswith("s") &&
6505      !(Mnemonic == "cps" || Mnemonic == "mls" ||
6506        Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
6507        Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
6508        Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
6509        Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
6510        Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
6511        Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
6512        Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
6513        Mnemonic == "vfms" || Mnemonic == "vfnms" || Mnemonic == "fconsts" ||
6514        Mnemonic == "bxns" || Mnemonic == "blxns" || Mnemonic == "vfmas" ||
6515        Mnemonic == "vmlas" ||
6516        (Mnemonic == "movs" && isThumb()))) {
6517    Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
6518    CarrySetting = true;
6519  }
6520
6521  // The "cps" instruction can have a interrupt mode operand which is glued into
6522  // the mnemonic. Check if this is the case, split it and parse the imod op
6523  if (Mnemonic.startswith("cps")) {
6524    // Split out any imod code.
6525    unsigned IMod =
6526      StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
6527      .Case("ie", ARM_PROC::IE)
6528      .Case("id", ARM_PROC::ID)
6529      .Default(~0U);
6530    if (IMod != ~0U) {
6531      Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
6532      ProcessorIMod = IMod;
6533    }
6534  }
6535
6536  if (isMnemonicVPTPredicable(Mnemonic, ExtraToken) && Mnemonic != "vmovlt" &&
6537      Mnemonic != "vshllt" && Mnemonic != "vrshrnt" && Mnemonic != "vshrnt" &&
6538      Mnemonic != "vqrshrunt" && Mnemonic != "vqshrunt" &&
6539      Mnemonic != "vqrshrnt" && Mnemonic != "vqshrnt" && Mnemonic != "vmullt" &&
6540      Mnemonic != "vqmovnt" && Mnemonic != "vqmovunt" &&
6541      Mnemonic != "vqmovnt" && Mnemonic != "vmovnt" && Mnemonic != "vqdmullt" &&
6542      Mnemonic != "vpnot" && Mnemonic != "vcvtt" && Mnemonic != "vcvt") {
6543    unsigned CC = ARMVectorCondCodeFromString(Mnemonic.substr(Mnemonic.size()-1));
6544    if (CC != ~0U) {
6545      Mnemonic = Mnemonic.slice(0, Mnemonic.size()-1);
6546      VPTPredicationCode = CC;
6547    }
6548    return Mnemonic;
6549  }
6550
6551  // The "it" instruction has the condition mask on the end of the mnemonic.
6552  if (Mnemonic.startswith("it")) {
6553    ITMask = Mnemonic.slice(2, Mnemonic.size());
6554    Mnemonic = Mnemonic.slice(0, 2);
6555  }
6556
6557  if (Mnemonic.startswith("vpst")) {
6558    ITMask = Mnemonic.slice(4, Mnemonic.size());
6559    Mnemonic = Mnemonic.slice(0, 4);
6560  }
6561  else if (Mnemonic.startswith("vpt")) {
6562    ITMask = Mnemonic.slice(3, Mnemonic.size());
6563    Mnemonic = Mnemonic.slice(0, 3);
6564  }
6565
6566  return Mnemonic;
6567}
6568
6569/// Given a canonical mnemonic, determine if the instruction ever allows
6570/// inclusion of carry set or predication code operands.
6571//
6572// FIXME: It would be nice to autogen this.
6573void ARMAsmParser::getMnemonicAcceptInfo(StringRef Mnemonic,
6574                                         StringRef ExtraToken,
6575                                         StringRef FullInst,
6576                                         bool &CanAcceptCarrySet,
6577                                         bool &CanAcceptPredicationCode,
6578                                         bool &CanAcceptVPTPredicationCode) {
6579  CanAcceptVPTPredicationCode = isMnemonicVPTPredicable(Mnemonic, ExtraToken);
6580
6581  CanAcceptCarrySet =
6582      Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
6583      Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
6584      Mnemonic == "add" || Mnemonic == "adc" || Mnemonic == "mul" ||
6585      Mnemonic == "bic" || Mnemonic == "asr" || Mnemonic == "orr" ||
6586      Mnemonic == "mvn" || Mnemonic == "rsb" || Mnemonic == "rsc" ||
6587      Mnemonic == "orn" || Mnemonic == "sbc" || Mnemonic == "eor" ||
6588      Mnemonic == "neg" || Mnemonic == "vfm" || Mnemonic == "vfnm" ||
6589      (!isThumb() &&
6590       (Mnemonic == "smull" || Mnemonic == "mov" || Mnemonic == "mla" ||
6591        Mnemonic == "smlal" || Mnemonic == "umlal" || Mnemonic == "umull"));
6592
6593  if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" ||
6594      Mnemonic == "cps" || Mnemonic == "it" || Mnemonic == "cbz" ||
6595      Mnemonic == "trap" || Mnemonic == "hlt" || Mnemonic == "udf" ||
6596      Mnemonic.startswith("crc32") || Mnemonic.startswith("cps") ||
6597      Mnemonic.startswith("vsel") || Mnemonic == "vmaxnm" ||
6598      Mnemonic == "vminnm" || Mnemonic == "vcvta" || Mnemonic == "vcvtn" ||
6599      Mnemonic == "vcvtp" || Mnemonic == "vcvtm" || Mnemonic == "vrinta" ||
6600      Mnemonic == "vrintn" || Mnemonic == "vrintp" || Mnemonic == "vrintm" ||
6601      Mnemonic.startswith("aes") || Mnemonic == "hvc" || Mnemonic == "setpan" ||
6602      Mnemonic.startswith("sha1") || Mnemonic.startswith("sha256") ||
6603      (FullInst.startswith("vmull") && FullInst.endswith(".p64")) ||
6604      Mnemonic == "vmovx" || Mnemonic == "vins" ||
6605      Mnemonic == "vudot" || Mnemonic == "vsdot" ||
6606      Mnemonic == "vcmla" || Mnemonic == "vcadd" ||
6607      Mnemonic == "vfmal" || Mnemonic == "vfmsl" ||
6608      Mnemonic == "vfmat" || Mnemonic == "vfmab" ||
6609      Mnemonic == "vdot"  || Mnemonic == "vmmla" ||
6610      Mnemonic == "sb"    || Mnemonic == "ssbb"  ||
6611      Mnemonic == "pssbb" || Mnemonic == "vsmmla" ||
6612      Mnemonic == "vummla" || Mnemonic == "vusmmla" ||
6613      Mnemonic == "vusdot" || Mnemonic == "vsudot" ||
6614      Mnemonic == "bfcsel" || Mnemonic == "wls" ||
6615      Mnemonic == "dls" || Mnemonic == "le" || Mnemonic == "csel" ||
6616      Mnemonic == "csinc" || Mnemonic == "csinv" || Mnemonic == "csneg" ||
6617      Mnemonic == "cinc" || Mnemonic == "cinv" || Mnemonic == "cneg" ||
6618      Mnemonic == "cset" || Mnemonic == "csetm" ||
6619      (hasCDE() && MS.isCDEInstr(Mnemonic) &&
6620       !MS.isITPredicableCDEInstr(Mnemonic)) ||
6621      Mnemonic.startswith("vpt") || Mnemonic.startswith("vpst") ||
6622      Mnemonic == "pac" || Mnemonic == "pacbti" || Mnemonic == "aut" ||
6623      Mnemonic == "bti" ||
6624      (hasMVE() &&
6625       (Mnemonic.startswith("vst2") || Mnemonic.startswith("vld2") ||
6626        Mnemonic.startswith("vst4") || Mnemonic.startswith("vld4") ||
6627        Mnemonic.startswith("wlstp") || Mnemonic.startswith("dlstp") ||
6628        Mnemonic.startswith("letp")))) {
6629    // These mnemonics are never predicable
6630    CanAcceptPredicationCode = false;
6631  } else if (!isThumb()) {
6632    // Some instructions are only predicable in Thumb mode
6633    CanAcceptPredicationCode =
6634        Mnemonic != "cdp2" && Mnemonic != "clrex" && Mnemonic != "mcr2" &&
6635        Mnemonic != "mcrr2" && Mnemonic != "mrc2" && Mnemonic != "mrrc2" &&
6636        Mnemonic != "dmb" && Mnemonic != "dfb" && Mnemonic != "dsb" &&
6637        Mnemonic != "isb" && Mnemonic != "pld" && Mnemonic != "pli" &&
6638        Mnemonic != "pldw" && Mnemonic != "ldc2" && Mnemonic != "ldc2l" &&
6639        Mnemonic != "stc2" && Mnemonic != "stc2l" &&
6640        Mnemonic != "tsb" &&
6641        !Mnemonic.startswith("rfe") && !Mnemonic.startswith("srs");
6642  } else if (isThumbOne()) {
6643    if (hasV6MOps())
6644      CanAcceptPredicationCode = Mnemonic != "movs";
6645    else
6646      CanAcceptPredicationCode = Mnemonic != "nop" && Mnemonic != "movs";
6647  } else
6648    CanAcceptPredicationCode = true;
6649}
6650
6651// Some Thumb instructions have two operand forms that are not
6652// available as three operand, convert to two operand form if possible.
6653//
6654// FIXME: We would really like to be able to tablegen'erate this.
6655void ARMAsmParser::tryConvertingToTwoOperandForm(StringRef Mnemonic,
6656                                                 bool CarrySetting,
6657                                                 OperandVector &Operands) {
6658  if (Operands.size() != 6)
6659    return;
6660
6661  const auto &Op3 = static_cast<ARMOperand &>(*Operands[3]);
6662        auto &Op4 = static_cast<ARMOperand &>(*Operands[4]);
6663  if (!Op3.isReg() || !Op4.isReg())
6664    return;
6665
6666  auto Op3Reg = Op3.getReg();
6667  auto Op4Reg = Op4.getReg();
6668
6669  // For most Thumb2 cases we just generate the 3 operand form and reduce
6670  // it in processInstruction(), but the 3 operand form of ADD (t2ADDrr)
6671  // won't accept SP or PC so we do the transformation here taking care
6672  // with immediate range in the 'add sp, sp #imm' case.
6673  auto &Op5 = static_cast<ARMOperand &>(*Operands[5]);
6674  if (isThumbTwo()) {
6675    if (Mnemonic != "add")
6676      return;
6677    bool TryTransform = Op3Reg == ARM::PC || Op4Reg == ARM::PC ||
6678                        (Op5.isReg() && Op5.getReg() == ARM::PC);
6679    if (!TryTransform) {
6680      TryTransform = (Op3Reg == ARM::SP || Op4Reg == ARM::SP ||
6681                      (Op5.isReg() && Op5.getReg() == ARM::SP)) &&
6682                     !(Op3Reg == ARM::SP && Op4Reg == ARM::SP &&
6683                       Op5.isImm() && !Op5.isImm0_508s4());
6684    }
6685    if (!TryTransform)
6686      return;
6687  } else if (!isThumbOne())
6688    return;
6689
6690  if (!(Mnemonic == "add" || Mnemonic == "sub" || Mnemonic == "and" ||
6691        Mnemonic == "eor" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
6692        Mnemonic == "asr" || Mnemonic == "adc" || Mnemonic == "sbc" ||
6693        Mnemonic == "ror" || Mnemonic == "orr" || Mnemonic == "bic"))
6694    return;
6695
6696  // If first 2 operands of a 3 operand instruction are the same
6697  // then transform to 2 operand version of the same instruction
6698  // e.g. 'adds r0, r0, #1' transforms to 'adds r0, #1'
6699  bool Transform = Op3Reg == Op4Reg;
6700
6701  // For communtative operations, we might be able to transform if we swap
6702  // Op4 and Op5.  The 'ADD Rdm, SP, Rdm' form is already handled specially
6703  // as tADDrsp.
6704  const ARMOperand *LastOp = &Op5;
6705  bool Swap = false;
6706  if (!Transform && Op5.isReg() && Op3Reg == Op5.getReg() &&
6707      ((Mnemonic == "add" && Op4Reg != ARM::SP) ||
6708       Mnemonic == "and" || Mnemonic == "eor" ||
6709       Mnemonic == "adc" || Mnemonic == "orr")) {
6710    Swap = true;
6711    LastOp = &Op4;
6712    Transform = true;
6713  }
6714
6715  // If both registers are the same then remove one of them from
6716  // the operand list, with certain exceptions.
6717  if (Transform) {
6718    // Don't transform 'adds Rd, Rd, Rm' or 'sub{s} Rd, Rd, Rm' because the
6719    // 2 operand forms don't exist.
6720    if (((Mnemonic == "add" && CarrySetting) || Mnemonic == "sub") &&
6721        LastOp->isReg())
6722      Transform = false;
6723
6724    // Don't transform 'add/sub{s} Rd, Rd, #imm' if the immediate fits into
6725    // 3-bits because the ARMARM says not to.
6726    if ((Mnemonic == "add" || Mnemonic == "sub") && LastOp->isImm0_7())
6727      Transform = false;
6728  }
6729
6730  if (Transform) {
6731    if (Swap)
6732      std::swap(Op4, Op5);
6733    Operands.erase(Operands.begin() + 3);
6734  }
6735}
6736
6737bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
6738                                          OperandVector &Operands) {
6739  // FIXME: This is all horribly hacky. We really need a better way to deal
6740  // with optional operands like this in the matcher table.
6741
6742  // The 'mov' mnemonic is special. One variant has a cc_out operand, while
6743  // another does not. Specifically, the MOVW instruction does not. So we
6744  // special case it here and remove the defaulted (non-setting) cc_out
6745  // operand if that's the instruction we're trying to match.
6746  //
6747  // We do this as post-processing of the explicit operands rather than just
6748  // conditionally adding the cc_out in the first place because we need
6749  // to check the type of the parsed immediate operand.
6750  if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
6751      !static_cast<ARMOperand &>(*Operands[4]).isModImm() &&
6752      static_cast<ARMOperand &>(*Operands[4]).isImm0_65535Expr() &&
6753      static_cast<ARMOperand &>(*Operands[1]).getReg() == 0)
6754    return true;
6755
6756  // Register-register 'add' for thumb does not have a cc_out operand
6757  // when there are only two register operands.
6758  if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
6759      static_cast<ARMOperand &>(*Operands[3]).isReg() &&
6760      static_cast<ARMOperand &>(*Operands[4]).isReg() &&
6761      static_cast<ARMOperand &>(*Operands[1]).getReg() == 0)
6762    return true;
6763  // Register-register 'add' for thumb does not have a cc_out operand
6764  // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
6765  // have to check the immediate range here since Thumb2 has a variant
6766  // that can handle a different range and has a cc_out operand.
6767  if (((isThumb() && Mnemonic == "add") ||
6768       (isThumbTwo() && Mnemonic == "sub")) &&
6769      Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() &&
6770      static_cast<ARMOperand &>(*Operands[4]).isReg() &&
6771      static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::SP &&
6772      static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
6773      ((Mnemonic == "add" && static_cast<ARMOperand &>(*Operands[5]).isReg()) ||
6774       static_cast<ARMOperand &>(*Operands[5]).isImm0_1020s4()))
6775    return true;
6776  // For Thumb2, add/sub immediate does not have a cc_out operand for the
6777  // imm0_4095 variant. That's the least-preferred variant when
6778  // selecting via the generic "add" mnemonic, so to know that we
6779  // should remove the cc_out operand, we have to explicitly check that
6780  // it's not one of the other variants. Ugh.
6781  if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
6782      Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() &&
6783      static_cast<ARMOperand &>(*Operands[4]).isReg() &&
6784      static_cast<ARMOperand &>(*Operands[5]).isImm()) {
6785    // Nest conditions rather than one big 'if' statement for readability.
6786    //
6787    // If both registers are low, we're in an IT block, and the immediate is
6788    // in range, we should use encoding T1 instead, which has a cc_out.
6789    if (inITBlock() &&
6790        isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) &&
6791        isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) &&
6792        static_cast<ARMOperand &>(*Operands[5]).isImm0_7())
6793      return false;
6794    // Check against T3. If the second register is the PC, this is an
6795    // alternate form of ADR, which uses encoding T4, so check for that too.
6796    if (static_cast<ARMOperand &>(*Operands[4]).getReg() != ARM::PC &&
6797        (static_cast<ARMOperand &>(*Operands[5]).isT2SOImm() ||
6798         static_cast<ARMOperand &>(*Operands[5]).isT2SOImmNeg()))
6799      return false;
6800
6801    // Otherwise, we use encoding T4, which does not have a cc_out
6802    // operand.
6803    return true;
6804  }
6805
6806  // The thumb2 multiply instruction doesn't have a CCOut register, so
6807  // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
6808  // use the 16-bit encoding or not.
6809  if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
6810      static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
6811      static_cast<ARMOperand &>(*Operands[3]).isReg() &&
6812      static_cast<ARMOperand &>(*Operands[4]).isReg() &&
6813      static_cast<ARMOperand &>(*Operands[5]).isReg() &&
6814      // If the registers aren't low regs, the destination reg isn't the
6815      // same as one of the source regs, or the cc_out operand is zero
6816      // outside of an IT block, we have to use the 32-bit encoding, so
6817      // remove the cc_out operand.
6818      (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) ||
6819       !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) ||
6820       !isARMLowRegister(static_cast<ARMOperand &>(*Operands[5]).getReg()) ||
6821       !inITBlock() || (static_cast<ARMOperand &>(*Operands[3]).getReg() !=
6822                            static_cast<ARMOperand &>(*Operands[5]).getReg() &&
6823                        static_cast<ARMOperand &>(*Operands[3]).getReg() !=
6824                            static_cast<ARMOperand &>(*Operands[4]).getReg())))
6825    return true;
6826
6827  // Also check the 'mul' syntax variant that doesn't specify an explicit
6828  // destination register.
6829  if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
6830      static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
6831      static_cast<ARMOperand &>(*Operands[3]).isReg() &&
6832      static_cast<ARMOperand &>(*Operands[4]).isReg() &&
6833      // If the registers aren't low regs  or the cc_out operand is zero
6834      // outside of an IT block, we have to use the 32-bit encoding, so
6835      // remove the cc_out operand.
6836      (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) ||
6837       !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) ||
6838       !inITBlock()))
6839    return true;
6840
6841  // Register-register 'add/sub' for thumb does not have a cc_out operand
6842  // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
6843  // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
6844  // right, this will result in better diagnostics (which operand is off)
6845  // anyway.
6846  if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
6847      (Operands.size() == 5 || Operands.size() == 6) &&
6848      static_cast<ARMOperand &>(*Operands[3]).isReg() &&
6849      static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::SP &&
6850      static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
6851      (static_cast<ARMOperand &>(*Operands[4]).isImm() ||
6852       (Operands.size() == 6 &&
6853        static_cast<ARMOperand &>(*Operands[5]).isImm()))) {
6854    // Thumb2 (add|sub){s}{p}.w GPRnopc, sp, #{T2SOImm} has cc_out
6855    return (!(isThumbTwo() &&
6856              (static_cast<ARMOperand &>(*Operands[4]).isT2SOImm() ||
6857               static_cast<ARMOperand &>(*Operands[4]).isT2SOImmNeg())));
6858  }
6859  // Fixme: Should join all the thumb+thumb2 (add|sub) in a single if case
6860  // Thumb2 ADD r0, #4095 -> ADDW r0, r0, #4095 (T4)
6861  // Thumb2 SUB r0, #4095 -> SUBW r0, r0, #4095
6862  if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
6863      (Operands.size() == 5) &&
6864      static_cast<ARMOperand &>(*Operands[3]).isReg() &&
6865      static_cast<ARMOperand &>(*Operands[3]).getReg() != ARM::SP &&
6866      static_cast<ARMOperand &>(*Operands[3]).getReg() != ARM::PC &&
6867      static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
6868      static_cast<ARMOperand &>(*Operands[4]).isImm()) {
6869    const ARMOperand &IMM = static_cast<ARMOperand &>(*Operands[4]);
6870    if (IMM.isT2SOImm() || IMM.isT2SOImmNeg())
6871      return false; // add.w / sub.w
6872    if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(IMM.getImm())) {
6873      const int64_t Value = CE->getValue();
6874      // Thumb1 imm8 sub / add
6875      if ((Value < ((1 << 7) - 1) << 2) && inITBlock() && (!(Value & 3)) &&
6876          isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()))
6877        return false;
6878      return true; // Thumb2 T4 addw / subw
6879    }
6880  }
6881  return false;
6882}
6883
6884bool ARMAsmParser::shouldOmitPredicateOperand(StringRef Mnemonic,
6885                                              OperandVector &Operands) {
6886  // VRINT{Z, X} have a predicate operand in VFP, but not in NEON
6887  unsigned RegIdx = 3;
6888  if ((((Mnemonic == "vrintz" || Mnemonic == "vrintx") && !hasMVE()) ||
6889      Mnemonic == "vrintr") &&
6890      (static_cast<ARMOperand &>(*Operands[2]).getToken() == ".f32" ||
6891       static_cast<ARMOperand &>(*Operands[2]).getToken() == ".f16")) {
6892    if (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
6893        (static_cast<ARMOperand &>(*Operands[3]).getToken() == ".f32" ||
6894         static_cast<ARMOperand &>(*Operands[3]).getToken() == ".f16"))
6895      RegIdx = 4;
6896
6897    if (static_cast<ARMOperand &>(*Operands[RegIdx]).isReg() &&
6898        (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(
6899             static_cast<ARMOperand &>(*Operands[RegIdx]).getReg()) ||
6900         ARMMCRegisterClasses[ARM::QPRRegClassID].contains(
6901             static_cast<ARMOperand &>(*Operands[RegIdx]).getReg())))
6902      return true;
6903  }
6904  return false;
6905}
6906
6907bool ARMAsmParser::shouldOmitVectorPredicateOperand(StringRef Mnemonic,
6908                                                    OperandVector &Operands) {
6909  if (!hasMVE() || Operands.size() < 3)
6910    return true;
6911
6912  if (Mnemonic.startswith("vld2") || Mnemonic.startswith("vld4") ||
6913      Mnemonic.startswith("vst2") || Mnemonic.startswith("vst4"))
6914    return true;
6915
6916  if (Mnemonic.startswith("vctp") || Mnemonic.startswith("vpnot"))
6917    return false;
6918
6919  if (Mnemonic.startswith("vmov") &&
6920      !(Mnemonic.startswith("vmovl") || Mnemonic.startswith("vmovn") ||
6921        Mnemonic.startswith("vmovx"))) {
6922    for (auto &Operand : Operands) {
6923      if (static_cast<ARMOperand &>(*Operand).isVectorIndex() ||
6924          ((*Operand).isReg() &&
6925           (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(
6926             (*Operand).getReg()) ||
6927            ARMMCRegisterClasses[ARM::DPRRegClassID].contains(
6928              (*Operand).getReg())))) {
6929        return true;
6930      }
6931    }
6932    return false;
6933  } else {
6934    for (auto &Operand : Operands) {
6935      // We check the larger class QPR instead of just the legal class
6936      // MQPR, to more accurately report errors when using Q registers
6937      // outside of the allowed range.
6938      if (static_cast<ARMOperand &>(*Operand).isVectorIndex() ||
6939          (Operand->isReg() &&
6940           (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(
6941             Operand->getReg()))))
6942        return false;
6943    }
6944    return true;
6945  }
6946}
6947
6948static bool isDataTypeToken(StringRef Tok) {
6949  return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
6950    Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
6951    Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
6952    Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
6953    Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
6954    Tok == ".f" || Tok == ".d";
6955}
6956
6957// FIXME: This bit should probably be handled via an explicit match class
6958// in the .td files that matches the suffix instead of having it be
6959// a literal string token the way it is now.
6960static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
6961  return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
6962}
6963
6964static void applyMnemonicAliases(StringRef &Mnemonic,
6965                                 const FeatureBitset &Features,
6966                                 unsigned VariantID);
6967
6968// The GNU assembler has aliases of ldrd and strd with the second register
6969// omitted. We don't have a way to do that in tablegen, so fix it up here.
6970//
6971// We have to be careful to not emit an invalid Rt2 here, because the rest of
6972// the assembly parser could then generate confusing diagnostics refering to
6973// it. If we do find anything that prevents us from doing the transformation we
6974// bail out, and let the assembly parser report an error on the instruction as
6975// it is written.
6976void ARMAsmParser::fixupGNULDRDAlias(StringRef Mnemonic,
6977                                     OperandVector &Operands) {
6978  if (Mnemonic != "ldrd" && Mnemonic != "strd")
6979    return;
6980  if (Operands.size() < 4)
6981    return;
6982
6983  ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[2]);
6984  ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[3]);
6985
6986  if (!Op2.isReg())
6987    return;
6988  if (!Op3.isGPRMem())
6989    return;
6990
6991  const MCRegisterClass &GPR = MRI->getRegClass(ARM::GPRRegClassID);
6992  if (!GPR.contains(Op2.getReg()))
6993    return;
6994
6995  unsigned RtEncoding = MRI->getEncodingValue(Op2.getReg());
6996  if (!isThumb() && (RtEncoding & 1)) {
6997    // In ARM mode, the registers must be from an aligned pair, this
6998    // restriction does not apply in Thumb mode.
6999    return;
7000  }
7001  if (Op2.getReg() == ARM::PC)
7002    return;
7003  unsigned PairedReg = GPR.getRegister(RtEncoding + 1);
7004  if (!PairedReg || PairedReg == ARM::PC ||
7005      (PairedReg == ARM::SP && !hasV8Ops()))
7006    return;
7007
7008  Operands.insert(
7009      Operands.begin() + 3,
7010      ARMOperand::CreateReg(PairedReg, Op2.getStartLoc(), Op2.getEndLoc()));
7011}
7012
7013// Dual-register instruction have the following syntax:
7014// <mnemonic> <predicate>? <coproc>, <Rdest>, <Rdest+1>, <Rsrc>, ..., #imm
7015// This function tries to remove <Rdest+1> and replace <Rdest> with a pair
7016// operand. If the conversion fails an error is diagnosed, and the function
7017// returns true.
7018bool ARMAsmParser::CDEConvertDualRegOperand(StringRef Mnemonic,
7019                                            OperandVector &Operands) {
7020  assert(MS.isCDEDualRegInstr(Mnemonic));
7021  bool isPredicable =
7022      Mnemonic == "cx1da" || Mnemonic == "cx2da" || Mnemonic == "cx3da";
7023  size_t NumPredOps = isPredicable ? 1 : 0;
7024
7025  if (Operands.size() <= 3 + NumPredOps)
7026    return false;
7027
7028  StringRef Op2Diag(
7029      "operand must be an even-numbered register in the range [r0, r10]");
7030
7031  const MCParsedAsmOperand &Op2 = *Operands[2 + NumPredOps];
7032  if (!Op2.isReg())
7033    return Error(Op2.getStartLoc(), Op2Diag);
7034
7035  unsigned RNext;
7036  unsigned RPair;
7037  switch (Op2.getReg()) {
7038  default:
7039    return Error(Op2.getStartLoc(), Op2Diag);
7040  case ARM::R0:
7041    RNext = ARM::R1;
7042    RPair = ARM::R0_R1;
7043    break;
7044  case ARM::R2:
7045    RNext = ARM::R3;
7046    RPair = ARM::R2_R3;
7047    break;
7048  case ARM::R4:
7049    RNext = ARM::R5;
7050    RPair = ARM::R4_R5;
7051    break;
7052  case ARM::R6:
7053    RNext = ARM::R7;
7054    RPair = ARM::R6_R7;
7055    break;
7056  case ARM::R8:
7057    RNext = ARM::R9;
7058    RPair = ARM::R8_R9;
7059    break;
7060  case ARM::R10:
7061    RNext = ARM::R11;
7062    RPair = ARM::R10_R11;
7063    break;
7064  }
7065
7066  const MCParsedAsmOperand &Op3 = *Operands[3 + NumPredOps];
7067  if (!Op3.isReg() || Op3.getReg() != RNext)
7068    return Error(Op3.getStartLoc(), "operand must be a consecutive register");
7069
7070  Operands.erase(Operands.begin() + 3 + NumPredOps);
7071  Operands[2 + NumPredOps] =
7072      ARMOperand::CreateReg(RPair, Op2.getStartLoc(), Op2.getEndLoc());
7073  return false;
7074}
7075
7076/// Parse an arm instruction mnemonic followed by its operands.
7077bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
7078                                    SMLoc NameLoc, OperandVector &Operands) {
7079  MCAsmParser &Parser = getParser();
7080
7081  // Apply mnemonic aliases before doing anything else, as the destination
7082  // mnemonic may include suffices and we want to handle them normally.
7083  // The generic tblgen'erated code does this later, at the start of
7084  // MatchInstructionImpl(), but that's too late for aliases that include
7085  // any sort of suffix.
7086  const FeatureBitset &AvailableFeatures = getAvailableFeatures();
7087  unsigned AssemblerDialect = getParser().getAssemblerDialect();
7088  applyMnemonicAliases(Name, AvailableFeatures, AssemblerDialect);
7089
7090  // First check for the ARM-specific .req directive.
7091  if (Parser.getTok().is(AsmToken::Identifier) &&
7092      Parser.getTok().getIdentifier().lower() == ".req") {
7093    parseDirectiveReq(Name, NameLoc);
7094    // We always return 'error' for this, as we're done with this
7095    // statement and don't need to match the 'instruction."
7096    return true;
7097  }
7098
7099  // Create the leading tokens for the mnemonic, split by '.' characters.
7100  size_t Start = 0, Next = Name.find('.');
7101  StringRef Mnemonic = Name.slice(Start, Next);
7102  StringRef ExtraToken = Name.slice(Next, Name.find(' ', Next + 1));
7103
7104  // Split out the predication code and carry setting flag from the mnemonic.
7105  unsigned PredicationCode;
7106  unsigned VPTPredicationCode;
7107  unsigned ProcessorIMod;
7108  bool CarrySetting;
7109  StringRef ITMask;
7110  Mnemonic = splitMnemonic(Mnemonic, ExtraToken, PredicationCode, VPTPredicationCode,
7111                           CarrySetting, ProcessorIMod, ITMask);
7112
7113  // In Thumb1, only the branch (B) instruction can be predicated.
7114  if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
7115    return Error(NameLoc, "conditional execution not supported in Thumb1");
7116  }
7117
7118  Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
7119
7120  // Handle the mask for IT and VPT instructions. In ARMOperand and
7121  // MCOperand, this is stored in a format independent of the
7122  // condition code: the lowest set bit indicates the end of the
7123  // encoding, and above that, a 1 bit indicates 'else', and an 0
7124  // indicates 'then'. E.g.
7125  //    IT    -> 1000
7126  //    ITx   -> x100    (ITT -> 0100, ITE -> 1100)
7127  //    ITxy  -> xy10    (e.g. ITET -> 1010)
7128  //    ITxyz -> xyz1    (e.g. ITEET -> 1101)
7129  // Note: See the ARM::PredBlockMask enum in
7130  //   /lib/Target/ARM/Utils/ARMBaseInfo.h
7131  if (Mnemonic == "it" || Mnemonic.startswith("vpt") ||
7132      Mnemonic.startswith("vpst")) {
7133    SMLoc Loc = Mnemonic == "it"  ? SMLoc::getFromPointer(NameLoc.getPointer() + 2) :
7134                Mnemonic == "vpt" ? SMLoc::getFromPointer(NameLoc.getPointer() + 3) :
7135                                    SMLoc::getFromPointer(NameLoc.getPointer() + 4);
7136    if (ITMask.size() > 3) {
7137      if (Mnemonic == "it")
7138        return Error(Loc, "too many conditions on IT instruction");
7139      return Error(Loc, "too many conditions on VPT instruction");
7140    }
7141    unsigned Mask = 8;
7142    for (char Pos : llvm::reverse(ITMask)) {
7143      if (Pos != 't' && Pos != 'e') {
7144        return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
7145      }
7146      Mask >>= 1;
7147      if (Pos == 'e')
7148        Mask |= 8;
7149    }
7150    Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
7151  }
7152
7153  // FIXME: This is all a pretty gross hack. We should automatically handle
7154  // optional operands like this via tblgen.
7155
7156  // Next, add the CCOut and ConditionCode operands, if needed.
7157  //
7158  // For mnemonics which can ever incorporate a carry setting bit or predication
7159  // code, our matching model involves us always generating CCOut and
7160  // ConditionCode operands to match the mnemonic "as written" and then we let
7161  // the matcher deal with finding the right instruction or generating an
7162  // appropriate error.
7163  bool CanAcceptCarrySet, CanAcceptPredicationCode, CanAcceptVPTPredicationCode;
7164  getMnemonicAcceptInfo(Mnemonic, ExtraToken, Name, CanAcceptCarrySet,
7165                        CanAcceptPredicationCode, CanAcceptVPTPredicationCode);
7166
7167  // If we had a carry-set on an instruction that can't do that, issue an
7168  // error.
7169  if (!CanAcceptCarrySet && CarrySetting) {
7170    return Error(NameLoc, "instruction '" + Mnemonic +
7171                 "' can not set flags, but 's' suffix specified");
7172  }
7173  // If we had a predication code on an instruction that can't do that, issue an
7174  // error.
7175  if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
7176    return Error(NameLoc, "instruction '" + Mnemonic +
7177                 "' is not predicable, but condition code specified");
7178  }
7179
7180  // If we had a VPT predication code on an instruction that can't do that, issue an
7181  // error.
7182  if (!CanAcceptVPTPredicationCode && VPTPredicationCode != ARMVCC::None) {
7183    return Error(NameLoc, "instruction '" + Mnemonic +
7184                 "' is not VPT predicable, but VPT code T/E is specified");
7185  }
7186
7187  // Add the carry setting operand, if necessary.
7188  if (CanAcceptCarrySet) {
7189    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
7190    Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
7191                                               Loc));
7192  }
7193
7194  // Add the predication code operand, if necessary.
7195  if (CanAcceptPredicationCode) {
7196    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
7197                                      CarrySetting);
7198    Operands.push_back(ARMOperand::CreateCondCode(
7199                       ARMCC::CondCodes(PredicationCode), Loc));
7200  }
7201
7202  // Add the VPT predication code operand, if necessary.
7203  // FIXME: We don't add them for the instructions filtered below as these can
7204  // have custom operands which need special parsing.  This parsing requires
7205  // the operand to be in the same place in the OperandVector as their
7206  // definition in tblgen.  Since these instructions may also have the
7207  // scalar predication operand we do not add the vector one and leave until
7208  // now to fix it up.
7209  if (CanAcceptVPTPredicationCode && Mnemonic != "vmov" &&
7210      !Mnemonic.startswith("vcmp") &&
7211      !(Mnemonic.startswith("vcvt") && Mnemonic != "vcvta" &&
7212        Mnemonic != "vcvtn" && Mnemonic != "vcvtp" && Mnemonic != "vcvtm")) {
7213    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
7214                                      CarrySetting);
7215    Operands.push_back(ARMOperand::CreateVPTPred(
7216                         ARMVCC::VPTCodes(VPTPredicationCode), Loc));
7217  }
7218
7219  // Add the processor imod operand, if necessary.
7220  if (ProcessorIMod) {
7221    Operands.push_back(ARMOperand::CreateImm(
7222          MCConstantExpr::create(ProcessorIMod, getContext()),
7223                                 NameLoc, NameLoc));
7224  } else if (Mnemonic == "cps" && isMClass()) {
7225    return Error(NameLoc, "instruction 'cps' requires effect for M-class");
7226  }
7227
7228  // Add the remaining tokens in the mnemonic.
7229  while (Next != StringRef::npos) {
7230    Start = Next;
7231    Next = Name.find('.', Start + 1);
7232    ExtraToken = Name.slice(Start, Next);
7233
7234    // Some NEON instructions have an optional datatype suffix that is
7235    // completely ignored. Check for that.
7236    if (isDataTypeToken(ExtraToken) &&
7237        doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
7238      continue;
7239
7240    // For for ARM mode generate an error if the .n qualifier is used.
7241    if (ExtraToken == ".n" && !isThumb()) {
7242      SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
7243      return Error(Loc, "instruction with .n (narrow) qualifier not allowed in "
7244                   "arm mode");
7245    }
7246
7247    // The .n qualifier is always discarded as that is what the tables
7248    // and matcher expect.  In ARM mode the .w qualifier has no effect,
7249    // so discard it to avoid errors that can be caused by the matcher.
7250    if (ExtraToken != ".n" && (isThumb() || ExtraToken != ".w")) {
7251      SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
7252      Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
7253    }
7254  }
7255
7256  // Read the remaining operands.
7257  if (getLexer().isNot(AsmToken::EndOfStatement)) {
7258    // Read the first operand.
7259    if (parseOperand(Operands, Mnemonic)) {
7260      return true;
7261    }
7262
7263    while (parseOptionalToken(AsmToken::Comma)) {
7264      // Parse and remember the operand.
7265      if (parseOperand(Operands, Mnemonic)) {
7266        return true;
7267      }
7268    }
7269  }
7270
7271  if (parseToken(AsmToken::EndOfStatement, "unexpected token in argument list"))
7272    return true;
7273
7274  tryConvertingToTwoOperandForm(Mnemonic, CarrySetting, Operands);
7275
7276  if (hasCDE() && MS.isCDEInstr(Mnemonic)) {
7277    // Dual-register instructions use even-odd register pairs as their
7278    // destination operand, in assembly such pair is spelled as two
7279    // consecutive registers, without any special syntax. ConvertDualRegOperand
7280    // tries to convert such operand into register pair, e.g. r2, r3 -> r2_r3.
7281    // It returns true, if an error message has been emitted. If the function
7282    // returns false, the function either succeeded or an error (e.g. missing
7283    // operand) will be diagnosed elsewhere.
7284    if (MS.isCDEDualRegInstr(Mnemonic)) {
7285      bool GotError = CDEConvertDualRegOperand(Mnemonic, Operands);
7286      if (GotError)
7287        return GotError;
7288    }
7289  }
7290
7291  // Some instructions, mostly Thumb, have forms for the same mnemonic that
7292  // do and don't have a cc_out optional-def operand. With some spot-checks
7293  // of the operand list, we can figure out which variant we're trying to
7294  // parse and adjust accordingly before actually matching. We shouldn't ever
7295  // try to remove a cc_out operand that was explicitly set on the
7296  // mnemonic, of course (CarrySetting == true). Reason number #317 the
7297  // table driven matcher doesn't fit well with the ARM instruction set.
7298  if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands))
7299    Operands.erase(Operands.begin() + 1);
7300
7301  // Some instructions have the same mnemonic, but don't always
7302  // have a predicate. Distinguish them here and delete the
7303  // appropriate predicate if needed.  This could be either the scalar
7304  // predication code or the vector predication code.
7305  if (PredicationCode == ARMCC::AL &&
7306      shouldOmitPredicateOperand(Mnemonic, Operands))
7307    Operands.erase(Operands.begin() + 1);
7308
7309
7310  if (hasMVE()) {
7311    if (!shouldOmitVectorPredicateOperand(Mnemonic, Operands) &&
7312        Mnemonic == "vmov" && PredicationCode == ARMCC::LT) {
7313      // Very nasty hack to deal with the vector predicated variant of vmovlt
7314      // the scalar predicated vmov with condition 'lt'.  We can not tell them
7315      // apart until we have parsed their operands.
7316      Operands.erase(Operands.begin() + 1);
7317      Operands.erase(Operands.begin());
7318      SMLoc MLoc = SMLoc::getFromPointer(NameLoc.getPointer());
7319      SMLoc PLoc = SMLoc::getFromPointer(NameLoc.getPointer() +
7320                                         Mnemonic.size() - 1 + CarrySetting);
7321      Operands.insert(Operands.begin(),
7322                      ARMOperand::CreateVPTPred(ARMVCC::None, PLoc));
7323      Operands.insert(Operands.begin(),
7324                      ARMOperand::CreateToken(StringRef("vmovlt"), MLoc));
7325    } else if (Mnemonic == "vcvt" && PredicationCode == ARMCC::NE &&
7326               !shouldOmitVectorPredicateOperand(Mnemonic, Operands)) {
7327      // Another nasty hack to deal with the ambiguity between vcvt with scalar
7328      // predication 'ne' and vcvtn with vector predication 'e'.  As above we
7329      // can only distinguish between the two after we have parsed their
7330      // operands.
7331      Operands.erase(Operands.begin() + 1);
7332      Operands.erase(Operands.begin());
7333      SMLoc MLoc = SMLoc::getFromPointer(NameLoc.getPointer());
7334      SMLoc PLoc = SMLoc::getFromPointer(NameLoc.getPointer() +
7335                                         Mnemonic.size() - 1 + CarrySetting);
7336      Operands.insert(Operands.begin(),
7337                      ARMOperand::CreateVPTPred(ARMVCC::Else, PLoc));
7338      Operands.insert(Operands.begin(),
7339                      ARMOperand::CreateToken(StringRef("vcvtn"), MLoc));
7340    } else if (Mnemonic == "vmul" && PredicationCode == ARMCC::LT &&
7341               !shouldOmitVectorPredicateOperand(Mnemonic, Operands)) {
7342      // Another hack, this time to distinguish between scalar predicated vmul
7343      // with 'lt' predication code and the vector instruction vmullt with
7344      // vector predication code "none"
7345      Operands.erase(Operands.begin() + 1);
7346      Operands.erase(Operands.begin());
7347      SMLoc MLoc = SMLoc::getFromPointer(NameLoc.getPointer());
7348      Operands.insert(Operands.begin(),
7349                      ARMOperand::CreateToken(StringRef("vmullt"), MLoc));
7350    }
7351    // For vmov and vcmp, as mentioned earlier, we did not add the vector
7352    // predication code, since these may contain operands that require
7353    // special parsing.  So now we have to see if they require vector
7354    // predication and replace the scalar one with the vector predication
7355    // operand if that is the case.
7356    else if (Mnemonic == "vmov" || Mnemonic.startswith("vcmp") ||
7357             (Mnemonic.startswith("vcvt") && !Mnemonic.startswith("vcvta") &&
7358              !Mnemonic.startswith("vcvtn") && !Mnemonic.startswith("vcvtp") &&
7359              !Mnemonic.startswith("vcvtm"))) {
7360      if (!shouldOmitVectorPredicateOperand(Mnemonic, Operands)) {
7361        // We could not split the vector predicate off vcvt because it might
7362        // have been the scalar vcvtt instruction.  Now we know its a vector
7363        // instruction, we still need to check whether its the vector
7364        // predicated vcvt with 'Then' predication or the vector vcvtt.  We can
7365        // distinguish the two based on the suffixes, if it is any of
7366        // ".f16.f32", ".f32.f16", ".f16.f64" or ".f64.f16" then it is the vcvtt.
7367        if (Mnemonic.startswith("vcvtt") && Operands.size() >= 4) {
7368          auto Sz1 = static_cast<ARMOperand &>(*Operands[2]);
7369          auto Sz2 = static_cast<ARMOperand &>(*Operands[3]);
7370          if (!(Sz1.isToken() && Sz1.getToken().startswith(".f") &&
7371              Sz2.isToken() && Sz2.getToken().startswith(".f"))) {
7372            Operands.erase(Operands.begin());
7373            SMLoc MLoc = SMLoc::getFromPointer(NameLoc.getPointer());
7374            VPTPredicationCode = ARMVCC::Then;
7375
7376            Mnemonic = Mnemonic.substr(0, 4);
7377            Operands.insert(Operands.begin(),
7378                            ARMOperand::CreateToken(Mnemonic, MLoc));
7379          }
7380        }
7381        Operands.erase(Operands.begin() + 1);
7382        SMLoc PLoc = SMLoc::getFromPointer(NameLoc.getPointer() +
7383                                          Mnemonic.size() + CarrySetting);
7384        Operands.insert(Operands.begin() + 1,
7385                        ARMOperand::CreateVPTPred(
7386                            ARMVCC::VPTCodes(VPTPredicationCode), PLoc));
7387      }
7388    } else if (CanAcceptVPTPredicationCode) {
7389      // For all other instructions, make sure only one of the two
7390      // predication operands is left behind, depending on whether we should
7391      // use the vector predication.
7392      if (shouldOmitVectorPredicateOperand(Mnemonic, Operands)) {
7393        if (CanAcceptPredicationCode)
7394          Operands.erase(Operands.begin() + 2);
7395        else
7396          Operands.erase(Operands.begin() + 1);
7397      } else if (CanAcceptPredicationCode && PredicationCode == ARMCC::AL) {
7398        Operands.erase(Operands.begin() + 1);
7399      }
7400    }
7401  }
7402
7403  if (VPTPredicationCode != ARMVCC::None) {
7404    bool usedVPTPredicationCode = false;
7405    for (unsigned I = 1; I < Operands.size(); ++I)
7406      if (static_cast<ARMOperand &>(*Operands[I]).isVPTPred())
7407        usedVPTPredicationCode = true;
7408    if (!usedVPTPredicationCode) {
7409      // If we have a VPT predication code and we haven't just turned it
7410      // into an operand, then it was a mistake for splitMnemonic to
7411      // separate it from the rest of the mnemonic in the first place,
7412      // and this may lead to wrong disassembly (e.g. scalar floating
7413      // point VCMPE is actually a different instruction from VCMP, so
7414      // we mustn't treat them the same). In that situation, glue it
7415      // back on.
7416      Mnemonic = Name.slice(0, Mnemonic.size() + 1);
7417      Operands.erase(Operands.begin());
7418      Operands.insert(Operands.begin(),
7419                      ARMOperand::CreateToken(Mnemonic, NameLoc));
7420    }
7421  }
7422
7423    // ARM mode 'blx' need special handling, as the register operand version
7424    // is predicable, but the label operand version is not. So, we can't rely
7425    // on the Mnemonic based checking to correctly figure out when to put
7426    // a k_CondCode operand in the list. If we're trying to match the label
7427    // version, remove the k_CondCode operand here.
7428    if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
7429        static_cast<ARMOperand &>(*Operands[2]).isImm())
7430      Operands.erase(Operands.begin() + 1);
7431
7432    // Adjust operands of ldrexd/strexd to MCK_GPRPair.
7433    // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
7434    // a single GPRPair reg operand is used in the .td file to replace the two
7435    // GPRs. However, when parsing from asm, the two GRPs cannot be
7436    // automatically
7437    // expressed as a GPRPair, so we have to manually merge them.
7438    // FIXME: We would really like to be able to tablegen'erate this.
7439    if (!isThumb() && Operands.size() > 4 &&
7440        (Mnemonic == "ldrexd" || Mnemonic == "strexd" || Mnemonic == "ldaexd" ||
7441         Mnemonic == "stlexd")) {
7442      bool isLoad = (Mnemonic == "ldrexd" || Mnemonic == "ldaexd");
7443      unsigned Idx = isLoad ? 2 : 3;
7444      ARMOperand &Op1 = static_cast<ARMOperand &>(*Operands[Idx]);
7445      ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[Idx + 1]);
7446
7447      const MCRegisterClass &MRC = MRI->getRegClass(ARM::GPRRegClassID);
7448      // Adjust only if Op1 and Op2 are GPRs.
7449      if (Op1.isReg() && Op2.isReg() && MRC.contains(Op1.getReg()) &&
7450          MRC.contains(Op2.getReg())) {
7451        unsigned Reg1 = Op1.getReg();
7452        unsigned Reg2 = Op2.getReg();
7453        unsigned Rt = MRI->getEncodingValue(Reg1);
7454        unsigned Rt2 = MRI->getEncodingValue(Reg2);
7455
7456        // Rt2 must be Rt + 1 and Rt must be even.
7457        if (Rt + 1 != Rt2 || (Rt & 1)) {
7458          return Error(Op2.getStartLoc(),
7459                       isLoad ? "destination operands must be sequential"
7460                              : "source operands must be sequential");
7461        }
7462        unsigned NewReg = MRI->getMatchingSuperReg(
7463            Reg1, ARM::gsub_0, &(MRI->getRegClass(ARM::GPRPairRegClassID)));
7464        Operands[Idx] =
7465            ARMOperand::CreateReg(NewReg, Op1.getStartLoc(), Op2.getEndLoc());
7466        Operands.erase(Operands.begin() + Idx + 1);
7467      }
7468  }
7469
7470  // GNU Assembler extension (compatibility).
7471  fixupGNULDRDAlias(Mnemonic, Operands);
7472
7473  // FIXME: As said above, this is all a pretty gross hack.  This instruction
7474  // does not fit with other "subs" and tblgen.
7475  // Adjust operands of B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction
7476  // so the Mnemonic is the original name "subs" and delete the predicate
7477  // operand so it will match the table entry.
7478  if (isThumbTwo() && Mnemonic == "sub" && Operands.size() == 6 &&
7479      static_cast<ARMOperand &>(*Operands[3]).isReg() &&
7480      static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::PC &&
7481      static_cast<ARMOperand &>(*Operands[4]).isReg() &&
7482      static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::LR &&
7483      static_cast<ARMOperand &>(*Operands[5]).isImm()) {
7484    Operands.front() = ARMOperand::CreateToken(Name, NameLoc);
7485    Operands.erase(Operands.begin() + 1);
7486  }
7487  return false;
7488}
7489
7490// Validate context-sensitive operand constraints.
7491
7492// return 'true' if register list contains non-low GPR registers,
7493// 'false' otherwise. If Reg is in the register list or is HiReg, set
7494// 'containsReg' to true.
7495static bool checkLowRegisterList(const MCInst &Inst, unsigned OpNo,
7496                                 unsigned Reg, unsigned HiReg,
7497                                 bool &containsReg) {
7498  containsReg = false;
7499  for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
7500    unsigned OpReg = Inst.getOperand(i).getReg();
7501    if (OpReg == Reg)
7502      containsReg = true;
7503    // Anything other than a low register isn't legal here.
7504    if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
7505      return true;
7506  }
7507  return false;
7508}
7509
7510// Check if the specified regisgter is in the register list of the inst,
7511// starting at the indicated operand number.
7512static bool listContainsReg(const MCInst &Inst, unsigned OpNo, unsigned Reg) {
7513  for (unsigned i = OpNo, e = Inst.getNumOperands(); i < e; ++i) {
7514    unsigned OpReg = Inst.getOperand(i).getReg();
7515    if (OpReg == Reg)
7516      return true;
7517  }
7518  return false;
7519}
7520
7521// Return true if instruction has the interesting property of being
7522// allowed in IT blocks, but not being predicable.
7523static bool instIsBreakpoint(const MCInst &Inst) {
7524    return Inst.getOpcode() == ARM::tBKPT ||
7525           Inst.getOpcode() == ARM::BKPT ||
7526           Inst.getOpcode() == ARM::tHLT ||
7527           Inst.getOpcode() == ARM::HLT;
7528}
7529
7530bool ARMAsmParser::validatetLDMRegList(const MCInst &Inst,
7531                                       const OperandVector &Operands,
7532                                       unsigned ListNo, bool IsARPop) {
7533  const ARMOperand &Op = static_cast<const ARMOperand &>(*Operands[ListNo]);
7534  bool HasWritebackToken = Op.isToken() && Op.getToken() == "!";
7535
7536  bool ListContainsSP = listContainsReg(Inst, ListNo, ARM::SP);
7537  bool ListContainsLR = listContainsReg(Inst, ListNo, ARM::LR);
7538  bool ListContainsPC = listContainsReg(Inst, ListNo, ARM::PC);
7539
7540  if (!IsARPop && ListContainsSP)
7541    return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
7542                 "SP may not be in the register list");
7543  else if (ListContainsPC && ListContainsLR)
7544    return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
7545                 "PC and LR may not be in the register list simultaneously");
7546  return false;
7547}
7548
7549bool ARMAsmParser::validatetSTMRegList(const MCInst &Inst,
7550                                       const OperandVector &Operands,
7551                                       unsigned ListNo) {
7552  const ARMOperand &Op = static_cast<const ARMOperand &>(*Operands[ListNo]);
7553  bool HasWritebackToken = Op.isToken() && Op.getToken() == "!";
7554
7555  bool ListContainsSP = listContainsReg(Inst, ListNo, ARM::SP);
7556  bool ListContainsPC = listContainsReg(Inst, ListNo, ARM::PC);
7557
7558  if (ListContainsSP && ListContainsPC)
7559    return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
7560                 "SP and PC may not be in the register list");
7561  else if (ListContainsSP)
7562    return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
7563                 "SP may not be in the register list");
7564  else if (ListContainsPC)
7565    return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
7566                 "PC may not be in the register list");
7567  return false;
7568}
7569
7570bool ARMAsmParser::validateLDRDSTRD(MCInst &Inst,
7571                                    const OperandVector &Operands,
7572                                    bool Load, bool ARMMode, bool Writeback) {
7573  unsigned RtIndex = Load || !Writeback ? 0 : 1;
7574  unsigned Rt = MRI->getEncodingValue(Inst.getOperand(RtIndex).getReg());
7575  unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(RtIndex + 1).getReg());
7576
7577  if (ARMMode) {
7578    // Rt can't be R14.
7579    if (Rt == 14)
7580      return Error(Operands[3]->getStartLoc(),
7581                  "Rt can't be R14");
7582
7583    // Rt must be even-numbered.
7584    if ((Rt & 1) == 1)
7585      return Error(Operands[3]->getStartLoc(),
7586                   "Rt must be even-numbered");
7587
7588    // Rt2 must be Rt + 1.
7589    if (Rt2 != Rt + 1) {
7590      if (Load)
7591        return Error(Operands[3]->getStartLoc(),
7592                     "destination operands must be sequential");
7593      else
7594        return Error(Operands[3]->getStartLoc(),
7595                     "source operands must be sequential");
7596    }
7597
7598    // FIXME: Diagnose m == 15
7599    // FIXME: Diagnose ldrd with m == t || m == t2.
7600  }
7601
7602  if (!ARMMode && Load) {
7603    if (Rt2 == Rt)
7604      return Error(Operands[3]->getStartLoc(),
7605                   "destination operands can't be identical");
7606  }
7607
7608  if (Writeback) {
7609    unsigned Rn = MRI->getEncodingValue(Inst.getOperand(3).getReg());
7610
7611    if (Rn == Rt || Rn == Rt2) {
7612      if (Load)
7613        return Error(Operands[3]->getStartLoc(),
7614                     "base register needs to be different from destination "
7615                     "registers");
7616      else
7617        return Error(Operands[3]->getStartLoc(),
7618                     "source register and base register can't be identical");
7619    }
7620
7621    // FIXME: Diagnose ldrd/strd with writeback and n == 15.
7622    // (Except the immediate form of ldrd?)
7623  }
7624
7625  return false;
7626}
7627
7628static int findFirstVectorPredOperandIdx(const MCInstrDesc &MCID) {
7629  for (unsigned i = 0; i < MCID.NumOperands; ++i) {
7630    if (ARM::isVpred(MCID.operands()[i].OperandType))
7631      return i;
7632  }
7633  return -1;
7634}
7635
7636static bool isVectorPredicable(const MCInstrDesc &MCID) {
7637  return findFirstVectorPredOperandIdx(MCID) != -1;
7638}
7639
7640// FIXME: We would really like to be able to tablegen'erate this.
7641bool ARMAsmParser::validateInstruction(MCInst &Inst,
7642                                       const OperandVector &Operands) {
7643  const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
7644  SMLoc Loc = Operands[0]->getStartLoc();
7645
7646  // Check the IT block state first.
7647  // NOTE: BKPT and HLT instructions have the interesting property of being
7648  // allowed in IT blocks, but not being predicable. They just always execute.
7649  if (inITBlock() && !instIsBreakpoint(Inst)) {
7650    // The instruction must be predicable.
7651    if (!MCID.isPredicable())
7652      return Error(Loc, "instructions in IT block must be predicable");
7653    ARMCC::CondCodes Cond = ARMCC::CondCodes(
7654        Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm());
7655    if (Cond != currentITCond()) {
7656      // Find the condition code Operand to get its SMLoc information.
7657      SMLoc CondLoc;
7658      for (unsigned I = 1; I < Operands.size(); ++I)
7659        if (static_cast<ARMOperand &>(*Operands[I]).isCondCode())
7660          CondLoc = Operands[I]->getStartLoc();
7661      return Error(CondLoc, "incorrect condition in IT block; got '" +
7662                                StringRef(ARMCondCodeToString(Cond)) +
7663                                "', but expected '" +
7664                                ARMCondCodeToString(currentITCond()) + "'");
7665    }
7666  // Check for non-'al' condition codes outside of the IT block.
7667  } else if (isThumbTwo() && MCID.isPredicable() &&
7668             Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
7669             ARMCC::AL && Inst.getOpcode() != ARM::tBcc &&
7670             Inst.getOpcode() != ARM::t2Bcc &&
7671             Inst.getOpcode() != ARM::t2BFic) {
7672    return Error(Loc, "predicated instructions must be in IT block");
7673  } else if (!isThumb() && !useImplicitITARM() && MCID.isPredicable() &&
7674             Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
7675                 ARMCC::AL) {
7676    return Warning(Loc, "predicated instructions should be in IT block");
7677  } else if (!MCID.isPredicable()) {
7678    // Check the instruction doesn't have a predicate operand anyway
7679    // that it's not allowed to use. Sometimes this happens in order
7680    // to keep instructions the same shape even though one cannot
7681    // legally be predicated, e.g. vmul.f16 vs vmul.f32.
7682    for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i) {
7683      if (MCID.operands()[i].isPredicate()) {
7684        if (Inst.getOperand(i).getImm() != ARMCC::AL)
7685          return Error(Loc, "instruction is not predicable");
7686        break;
7687      }
7688    }
7689  }
7690
7691  // PC-setting instructions in an IT block, but not the last instruction of
7692  // the block, are UNPREDICTABLE.
7693  if (inExplicitITBlock() && !lastInITBlock() && isITBlockTerminator(Inst)) {
7694    return Error(Loc, "instruction must be outside of IT block or the last instruction in an IT block");
7695  }
7696
7697  if (inVPTBlock() && !instIsBreakpoint(Inst)) {
7698    unsigned Bit = extractITMaskBit(VPTState.Mask, VPTState.CurPosition);
7699    if (!isVectorPredicable(MCID))
7700      return Error(Loc, "instruction in VPT block must be predicable");
7701    unsigned Pred = Inst.getOperand(findFirstVectorPredOperandIdx(MCID)).getImm();
7702    unsigned VPTPred = Bit ? ARMVCC::Else : ARMVCC::Then;
7703    if (Pred != VPTPred) {
7704      SMLoc PredLoc;
7705      for (unsigned I = 1; I < Operands.size(); ++I)
7706        if (static_cast<ARMOperand &>(*Operands[I]).isVPTPred())
7707          PredLoc = Operands[I]->getStartLoc();
7708      return Error(PredLoc, "incorrect predication in VPT block; got '" +
7709                   StringRef(ARMVPTPredToString(ARMVCC::VPTCodes(Pred))) +
7710                   "', but expected '" +
7711                   ARMVPTPredToString(ARMVCC::VPTCodes(VPTPred)) + "'");
7712    }
7713  }
7714  else if (isVectorPredicable(MCID) &&
7715           Inst.getOperand(findFirstVectorPredOperandIdx(MCID)).getImm() !=
7716           ARMVCC::None)
7717    return Error(Loc, "VPT predicated instructions must be in VPT block");
7718
7719  const unsigned Opcode = Inst.getOpcode();
7720  switch (Opcode) {
7721  case ARM::t2IT: {
7722    // Encoding is unpredictable if it ever results in a notional 'NV'
7723    // predicate. Since we don't parse 'NV' directly this means an 'AL'
7724    // predicate with an "else" mask bit.
7725    unsigned Cond = Inst.getOperand(0).getImm();
7726    unsigned Mask = Inst.getOperand(1).getImm();
7727
7728    // Conditions only allowing a 't' are those with no set bit except
7729    // the lowest-order one that indicates the end of the sequence. In
7730    // other words, powers of 2.
7731    if (Cond == ARMCC::AL && llvm::popcount(Mask) != 1)
7732      return Error(Loc, "unpredictable IT predicate sequence");
7733    break;
7734  }
7735  case ARM::LDRD:
7736    if (validateLDRDSTRD(Inst, Operands, /*Load*/true, /*ARMMode*/true,
7737                         /*Writeback*/false))
7738      return true;
7739    break;
7740  case ARM::LDRD_PRE:
7741  case ARM::LDRD_POST:
7742    if (validateLDRDSTRD(Inst, Operands, /*Load*/true, /*ARMMode*/true,
7743                         /*Writeback*/true))
7744      return true;
7745    break;
7746  case ARM::t2LDRDi8:
7747    if (validateLDRDSTRD(Inst, Operands, /*Load*/true, /*ARMMode*/false,
7748                         /*Writeback*/false))
7749      return true;
7750    break;
7751  case ARM::t2LDRD_PRE:
7752  case ARM::t2LDRD_POST:
7753    if (validateLDRDSTRD(Inst, Operands, /*Load*/true, /*ARMMode*/false,
7754                         /*Writeback*/true))
7755      return true;
7756    break;
7757  case ARM::t2BXJ: {
7758    const unsigned RmReg = Inst.getOperand(0).getReg();
7759    // Rm = SP is no longer unpredictable in v8-A
7760    if (RmReg == ARM::SP && !hasV8Ops())
7761      return Error(Operands[2]->getStartLoc(),
7762                   "r13 (SP) is an unpredictable operand to BXJ");
7763    return false;
7764  }
7765  case ARM::STRD:
7766    if (validateLDRDSTRD(Inst, Operands, /*Load*/false, /*ARMMode*/true,
7767                         /*Writeback*/false))
7768      return true;
7769    break;
7770  case ARM::STRD_PRE:
7771  case ARM::STRD_POST:
7772    if (validateLDRDSTRD(Inst, Operands, /*Load*/false, /*ARMMode*/true,
7773                         /*Writeback*/true))
7774      return true;
7775    break;
7776  case ARM::t2STRD_PRE:
7777  case ARM::t2STRD_POST:
7778    if (validateLDRDSTRD(Inst, Operands, /*Load*/false, /*ARMMode*/false,
7779                         /*Writeback*/true))
7780      return true;
7781    break;
7782  case ARM::STR_PRE_IMM:
7783  case ARM::STR_PRE_REG:
7784  case ARM::t2STR_PRE:
7785  case ARM::STR_POST_IMM:
7786  case ARM::STR_POST_REG:
7787  case ARM::t2STR_POST:
7788  case ARM::STRH_PRE:
7789  case ARM::t2STRH_PRE:
7790  case ARM::STRH_POST:
7791  case ARM::t2STRH_POST:
7792  case ARM::STRB_PRE_IMM:
7793  case ARM::STRB_PRE_REG:
7794  case ARM::t2STRB_PRE:
7795  case ARM::STRB_POST_IMM:
7796  case ARM::STRB_POST_REG:
7797  case ARM::t2STRB_POST: {
7798    // Rt must be different from Rn.
7799    const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
7800    const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg());
7801
7802    if (Rt == Rn)
7803      return Error(Operands[3]->getStartLoc(),
7804                   "source register and base register can't be identical");
7805    return false;
7806  }
7807  case ARM::t2LDR_PRE_imm:
7808  case ARM::t2LDR_POST_imm:
7809  case ARM::t2STR_PRE_imm:
7810  case ARM::t2STR_POST_imm: {
7811    // Rt must be different from Rn.
7812    const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
7813    const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(1).getReg());
7814
7815    if (Rt == Rn)
7816      return Error(Operands[3]->getStartLoc(),
7817                   "destination register and base register can't be identical");
7818    if (Inst.getOpcode() == ARM::t2LDR_POST_imm ||
7819        Inst.getOpcode() == ARM::t2STR_POST_imm) {
7820      int Imm = Inst.getOperand(2).getImm();
7821      if (Imm > 255 || Imm < -255)
7822        return Error(Operands[5]->getStartLoc(),
7823                     "operand must be in range [-255, 255]");
7824    }
7825    if (Inst.getOpcode() == ARM::t2STR_PRE_imm ||
7826        Inst.getOpcode() == ARM::t2STR_POST_imm) {
7827      if (Inst.getOperand(0).getReg() == ARM::PC) {
7828        return Error(Operands[3]->getStartLoc(),
7829                     "operand must be a register in range [r0, r14]");
7830      }
7831    }
7832    return false;
7833  }
7834  case ARM::LDR_PRE_IMM:
7835  case ARM::LDR_PRE_REG:
7836  case ARM::t2LDR_PRE:
7837  case ARM::LDR_POST_IMM:
7838  case ARM::LDR_POST_REG:
7839  case ARM::t2LDR_POST:
7840  case ARM::LDRH_PRE:
7841  case ARM::t2LDRH_PRE:
7842  case ARM::LDRH_POST:
7843  case ARM::t2LDRH_POST:
7844  case ARM::LDRSH_PRE:
7845  case ARM::t2LDRSH_PRE:
7846  case ARM::LDRSH_POST:
7847  case ARM::t2LDRSH_POST:
7848  case ARM::LDRB_PRE_IMM:
7849  case ARM::LDRB_PRE_REG:
7850  case ARM::t2LDRB_PRE:
7851  case ARM::LDRB_POST_IMM:
7852  case ARM::LDRB_POST_REG:
7853  case ARM::t2LDRB_POST:
7854  case ARM::LDRSB_PRE:
7855  case ARM::t2LDRSB_PRE:
7856  case ARM::LDRSB_POST:
7857  case ARM::t2LDRSB_POST: {
7858    // Rt must be different from Rn.
7859    const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
7860    const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg());
7861
7862    if (Rt == Rn)
7863      return Error(Operands[3]->getStartLoc(),
7864                   "destination register and base register can't be identical");
7865    return false;
7866  }
7867
7868  case ARM::MVE_VLDRBU8_rq:
7869  case ARM::MVE_VLDRBU16_rq:
7870  case ARM::MVE_VLDRBS16_rq:
7871  case ARM::MVE_VLDRBU32_rq:
7872  case ARM::MVE_VLDRBS32_rq:
7873  case ARM::MVE_VLDRHU16_rq:
7874  case ARM::MVE_VLDRHU16_rq_u:
7875  case ARM::MVE_VLDRHU32_rq:
7876  case ARM::MVE_VLDRHU32_rq_u:
7877  case ARM::MVE_VLDRHS32_rq:
7878  case ARM::MVE_VLDRHS32_rq_u:
7879  case ARM::MVE_VLDRWU32_rq:
7880  case ARM::MVE_VLDRWU32_rq_u:
7881  case ARM::MVE_VLDRDU64_rq:
7882  case ARM::MVE_VLDRDU64_rq_u:
7883  case ARM::MVE_VLDRWU32_qi:
7884  case ARM::MVE_VLDRWU32_qi_pre:
7885  case ARM::MVE_VLDRDU64_qi:
7886  case ARM::MVE_VLDRDU64_qi_pre: {
7887    // Qd must be different from Qm.
7888    unsigned QdIdx = 0, QmIdx = 2;
7889    bool QmIsPointer = false;
7890    switch (Opcode) {
7891    case ARM::MVE_VLDRWU32_qi:
7892    case ARM::MVE_VLDRDU64_qi:
7893      QmIdx = 1;
7894      QmIsPointer = true;
7895      break;
7896    case ARM::MVE_VLDRWU32_qi_pre:
7897    case ARM::MVE_VLDRDU64_qi_pre:
7898      QdIdx = 1;
7899      QmIsPointer = true;
7900      break;
7901    }
7902
7903    const unsigned Qd = MRI->getEncodingValue(Inst.getOperand(QdIdx).getReg());
7904    const unsigned Qm = MRI->getEncodingValue(Inst.getOperand(QmIdx).getReg());
7905
7906    if (Qd == Qm) {
7907      return Error(Operands[3]->getStartLoc(),
7908                   Twine("destination vector register and vector ") +
7909                   (QmIsPointer ? "pointer" : "offset") +
7910                   " register can't be identical");
7911    }
7912    return false;
7913  }
7914
7915  case ARM::SBFX:
7916  case ARM::t2SBFX:
7917  case ARM::UBFX:
7918  case ARM::t2UBFX: {
7919    // Width must be in range [1, 32-lsb].
7920    unsigned LSB = Inst.getOperand(2).getImm();
7921    unsigned Widthm1 = Inst.getOperand(3).getImm();
7922    if (Widthm1 >= 32 - LSB)
7923      return Error(Operands[5]->getStartLoc(),
7924                   "bitfield width must be in range [1,32-lsb]");
7925    return false;
7926  }
7927  // Notionally handles ARM::tLDMIA_UPD too.
7928  case ARM::tLDMIA: {
7929    // If we're parsing Thumb2, the .w variant is available and handles
7930    // most cases that are normally illegal for a Thumb1 LDM instruction.
7931    // We'll make the transformation in processInstruction() if necessary.
7932    //
7933    // Thumb LDM instructions are writeback iff the base register is not
7934    // in the register list.
7935    unsigned Rn = Inst.getOperand(0).getReg();
7936    bool HasWritebackToken =
7937        (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
7938         static_cast<ARMOperand &>(*Operands[3]).getToken() == "!");
7939    bool ListContainsBase;
7940    if (checkLowRegisterList(Inst, 3, Rn, 0, ListContainsBase) && !isThumbTwo())
7941      return Error(Operands[3 + HasWritebackToken]->getStartLoc(),
7942                   "registers must be in range r0-r7");
7943    // If we should have writeback, then there should be a '!' token.
7944    if (!ListContainsBase && !HasWritebackToken && !isThumbTwo())
7945      return Error(Operands[2]->getStartLoc(),
7946                   "writeback operator '!' expected");
7947    // If we should not have writeback, there must not be a '!'. This is
7948    // true even for the 32-bit wide encodings.
7949    if (ListContainsBase && HasWritebackToken)
7950      return Error(Operands[3]->getStartLoc(),
7951                   "writeback operator '!' not allowed when base register "
7952                   "in register list");
7953
7954    if (validatetLDMRegList(Inst, Operands, 3))
7955      return true;
7956    break;
7957  }
7958  case ARM::LDMIA_UPD:
7959  case ARM::LDMDB_UPD:
7960  case ARM::LDMIB_UPD:
7961  case ARM::LDMDA_UPD:
7962    // ARM variants loading and updating the same register are only officially
7963    // UNPREDICTABLE on v7 upwards. Goodness knows what they did before.
7964    if (!hasV7Ops())
7965      break;
7966    if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
7967      return Error(Operands.back()->getStartLoc(),
7968                   "writeback register not allowed in register list");
7969    break;
7970  case ARM::t2LDMIA:
7971  case ARM::t2LDMDB:
7972    if (validatetLDMRegList(Inst, Operands, 3))
7973      return true;
7974    break;
7975  case ARM::t2STMIA:
7976  case ARM::t2STMDB:
7977    if (validatetSTMRegList(Inst, Operands, 3))
7978      return true;
7979    break;
7980  case ARM::t2LDMIA_UPD:
7981  case ARM::t2LDMDB_UPD:
7982  case ARM::t2STMIA_UPD:
7983  case ARM::t2STMDB_UPD:
7984    if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
7985      return Error(Operands.back()->getStartLoc(),
7986                   "writeback register not allowed in register list");
7987
7988    if (Opcode == ARM::t2LDMIA_UPD || Opcode == ARM::t2LDMDB_UPD) {
7989      if (validatetLDMRegList(Inst, Operands, 3))
7990        return true;
7991    } else {
7992      if (validatetSTMRegList(Inst, Operands, 3))
7993        return true;
7994    }
7995    break;
7996
7997  case ARM::sysLDMIA_UPD:
7998  case ARM::sysLDMDA_UPD:
7999  case ARM::sysLDMDB_UPD:
8000  case ARM::sysLDMIB_UPD:
8001    if (!listContainsReg(Inst, 3, ARM::PC))
8002      return Error(Operands[4]->getStartLoc(),
8003                   "writeback register only allowed on system LDM "
8004                   "if PC in register-list");
8005    break;
8006  case ARM::sysSTMIA_UPD:
8007  case ARM::sysSTMDA_UPD:
8008  case ARM::sysSTMDB_UPD:
8009  case ARM::sysSTMIB_UPD:
8010    return Error(Operands[2]->getStartLoc(),
8011                 "system STM cannot have writeback register");
8012  case ARM::tMUL:
8013    // The second source operand must be the same register as the destination
8014    // operand.
8015    //
8016    // In this case, we must directly check the parsed operands because the
8017    // cvtThumbMultiply() function is written in such a way that it guarantees
8018    // this first statement is always true for the new Inst.  Essentially, the
8019    // destination is unconditionally copied into the second source operand
8020    // without checking to see if it matches what we actually parsed.
8021    if (Operands.size() == 6 && (((ARMOperand &)*Operands[3]).getReg() !=
8022                                 ((ARMOperand &)*Operands[5]).getReg()) &&
8023        (((ARMOperand &)*Operands[3]).getReg() !=
8024         ((ARMOperand &)*Operands[4]).getReg())) {
8025      return Error(Operands[3]->getStartLoc(),
8026                   "destination register must match source register");
8027    }
8028    break;
8029
8030  // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
8031  // so only issue a diagnostic for thumb1. The instructions will be
8032  // switched to the t2 encodings in processInstruction() if necessary.
8033  case ARM::tPOP: {
8034    bool ListContainsBase;
8035    if (checkLowRegisterList(Inst, 2, 0, ARM::PC, ListContainsBase) &&
8036        !isThumbTwo())
8037      return Error(Operands[2]->getStartLoc(),
8038                   "registers must be in range r0-r7 or pc");
8039    if (validatetLDMRegList(Inst, Operands, 2, !isMClass()))
8040      return true;
8041    break;
8042  }
8043  case ARM::tPUSH: {
8044    bool ListContainsBase;
8045    if (checkLowRegisterList(Inst, 2, 0, ARM::LR, ListContainsBase) &&
8046        !isThumbTwo())
8047      return Error(Operands[2]->getStartLoc(),
8048                   "registers must be in range r0-r7 or lr");
8049    if (validatetSTMRegList(Inst, Operands, 2))
8050      return true;
8051    break;
8052  }
8053  case ARM::tSTMIA_UPD: {
8054    bool ListContainsBase, InvalidLowList;
8055    InvalidLowList = checkLowRegisterList(Inst, 4, Inst.getOperand(0).getReg(),
8056                                          0, ListContainsBase);
8057    if (InvalidLowList && !isThumbTwo())
8058      return Error(Operands[4]->getStartLoc(),
8059                   "registers must be in range r0-r7");
8060
8061    // This would be converted to a 32-bit stm, but that's not valid if the
8062    // writeback register is in the list.
8063    if (InvalidLowList && ListContainsBase)
8064      return Error(Operands[4]->getStartLoc(),
8065                   "writeback operator '!' not allowed when base register "
8066                   "in register list");
8067
8068    if (validatetSTMRegList(Inst, Operands, 4))
8069      return true;
8070    break;
8071  }
8072  case ARM::tADDrSP:
8073    // If the non-SP source operand and the destination operand are not the
8074    // same, we need thumb2 (for the wide encoding), or we have an error.
8075    if (!isThumbTwo() &&
8076        Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
8077      return Error(Operands[4]->getStartLoc(),
8078                   "source register must be the same as destination");
8079    }
8080    break;
8081
8082  case ARM::t2ADDrr:
8083  case ARM::t2ADDrs:
8084  case ARM::t2SUBrr:
8085  case ARM::t2SUBrs:
8086    if (Inst.getOperand(0).getReg() == ARM::SP &&
8087        Inst.getOperand(1).getReg() != ARM::SP)
8088      return Error(Operands[4]->getStartLoc(),
8089                   "source register must be sp if destination is sp");
8090    break;
8091
8092  // Final range checking for Thumb unconditional branch instructions.
8093  case ARM::tB:
8094    if (!(static_cast<ARMOperand &>(*Operands[2])).isSignedOffset<11, 1>())
8095      return Error(Operands[2]->getStartLoc(), "branch target out of range");
8096    break;
8097  case ARM::t2B: {
8098    int op = (Operands[2]->isImm()) ? 2 : 3;
8099    ARMOperand &Operand = static_cast<ARMOperand &>(*Operands[op]);
8100    // Delay the checks of symbolic expressions until they are resolved.
8101    if (!isa<MCBinaryExpr>(Operand.getImm()) &&
8102        !Operand.isSignedOffset<24, 1>())
8103      return Error(Operands[op]->getStartLoc(), "branch target out of range");
8104    break;
8105  }
8106  // Final range checking for Thumb conditional branch instructions.
8107  case ARM::tBcc:
8108    if (!static_cast<ARMOperand &>(*Operands[2]).isSignedOffset<8, 1>())
8109      return Error(Operands[2]->getStartLoc(), "branch target out of range");
8110    break;
8111  case ARM::t2Bcc: {
8112    int Op = (Operands[2]->isImm()) ? 2 : 3;
8113    if (!static_cast<ARMOperand &>(*Operands[Op]).isSignedOffset<20, 1>())
8114      return Error(Operands[Op]->getStartLoc(), "branch target out of range");
8115    break;
8116  }
8117  case ARM::tCBZ:
8118  case ARM::tCBNZ: {
8119    if (!static_cast<ARMOperand &>(*Operands[2]).isUnsignedOffset<6, 1>())
8120      return Error(Operands[2]->getStartLoc(), "branch target out of range");
8121    break;
8122  }
8123  case ARM::MOVi16:
8124  case ARM::MOVTi16:
8125  case ARM::t2MOVi16:
8126  case ARM::t2MOVTi16:
8127    {
8128    // We want to avoid misleadingly allowing something like "mov r0, <symbol>"
8129    // especially when we turn it into a movw and the expression <symbol> does
8130    // not have a :lower16: or :upper16 as part of the expression.  We don't
8131    // want the behavior of silently truncating, which can be unexpected and
8132    // lead to bugs that are difficult to find since this is an easy mistake
8133    // to make.
8134    int i = (Operands[3]->isImm()) ? 3 : 4;
8135    ARMOperand &Op = static_cast<ARMOperand &>(*Operands[i]);
8136    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm());
8137    if (CE) break;
8138    const MCExpr *E = dyn_cast<MCExpr>(Op.getImm());
8139    if (!E) break;
8140    const ARMMCExpr *ARM16Expr = dyn_cast<ARMMCExpr>(E);
8141    if (!ARM16Expr || (ARM16Expr->getKind() != ARMMCExpr::VK_ARM_HI16 &&
8142                       ARM16Expr->getKind() != ARMMCExpr::VK_ARM_LO16))
8143      return Error(
8144          Op.getStartLoc(),
8145          "immediate expression for mov requires :lower16: or :upper16");
8146    break;
8147  }
8148  case ARM::HINT:
8149  case ARM::t2HINT: {
8150    unsigned Imm8 = Inst.getOperand(0).getImm();
8151    unsigned Pred = Inst.getOperand(1).getImm();
8152    // ESB is not predicable (pred must be AL). Without the RAS extension, this
8153    // behaves as any other unallocated hint.
8154    if (Imm8 == 0x10 && Pred != ARMCC::AL && hasRAS())
8155      return Error(Operands[1]->getStartLoc(), "instruction 'esb' is not "
8156                                               "predicable, but condition "
8157                                               "code specified");
8158    if (Imm8 == 0x14 && Pred != ARMCC::AL)
8159      return Error(Operands[1]->getStartLoc(), "instruction 'csdb' is not "
8160                                               "predicable, but condition "
8161                                               "code specified");
8162    break;
8163  }
8164  case ARM::t2BFi:
8165  case ARM::t2BFr:
8166  case ARM::t2BFLi:
8167  case ARM::t2BFLr: {
8168    if (!static_cast<ARMOperand &>(*Operands[2]).isUnsignedOffset<4, 1>() ||
8169        (Inst.getOperand(0).isImm() && Inst.getOperand(0).getImm() == 0))
8170      return Error(Operands[2]->getStartLoc(),
8171                   "branch location out of range or not a multiple of 2");
8172
8173    if (Opcode == ARM::t2BFi) {
8174      if (!static_cast<ARMOperand &>(*Operands[3]).isSignedOffset<16, 1>())
8175        return Error(Operands[3]->getStartLoc(),
8176                     "branch target out of range or not a multiple of 2");
8177    } else if (Opcode == ARM::t2BFLi) {
8178      if (!static_cast<ARMOperand &>(*Operands[3]).isSignedOffset<18, 1>())
8179        return Error(Operands[3]->getStartLoc(),
8180                     "branch target out of range or not a multiple of 2");
8181    }
8182    break;
8183  }
8184  case ARM::t2BFic: {
8185    if (!static_cast<ARMOperand &>(*Operands[1]).isUnsignedOffset<4, 1>() ||
8186        (Inst.getOperand(0).isImm() && Inst.getOperand(0).getImm() == 0))
8187      return Error(Operands[1]->getStartLoc(),
8188                   "branch location out of range or not a multiple of 2");
8189
8190    if (!static_cast<ARMOperand &>(*Operands[2]).isSignedOffset<16, 1>())
8191      return Error(Operands[2]->getStartLoc(),
8192                   "branch target out of range or not a multiple of 2");
8193
8194    assert(Inst.getOperand(0).isImm() == Inst.getOperand(2).isImm() &&
8195           "branch location and else branch target should either both be "
8196           "immediates or both labels");
8197
8198    if (Inst.getOperand(0).isImm() && Inst.getOperand(2).isImm()) {
8199      int Diff = Inst.getOperand(2).getImm() - Inst.getOperand(0).getImm();
8200      if (Diff != 4 && Diff != 2)
8201        return Error(
8202            Operands[3]->getStartLoc(),
8203            "else branch target must be 2 or 4 greater than the branch location");
8204    }
8205    break;
8206  }
8207  case ARM::t2CLRM: {
8208    for (unsigned i = 2; i < Inst.getNumOperands(); i++) {
8209      if (Inst.getOperand(i).isReg() &&
8210          !ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID].contains(
8211              Inst.getOperand(i).getReg())) {
8212        return Error(Operands[2]->getStartLoc(),
8213                     "invalid register in register list. Valid registers are "
8214                     "r0-r12, lr/r14 and APSR.");
8215      }
8216    }
8217    break;
8218  }
8219  case ARM::DSB:
8220  case ARM::t2DSB: {
8221
8222    if (Inst.getNumOperands() < 2)
8223      break;
8224
8225    unsigned Option = Inst.getOperand(0).getImm();
8226    unsigned Pred = Inst.getOperand(1).getImm();
8227
8228    // SSBB and PSSBB (DSB #0|#4) are not predicable (pred must be AL).
8229    if (Option == 0 && Pred != ARMCC::AL)
8230      return Error(Operands[1]->getStartLoc(),
8231                   "instruction 'ssbb' is not predicable, but condition code "
8232                   "specified");
8233    if (Option == 4 && Pred != ARMCC::AL)
8234      return Error(Operands[1]->getStartLoc(),
8235                   "instruction 'pssbb' is not predicable, but condition code "
8236                   "specified");
8237    break;
8238  }
8239  case ARM::VMOVRRS: {
8240    // Source registers must be sequential.
8241    const unsigned Sm = MRI->getEncodingValue(Inst.getOperand(2).getReg());
8242    const unsigned Sm1 = MRI->getEncodingValue(Inst.getOperand(3).getReg());
8243    if (Sm1 != Sm + 1)
8244      return Error(Operands[5]->getStartLoc(),
8245                   "source operands must be sequential");
8246    break;
8247  }
8248  case ARM::VMOVSRR: {
8249    // Destination registers must be sequential.
8250    const unsigned Sm = MRI->getEncodingValue(Inst.getOperand(0).getReg());
8251    const unsigned Sm1 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
8252    if (Sm1 != Sm + 1)
8253      return Error(Operands[3]->getStartLoc(),
8254                   "destination operands must be sequential");
8255    break;
8256  }
8257  case ARM::VLDMDIA:
8258  case ARM::VSTMDIA: {
8259    ARMOperand &Op = static_cast<ARMOperand&>(*Operands[3]);
8260    auto &RegList = Op.getRegList();
8261    if (RegList.size() < 1 || RegList.size() > 16)
8262      return Error(Operands[3]->getStartLoc(),
8263                   "list of registers must be at least 1 and at most 16");
8264    break;
8265  }
8266  case ARM::MVE_VQDMULLs32bh:
8267  case ARM::MVE_VQDMULLs32th:
8268  case ARM::MVE_VCMULf32:
8269  case ARM::MVE_VMULLBs32:
8270  case ARM::MVE_VMULLTs32:
8271  case ARM::MVE_VMULLBu32:
8272  case ARM::MVE_VMULLTu32: {
8273    if (Operands[3]->getReg() == Operands[4]->getReg()) {
8274      return Error (Operands[3]->getStartLoc(),
8275                    "Qd register and Qn register can't be identical");
8276    }
8277    if (Operands[3]->getReg() == Operands[5]->getReg()) {
8278      return Error (Operands[3]->getStartLoc(),
8279                    "Qd register and Qm register can't be identical");
8280    }
8281    break;
8282  }
8283  case ARM::MVE_VREV64_8:
8284  case ARM::MVE_VREV64_16:
8285  case ARM::MVE_VREV64_32:
8286  case ARM::MVE_VQDMULL_qr_s32bh:
8287  case ARM::MVE_VQDMULL_qr_s32th: {
8288    if (Operands[3]->getReg() == Operands[4]->getReg()) {
8289      return Error (Operands[3]->getStartLoc(),
8290                    "Qd register and Qn register can't be identical");
8291    }
8292    break;
8293  }
8294  case ARM::MVE_VCADDi32:
8295  case ARM::MVE_VCADDf32:
8296  case ARM::MVE_VHCADDs32: {
8297    if (Operands[3]->getReg() == Operands[5]->getReg()) {
8298      return Error (Operands[3]->getStartLoc(),
8299                    "Qd register and Qm register can't be identical");
8300    }
8301    break;
8302  }
8303  case ARM::MVE_VMOV_rr_q: {
8304    if (Operands[4]->getReg() != Operands[6]->getReg())
8305      return Error (Operands[4]->getStartLoc(), "Q-registers must be the same");
8306    if (static_cast<ARMOperand &>(*Operands[5]).getVectorIndex() !=
8307        static_cast<ARMOperand &>(*Operands[7]).getVectorIndex() + 2)
8308      return Error (Operands[5]->getStartLoc(), "Q-register indexes must be 2 and 0 or 3 and 1");
8309    break;
8310  }
8311  case ARM::MVE_VMOV_q_rr: {
8312    if (Operands[2]->getReg() != Operands[4]->getReg())
8313      return Error (Operands[2]->getStartLoc(), "Q-registers must be the same");
8314    if (static_cast<ARMOperand &>(*Operands[3]).getVectorIndex() !=
8315        static_cast<ARMOperand &>(*Operands[5]).getVectorIndex() + 2)
8316      return Error (Operands[3]->getStartLoc(), "Q-register indexes must be 2 and 0 or 3 and 1");
8317    break;
8318  }
8319  case ARM::UMAAL:
8320  case ARM::UMLAL:
8321  case ARM::UMULL:
8322  case ARM::t2UMAAL:
8323  case ARM::t2UMLAL:
8324  case ARM::t2UMULL:
8325  case ARM::SMLAL:
8326  case ARM::SMLALBB:
8327  case ARM::SMLALBT:
8328  case ARM::SMLALD:
8329  case ARM::SMLALDX:
8330  case ARM::SMLALTB:
8331  case ARM::SMLALTT:
8332  case ARM::SMLSLD:
8333  case ARM::SMLSLDX:
8334  case ARM::SMULL:
8335  case ARM::t2SMLAL:
8336  case ARM::t2SMLALBB:
8337  case ARM::t2SMLALBT:
8338  case ARM::t2SMLALD:
8339  case ARM::t2SMLALDX:
8340  case ARM::t2SMLALTB:
8341  case ARM::t2SMLALTT:
8342  case ARM::t2SMLSLD:
8343  case ARM::t2SMLSLDX:
8344  case ARM::t2SMULL: {
8345    unsigned RdHi = Inst.getOperand(0).getReg();
8346    unsigned RdLo = Inst.getOperand(1).getReg();
8347    if(RdHi == RdLo) {
8348      return Error(Loc,
8349                   "unpredictable instruction, RdHi and RdLo must be different");
8350    }
8351    break;
8352  }
8353
8354  case ARM::CDE_CX1:
8355  case ARM::CDE_CX1A:
8356  case ARM::CDE_CX1D:
8357  case ARM::CDE_CX1DA:
8358  case ARM::CDE_CX2:
8359  case ARM::CDE_CX2A:
8360  case ARM::CDE_CX2D:
8361  case ARM::CDE_CX2DA:
8362  case ARM::CDE_CX3:
8363  case ARM::CDE_CX3A:
8364  case ARM::CDE_CX3D:
8365  case ARM::CDE_CX3DA:
8366  case ARM::CDE_VCX1_vec:
8367  case ARM::CDE_VCX1_fpsp:
8368  case ARM::CDE_VCX1_fpdp:
8369  case ARM::CDE_VCX1A_vec:
8370  case ARM::CDE_VCX1A_fpsp:
8371  case ARM::CDE_VCX1A_fpdp:
8372  case ARM::CDE_VCX2_vec:
8373  case ARM::CDE_VCX2_fpsp:
8374  case ARM::CDE_VCX2_fpdp:
8375  case ARM::CDE_VCX2A_vec:
8376  case ARM::CDE_VCX2A_fpsp:
8377  case ARM::CDE_VCX2A_fpdp:
8378  case ARM::CDE_VCX3_vec:
8379  case ARM::CDE_VCX3_fpsp:
8380  case ARM::CDE_VCX3_fpdp:
8381  case ARM::CDE_VCX3A_vec:
8382  case ARM::CDE_VCX3A_fpsp:
8383  case ARM::CDE_VCX3A_fpdp: {
8384    assert(Inst.getOperand(1).isImm() &&
8385           "CDE operand 1 must be a coprocessor ID");
8386    int64_t Coproc = Inst.getOperand(1).getImm();
8387    if (Coproc < 8 && !ARM::isCDECoproc(Coproc, *STI))
8388      return Error(Operands[1]->getStartLoc(),
8389                   "coprocessor must be configured as CDE");
8390    else if (Coproc >= 8)
8391      return Error(Operands[1]->getStartLoc(),
8392                   "coprocessor must be in the range [p0, p7]");
8393    break;
8394  }
8395
8396  case ARM::t2CDP:
8397  case ARM::t2CDP2:
8398  case ARM::t2LDC2L_OFFSET:
8399  case ARM::t2LDC2L_OPTION:
8400  case ARM::t2LDC2L_POST:
8401  case ARM::t2LDC2L_PRE:
8402  case ARM::t2LDC2_OFFSET:
8403  case ARM::t2LDC2_OPTION:
8404  case ARM::t2LDC2_POST:
8405  case ARM::t2LDC2_PRE:
8406  case ARM::t2LDCL_OFFSET:
8407  case ARM::t2LDCL_OPTION:
8408  case ARM::t2LDCL_POST:
8409  case ARM::t2LDCL_PRE:
8410  case ARM::t2LDC_OFFSET:
8411  case ARM::t2LDC_OPTION:
8412  case ARM::t2LDC_POST:
8413  case ARM::t2LDC_PRE:
8414  case ARM::t2MCR:
8415  case ARM::t2MCR2:
8416  case ARM::t2MCRR:
8417  case ARM::t2MCRR2:
8418  case ARM::t2MRC:
8419  case ARM::t2MRC2:
8420  case ARM::t2MRRC:
8421  case ARM::t2MRRC2:
8422  case ARM::t2STC2L_OFFSET:
8423  case ARM::t2STC2L_OPTION:
8424  case ARM::t2STC2L_POST:
8425  case ARM::t2STC2L_PRE:
8426  case ARM::t2STC2_OFFSET:
8427  case ARM::t2STC2_OPTION:
8428  case ARM::t2STC2_POST:
8429  case ARM::t2STC2_PRE:
8430  case ARM::t2STCL_OFFSET:
8431  case ARM::t2STCL_OPTION:
8432  case ARM::t2STCL_POST:
8433  case ARM::t2STCL_PRE:
8434  case ARM::t2STC_OFFSET:
8435  case ARM::t2STC_OPTION:
8436  case ARM::t2STC_POST:
8437  case ARM::t2STC_PRE: {
8438    unsigned Opcode = Inst.getOpcode();
8439    // Inst.getOperand indexes operands in the (oops ...) and (iops ...) dags,
8440    // CopInd is the index of the coprocessor operand.
8441    size_t CopInd = 0;
8442    if (Opcode == ARM::t2MRRC || Opcode == ARM::t2MRRC2)
8443      CopInd = 2;
8444    else if (Opcode == ARM::t2MRC || Opcode == ARM::t2MRC2)
8445      CopInd = 1;
8446    assert(Inst.getOperand(CopInd).isImm() &&
8447           "Operand must be a coprocessor ID");
8448    int64_t Coproc = Inst.getOperand(CopInd).getImm();
8449    // Operands[2] is the coprocessor operand at syntactic level
8450    if (ARM::isCDECoproc(Coproc, *STI))
8451      return Error(Operands[2]->getStartLoc(),
8452                   "coprocessor must be configured as GCP");
8453    break;
8454  }
8455  }
8456
8457  return false;
8458}
8459
8460static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
8461  switch(Opc) {
8462  default: llvm_unreachable("unexpected opcode!");
8463  // VST1LN
8464  case ARM::VST1LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST1LNd8_UPD;
8465  case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
8466  case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
8467  case ARM::VST1LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST1LNd8_UPD;
8468  case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
8469  case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
8470  case ARM::VST1LNdAsm_8:  Spacing = 1; return ARM::VST1LNd8;
8471  case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16;
8472  case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32;
8473
8474  // VST2LN
8475  case ARM::VST2LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST2LNd8_UPD;
8476  case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
8477  case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
8478  case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
8479  case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
8480
8481  case ARM::VST2LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST2LNd8_UPD;
8482  case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
8483  case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
8484  case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
8485  case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
8486
8487  case ARM::VST2LNdAsm_8:  Spacing = 1; return ARM::VST2LNd8;
8488  case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16;
8489  case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32;
8490  case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16;
8491  case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32;
8492
8493  // VST3LN
8494  case ARM::VST3LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST3LNd8_UPD;
8495  case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
8496  case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
8497  case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD;
8498  case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
8499  case ARM::VST3LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST3LNd8_UPD;
8500  case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
8501  case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
8502  case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD;
8503  case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
8504  case ARM::VST3LNdAsm_8:  Spacing = 1; return ARM::VST3LNd8;
8505  case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16;
8506  case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32;
8507  case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16;
8508  case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32;
8509
8510  // VST3
8511  case ARM::VST3dWB_fixed_Asm_8:  Spacing = 1; return ARM::VST3d8_UPD;
8512  case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
8513  case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
8514  case ARM::VST3qWB_fixed_Asm_8:  Spacing = 2; return ARM::VST3q8_UPD;
8515  case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
8516  case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
8517  case ARM::VST3dWB_register_Asm_8:  Spacing = 1; return ARM::VST3d8_UPD;
8518  case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
8519  case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
8520  case ARM::VST3qWB_register_Asm_8:  Spacing = 2; return ARM::VST3q8_UPD;
8521  case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
8522  case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
8523  case ARM::VST3dAsm_8:  Spacing = 1; return ARM::VST3d8;
8524  case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16;
8525  case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32;
8526  case ARM::VST3qAsm_8:  Spacing = 2; return ARM::VST3q8;
8527  case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16;
8528  case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32;
8529
8530  // VST4LN
8531  case ARM::VST4LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST4LNd8_UPD;
8532  case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
8533  case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
8534  case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD;
8535  case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
8536  case ARM::VST4LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST4LNd8_UPD;
8537  case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
8538  case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
8539  case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD;
8540  case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
8541  case ARM::VST4LNdAsm_8:  Spacing = 1; return ARM::VST4LNd8;
8542  case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16;
8543  case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32;
8544  case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16;
8545  case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32;
8546
8547  // VST4
8548  case ARM::VST4dWB_fixed_Asm_8:  Spacing = 1; return ARM::VST4d8_UPD;
8549  case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
8550  case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
8551  case ARM::VST4qWB_fixed_Asm_8:  Spacing = 2; return ARM::VST4q8_UPD;
8552  case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
8553  case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
8554  case ARM::VST4dWB_register_Asm_8:  Spacing = 1; return ARM::VST4d8_UPD;
8555  case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
8556  case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
8557  case ARM::VST4qWB_register_Asm_8:  Spacing = 2; return ARM::VST4q8_UPD;
8558  case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
8559  case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
8560  case ARM::VST4dAsm_8:  Spacing = 1; return ARM::VST4d8;
8561  case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16;
8562  case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32;
8563  case ARM::VST4qAsm_8:  Spacing = 2; return ARM::VST4q8;
8564  case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16;
8565  case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32;
8566  }
8567}
8568
8569static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
8570  switch(Opc) {
8571  default: llvm_unreachable("unexpected opcode!");
8572  // VLD1LN
8573  case ARM::VLD1LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD1LNd8_UPD;
8574  case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
8575  case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
8576  case ARM::VLD1LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD1LNd8_UPD;
8577  case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
8578  case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
8579  case ARM::VLD1LNdAsm_8:  Spacing = 1; return ARM::VLD1LNd8;
8580  case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16;
8581  case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32;
8582
8583  // VLD2LN
8584  case ARM::VLD2LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD2LNd8_UPD;
8585  case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
8586  case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
8587  case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD;
8588  case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
8589  case ARM::VLD2LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD2LNd8_UPD;
8590  case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
8591  case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
8592  case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD;
8593  case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
8594  case ARM::VLD2LNdAsm_8:  Spacing = 1; return ARM::VLD2LNd8;
8595  case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16;
8596  case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32;
8597  case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16;
8598  case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32;
8599
8600  // VLD3DUP
8601  case ARM::VLD3DUPdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3DUPd8_UPD;
8602  case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
8603  case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
8604  case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD;
8605  case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
8606  case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
8607  case ARM::VLD3DUPdWB_register_Asm_8:  Spacing = 1; return ARM::VLD3DUPd8_UPD;
8608  case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
8609  case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
8610  case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD;
8611  case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
8612  case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
8613  case ARM::VLD3DUPdAsm_8:  Spacing = 1; return ARM::VLD3DUPd8;
8614  case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16;
8615  case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32;
8616  case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8;
8617  case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16;
8618  case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32;
8619
8620  // VLD3LN
8621  case ARM::VLD3LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3LNd8_UPD;
8622  case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
8623  case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
8624  case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD;
8625  case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
8626  case ARM::VLD3LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD3LNd8_UPD;
8627  case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
8628  case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
8629  case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD;
8630  case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
8631  case ARM::VLD3LNdAsm_8:  Spacing = 1; return ARM::VLD3LNd8;
8632  case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16;
8633  case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32;
8634  case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16;
8635  case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32;
8636
8637  // VLD3
8638  case ARM::VLD3dWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3d8_UPD;
8639  case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
8640  case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
8641  case ARM::VLD3qWB_fixed_Asm_8:  Spacing = 2; return ARM::VLD3q8_UPD;
8642  case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
8643  case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
8644  case ARM::VLD3dWB_register_Asm_8:  Spacing = 1; return ARM::VLD3d8_UPD;
8645  case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
8646  case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
8647  case ARM::VLD3qWB_register_Asm_8:  Spacing = 2; return ARM::VLD3q8_UPD;
8648  case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
8649  case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
8650  case ARM::VLD3dAsm_8:  Spacing = 1; return ARM::VLD3d8;
8651  case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16;
8652  case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32;
8653  case ARM::VLD3qAsm_8:  Spacing = 2; return ARM::VLD3q8;
8654  case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16;
8655  case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32;
8656
8657  // VLD4LN
8658  case ARM::VLD4LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4LNd8_UPD;
8659  case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
8660  case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
8661  case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
8662  case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
8663  case ARM::VLD4LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD4LNd8_UPD;
8664  case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
8665  case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
8666  case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
8667  case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
8668  case ARM::VLD4LNdAsm_8:  Spacing = 1; return ARM::VLD4LNd8;
8669  case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16;
8670  case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32;
8671  case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16;
8672  case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32;
8673
8674  // VLD4DUP
8675  case ARM::VLD4DUPdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4DUPd8_UPD;
8676  case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
8677  case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
8678  case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD;
8679  case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD;
8680  case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
8681  case ARM::VLD4DUPdWB_register_Asm_8:  Spacing = 1; return ARM::VLD4DUPd8_UPD;
8682  case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
8683  case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
8684  case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD;
8685  case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD;
8686  case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
8687  case ARM::VLD4DUPdAsm_8:  Spacing = 1; return ARM::VLD4DUPd8;
8688  case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16;
8689  case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32;
8690  case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8;
8691  case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16;
8692  case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32;
8693
8694  // VLD4
8695  case ARM::VLD4dWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4d8_UPD;
8696  case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
8697  case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
8698  case ARM::VLD4qWB_fixed_Asm_8:  Spacing = 2; return ARM::VLD4q8_UPD;
8699  case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
8700  case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
8701  case ARM::VLD4dWB_register_Asm_8:  Spacing = 1; return ARM::VLD4d8_UPD;
8702  case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
8703  case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
8704  case ARM::VLD4qWB_register_Asm_8:  Spacing = 2; return ARM::VLD4q8_UPD;
8705  case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
8706  case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
8707  case ARM::VLD4dAsm_8:  Spacing = 1; return ARM::VLD4d8;
8708  case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16;
8709  case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32;
8710  case ARM::VLD4qAsm_8:  Spacing = 2; return ARM::VLD4q8;
8711  case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16;
8712  case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32;
8713  }
8714}
8715
8716bool ARMAsmParser::processInstruction(MCInst &Inst,
8717                                      const OperandVector &Operands,
8718                                      MCStreamer &Out) {
8719  // Check if we have the wide qualifier, because if it's present we
8720  // must avoid selecting a 16-bit thumb instruction.
8721  bool HasWideQualifier = false;
8722  for (auto &Op : Operands) {
8723    ARMOperand &ARMOp = static_cast<ARMOperand&>(*Op);
8724    if (ARMOp.isToken() && ARMOp.getToken() == ".w") {
8725      HasWideQualifier = true;
8726      break;
8727    }
8728  }
8729
8730  switch (Inst.getOpcode()) {
8731  // Alias for alternate form of 'ldr{,b}t Rt, [Rn], #imm' instruction.
8732  case ARM::LDRT_POST:
8733  case ARM::LDRBT_POST: {
8734    const unsigned Opcode =
8735      (Inst.getOpcode() == ARM::LDRT_POST) ? ARM::LDRT_POST_IMM
8736                                           : ARM::LDRBT_POST_IMM;
8737    MCInst TmpInst;
8738    TmpInst.setOpcode(Opcode);
8739    TmpInst.addOperand(Inst.getOperand(0));
8740    TmpInst.addOperand(Inst.getOperand(1));
8741    TmpInst.addOperand(Inst.getOperand(1));
8742    TmpInst.addOperand(MCOperand::createReg(0));
8743    TmpInst.addOperand(MCOperand::createImm(0));
8744    TmpInst.addOperand(Inst.getOperand(2));
8745    TmpInst.addOperand(Inst.getOperand(3));
8746    Inst = TmpInst;
8747    return true;
8748  }
8749  // Alias for 'ldr{sb,h,sh}t Rt, [Rn] {, #imm}' for ommitted immediate.
8750  case ARM::LDRSBTii:
8751  case ARM::LDRHTii:
8752  case ARM::LDRSHTii: {
8753    MCInst TmpInst;
8754
8755    if (Inst.getOpcode() == ARM::LDRSBTii)
8756      TmpInst.setOpcode(ARM::LDRSBTi);
8757    else if (Inst.getOpcode() == ARM::LDRHTii)
8758      TmpInst.setOpcode(ARM::LDRHTi);
8759    else if (Inst.getOpcode() == ARM::LDRSHTii)
8760      TmpInst.setOpcode(ARM::LDRSHTi);
8761    TmpInst.addOperand(Inst.getOperand(0));
8762    TmpInst.addOperand(Inst.getOperand(1));
8763    TmpInst.addOperand(Inst.getOperand(1));
8764    TmpInst.addOperand(MCOperand::createImm(256));
8765    TmpInst.addOperand(Inst.getOperand(2));
8766    Inst = TmpInst;
8767    return true;
8768  }
8769  // Alias for alternate form of 'str{,b}t Rt, [Rn], #imm' instruction.
8770  case ARM::STRT_POST:
8771  case ARM::STRBT_POST: {
8772    const unsigned Opcode =
8773      (Inst.getOpcode() == ARM::STRT_POST) ? ARM::STRT_POST_IMM
8774                                           : ARM::STRBT_POST_IMM;
8775    MCInst TmpInst;
8776    TmpInst.setOpcode(Opcode);
8777    TmpInst.addOperand(Inst.getOperand(1));
8778    TmpInst.addOperand(Inst.getOperand(0));
8779    TmpInst.addOperand(Inst.getOperand(1));
8780    TmpInst.addOperand(MCOperand::createReg(0));
8781    TmpInst.addOperand(MCOperand::createImm(0));
8782    TmpInst.addOperand(Inst.getOperand(2));
8783    TmpInst.addOperand(Inst.getOperand(3));
8784    Inst = TmpInst;
8785    return true;
8786  }
8787  // Alias for alternate form of 'ADR Rd, #imm' instruction.
8788  case ARM::ADDri: {
8789    if (Inst.getOperand(1).getReg() != ARM::PC ||
8790        Inst.getOperand(5).getReg() != 0 ||
8791        !(Inst.getOperand(2).isExpr() || Inst.getOperand(2).isImm()))
8792      return false;
8793    MCInst TmpInst;
8794    TmpInst.setOpcode(ARM::ADR);
8795    TmpInst.addOperand(Inst.getOperand(0));
8796    if (Inst.getOperand(2).isImm()) {
8797      // Immediate (mod_imm) will be in its encoded form, we must unencode it
8798      // before passing it to the ADR instruction.
8799      unsigned Enc = Inst.getOperand(2).getImm();
8800      TmpInst.addOperand(MCOperand::createImm(
8801        ARM_AM::rotr32(Enc & 0xFF, (Enc & 0xF00) >> 7)));
8802    } else {
8803      // Turn PC-relative expression into absolute expression.
8804      // Reading PC provides the start of the current instruction + 8 and
8805      // the transform to adr is biased by that.
8806      MCSymbol *Dot = getContext().createTempSymbol();
8807      Out.emitLabel(Dot);
8808      const MCExpr *OpExpr = Inst.getOperand(2).getExpr();
8809      const MCExpr *InstPC = MCSymbolRefExpr::create(Dot,
8810                                                     MCSymbolRefExpr::VK_None,
8811                                                     getContext());
8812      const MCExpr *Const8 = MCConstantExpr::create(8, getContext());
8813      const MCExpr *ReadPC = MCBinaryExpr::createAdd(InstPC, Const8,
8814                                                     getContext());
8815      const MCExpr *FixupAddr = MCBinaryExpr::createAdd(ReadPC, OpExpr,
8816                                                        getContext());
8817      TmpInst.addOperand(MCOperand::createExpr(FixupAddr));
8818    }
8819    TmpInst.addOperand(Inst.getOperand(3));
8820    TmpInst.addOperand(Inst.getOperand(4));
8821    Inst = TmpInst;
8822    return true;
8823  }
8824  // Aliases for imm syntax of LDR instructions.
8825  case ARM::t2LDR_PRE_imm:
8826  case ARM::t2LDR_POST_imm: {
8827    MCInst TmpInst;
8828    TmpInst.setOpcode(Inst.getOpcode() == ARM::t2LDR_PRE_imm ? ARM::t2LDR_PRE
8829                                                             : ARM::t2LDR_POST);
8830    TmpInst.addOperand(Inst.getOperand(0)); // Rt
8831    TmpInst.addOperand(Inst.getOperand(4)); // Rt_wb
8832    TmpInst.addOperand(Inst.getOperand(1)); // Rn
8833    TmpInst.addOperand(Inst.getOperand(2)); // imm
8834    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
8835    Inst = TmpInst;
8836    return true;
8837  }
8838  // Aliases for imm syntax of STR instructions.
8839  case ARM::t2STR_PRE_imm:
8840  case ARM::t2STR_POST_imm: {
8841    MCInst TmpInst;
8842    TmpInst.setOpcode(Inst.getOpcode() == ARM::t2STR_PRE_imm ? ARM::t2STR_PRE
8843                                                             : ARM::t2STR_POST);
8844    TmpInst.addOperand(Inst.getOperand(4)); // Rt_wb
8845    TmpInst.addOperand(Inst.getOperand(0)); // Rt
8846    TmpInst.addOperand(Inst.getOperand(1)); // Rn
8847    TmpInst.addOperand(Inst.getOperand(2)); // imm
8848    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
8849    Inst = TmpInst;
8850    return true;
8851  }
8852  // Aliases for alternate PC+imm syntax of LDR instructions.
8853  case ARM::t2LDRpcrel:
8854    // Select the narrow version if the immediate will fit.
8855    if (Inst.getOperand(1).getImm() > 0 &&
8856        Inst.getOperand(1).getImm() <= 0xff &&
8857        !HasWideQualifier)
8858      Inst.setOpcode(ARM::tLDRpci);
8859    else
8860      Inst.setOpcode(ARM::t2LDRpci);
8861    return true;
8862  case ARM::t2LDRBpcrel:
8863    Inst.setOpcode(ARM::t2LDRBpci);
8864    return true;
8865  case ARM::t2LDRHpcrel:
8866    Inst.setOpcode(ARM::t2LDRHpci);
8867    return true;
8868  case ARM::t2LDRSBpcrel:
8869    Inst.setOpcode(ARM::t2LDRSBpci);
8870    return true;
8871  case ARM::t2LDRSHpcrel:
8872    Inst.setOpcode(ARM::t2LDRSHpci);
8873    return true;
8874  case ARM::LDRConstPool:
8875  case ARM::tLDRConstPool:
8876  case ARM::t2LDRConstPool: {
8877    // Pseudo instruction ldr rt, =immediate is converted to a
8878    // MOV rt, immediate if immediate is known and representable
8879    // otherwise we create a constant pool entry that we load from.
8880    MCInst TmpInst;
8881    if (Inst.getOpcode() == ARM::LDRConstPool)
8882      TmpInst.setOpcode(ARM::LDRi12);
8883    else if (Inst.getOpcode() == ARM::tLDRConstPool)
8884      TmpInst.setOpcode(ARM::tLDRpci);
8885    else if (Inst.getOpcode() == ARM::t2LDRConstPool)
8886      TmpInst.setOpcode(ARM::t2LDRpci);
8887    const ARMOperand &PoolOperand =
8888      (HasWideQualifier ?
8889       static_cast<ARMOperand &>(*Operands[4]) :
8890       static_cast<ARMOperand &>(*Operands[3]));
8891    const MCExpr *SubExprVal = PoolOperand.getConstantPoolImm();
8892    // If SubExprVal is a constant we may be able to use a MOV
8893    if (isa<MCConstantExpr>(SubExprVal) &&
8894        Inst.getOperand(0).getReg() != ARM::PC &&
8895        Inst.getOperand(0).getReg() != ARM::SP) {
8896      int64_t Value =
8897        (int64_t) (cast<MCConstantExpr>(SubExprVal))->getValue();
8898      bool UseMov  = true;
8899      bool MovHasS = true;
8900      if (Inst.getOpcode() == ARM::LDRConstPool) {
8901        // ARM Constant
8902        if (ARM_AM::getSOImmVal(Value) != -1) {
8903          Value = ARM_AM::getSOImmVal(Value);
8904          TmpInst.setOpcode(ARM::MOVi);
8905        }
8906        else if (ARM_AM::getSOImmVal(~Value) != -1) {
8907          Value = ARM_AM::getSOImmVal(~Value);
8908          TmpInst.setOpcode(ARM::MVNi);
8909        }
8910        else if (hasV6T2Ops() &&
8911                 Value >=0 && Value < 65536) {
8912          TmpInst.setOpcode(ARM::MOVi16);
8913          MovHasS = false;
8914        }
8915        else
8916          UseMov = false;
8917      }
8918      else {
8919        // Thumb/Thumb2 Constant
8920        if (hasThumb2() &&
8921            ARM_AM::getT2SOImmVal(Value) != -1)
8922          TmpInst.setOpcode(ARM::t2MOVi);
8923        else if (hasThumb2() &&
8924                 ARM_AM::getT2SOImmVal(~Value) != -1) {
8925          TmpInst.setOpcode(ARM::t2MVNi);
8926          Value = ~Value;
8927        }
8928        else if (hasV8MBaseline() &&
8929                 Value >=0 && Value < 65536) {
8930          TmpInst.setOpcode(ARM::t2MOVi16);
8931          MovHasS = false;
8932        }
8933        else
8934          UseMov = false;
8935      }
8936      if (UseMov) {
8937        TmpInst.addOperand(Inst.getOperand(0));           // Rt
8938        TmpInst.addOperand(MCOperand::createImm(Value));  // Immediate
8939        TmpInst.addOperand(Inst.getOperand(2));           // CondCode
8940        TmpInst.addOperand(Inst.getOperand(3));           // CondCode
8941        if (MovHasS)
8942          TmpInst.addOperand(MCOperand::createReg(0));    // S
8943        Inst = TmpInst;
8944        return true;
8945      }
8946    }
8947    // No opportunity to use MOV/MVN create constant pool
8948    const MCExpr *CPLoc =
8949      getTargetStreamer().addConstantPoolEntry(SubExprVal,
8950                                               PoolOperand.getStartLoc());
8951    TmpInst.addOperand(Inst.getOperand(0));           // Rt
8952    TmpInst.addOperand(MCOperand::createExpr(CPLoc)); // offset to constpool
8953    if (TmpInst.getOpcode() == ARM::LDRi12)
8954      TmpInst.addOperand(MCOperand::createImm(0));    // unused offset
8955    TmpInst.addOperand(Inst.getOperand(2));           // CondCode
8956    TmpInst.addOperand(Inst.getOperand(3));           // CondCode
8957    Inst = TmpInst;
8958    return true;
8959  }
8960  // Handle NEON VST complex aliases.
8961  case ARM::VST1LNdWB_register_Asm_8:
8962  case ARM::VST1LNdWB_register_Asm_16:
8963  case ARM::VST1LNdWB_register_Asm_32: {
8964    MCInst TmpInst;
8965    // Shuffle the operands around so the lane index operand is in the
8966    // right place.
8967    unsigned Spacing;
8968    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8969    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
8970    TmpInst.addOperand(Inst.getOperand(2)); // Rn
8971    TmpInst.addOperand(Inst.getOperand(3)); // alignment
8972    TmpInst.addOperand(Inst.getOperand(4)); // Rm
8973    TmpInst.addOperand(Inst.getOperand(0)); // Vd
8974    TmpInst.addOperand(Inst.getOperand(1)); // lane
8975    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
8976    TmpInst.addOperand(Inst.getOperand(6));
8977    Inst = TmpInst;
8978    return true;
8979  }
8980
8981  case ARM::VST2LNdWB_register_Asm_8:
8982  case ARM::VST2LNdWB_register_Asm_16:
8983  case ARM::VST2LNdWB_register_Asm_32:
8984  case ARM::VST2LNqWB_register_Asm_16:
8985  case ARM::VST2LNqWB_register_Asm_32: {
8986    MCInst TmpInst;
8987    // Shuffle the operands around so the lane index operand is in the
8988    // right place.
8989    unsigned Spacing;
8990    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8991    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
8992    TmpInst.addOperand(Inst.getOperand(2)); // Rn
8993    TmpInst.addOperand(Inst.getOperand(3)); // alignment
8994    TmpInst.addOperand(Inst.getOperand(4)); // Rm
8995    TmpInst.addOperand(Inst.getOperand(0)); // Vd
8996    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8997                                            Spacing));
8998    TmpInst.addOperand(Inst.getOperand(1)); // lane
8999    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
9000    TmpInst.addOperand(Inst.getOperand(6));
9001    Inst = TmpInst;
9002    return true;
9003  }
9004
9005  case ARM::VST3LNdWB_register_Asm_8:
9006  case ARM::VST3LNdWB_register_Asm_16:
9007  case ARM::VST3LNdWB_register_Asm_32:
9008  case ARM::VST3LNqWB_register_Asm_16:
9009  case ARM::VST3LNqWB_register_Asm_32: {
9010    MCInst TmpInst;
9011    // Shuffle the operands around so the lane index operand is in the
9012    // right place.
9013    unsigned Spacing;
9014    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
9015    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
9016    TmpInst.addOperand(Inst.getOperand(2)); // Rn
9017    TmpInst.addOperand(Inst.getOperand(3)); // alignment
9018    TmpInst.addOperand(Inst.getOperand(4)); // Rm
9019    TmpInst.addOperand(Inst.getOperand(0)); // Vd
9020    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9021                                            Spacing));
9022    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9023                                            Spacing * 2));
9024    TmpInst.addOperand(Inst.getOperand(1)); // lane
9025    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
9026    TmpInst.addOperand(Inst.getOperand(6));
9027    Inst = TmpInst;
9028    return true;
9029  }
9030
9031  case ARM::VST4LNdWB_register_Asm_8:
9032  case ARM::VST4LNdWB_register_Asm_16:
9033  case ARM::VST4LNdWB_register_Asm_32:
9034  case ARM::VST4LNqWB_register_Asm_16:
9035  case ARM::VST4LNqWB_register_Asm_32: {
9036    MCInst TmpInst;
9037    // Shuffle the operands around so the lane index operand is in the
9038    // right place.
9039    unsigned Spacing;
9040    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
9041    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
9042    TmpInst.addOperand(Inst.getOperand(2)); // Rn
9043    TmpInst.addOperand(Inst.getOperand(3)); // alignment
9044    TmpInst.addOperand(Inst.getOperand(4)); // Rm
9045    TmpInst.addOperand(Inst.getOperand(0)); // Vd
9046    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9047                                            Spacing));
9048    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9049                                            Spacing * 2));
9050    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9051                                            Spacing * 3));
9052    TmpInst.addOperand(Inst.getOperand(1)); // lane
9053    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
9054    TmpInst.addOperand(Inst.getOperand(6));
9055    Inst = TmpInst;
9056    return true;
9057  }
9058
9059  case ARM::VST1LNdWB_fixed_Asm_8:
9060  case ARM::VST1LNdWB_fixed_Asm_16:
9061  case ARM::VST1LNdWB_fixed_Asm_32: {
9062    MCInst TmpInst;
9063    // Shuffle the operands around so the lane index operand is in the
9064    // right place.
9065    unsigned Spacing;
9066    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
9067    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
9068    TmpInst.addOperand(Inst.getOperand(2)); // Rn
9069    TmpInst.addOperand(Inst.getOperand(3)); // alignment
9070    TmpInst.addOperand(MCOperand::createReg(0)); // Rm
9071    TmpInst.addOperand(Inst.getOperand(0)); // Vd
9072    TmpInst.addOperand(Inst.getOperand(1)); // lane
9073    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9074    TmpInst.addOperand(Inst.getOperand(5));
9075    Inst = TmpInst;
9076    return true;
9077  }
9078
9079  case ARM::VST2LNdWB_fixed_Asm_8:
9080  case ARM::VST2LNdWB_fixed_Asm_16:
9081  case ARM::VST2LNdWB_fixed_Asm_32:
9082  case ARM::VST2LNqWB_fixed_Asm_16:
9083  case ARM::VST2LNqWB_fixed_Asm_32: {
9084    MCInst TmpInst;
9085    // Shuffle the operands around so the lane index operand is in the
9086    // right place.
9087    unsigned Spacing;
9088    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
9089    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
9090    TmpInst.addOperand(Inst.getOperand(2)); // Rn
9091    TmpInst.addOperand(Inst.getOperand(3)); // alignment
9092    TmpInst.addOperand(MCOperand::createReg(0)); // Rm
9093    TmpInst.addOperand(Inst.getOperand(0)); // Vd
9094    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9095                                            Spacing));
9096    TmpInst.addOperand(Inst.getOperand(1)); // lane
9097    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9098    TmpInst.addOperand(Inst.getOperand(5));
9099    Inst = TmpInst;
9100    return true;
9101  }
9102
9103  case ARM::VST3LNdWB_fixed_Asm_8:
9104  case ARM::VST3LNdWB_fixed_Asm_16:
9105  case ARM::VST3LNdWB_fixed_Asm_32:
9106  case ARM::VST3LNqWB_fixed_Asm_16:
9107  case ARM::VST3LNqWB_fixed_Asm_32: {
9108    MCInst TmpInst;
9109    // Shuffle the operands around so the lane index operand is in the
9110    // right place.
9111    unsigned Spacing;
9112    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
9113    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
9114    TmpInst.addOperand(Inst.getOperand(2)); // Rn
9115    TmpInst.addOperand(Inst.getOperand(3)); // alignment
9116    TmpInst.addOperand(MCOperand::createReg(0)); // Rm
9117    TmpInst.addOperand(Inst.getOperand(0)); // Vd
9118    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9119                                            Spacing));
9120    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9121                                            Spacing * 2));
9122    TmpInst.addOperand(Inst.getOperand(1)); // lane
9123    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9124    TmpInst.addOperand(Inst.getOperand(5));
9125    Inst = TmpInst;
9126    return true;
9127  }
9128
9129  case ARM::VST4LNdWB_fixed_Asm_8:
9130  case ARM::VST4LNdWB_fixed_Asm_16:
9131  case ARM::VST4LNdWB_fixed_Asm_32:
9132  case ARM::VST4LNqWB_fixed_Asm_16:
9133  case ARM::VST4LNqWB_fixed_Asm_32: {
9134    MCInst TmpInst;
9135    // Shuffle the operands around so the lane index operand is in the
9136    // right place.
9137    unsigned Spacing;
9138    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
9139    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
9140    TmpInst.addOperand(Inst.getOperand(2)); // Rn
9141    TmpInst.addOperand(Inst.getOperand(3)); // alignment
9142    TmpInst.addOperand(MCOperand::createReg(0)); // Rm
9143    TmpInst.addOperand(Inst.getOperand(0)); // Vd
9144    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9145                                            Spacing));
9146    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9147                                            Spacing * 2));
9148    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9149                                            Spacing * 3));
9150    TmpInst.addOperand(Inst.getOperand(1)); // lane
9151    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9152    TmpInst.addOperand(Inst.getOperand(5));
9153    Inst = TmpInst;
9154    return true;
9155  }
9156
9157  case ARM::VST1LNdAsm_8:
9158  case ARM::VST1LNdAsm_16:
9159  case ARM::VST1LNdAsm_32: {
9160    MCInst TmpInst;
9161    // Shuffle the operands around so the lane index operand is in the
9162    // right place.
9163    unsigned Spacing;
9164    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
9165    TmpInst.addOperand(Inst.getOperand(2)); // Rn
9166    TmpInst.addOperand(Inst.getOperand(3)); // alignment
9167    TmpInst.addOperand(Inst.getOperand(0)); // Vd
9168    TmpInst.addOperand(Inst.getOperand(1)); // lane
9169    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9170    TmpInst.addOperand(Inst.getOperand(5));
9171    Inst = TmpInst;
9172    return true;
9173  }
9174
9175  case ARM::VST2LNdAsm_8:
9176  case ARM::VST2LNdAsm_16:
9177  case ARM::VST2LNdAsm_32:
9178  case ARM::VST2LNqAsm_16:
9179  case ARM::VST2LNqAsm_32: {
9180    MCInst TmpInst;
9181    // Shuffle the operands around so the lane index operand is in the
9182    // right place.
9183    unsigned Spacing;
9184    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
9185    TmpInst.addOperand(Inst.getOperand(2)); // Rn
9186    TmpInst.addOperand(Inst.getOperand(3)); // alignment
9187    TmpInst.addOperand(Inst.getOperand(0)); // Vd
9188    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9189                                            Spacing));
9190    TmpInst.addOperand(Inst.getOperand(1)); // lane
9191    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9192    TmpInst.addOperand(Inst.getOperand(5));
9193    Inst = TmpInst;
9194    return true;
9195  }
9196
9197  case ARM::VST3LNdAsm_8:
9198  case ARM::VST3LNdAsm_16:
9199  case ARM::VST3LNdAsm_32:
9200  case ARM::VST3LNqAsm_16:
9201  case ARM::VST3LNqAsm_32: {
9202    MCInst TmpInst;
9203    // Shuffle the operands around so the lane index operand is in the
9204    // right place.
9205    unsigned Spacing;
9206    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
9207    TmpInst.addOperand(Inst.getOperand(2)); // Rn
9208    TmpInst.addOperand(Inst.getOperand(3)); // alignment
9209    TmpInst.addOperand(Inst.getOperand(0)); // Vd
9210    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9211                                            Spacing));
9212    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9213                                            Spacing * 2));
9214    TmpInst.addOperand(Inst.getOperand(1)); // lane
9215    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9216    TmpInst.addOperand(Inst.getOperand(5));
9217    Inst = TmpInst;
9218    return true;
9219  }
9220
9221  case ARM::VST4LNdAsm_8:
9222  case ARM::VST4LNdAsm_16:
9223  case ARM::VST4LNdAsm_32:
9224  case ARM::VST4LNqAsm_16:
9225  case ARM::VST4LNqAsm_32: {
9226    MCInst TmpInst;
9227    // Shuffle the operands around so the lane index operand is in the
9228    // right place.
9229    unsigned Spacing;
9230    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
9231    TmpInst.addOperand(Inst.getOperand(2)); // Rn
9232    TmpInst.addOperand(Inst.getOperand(3)); // alignment
9233    TmpInst.addOperand(Inst.getOperand(0)); // Vd
9234    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9235                                            Spacing));
9236    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9237                                            Spacing * 2));
9238    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9239                                            Spacing * 3));
9240    TmpInst.addOperand(Inst.getOperand(1)); // lane
9241    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9242    TmpInst.addOperand(Inst.getOperand(5));
9243    Inst = TmpInst;
9244    return true;
9245  }
9246
9247  // Handle NEON VLD complex aliases.
9248  case ARM::VLD1LNdWB_register_Asm_8:
9249  case ARM::VLD1LNdWB_register_Asm_16:
9250  case ARM::VLD1LNdWB_register_Asm_32: {
9251    MCInst TmpInst;
9252    // Shuffle the operands around so the lane index operand is in the
9253    // right place.
9254    unsigned Spacing;
9255    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9256    TmpInst.addOperand(Inst.getOperand(0)); // Vd
9257    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
9258    TmpInst.addOperand(Inst.getOperand(2)); // Rn
9259    TmpInst.addOperand(Inst.getOperand(3)); // alignment
9260    TmpInst.addOperand(Inst.getOperand(4)); // Rm
9261    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
9262    TmpInst.addOperand(Inst.getOperand(1)); // lane
9263    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
9264    TmpInst.addOperand(Inst.getOperand(6));
9265    Inst = TmpInst;
9266    return true;
9267  }
9268
9269  case ARM::VLD2LNdWB_register_Asm_8:
9270  case ARM::VLD2LNdWB_register_Asm_16:
9271  case ARM::VLD2LNdWB_register_Asm_32:
9272  case ARM::VLD2LNqWB_register_Asm_16:
9273  case ARM::VLD2LNqWB_register_Asm_32: {
9274    MCInst TmpInst;
9275    // Shuffle the operands around so the lane index operand is in the
9276    // right place.
9277    unsigned Spacing;
9278    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9279    TmpInst.addOperand(Inst.getOperand(0)); // Vd
9280    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9281                                            Spacing));
9282    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
9283    TmpInst.addOperand(Inst.getOperand(2)); // Rn
9284    TmpInst.addOperand(Inst.getOperand(3)); // alignment
9285    TmpInst.addOperand(Inst.getOperand(4)); // Rm
9286    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
9287    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9288                                            Spacing));
9289    TmpInst.addOperand(Inst.getOperand(1)); // lane
9290    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
9291    TmpInst.addOperand(Inst.getOperand(6));
9292    Inst = TmpInst;
9293    return true;
9294  }
9295
9296  case ARM::VLD3LNdWB_register_Asm_8:
9297  case ARM::VLD3LNdWB_register_Asm_16:
9298  case ARM::VLD3LNdWB_register_Asm_32:
9299  case ARM::VLD3LNqWB_register_Asm_16:
9300  case ARM::VLD3LNqWB_register_Asm_32: {
9301    MCInst TmpInst;
9302    // Shuffle the operands around so the lane index operand is in the
9303    // right place.
9304    unsigned Spacing;
9305    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9306    TmpInst.addOperand(Inst.getOperand(0)); // Vd
9307    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9308                                            Spacing));
9309    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9310                                            Spacing * 2));
9311    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
9312    TmpInst.addOperand(Inst.getOperand(2)); // Rn
9313    TmpInst.addOperand(Inst.getOperand(3)); // alignment
9314    TmpInst.addOperand(Inst.getOperand(4)); // Rm
9315    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
9316    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9317                                            Spacing));
9318    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9319                                            Spacing * 2));
9320    TmpInst.addOperand(Inst.getOperand(1)); // lane
9321    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
9322    TmpInst.addOperand(Inst.getOperand(6));
9323    Inst = TmpInst;
9324    return true;
9325  }
9326
9327  case ARM::VLD4LNdWB_register_Asm_8:
9328  case ARM::VLD4LNdWB_register_Asm_16:
9329  case ARM::VLD4LNdWB_register_Asm_32:
9330  case ARM::VLD4LNqWB_register_Asm_16:
9331  case ARM::VLD4LNqWB_register_Asm_32: {
9332    MCInst TmpInst;
9333    // Shuffle the operands around so the lane index operand is in the
9334    // right place.
9335    unsigned Spacing;
9336    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9337    TmpInst.addOperand(Inst.getOperand(0)); // Vd
9338    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9339                                            Spacing));
9340    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9341                                            Spacing * 2));
9342    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9343                                            Spacing * 3));
9344    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
9345    TmpInst.addOperand(Inst.getOperand(2)); // Rn
9346    TmpInst.addOperand(Inst.getOperand(3)); // alignment
9347    TmpInst.addOperand(Inst.getOperand(4)); // Rm
9348    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
9349    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9350                                            Spacing));
9351    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9352                                            Spacing * 2));
9353    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9354                                            Spacing * 3));
9355    TmpInst.addOperand(Inst.getOperand(1)); // lane
9356    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
9357    TmpInst.addOperand(Inst.getOperand(6));
9358    Inst = TmpInst;
9359    return true;
9360  }
9361
9362  case ARM::VLD1LNdWB_fixed_Asm_8:
9363  case ARM::VLD1LNdWB_fixed_Asm_16:
9364  case ARM::VLD1LNdWB_fixed_Asm_32: {
9365    MCInst TmpInst;
9366    // Shuffle the operands around so the lane index operand is in the
9367    // right place.
9368    unsigned Spacing;
9369    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9370    TmpInst.addOperand(Inst.getOperand(0)); // Vd
9371    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
9372    TmpInst.addOperand(Inst.getOperand(2)); // Rn
9373    TmpInst.addOperand(Inst.getOperand(3)); // alignment
9374    TmpInst.addOperand(MCOperand::createReg(0)); // Rm
9375    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
9376    TmpInst.addOperand(Inst.getOperand(1)); // lane
9377    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9378    TmpInst.addOperand(Inst.getOperand(5));
9379    Inst = TmpInst;
9380    return true;
9381  }
9382
9383  case ARM::VLD2LNdWB_fixed_Asm_8:
9384  case ARM::VLD2LNdWB_fixed_Asm_16:
9385  case ARM::VLD2LNdWB_fixed_Asm_32:
9386  case ARM::VLD2LNqWB_fixed_Asm_16:
9387  case ARM::VLD2LNqWB_fixed_Asm_32: {
9388    MCInst TmpInst;
9389    // Shuffle the operands around so the lane index operand is in the
9390    // right place.
9391    unsigned Spacing;
9392    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9393    TmpInst.addOperand(Inst.getOperand(0)); // Vd
9394    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9395                                            Spacing));
9396    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
9397    TmpInst.addOperand(Inst.getOperand(2)); // Rn
9398    TmpInst.addOperand(Inst.getOperand(3)); // alignment
9399    TmpInst.addOperand(MCOperand::createReg(0)); // Rm
9400    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
9401    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9402                                            Spacing));
9403    TmpInst.addOperand(Inst.getOperand(1)); // lane
9404    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9405    TmpInst.addOperand(Inst.getOperand(5));
9406    Inst = TmpInst;
9407    return true;
9408  }
9409
9410  case ARM::VLD3LNdWB_fixed_Asm_8:
9411  case ARM::VLD3LNdWB_fixed_Asm_16:
9412  case ARM::VLD3LNdWB_fixed_Asm_32:
9413  case ARM::VLD3LNqWB_fixed_Asm_16:
9414  case ARM::VLD3LNqWB_fixed_Asm_32: {
9415    MCInst TmpInst;
9416    // Shuffle the operands around so the lane index operand is in the
9417    // right place.
9418    unsigned Spacing;
9419    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9420    TmpInst.addOperand(Inst.getOperand(0)); // Vd
9421    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9422                                            Spacing));
9423    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9424                                            Spacing * 2));
9425    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
9426    TmpInst.addOperand(Inst.getOperand(2)); // Rn
9427    TmpInst.addOperand(Inst.getOperand(3)); // alignment
9428    TmpInst.addOperand(MCOperand::createReg(0)); // Rm
9429    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
9430    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9431                                            Spacing));
9432    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9433                                            Spacing * 2));
9434    TmpInst.addOperand(Inst.getOperand(1)); // lane
9435    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9436    TmpInst.addOperand(Inst.getOperand(5));
9437    Inst = TmpInst;
9438    return true;
9439  }
9440
9441  case ARM::VLD4LNdWB_fixed_Asm_8:
9442  case ARM::VLD4LNdWB_fixed_Asm_16:
9443  case ARM::VLD4LNdWB_fixed_Asm_32:
9444  case ARM::VLD4LNqWB_fixed_Asm_16:
9445  case ARM::VLD4LNqWB_fixed_Asm_32: {
9446    MCInst TmpInst;
9447    // Shuffle the operands around so the lane index operand is in the
9448    // right place.
9449    unsigned Spacing;
9450    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9451    TmpInst.addOperand(Inst.getOperand(0)); // Vd
9452    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9453                                            Spacing));
9454    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9455                                            Spacing * 2));
9456    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9457                                            Spacing * 3));
9458    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
9459    TmpInst.addOperand(Inst.getOperand(2)); // Rn
9460    TmpInst.addOperand(Inst.getOperand(3)); // alignment
9461    TmpInst.addOperand(MCOperand::createReg(0)); // Rm
9462    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
9463    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9464                                            Spacing));
9465    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9466                                            Spacing * 2));
9467    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9468                                            Spacing * 3));
9469    TmpInst.addOperand(Inst.getOperand(1)); // lane
9470    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9471    TmpInst.addOperand(Inst.getOperand(5));
9472    Inst = TmpInst;
9473    return true;
9474  }
9475
9476  case ARM::VLD1LNdAsm_8:
9477  case ARM::VLD1LNdAsm_16:
9478  case ARM::VLD1LNdAsm_32: {
9479    MCInst TmpInst;
9480    // Shuffle the operands around so the lane index operand is in the
9481    // right place.
9482    unsigned Spacing;
9483    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9484    TmpInst.addOperand(Inst.getOperand(0)); // Vd
9485    TmpInst.addOperand(Inst.getOperand(2)); // Rn
9486    TmpInst.addOperand(Inst.getOperand(3)); // alignment
9487    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
9488    TmpInst.addOperand(Inst.getOperand(1)); // lane
9489    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9490    TmpInst.addOperand(Inst.getOperand(5));
9491    Inst = TmpInst;
9492    return true;
9493  }
9494
9495  case ARM::VLD2LNdAsm_8:
9496  case ARM::VLD2LNdAsm_16:
9497  case ARM::VLD2LNdAsm_32:
9498  case ARM::VLD2LNqAsm_16:
9499  case ARM::VLD2LNqAsm_32: {
9500    MCInst TmpInst;
9501    // Shuffle the operands around so the lane index operand is in the
9502    // right place.
9503    unsigned Spacing;
9504    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9505    TmpInst.addOperand(Inst.getOperand(0)); // Vd
9506    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9507                                            Spacing));
9508    TmpInst.addOperand(Inst.getOperand(2)); // Rn
9509    TmpInst.addOperand(Inst.getOperand(3)); // alignment
9510    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
9511    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9512                                            Spacing));
9513    TmpInst.addOperand(Inst.getOperand(1)); // lane
9514    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9515    TmpInst.addOperand(Inst.getOperand(5));
9516    Inst = TmpInst;
9517    return true;
9518  }
9519
9520  case ARM::VLD3LNdAsm_8:
9521  case ARM::VLD3LNdAsm_16:
9522  case ARM::VLD3LNdAsm_32:
9523  case ARM::VLD3LNqAsm_16:
9524  case ARM::VLD3LNqAsm_32: {
9525    MCInst TmpInst;
9526    // Shuffle the operands around so the lane index operand is in the
9527    // right place.
9528    unsigned Spacing;
9529    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9530    TmpInst.addOperand(Inst.getOperand(0)); // Vd
9531    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9532                                            Spacing));
9533    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9534                                            Spacing * 2));
9535    TmpInst.addOperand(Inst.getOperand(2)); // Rn
9536    TmpInst.addOperand(Inst.getOperand(3)); // alignment
9537    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
9538    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9539                                            Spacing));
9540    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9541                                            Spacing * 2));
9542    TmpInst.addOperand(Inst.getOperand(1)); // lane
9543    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9544    TmpInst.addOperand(Inst.getOperand(5));
9545    Inst = TmpInst;
9546    return true;
9547  }
9548
9549  case ARM::VLD4LNdAsm_8:
9550  case ARM::VLD4LNdAsm_16:
9551  case ARM::VLD4LNdAsm_32:
9552  case ARM::VLD4LNqAsm_16:
9553  case ARM::VLD4LNqAsm_32: {
9554    MCInst TmpInst;
9555    // Shuffle the operands around so the lane index operand is in the
9556    // right place.
9557    unsigned Spacing;
9558    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9559    TmpInst.addOperand(Inst.getOperand(0)); // Vd
9560    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9561                                            Spacing));
9562    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9563                                            Spacing * 2));
9564    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9565                                            Spacing * 3));
9566    TmpInst.addOperand(Inst.getOperand(2)); // Rn
9567    TmpInst.addOperand(Inst.getOperand(3)); // alignment
9568    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
9569    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9570                                            Spacing));
9571    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9572                                            Spacing * 2));
9573    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9574                                            Spacing * 3));
9575    TmpInst.addOperand(Inst.getOperand(1)); // lane
9576    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9577    TmpInst.addOperand(Inst.getOperand(5));
9578    Inst = TmpInst;
9579    return true;
9580  }
9581
9582  // VLD3DUP single 3-element structure to all lanes instructions.
9583  case ARM::VLD3DUPdAsm_8:
9584  case ARM::VLD3DUPdAsm_16:
9585  case ARM::VLD3DUPdAsm_32:
9586  case ARM::VLD3DUPqAsm_8:
9587  case ARM::VLD3DUPqAsm_16:
9588  case ARM::VLD3DUPqAsm_32: {
9589    MCInst TmpInst;
9590    unsigned Spacing;
9591    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9592    TmpInst.addOperand(Inst.getOperand(0)); // Vd
9593    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9594                                            Spacing));
9595    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9596                                            Spacing * 2));
9597    TmpInst.addOperand(Inst.getOperand(1)); // Rn
9598    TmpInst.addOperand(Inst.getOperand(2)); // alignment
9599    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9600    TmpInst.addOperand(Inst.getOperand(4));
9601    Inst = TmpInst;
9602    return true;
9603  }
9604
9605  case ARM::VLD3DUPdWB_fixed_Asm_8:
9606  case ARM::VLD3DUPdWB_fixed_Asm_16:
9607  case ARM::VLD3DUPdWB_fixed_Asm_32:
9608  case ARM::VLD3DUPqWB_fixed_Asm_8:
9609  case ARM::VLD3DUPqWB_fixed_Asm_16:
9610  case ARM::VLD3DUPqWB_fixed_Asm_32: {
9611    MCInst TmpInst;
9612    unsigned Spacing;
9613    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9614    TmpInst.addOperand(Inst.getOperand(0)); // Vd
9615    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9616                                            Spacing));
9617    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9618                                            Spacing * 2));
9619    TmpInst.addOperand(Inst.getOperand(1)); // Rn
9620    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
9621    TmpInst.addOperand(Inst.getOperand(2)); // alignment
9622    TmpInst.addOperand(MCOperand::createReg(0)); // Rm
9623    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9624    TmpInst.addOperand(Inst.getOperand(4));
9625    Inst = TmpInst;
9626    return true;
9627  }
9628
9629  case ARM::VLD3DUPdWB_register_Asm_8:
9630  case ARM::VLD3DUPdWB_register_Asm_16:
9631  case ARM::VLD3DUPdWB_register_Asm_32:
9632  case ARM::VLD3DUPqWB_register_Asm_8:
9633  case ARM::VLD3DUPqWB_register_Asm_16:
9634  case ARM::VLD3DUPqWB_register_Asm_32: {
9635    MCInst TmpInst;
9636    unsigned Spacing;
9637    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9638    TmpInst.addOperand(Inst.getOperand(0)); // Vd
9639    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9640                                            Spacing));
9641    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9642                                            Spacing * 2));
9643    TmpInst.addOperand(Inst.getOperand(1)); // Rn
9644    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
9645    TmpInst.addOperand(Inst.getOperand(2)); // alignment
9646    TmpInst.addOperand(Inst.getOperand(3)); // Rm
9647    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9648    TmpInst.addOperand(Inst.getOperand(5));
9649    Inst = TmpInst;
9650    return true;
9651  }
9652
9653  // VLD3 multiple 3-element structure instructions.
9654  case ARM::VLD3dAsm_8:
9655  case ARM::VLD3dAsm_16:
9656  case ARM::VLD3dAsm_32:
9657  case ARM::VLD3qAsm_8:
9658  case ARM::VLD3qAsm_16:
9659  case ARM::VLD3qAsm_32: {
9660    MCInst TmpInst;
9661    unsigned Spacing;
9662    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9663    TmpInst.addOperand(Inst.getOperand(0)); // Vd
9664    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9665                                            Spacing));
9666    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9667                                            Spacing * 2));
9668    TmpInst.addOperand(Inst.getOperand(1)); // Rn
9669    TmpInst.addOperand(Inst.getOperand(2)); // alignment
9670    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9671    TmpInst.addOperand(Inst.getOperand(4));
9672    Inst = TmpInst;
9673    return true;
9674  }
9675
9676  case ARM::VLD3dWB_fixed_Asm_8:
9677  case ARM::VLD3dWB_fixed_Asm_16:
9678  case ARM::VLD3dWB_fixed_Asm_32:
9679  case ARM::VLD3qWB_fixed_Asm_8:
9680  case ARM::VLD3qWB_fixed_Asm_16:
9681  case ARM::VLD3qWB_fixed_Asm_32: {
9682    MCInst TmpInst;
9683    unsigned Spacing;
9684    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9685    TmpInst.addOperand(Inst.getOperand(0)); // Vd
9686    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9687                                            Spacing));
9688    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9689                                            Spacing * 2));
9690    TmpInst.addOperand(Inst.getOperand(1)); // Rn
9691    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
9692    TmpInst.addOperand(Inst.getOperand(2)); // alignment
9693    TmpInst.addOperand(MCOperand::createReg(0)); // Rm
9694    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9695    TmpInst.addOperand(Inst.getOperand(4));
9696    Inst = TmpInst;
9697    return true;
9698  }
9699
9700  case ARM::VLD3dWB_register_Asm_8:
9701  case ARM::VLD3dWB_register_Asm_16:
9702  case ARM::VLD3dWB_register_Asm_32:
9703  case ARM::VLD3qWB_register_Asm_8:
9704  case ARM::VLD3qWB_register_Asm_16:
9705  case ARM::VLD3qWB_register_Asm_32: {
9706    MCInst TmpInst;
9707    unsigned Spacing;
9708    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9709    TmpInst.addOperand(Inst.getOperand(0)); // Vd
9710    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9711                                            Spacing));
9712    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9713                                            Spacing * 2));
9714    TmpInst.addOperand(Inst.getOperand(1)); // Rn
9715    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
9716    TmpInst.addOperand(Inst.getOperand(2)); // alignment
9717    TmpInst.addOperand(Inst.getOperand(3)); // Rm
9718    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9719    TmpInst.addOperand(Inst.getOperand(5));
9720    Inst = TmpInst;
9721    return true;
9722  }
9723
9724  // VLD4DUP single 3-element structure to all lanes instructions.
9725  case ARM::VLD4DUPdAsm_8:
9726  case ARM::VLD4DUPdAsm_16:
9727  case ARM::VLD4DUPdAsm_32:
9728  case ARM::VLD4DUPqAsm_8:
9729  case ARM::VLD4DUPqAsm_16:
9730  case ARM::VLD4DUPqAsm_32: {
9731    MCInst TmpInst;
9732    unsigned Spacing;
9733    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9734    TmpInst.addOperand(Inst.getOperand(0)); // Vd
9735    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9736                                            Spacing));
9737    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9738                                            Spacing * 2));
9739    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9740                                            Spacing * 3));
9741    TmpInst.addOperand(Inst.getOperand(1)); // Rn
9742    TmpInst.addOperand(Inst.getOperand(2)); // alignment
9743    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9744    TmpInst.addOperand(Inst.getOperand(4));
9745    Inst = TmpInst;
9746    return true;
9747  }
9748
9749  case ARM::VLD4DUPdWB_fixed_Asm_8:
9750  case ARM::VLD4DUPdWB_fixed_Asm_16:
9751  case ARM::VLD4DUPdWB_fixed_Asm_32:
9752  case ARM::VLD4DUPqWB_fixed_Asm_8:
9753  case ARM::VLD4DUPqWB_fixed_Asm_16:
9754  case ARM::VLD4DUPqWB_fixed_Asm_32: {
9755    MCInst TmpInst;
9756    unsigned Spacing;
9757    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9758    TmpInst.addOperand(Inst.getOperand(0)); // Vd
9759    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9760                                            Spacing));
9761    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9762                                            Spacing * 2));
9763    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9764                                            Spacing * 3));
9765    TmpInst.addOperand(Inst.getOperand(1)); // Rn
9766    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
9767    TmpInst.addOperand(Inst.getOperand(2)); // alignment
9768    TmpInst.addOperand(MCOperand::createReg(0)); // Rm
9769    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9770    TmpInst.addOperand(Inst.getOperand(4));
9771    Inst = TmpInst;
9772    return true;
9773  }
9774
9775  case ARM::VLD4DUPdWB_register_Asm_8:
9776  case ARM::VLD4DUPdWB_register_Asm_16:
9777  case ARM::VLD4DUPdWB_register_Asm_32:
9778  case ARM::VLD4DUPqWB_register_Asm_8:
9779  case ARM::VLD4DUPqWB_register_Asm_16:
9780  case ARM::VLD4DUPqWB_register_Asm_32: {
9781    MCInst TmpInst;
9782    unsigned Spacing;
9783    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9784    TmpInst.addOperand(Inst.getOperand(0)); // Vd
9785    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9786                                            Spacing));
9787    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9788                                            Spacing * 2));
9789    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9790                                            Spacing * 3));
9791    TmpInst.addOperand(Inst.getOperand(1)); // Rn
9792    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
9793    TmpInst.addOperand(Inst.getOperand(2)); // alignment
9794    TmpInst.addOperand(Inst.getOperand(3)); // Rm
9795    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9796    TmpInst.addOperand(Inst.getOperand(5));
9797    Inst = TmpInst;
9798    return true;
9799  }
9800
9801  // VLD4 multiple 4-element structure instructions.
9802  case ARM::VLD4dAsm_8:
9803  case ARM::VLD4dAsm_16:
9804  case ARM::VLD4dAsm_32:
9805  case ARM::VLD4qAsm_8:
9806  case ARM::VLD4qAsm_16:
9807  case ARM::VLD4qAsm_32: {
9808    MCInst TmpInst;
9809    unsigned Spacing;
9810    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9811    TmpInst.addOperand(Inst.getOperand(0)); // Vd
9812    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9813                                            Spacing));
9814    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9815                                            Spacing * 2));
9816    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9817                                            Spacing * 3));
9818    TmpInst.addOperand(Inst.getOperand(1)); // Rn
9819    TmpInst.addOperand(Inst.getOperand(2)); // alignment
9820    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9821    TmpInst.addOperand(Inst.getOperand(4));
9822    Inst = TmpInst;
9823    return true;
9824  }
9825
9826  case ARM::VLD4dWB_fixed_Asm_8:
9827  case ARM::VLD4dWB_fixed_Asm_16:
9828  case ARM::VLD4dWB_fixed_Asm_32:
9829  case ARM::VLD4qWB_fixed_Asm_8:
9830  case ARM::VLD4qWB_fixed_Asm_16:
9831  case ARM::VLD4qWB_fixed_Asm_32: {
9832    MCInst TmpInst;
9833    unsigned Spacing;
9834    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9835    TmpInst.addOperand(Inst.getOperand(0)); // Vd
9836    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9837                                            Spacing));
9838    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9839                                            Spacing * 2));
9840    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9841                                            Spacing * 3));
9842    TmpInst.addOperand(Inst.getOperand(1)); // Rn
9843    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
9844    TmpInst.addOperand(Inst.getOperand(2)); // alignment
9845    TmpInst.addOperand(MCOperand::createReg(0)); // Rm
9846    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9847    TmpInst.addOperand(Inst.getOperand(4));
9848    Inst = TmpInst;
9849    return true;
9850  }
9851
9852  case ARM::VLD4dWB_register_Asm_8:
9853  case ARM::VLD4dWB_register_Asm_16:
9854  case ARM::VLD4dWB_register_Asm_32:
9855  case ARM::VLD4qWB_register_Asm_8:
9856  case ARM::VLD4qWB_register_Asm_16:
9857  case ARM::VLD4qWB_register_Asm_32: {
9858    MCInst TmpInst;
9859    unsigned Spacing;
9860    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9861    TmpInst.addOperand(Inst.getOperand(0)); // Vd
9862    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9863                                            Spacing));
9864    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9865                                            Spacing * 2));
9866    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9867                                            Spacing * 3));
9868    TmpInst.addOperand(Inst.getOperand(1)); // Rn
9869    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
9870    TmpInst.addOperand(Inst.getOperand(2)); // alignment
9871    TmpInst.addOperand(Inst.getOperand(3)); // Rm
9872    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9873    TmpInst.addOperand(Inst.getOperand(5));
9874    Inst = TmpInst;
9875    return true;
9876  }
9877
9878  // VST3 multiple 3-element structure instructions.
9879  case ARM::VST3dAsm_8:
9880  case ARM::VST3dAsm_16:
9881  case ARM::VST3dAsm_32:
9882  case ARM::VST3qAsm_8:
9883  case ARM::VST3qAsm_16:
9884  case ARM::VST3qAsm_32: {
9885    MCInst TmpInst;
9886    unsigned Spacing;
9887    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
9888    TmpInst.addOperand(Inst.getOperand(1)); // Rn
9889    TmpInst.addOperand(Inst.getOperand(2)); // alignment
9890    TmpInst.addOperand(Inst.getOperand(0)); // Vd
9891    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9892                                            Spacing));
9893    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9894                                            Spacing * 2));
9895    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9896    TmpInst.addOperand(Inst.getOperand(4));
9897    Inst = TmpInst;
9898    return true;
9899  }
9900
9901  case ARM::VST3dWB_fixed_Asm_8:
9902  case ARM::VST3dWB_fixed_Asm_16:
9903  case ARM::VST3dWB_fixed_Asm_32:
9904  case ARM::VST3qWB_fixed_Asm_8:
9905  case ARM::VST3qWB_fixed_Asm_16:
9906  case ARM::VST3qWB_fixed_Asm_32: {
9907    MCInst TmpInst;
9908    unsigned Spacing;
9909    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
9910    TmpInst.addOperand(Inst.getOperand(1)); // Rn
9911    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
9912    TmpInst.addOperand(Inst.getOperand(2)); // alignment
9913    TmpInst.addOperand(MCOperand::createReg(0)); // Rm
9914    TmpInst.addOperand(Inst.getOperand(0)); // Vd
9915    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9916                                            Spacing));
9917    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9918                                            Spacing * 2));
9919    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9920    TmpInst.addOperand(Inst.getOperand(4));
9921    Inst = TmpInst;
9922    return true;
9923  }
9924
9925  case ARM::VST3dWB_register_Asm_8:
9926  case ARM::VST3dWB_register_Asm_16:
9927  case ARM::VST3dWB_register_Asm_32:
9928  case ARM::VST3qWB_register_Asm_8:
9929  case ARM::VST3qWB_register_Asm_16:
9930  case ARM::VST3qWB_register_Asm_32: {
9931    MCInst TmpInst;
9932    unsigned Spacing;
9933    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
9934    TmpInst.addOperand(Inst.getOperand(1)); // Rn
9935    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
9936    TmpInst.addOperand(Inst.getOperand(2)); // alignment
9937    TmpInst.addOperand(Inst.getOperand(3)); // Rm
9938    TmpInst.addOperand(Inst.getOperand(0)); // Vd
9939    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9940                                            Spacing));
9941    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9942                                            Spacing * 2));
9943    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9944    TmpInst.addOperand(Inst.getOperand(5));
9945    Inst = TmpInst;
9946    return true;
9947  }
9948
9949  // VST4 multiple 3-element structure instructions.
9950  case ARM::VST4dAsm_8:
9951  case ARM::VST4dAsm_16:
9952  case ARM::VST4dAsm_32:
9953  case ARM::VST4qAsm_8:
9954  case ARM::VST4qAsm_16:
9955  case ARM::VST4qAsm_32: {
9956    MCInst TmpInst;
9957    unsigned Spacing;
9958    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
9959    TmpInst.addOperand(Inst.getOperand(1)); // Rn
9960    TmpInst.addOperand(Inst.getOperand(2)); // alignment
9961    TmpInst.addOperand(Inst.getOperand(0)); // Vd
9962    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9963                                            Spacing));
9964    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9965                                            Spacing * 2));
9966    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9967                                            Spacing * 3));
9968    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9969    TmpInst.addOperand(Inst.getOperand(4));
9970    Inst = TmpInst;
9971    return true;
9972  }
9973
9974  case ARM::VST4dWB_fixed_Asm_8:
9975  case ARM::VST4dWB_fixed_Asm_16:
9976  case ARM::VST4dWB_fixed_Asm_32:
9977  case ARM::VST4qWB_fixed_Asm_8:
9978  case ARM::VST4qWB_fixed_Asm_16:
9979  case ARM::VST4qWB_fixed_Asm_32: {
9980    MCInst TmpInst;
9981    unsigned Spacing;
9982    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
9983    TmpInst.addOperand(Inst.getOperand(1)); // Rn
9984    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
9985    TmpInst.addOperand(Inst.getOperand(2)); // alignment
9986    TmpInst.addOperand(MCOperand::createReg(0)); // Rm
9987    TmpInst.addOperand(Inst.getOperand(0)); // Vd
9988    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9989                                            Spacing));
9990    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9991                                            Spacing * 2));
9992    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9993                                            Spacing * 3));
9994    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9995    TmpInst.addOperand(Inst.getOperand(4));
9996    Inst = TmpInst;
9997    return true;
9998  }
9999
10000  case ARM::VST4dWB_register_Asm_8:
10001  case ARM::VST4dWB_register_Asm_16:
10002  case ARM::VST4dWB_register_Asm_32:
10003  case ARM::VST4qWB_register_Asm_8:
10004  case ARM::VST4qWB_register_Asm_16:
10005  case ARM::VST4qWB_register_Asm_32: {
10006    MCInst TmpInst;
10007    unsigned Spacing;
10008    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
10009    TmpInst.addOperand(Inst.getOperand(1)); // Rn
10010    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
10011    TmpInst.addOperand(Inst.getOperand(2)); // alignment
10012    TmpInst.addOperand(Inst.getOperand(3)); // Rm
10013    TmpInst.addOperand(Inst.getOperand(0)); // Vd
10014    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
10015                                            Spacing));
10016    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
10017                                            Spacing * 2));
10018    TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
10019                                            Spacing * 3));
10020    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
10021    TmpInst.addOperand(Inst.getOperand(5));
10022    Inst = TmpInst;
10023    return true;
10024  }
10025
10026  // Handle encoding choice for the shift-immediate instructions.
10027  case ARM::t2LSLri:
10028  case ARM::t2LSRri:
10029  case ARM::t2ASRri:
10030    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
10031        isARMLowRegister(Inst.getOperand(1).getReg()) &&
10032        Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
10033        !HasWideQualifier) {
10034      unsigned NewOpc;
10035      switch (Inst.getOpcode()) {
10036      default: llvm_unreachable("unexpected opcode");
10037      case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
10038      case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
10039      case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
10040      }
10041      // The Thumb1 operands aren't in the same order. Awesome, eh?
10042      MCInst TmpInst;
10043      TmpInst.setOpcode(NewOpc);
10044      TmpInst.addOperand(Inst.getOperand(0));
10045      TmpInst.addOperand(Inst.getOperand(5));
10046      TmpInst.addOperand(Inst.getOperand(1));
10047      TmpInst.addOperand(Inst.getOperand(2));
10048      TmpInst.addOperand(Inst.getOperand(3));
10049      TmpInst.addOperand(Inst.getOperand(4));
10050      Inst = TmpInst;
10051      return true;
10052    }
10053    return false;
10054
10055  // Handle the Thumb2 mode MOV complex aliases.
10056  case ARM::t2MOVsr:
10057  case ARM::t2MOVSsr: {
10058    // Which instruction to expand to depends on the CCOut operand and
10059    // whether we're in an IT block if the register operands are low
10060    // registers.
10061    bool isNarrow = false;
10062    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
10063        isARMLowRegister(Inst.getOperand(1).getReg()) &&
10064        isARMLowRegister(Inst.getOperand(2).getReg()) &&
10065        Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
10066        inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr) &&
10067        !HasWideQualifier)
10068      isNarrow = true;
10069    MCInst TmpInst;
10070    unsigned newOpc;
10071    switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
10072    default: llvm_unreachable("unexpected opcode!");
10073    case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
10074    case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
10075    case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
10076    case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR   : ARM::t2RORrr; break;
10077    }
10078    TmpInst.setOpcode(newOpc);
10079    TmpInst.addOperand(Inst.getOperand(0)); // Rd
10080    if (isNarrow)
10081      TmpInst.addOperand(MCOperand::createReg(
10082          Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
10083    TmpInst.addOperand(Inst.getOperand(1)); // Rn
10084    TmpInst.addOperand(Inst.getOperand(2)); // Rm
10085    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
10086    TmpInst.addOperand(Inst.getOperand(5));
10087    if (!isNarrow)
10088      TmpInst.addOperand(MCOperand::createReg(
10089          Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
10090    Inst = TmpInst;
10091    return true;
10092  }
10093  case ARM::t2MOVsi:
10094  case ARM::t2MOVSsi: {
10095    // Which instruction to expand to depends on the CCOut operand and
10096    // whether we're in an IT block if the register operands are low
10097    // registers.
10098    bool isNarrow = false;
10099    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
10100        isARMLowRegister(Inst.getOperand(1).getReg()) &&
10101        inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi) &&
10102        !HasWideQualifier)
10103      isNarrow = true;
10104    MCInst TmpInst;
10105    unsigned newOpc;
10106    unsigned Shift = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
10107    unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
10108    bool isMov = false;
10109    // MOV rd, rm, LSL #0 is actually a MOV instruction
10110    if (Shift == ARM_AM::lsl && Amount == 0) {
10111      isMov = true;
10112      // The 16-bit encoding of MOV rd, rm, LSL #N is explicitly encoding T2 of
10113      // MOV (register) in the ARMv8-A and ARMv8-M manuals, and immediate 0 is
10114      // unpredictable in an IT block so the 32-bit encoding T3 has to be used
10115      // instead.
10116      if (inITBlock()) {
10117        isNarrow = false;
10118      }
10119      newOpc = isNarrow ? ARM::tMOVSr : ARM::t2MOVr;
10120    } else {
10121      switch(Shift) {
10122      default: llvm_unreachable("unexpected opcode!");
10123      case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
10124      case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
10125      case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
10126      case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
10127      case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
10128      }
10129    }
10130    if (Amount == 32) Amount = 0;
10131    TmpInst.setOpcode(newOpc);
10132    TmpInst.addOperand(Inst.getOperand(0)); // Rd
10133    if (isNarrow && !isMov)
10134      TmpInst.addOperand(MCOperand::createReg(
10135          Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
10136    TmpInst.addOperand(Inst.getOperand(1)); // Rn
10137    if (newOpc != ARM::t2RRX && !isMov)
10138      TmpInst.addOperand(MCOperand::createImm(Amount));
10139    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
10140    TmpInst.addOperand(Inst.getOperand(4));
10141    if (!isNarrow)
10142      TmpInst.addOperand(MCOperand::createReg(
10143          Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
10144    Inst = TmpInst;
10145    return true;
10146  }
10147  // Handle the ARM mode MOV complex aliases.
10148  case ARM::ASRr:
10149  case ARM::LSRr:
10150  case ARM::LSLr:
10151  case ARM::RORr: {
10152    ARM_AM::ShiftOpc ShiftTy;
10153    switch(Inst.getOpcode()) {
10154    default: llvm_unreachable("unexpected opcode!");
10155    case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
10156    case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
10157    case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
10158    case ARM::RORr: ShiftTy = ARM_AM::ror; break;
10159    }
10160    unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
10161    MCInst TmpInst;
10162    TmpInst.setOpcode(ARM::MOVsr);
10163    TmpInst.addOperand(Inst.getOperand(0)); // Rd
10164    TmpInst.addOperand(Inst.getOperand(1)); // Rn
10165    TmpInst.addOperand(Inst.getOperand(2)); // Rm
10166    TmpInst.addOperand(MCOperand::createImm(Shifter)); // Shift value and ty
10167    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
10168    TmpInst.addOperand(Inst.getOperand(4));
10169    TmpInst.addOperand(Inst.getOperand(5)); // cc_out
10170    Inst = TmpInst;
10171    return true;
10172  }
10173  case ARM::ASRi:
10174  case ARM::LSRi:
10175  case ARM::LSLi:
10176  case ARM::RORi: {
10177    ARM_AM::ShiftOpc ShiftTy;
10178    switch(Inst.getOpcode()) {
10179    default: llvm_unreachable("unexpected opcode!");
10180    case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
10181    case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
10182    case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
10183    case ARM::RORi: ShiftTy = ARM_AM::ror; break;
10184    }
10185    // A shift by zero is a plain MOVr, not a MOVsi.
10186    unsigned Amt = Inst.getOperand(2).getImm();
10187    unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
10188    // A shift by 32 should be encoded as 0 when permitted
10189    if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
10190      Amt = 0;
10191    unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
10192    MCInst TmpInst;
10193    TmpInst.setOpcode(Opc);
10194    TmpInst.addOperand(Inst.getOperand(0)); // Rd
10195    TmpInst.addOperand(Inst.getOperand(1)); // Rn
10196    if (Opc == ARM::MOVsi)
10197      TmpInst.addOperand(MCOperand::createImm(Shifter)); // Shift value and ty
10198    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
10199    TmpInst.addOperand(Inst.getOperand(4));
10200    TmpInst.addOperand(Inst.getOperand(5)); // cc_out
10201    Inst = TmpInst;
10202    return true;
10203  }
10204  case ARM::RRXi: {
10205    unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
10206    MCInst TmpInst;
10207    TmpInst.setOpcode(ARM::MOVsi);
10208    TmpInst.addOperand(Inst.getOperand(0)); // Rd
10209    TmpInst.addOperand(Inst.getOperand(1)); // Rn
10210    TmpInst.addOperand(MCOperand::createImm(Shifter)); // Shift value and ty
10211    TmpInst.addOperand(Inst.getOperand(2)); // CondCode
10212    TmpInst.addOperand(Inst.getOperand(3));
10213    TmpInst.addOperand(Inst.getOperand(4)); // cc_out
10214    Inst = TmpInst;
10215    return true;
10216  }
10217  case ARM::t2LDMIA_UPD: {
10218    // If this is a load of a single register, then we should use
10219    // a post-indexed LDR instruction instead, per the ARM ARM.
10220    if (Inst.getNumOperands() != 5)
10221      return false;
10222    MCInst TmpInst;
10223    TmpInst.setOpcode(ARM::t2LDR_POST);
10224    TmpInst.addOperand(Inst.getOperand(4)); // Rt
10225    TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
10226    TmpInst.addOperand(Inst.getOperand(1)); // Rn
10227    TmpInst.addOperand(MCOperand::createImm(4));
10228    TmpInst.addOperand(Inst.getOperand(2)); // CondCode
10229    TmpInst.addOperand(Inst.getOperand(3));
10230    Inst = TmpInst;
10231    return true;
10232  }
10233  case ARM::t2STMDB_UPD: {
10234    // If this is a store of a single register, then we should use
10235    // a pre-indexed STR instruction instead, per the ARM ARM.
10236    if (Inst.getNumOperands() != 5)
10237      return false;
10238    MCInst TmpInst;
10239    TmpInst.setOpcode(ARM::t2STR_PRE);
10240    TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
10241    TmpInst.addOperand(Inst.getOperand(4)); // Rt
10242    TmpInst.addOperand(Inst.getOperand(1)); // Rn
10243    TmpInst.addOperand(MCOperand::createImm(-4));
10244    TmpInst.addOperand(Inst.getOperand(2)); // CondCode
10245    TmpInst.addOperand(Inst.getOperand(3));
10246    Inst = TmpInst;
10247    return true;
10248  }
10249  case ARM::LDMIA_UPD:
10250    // If this is a load of a single register via a 'pop', then we should use
10251    // a post-indexed LDR instruction instead, per the ARM ARM.
10252    if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "pop" &&
10253        Inst.getNumOperands() == 5) {
10254      MCInst TmpInst;
10255      TmpInst.setOpcode(ARM::LDR_POST_IMM);
10256      TmpInst.addOperand(Inst.getOperand(4)); // Rt
10257      TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
10258      TmpInst.addOperand(Inst.getOperand(1)); // Rn
10259      TmpInst.addOperand(MCOperand::createReg(0));  // am2offset
10260      TmpInst.addOperand(MCOperand::createImm(4));
10261      TmpInst.addOperand(Inst.getOperand(2)); // CondCode
10262      TmpInst.addOperand(Inst.getOperand(3));
10263      Inst = TmpInst;
10264      return true;
10265    }
10266    break;
10267  case ARM::STMDB_UPD:
10268    // If this is a store of a single register via a 'push', then we should use
10269    // a pre-indexed STR instruction instead, per the ARM ARM.
10270    if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "push" &&
10271        Inst.getNumOperands() == 5) {
10272      MCInst TmpInst;
10273      TmpInst.setOpcode(ARM::STR_PRE_IMM);
10274      TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
10275      TmpInst.addOperand(Inst.getOperand(4)); // Rt
10276      TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
10277      TmpInst.addOperand(MCOperand::createImm(-4));
10278      TmpInst.addOperand(Inst.getOperand(2)); // CondCode
10279      TmpInst.addOperand(Inst.getOperand(3));
10280      Inst = TmpInst;
10281    }
10282    break;
10283  case ARM::t2ADDri12:
10284  case ARM::t2SUBri12:
10285  case ARM::t2ADDspImm12:
10286  case ARM::t2SUBspImm12: {
10287    // If the immediate fits for encoding T3 and the generic
10288    // mnemonic was used, encoding T3 is preferred.
10289    const StringRef Token = static_cast<ARMOperand &>(*Operands[0]).getToken();
10290    if ((Token != "add" && Token != "sub") ||
10291        ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
10292      break;
10293    switch (Inst.getOpcode()) {
10294    case ARM::t2ADDri12:
10295      Inst.setOpcode(ARM::t2ADDri);
10296      break;
10297    case ARM::t2SUBri12:
10298      Inst.setOpcode(ARM::t2SUBri);
10299      break;
10300    case ARM::t2ADDspImm12:
10301      Inst.setOpcode(ARM::t2ADDspImm);
10302      break;
10303    case ARM::t2SUBspImm12:
10304      Inst.setOpcode(ARM::t2SUBspImm);
10305      break;
10306    }
10307
10308    Inst.addOperand(MCOperand::createReg(0)); // cc_out
10309    return true;
10310  }
10311  case ARM::tADDi8:
10312    // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
10313    // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
10314    // to encoding T2 if <Rd> is specified and encoding T2 is preferred
10315    // to encoding T1 if <Rd> is omitted."
10316    if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
10317      Inst.setOpcode(ARM::tADDi3);
10318      return true;
10319    }
10320    break;
10321  case ARM::tSUBi8:
10322    // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
10323    // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
10324    // to encoding T2 if <Rd> is specified and encoding T2 is preferred
10325    // to encoding T1 if <Rd> is omitted."
10326    if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
10327      Inst.setOpcode(ARM::tSUBi3);
10328      return true;
10329    }
10330    break;
10331  case ARM::t2ADDri:
10332  case ARM::t2SUBri: {
10333    // If the destination and first source operand are the same, and
10334    // the flags are compatible with the current IT status, use encoding T2
10335    // instead of T3. For compatibility with the system 'as'. Make sure the
10336    // wide encoding wasn't explicit.
10337    if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
10338        !isARMLowRegister(Inst.getOperand(0).getReg()) ||
10339        (Inst.getOperand(2).isImm() &&
10340         (unsigned)Inst.getOperand(2).getImm() > 255) ||
10341        Inst.getOperand(5).getReg() != (inITBlock() ? 0 : ARM::CPSR) ||
10342        HasWideQualifier)
10343      break;
10344    MCInst TmpInst;
10345    TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
10346                      ARM::tADDi8 : ARM::tSUBi8);
10347    TmpInst.addOperand(Inst.getOperand(0));
10348    TmpInst.addOperand(Inst.getOperand(5));
10349    TmpInst.addOperand(Inst.getOperand(0));
10350    TmpInst.addOperand(Inst.getOperand(2));
10351    TmpInst.addOperand(Inst.getOperand(3));
10352    TmpInst.addOperand(Inst.getOperand(4));
10353    Inst = TmpInst;
10354    return true;
10355  }
10356  case ARM::t2ADDspImm:
10357  case ARM::t2SUBspImm: {
10358    // Prefer T1 encoding if possible
10359    if (Inst.getOperand(5).getReg() != 0 || HasWideQualifier)
10360      break;
10361    unsigned V = Inst.getOperand(2).getImm();
10362    if (V & 3 || V > ((1 << 7) - 1) << 2)
10363      break;
10364    MCInst TmpInst;
10365    TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDspImm ? ARM::tADDspi
10366                                                          : ARM::tSUBspi);
10367    TmpInst.addOperand(MCOperand::createReg(ARM::SP)); // destination reg
10368    TmpInst.addOperand(MCOperand::createReg(ARM::SP)); // source reg
10369    TmpInst.addOperand(MCOperand::createImm(V / 4));   // immediate
10370    TmpInst.addOperand(Inst.getOperand(3));            // pred
10371    TmpInst.addOperand(Inst.getOperand(4));
10372    Inst = TmpInst;
10373    return true;
10374  }
10375  case ARM::t2ADDrr: {
10376    // If the destination and first source operand are the same, and
10377    // there's no setting of the flags, use encoding T2 instead of T3.
10378    // Note that this is only for ADD, not SUB. This mirrors the system
10379    // 'as' behaviour.  Also take advantage of ADD being commutative.
10380    // Make sure the wide encoding wasn't explicit.
10381    bool Swap = false;
10382    auto DestReg = Inst.getOperand(0).getReg();
10383    bool Transform = DestReg == Inst.getOperand(1).getReg();
10384    if (!Transform && DestReg == Inst.getOperand(2).getReg()) {
10385      Transform = true;
10386      Swap = true;
10387    }
10388    if (!Transform ||
10389        Inst.getOperand(5).getReg() != 0 ||
10390        HasWideQualifier)
10391      break;
10392    MCInst TmpInst;
10393    TmpInst.setOpcode(ARM::tADDhirr);
10394    TmpInst.addOperand(Inst.getOperand(0));
10395    TmpInst.addOperand(Inst.getOperand(0));
10396    TmpInst.addOperand(Inst.getOperand(Swap ? 1 : 2));
10397    TmpInst.addOperand(Inst.getOperand(3));
10398    TmpInst.addOperand(Inst.getOperand(4));
10399    Inst = TmpInst;
10400    return true;
10401  }
10402  case ARM::tADDrSP:
10403    // If the non-SP source operand and the destination operand are not the
10404    // same, we need to use the 32-bit encoding if it's available.
10405    if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
10406      Inst.setOpcode(ARM::t2ADDrr);
10407      Inst.addOperand(MCOperand::createReg(0)); // cc_out
10408      return true;
10409    }
10410    break;
10411  case ARM::tB:
10412    // A Thumb conditional branch outside of an IT block is a tBcc.
10413    if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
10414      Inst.setOpcode(ARM::tBcc);
10415      return true;
10416    }
10417    break;
10418  case ARM::t2B:
10419    // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
10420    if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
10421      Inst.setOpcode(ARM::t2Bcc);
10422      return true;
10423    }
10424    break;
10425  case ARM::t2Bcc:
10426    // If the conditional is AL or we're in an IT block, we really want t2B.
10427    if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
10428      Inst.setOpcode(ARM::t2B);
10429      return true;
10430    }
10431    break;
10432  case ARM::tBcc:
10433    // If the conditional is AL, we really want tB.
10434    if (Inst.getOperand(1).getImm() == ARMCC::AL) {
10435      Inst.setOpcode(ARM::tB);
10436      return true;
10437    }
10438    break;
10439  case ARM::tLDMIA: {
10440    // If the register list contains any high registers, or if the writeback
10441    // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
10442    // instead if we're in Thumb2. Otherwise, this should have generated
10443    // an error in validateInstruction().
10444    unsigned Rn = Inst.getOperand(0).getReg();
10445    bool hasWritebackToken =
10446        (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
10447         static_cast<ARMOperand &>(*Operands[3]).getToken() == "!");
10448    bool listContainsBase;
10449    if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
10450        (!listContainsBase && !hasWritebackToken) ||
10451        (listContainsBase && hasWritebackToken)) {
10452      // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
10453      assert(isThumbTwo());
10454      Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
10455      // If we're switching to the updating version, we need to insert
10456      // the writeback tied operand.
10457      if (hasWritebackToken)
10458        Inst.insert(Inst.begin(),
10459                    MCOperand::createReg(Inst.getOperand(0).getReg()));
10460      return true;
10461    }
10462    break;
10463  }
10464  case ARM::tSTMIA_UPD: {
10465    // If the register list contains any high registers, we need to use
10466    // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
10467    // should have generated an error in validateInstruction().
10468    unsigned Rn = Inst.getOperand(0).getReg();
10469    bool listContainsBase;
10470    if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
10471      // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
10472      assert(isThumbTwo());
10473      Inst.setOpcode(ARM::t2STMIA_UPD);
10474      return true;
10475    }
10476    break;
10477  }
10478  case ARM::tPOP: {
10479    bool listContainsBase;
10480    // If the register list contains any high registers, we need to use
10481    // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
10482    // should have generated an error in validateInstruction().
10483    if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
10484      return false;
10485    assert(isThumbTwo());
10486    Inst.setOpcode(ARM::t2LDMIA_UPD);
10487    // Add the base register and writeback operands.
10488    Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
10489    Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
10490    return true;
10491  }
10492  case ARM::tPUSH: {
10493    bool listContainsBase;
10494    if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
10495      return false;
10496    assert(isThumbTwo());
10497    Inst.setOpcode(ARM::t2STMDB_UPD);
10498    // Add the base register and writeback operands.
10499    Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
10500    Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
10501    return true;
10502  }
10503  case ARM::t2MOVi:
10504    // If we can use the 16-bit encoding and the user didn't explicitly
10505    // request the 32-bit variant, transform it here.
10506    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
10507        (Inst.getOperand(1).isImm() &&
10508         (unsigned)Inst.getOperand(1).getImm() <= 255) &&
10509        Inst.getOperand(4).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
10510        !HasWideQualifier) {
10511      // The operands aren't in the same order for tMOVi8...
10512      MCInst TmpInst;
10513      TmpInst.setOpcode(ARM::tMOVi8);
10514      TmpInst.addOperand(Inst.getOperand(0));
10515      TmpInst.addOperand(Inst.getOperand(4));
10516      TmpInst.addOperand(Inst.getOperand(1));
10517      TmpInst.addOperand(Inst.getOperand(2));
10518      TmpInst.addOperand(Inst.getOperand(3));
10519      Inst = TmpInst;
10520      return true;
10521    }
10522    break;
10523
10524  case ARM::t2MOVr:
10525    // If we can use the 16-bit encoding and the user didn't explicitly
10526    // request the 32-bit variant, transform it here.
10527    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
10528        isARMLowRegister(Inst.getOperand(1).getReg()) &&
10529        Inst.getOperand(2).getImm() == ARMCC::AL &&
10530        Inst.getOperand(4).getReg() == ARM::CPSR &&
10531        !HasWideQualifier) {
10532      // The operands aren't the same for tMOV[S]r... (no cc_out)
10533      MCInst TmpInst;
10534      unsigned Op = Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr;
10535      TmpInst.setOpcode(Op);
10536      TmpInst.addOperand(Inst.getOperand(0));
10537      TmpInst.addOperand(Inst.getOperand(1));
10538      if (Op == ARM::tMOVr) {
10539        TmpInst.addOperand(Inst.getOperand(2));
10540        TmpInst.addOperand(Inst.getOperand(3));
10541      }
10542      Inst = TmpInst;
10543      return true;
10544    }
10545    break;
10546
10547  case ARM::t2SXTH:
10548  case ARM::t2SXTB:
10549  case ARM::t2UXTH:
10550  case ARM::t2UXTB:
10551    // If we can use the 16-bit encoding and the user didn't explicitly
10552    // request the 32-bit variant, transform it here.
10553    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
10554        isARMLowRegister(Inst.getOperand(1).getReg()) &&
10555        Inst.getOperand(2).getImm() == 0 &&
10556        !HasWideQualifier) {
10557      unsigned NewOpc;
10558      switch (Inst.getOpcode()) {
10559      default: llvm_unreachable("Illegal opcode!");
10560      case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
10561      case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
10562      case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
10563      case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
10564      }
10565      // The operands aren't the same for thumb1 (no rotate operand).
10566      MCInst TmpInst;
10567      TmpInst.setOpcode(NewOpc);
10568      TmpInst.addOperand(Inst.getOperand(0));
10569      TmpInst.addOperand(Inst.getOperand(1));
10570      TmpInst.addOperand(Inst.getOperand(3));
10571      TmpInst.addOperand(Inst.getOperand(4));
10572      Inst = TmpInst;
10573      return true;
10574    }
10575    break;
10576
10577  case ARM::MOVsi: {
10578    ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
10579    // rrx shifts and asr/lsr of #32 is encoded as 0
10580    if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr)
10581      return false;
10582    if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
10583      // Shifting by zero is accepted as a vanilla 'MOVr'
10584      MCInst TmpInst;
10585      TmpInst.setOpcode(ARM::MOVr);
10586      TmpInst.addOperand(Inst.getOperand(0));
10587      TmpInst.addOperand(Inst.getOperand(1));
10588      TmpInst.addOperand(Inst.getOperand(3));
10589      TmpInst.addOperand(Inst.getOperand(4));
10590      TmpInst.addOperand(Inst.getOperand(5));
10591      Inst = TmpInst;
10592      return true;
10593    }
10594    return false;
10595  }
10596  case ARM::ANDrsi:
10597  case ARM::ORRrsi:
10598  case ARM::EORrsi:
10599  case ARM::BICrsi:
10600  case ARM::SUBrsi:
10601  case ARM::ADDrsi: {
10602    unsigned newOpc;
10603    ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
10604    if (SOpc == ARM_AM::rrx) return false;
10605    switch (Inst.getOpcode()) {
10606    default: llvm_unreachable("unexpected opcode!");
10607    case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
10608    case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
10609    case ARM::EORrsi: newOpc = ARM::EORrr; break;
10610    case ARM::BICrsi: newOpc = ARM::BICrr; break;
10611    case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
10612    case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
10613    }
10614    // If the shift is by zero, use the non-shifted instruction definition.
10615    // The exception is for right shifts, where 0 == 32
10616    if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
10617        !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) {
10618      MCInst TmpInst;
10619      TmpInst.setOpcode(newOpc);
10620      TmpInst.addOperand(Inst.getOperand(0));
10621      TmpInst.addOperand(Inst.getOperand(1));
10622      TmpInst.addOperand(Inst.getOperand(2));
10623      TmpInst.addOperand(Inst.getOperand(4));
10624      TmpInst.addOperand(Inst.getOperand(5));
10625      TmpInst.addOperand(Inst.getOperand(6));
10626      Inst = TmpInst;
10627      return true;
10628    }
10629    return false;
10630  }
10631  case ARM::ITasm:
10632  case ARM::t2IT: {
10633    // Set up the IT block state according to the IT instruction we just
10634    // matched.
10635    assert(!inITBlock() && "nested IT blocks?!");
10636    startExplicitITBlock(ARMCC::CondCodes(Inst.getOperand(0).getImm()),
10637                         Inst.getOperand(1).getImm());
10638    break;
10639  }
10640  case ARM::t2LSLrr:
10641  case ARM::t2LSRrr:
10642  case ARM::t2ASRrr:
10643  case ARM::t2SBCrr:
10644  case ARM::t2RORrr:
10645  case ARM::t2BICrr:
10646    // Assemblers should use the narrow encodings of these instructions when permissible.
10647    if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
10648         isARMLowRegister(Inst.getOperand(2).getReg())) &&
10649        Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
10650        Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
10651        !HasWideQualifier) {
10652      unsigned NewOpc;
10653      switch (Inst.getOpcode()) {
10654        default: llvm_unreachable("unexpected opcode");
10655        case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;
10656        case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break;
10657        case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break;
10658        case ARM::t2SBCrr: NewOpc = ARM::tSBC; break;
10659        case ARM::t2RORrr: NewOpc = ARM::tROR; break;
10660        case ARM::t2BICrr: NewOpc = ARM::tBIC; break;
10661      }
10662      MCInst TmpInst;
10663      TmpInst.setOpcode(NewOpc);
10664      TmpInst.addOperand(Inst.getOperand(0));
10665      TmpInst.addOperand(Inst.getOperand(5));
10666      TmpInst.addOperand(Inst.getOperand(1));
10667      TmpInst.addOperand(Inst.getOperand(2));
10668      TmpInst.addOperand(Inst.getOperand(3));
10669      TmpInst.addOperand(Inst.getOperand(4));
10670      Inst = TmpInst;
10671      return true;
10672    }
10673    return false;
10674
10675  case ARM::t2ANDrr:
10676  case ARM::t2EORrr:
10677  case ARM::t2ADCrr:
10678  case ARM::t2ORRrr:
10679    // Assemblers should use the narrow encodings of these instructions when permissible.
10680    // These instructions are special in that they are commutable, so shorter encodings
10681    // are available more often.
10682    if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
10683         isARMLowRegister(Inst.getOperand(2).getReg())) &&
10684        (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
10685         Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
10686        Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
10687        !HasWideQualifier) {
10688      unsigned NewOpc;
10689      switch (Inst.getOpcode()) {
10690        default: llvm_unreachable("unexpected opcode");
10691        case ARM::t2ADCrr: NewOpc = ARM::tADC; break;
10692        case ARM::t2ANDrr: NewOpc = ARM::tAND; break;
10693        case ARM::t2EORrr: NewOpc = ARM::tEOR; break;
10694        case ARM::t2ORRrr: NewOpc = ARM::tORR; break;
10695      }
10696      MCInst TmpInst;
10697      TmpInst.setOpcode(NewOpc);
10698      TmpInst.addOperand(Inst.getOperand(0));
10699      TmpInst.addOperand(Inst.getOperand(5));
10700      if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
10701        TmpInst.addOperand(Inst.getOperand(1));
10702        TmpInst.addOperand(Inst.getOperand(2));
10703      } else {
10704        TmpInst.addOperand(Inst.getOperand(2));
10705        TmpInst.addOperand(Inst.getOperand(1));
10706      }
10707      TmpInst.addOperand(Inst.getOperand(3));
10708      TmpInst.addOperand(Inst.getOperand(4));
10709      Inst = TmpInst;
10710      return true;
10711    }
10712    return false;
10713  case ARM::MVE_VPST:
10714  case ARM::MVE_VPTv16i8:
10715  case ARM::MVE_VPTv8i16:
10716  case ARM::MVE_VPTv4i32:
10717  case ARM::MVE_VPTv16u8:
10718  case ARM::MVE_VPTv8u16:
10719  case ARM::MVE_VPTv4u32:
10720  case ARM::MVE_VPTv16s8:
10721  case ARM::MVE_VPTv8s16:
10722  case ARM::MVE_VPTv4s32:
10723  case ARM::MVE_VPTv4f32:
10724  case ARM::MVE_VPTv8f16:
10725  case ARM::MVE_VPTv16i8r:
10726  case ARM::MVE_VPTv8i16r:
10727  case ARM::MVE_VPTv4i32r:
10728  case ARM::MVE_VPTv16u8r:
10729  case ARM::MVE_VPTv8u16r:
10730  case ARM::MVE_VPTv4u32r:
10731  case ARM::MVE_VPTv16s8r:
10732  case ARM::MVE_VPTv8s16r:
10733  case ARM::MVE_VPTv4s32r:
10734  case ARM::MVE_VPTv4f32r:
10735  case ARM::MVE_VPTv8f16r: {
10736    assert(!inVPTBlock() && "Nested VPT blocks are not allowed");
10737    MCOperand &MO = Inst.getOperand(0);
10738    VPTState.Mask = MO.getImm();
10739    VPTState.CurPosition = 0;
10740    break;
10741  }
10742  }
10743  return false;
10744}
10745
10746unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
10747  // 16-bit thumb arithmetic instructions either require or preclude the 'S'
10748  // suffix depending on whether they're in an IT block or not.
10749  unsigned Opc = Inst.getOpcode();
10750  const MCInstrDesc &MCID = MII.get(Opc);
10751  if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
10752    assert(MCID.hasOptionalDef() &&
10753           "optionally flag setting instruction missing optional def operand");
10754    assert(MCID.NumOperands == Inst.getNumOperands() &&
10755           "operand count mismatch!");
10756    // Find the optional-def operand (cc_out).
10757    unsigned OpNo;
10758    for (OpNo = 0;
10759         !MCID.operands()[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
10760         ++OpNo)
10761      ;
10762    // If we're parsing Thumb1, reject it completely.
10763    if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
10764      return Match_RequiresFlagSetting;
10765    // If we're parsing Thumb2, which form is legal depends on whether we're
10766    // in an IT block.
10767    if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
10768        !inITBlock())
10769      return Match_RequiresITBlock;
10770    if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
10771        inITBlock())
10772      return Match_RequiresNotITBlock;
10773    // LSL with zero immediate is not allowed in an IT block
10774    if (Opc == ARM::tLSLri && Inst.getOperand(3).getImm() == 0 && inITBlock())
10775      return Match_RequiresNotITBlock;
10776  } else if (isThumbOne()) {
10777    // Some high-register supporting Thumb1 encodings only allow both registers
10778    // to be from r0-r7 when in Thumb2.
10779    if (Opc == ARM::tADDhirr && !hasV6MOps() &&
10780        isARMLowRegister(Inst.getOperand(1).getReg()) &&
10781        isARMLowRegister(Inst.getOperand(2).getReg()))
10782      return Match_RequiresThumb2;
10783    // Others only require ARMv6 or later.
10784    else if (Opc == ARM::tMOVr && !hasV6Ops() &&
10785             isARMLowRegister(Inst.getOperand(0).getReg()) &&
10786             isARMLowRegister(Inst.getOperand(1).getReg()))
10787      return Match_RequiresV6;
10788  }
10789
10790  // Before ARMv8 the rules for when SP is allowed in t2MOVr are more complex
10791  // than the loop below can handle, so it uses the GPRnopc register class and
10792  // we do SP handling here.
10793  if (Opc == ARM::t2MOVr && !hasV8Ops())
10794  {
10795    // SP as both source and destination is not allowed
10796    if (Inst.getOperand(0).getReg() == ARM::SP &&
10797        Inst.getOperand(1).getReg() == ARM::SP)
10798      return Match_RequiresV8;
10799    // When flags-setting SP as either source or destination is not allowed
10800    if (Inst.getOperand(4).getReg() == ARM::CPSR &&
10801        (Inst.getOperand(0).getReg() == ARM::SP ||
10802         Inst.getOperand(1).getReg() == ARM::SP))
10803      return Match_RequiresV8;
10804  }
10805
10806  switch (Inst.getOpcode()) {
10807  case ARM::VMRS:
10808  case ARM::VMSR:
10809  case ARM::VMRS_FPCXTS:
10810  case ARM::VMRS_FPCXTNS:
10811  case ARM::VMSR_FPCXTS:
10812  case ARM::VMSR_FPCXTNS:
10813  case ARM::VMRS_FPSCR_NZCVQC:
10814  case ARM::VMSR_FPSCR_NZCVQC:
10815  case ARM::FMSTAT:
10816  case ARM::VMRS_VPR:
10817  case ARM::VMRS_P0:
10818  case ARM::VMSR_VPR:
10819  case ARM::VMSR_P0:
10820    // Use of SP for VMRS/VMSR is only allowed in ARM mode with the exception of
10821    // ARMv8-A.
10822    if (Inst.getOperand(0).isReg() && Inst.getOperand(0).getReg() == ARM::SP &&
10823        (isThumb() && !hasV8Ops()))
10824      return Match_InvalidOperand;
10825    break;
10826  case ARM::t2TBB:
10827  case ARM::t2TBH:
10828    // Rn = sp is only allowed with ARMv8-A
10829    if (!hasV8Ops() && (Inst.getOperand(0).getReg() == ARM::SP))
10830      return Match_RequiresV8;
10831    break;
10832  default:
10833    break;
10834  }
10835
10836  for (unsigned I = 0; I < MCID.NumOperands; ++I)
10837    if (MCID.operands()[I].RegClass == ARM::rGPRRegClassID) {
10838      // rGPRRegClass excludes PC, and also excluded SP before ARMv8
10839      const auto &Op = Inst.getOperand(I);
10840      if (!Op.isReg()) {
10841        // This can happen in awkward cases with tied operands, e.g. a
10842        // writeback load/store with a complex addressing mode in
10843        // which there's an output operand corresponding to the
10844        // updated written-back base register: the Tablegen-generated
10845        // AsmMatcher will have written a placeholder operand to that
10846        // slot in the form of an immediate 0, because it can't
10847        // generate the register part of the complex addressing-mode
10848        // operand ahead of time.
10849        continue;
10850      }
10851
10852      unsigned Reg = Op.getReg();
10853      if ((Reg == ARM::SP) && !hasV8Ops())
10854        return Match_RequiresV8;
10855      else if (Reg == ARM::PC)
10856        return Match_InvalidOperand;
10857    }
10858
10859  return Match_Success;
10860}
10861
10862namespace llvm {
10863
10864template <> inline bool IsCPSRDead<MCInst>(const MCInst *Instr) {
10865  return true; // In an assembly source, no need to second-guess
10866}
10867
10868} // end namespace llvm
10869
10870// Returns true if Inst is unpredictable if it is in and IT block, but is not
10871// the last instruction in the block.
10872bool ARMAsmParser::isITBlockTerminator(MCInst &Inst) const {
10873  const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
10874
10875  // All branch & call instructions terminate IT blocks with the exception of
10876  // SVC.
10877  if (MCID.isTerminator() || (MCID.isCall() && Inst.getOpcode() != ARM::tSVC) ||
10878      MCID.isReturn() || MCID.isBranch() || MCID.isIndirectBranch())
10879    return true;
10880
10881  // Any arithmetic instruction which writes to the PC also terminates the IT
10882  // block.
10883  if (MCID.hasDefOfPhysReg(Inst, ARM::PC, *MRI))
10884    return true;
10885
10886  return false;
10887}
10888
10889unsigned ARMAsmParser::MatchInstruction(OperandVector &Operands, MCInst &Inst,
10890                                          SmallVectorImpl<NearMissInfo> &NearMisses,
10891                                          bool MatchingInlineAsm,
10892                                          bool &EmitInITBlock,
10893                                          MCStreamer &Out) {
10894  // If we can't use an implicit IT block here, just match as normal.
10895  if (inExplicitITBlock() || !isThumbTwo() || !useImplicitITThumb())
10896    return MatchInstructionImpl(Operands, Inst, &NearMisses, MatchingInlineAsm);
10897
10898  // Try to match the instruction in an extension of the current IT block (if
10899  // there is one).
10900  if (inImplicitITBlock()) {
10901    extendImplicitITBlock(ITState.Cond);
10902    if (MatchInstructionImpl(Operands, Inst, nullptr, MatchingInlineAsm) ==
10903            Match_Success) {
10904      // The match succeded, but we still have to check that the instruction is
10905      // valid in this implicit IT block.
10906      const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
10907      if (MCID.isPredicable()) {
10908        ARMCC::CondCodes InstCond =
10909            (ARMCC::CondCodes)Inst.getOperand(MCID.findFirstPredOperandIdx())
10910                .getImm();
10911        ARMCC::CondCodes ITCond = currentITCond();
10912        if (InstCond == ITCond) {
10913          EmitInITBlock = true;
10914          return Match_Success;
10915        } else if (InstCond == ARMCC::getOppositeCondition(ITCond)) {
10916          invertCurrentITCondition();
10917          EmitInITBlock = true;
10918          return Match_Success;
10919        }
10920      }
10921    }
10922    rewindImplicitITPosition();
10923  }
10924
10925  // Finish the current IT block, and try to match outside any IT block.
10926  flushPendingInstructions(Out);
10927  unsigned PlainMatchResult =
10928      MatchInstructionImpl(Operands, Inst, &NearMisses, MatchingInlineAsm);
10929  if (PlainMatchResult == Match_Success) {
10930    const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
10931    if (MCID.isPredicable()) {
10932      ARMCC::CondCodes InstCond =
10933          (ARMCC::CondCodes)Inst.getOperand(MCID.findFirstPredOperandIdx())
10934              .getImm();
10935      // Some forms of the branch instruction have their own condition code
10936      // fields, so can be conditionally executed without an IT block.
10937      if (Inst.getOpcode() == ARM::tBcc || Inst.getOpcode() == ARM::t2Bcc) {
10938        EmitInITBlock = false;
10939        return Match_Success;
10940      }
10941      if (InstCond == ARMCC::AL) {
10942        EmitInITBlock = false;
10943        return Match_Success;
10944      }
10945    } else {
10946      EmitInITBlock = false;
10947      return Match_Success;
10948    }
10949  }
10950
10951  // Try to match in a new IT block. The matcher doesn't check the actual
10952  // condition, so we create an IT block with a dummy condition, and fix it up
10953  // once we know the actual condition.
10954  startImplicitITBlock();
10955  if (MatchInstructionImpl(Operands, Inst, nullptr, MatchingInlineAsm) ==
10956      Match_Success) {
10957    const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
10958    if (MCID.isPredicable()) {
10959      ITState.Cond =
10960          (ARMCC::CondCodes)Inst.getOperand(MCID.findFirstPredOperandIdx())
10961              .getImm();
10962      EmitInITBlock = true;
10963      return Match_Success;
10964    }
10965  }
10966  discardImplicitITBlock();
10967
10968  // If none of these succeed, return the error we got when trying to match
10969  // outside any IT blocks.
10970  EmitInITBlock = false;
10971  return PlainMatchResult;
10972}
10973
10974static std::string ARMMnemonicSpellCheck(StringRef S, const FeatureBitset &FBS,
10975                                         unsigned VariantID = 0);
10976
10977static const char *getSubtargetFeatureName(uint64_t Val);
10978bool ARMAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
10979                                           OperandVector &Operands,
10980                                           MCStreamer &Out, uint64_t &ErrorInfo,
10981                                           bool MatchingInlineAsm) {
10982  MCInst Inst;
10983  unsigned MatchResult;
10984  bool PendConditionalInstruction = false;
10985
10986  SmallVector<NearMissInfo, 4> NearMisses;
10987  MatchResult = MatchInstruction(Operands, Inst, NearMisses, MatchingInlineAsm,
10988                                 PendConditionalInstruction, Out);
10989
10990  switch (MatchResult) {
10991  case Match_Success:
10992    LLVM_DEBUG(dbgs() << "Parsed as: ";
10993               Inst.dump_pretty(dbgs(), MII.getName(Inst.getOpcode()));
10994               dbgs() << "\n");
10995
10996    // Context sensitive operand constraints aren't handled by the matcher,
10997    // so check them here.
10998    if (validateInstruction(Inst, Operands)) {
10999      // Still progress the IT block, otherwise one wrong condition causes
11000      // nasty cascading errors.
11001      forwardITPosition();
11002      forwardVPTPosition();
11003      return true;
11004    }
11005
11006    {
11007      // Some instructions need post-processing to, for example, tweak which
11008      // encoding is selected. Loop on it while changes happen so the
11009      // individual transformations can chain off each other. E.g.,
11010      // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
11011      while (processInstruction(Inst, Operands, Out))
11012        LLVM_DEBUG(dbgs() << "Changed to: ";
11013                   Inst.dump_pretty(dbgs(), MII.getName(Inst.getOpcode()));
11014                   dbgs() << "\n");
11015    }
11016
11017    // Only move forward at the very end so that everything in validate
11018    // and process gets a consistent answer about whether we're in an IT
11019    // block.
11020    forwardITPosition();
11021    forwardVPTPosition();
11022
11023    // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
11024    // doesn't actually encode.
11025    if (Inst.getOpcode() == ARM::ITasm)
11026      return false;
11027
11028    Inst.setLoc(IDLoc);
11029    if (PendConditionalInstruction) {
11030      PendingConditionalInsts.push_back(Inst);
11031      if (isITBlockFull() || isITBlockTerminator(Inst))
11032        flushPendingInstructions(Out);
11033    } else {
11034      Out.emitInstruction(Inst, getSTI());
11035    }
11036    return false;
11037  case Match_NearMisses:
11038    ReportNearMisses(NearMisses, IDLoc, Operands);
11039    return true;
11040  case Match_MnemonicFail: {
11041    FeatureBitset FBS = ComputeAvailableFeatures(getSTI().getFeatureBits());
11042    std::string Suggestion = ARMMnemonicSpellCheck(
11043      ((ARMOperand &)*Operands[0]).getToken(), FBS);
11044    return Error(IDLoc, "invalid instruction" + Suggestion,
11045                 ((ARMOperand &)*Operands[0]).getLocRange());
11046  }
11047  }
11048
11049  llvm_unreachable("Implement any new match types added!");
11050}
11051
11052/// parseDirective parses the arm specific directives
11053bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
11054  const MCContext::Environment Format = getContext().getObjectFileType();
11055  bool IsMachO = Format == MCContext::IsMachO;
11056  bool IsCOFF = Format == MCContext::IsCOFF;
11057
11058  std::string IDVal = DirectiveID.getIdentifier().lower();
11059  if (IDVal == ".word")
11060    parseLiteralValues(4, DirectiveID.getLoc());
11061  else if (IDVal == ".short" || IDVal == ".hword")
11062    parseLiteralValues(2, DirectiveID.getLoc());
11063  else if (IDVal == ".thumb")
11064    parseDirectiveThumb(DirectiveID.getLoc());
11065  else if (IDVal == ".arm")
11066    parseDirectiveARM(DirectiveID.getLoc());
11067  else if (IDVal == ".thumb_func")
11068    parseDirectiveThumbFunc(DirectiveID.getLoc());
11069  else if (IDVal == ".code")
11070    parseDirectiveCode(DirectiveID.getLoc());
11071  else if (IDVal == ".syntax")
11072    parseDirectiveSyntax(DirectiveID.getLoc());
11073  else if (IDVal == ".unreq")
11074    parseDirectiveUnreq(DirectiveID.getLoc());
11075  else if (IDVal == ".fnend")
11076    parseDirectiveFnEnd(DirectiveID.getLoc());
11077  else if (IDVal == ".cantunwind")
11078    parseDirectiveCantUnwind(DirectiveID.getLoc());
11079  else if (IDVal == ".personality")
11080    parseDirectivePersonality(DirectiveID.getLoc());
11081  else if (IDVal == ".handlerdata")
11082    parseDirectiveHandlerData(DirectiveID.getLoc());
11083  else if (IDVal == ".setfp")
11084    parseDirectiveSetFP(DirectiveID.getLoc());
11085  else if (IDVal == ".pad")
11086    parseDirectivePad(DirectiveID.getLoc());
11087  else if (IDVal == ".save")
11088    parseDirectiveRegSave(DirectiveID.getLoc(), false);
11089  else if (IDVal == ".vsave")
11090    parseDirectiveRegSave(DirectiveID.getLoc(), true);
11091  else if (IDVal == ".ltorg" || IDVal == ".pool")
11092    parseDirectiveLtorg(DirectiveID.getLoc());
11093  else if (IDVal == ".even")
11094    parseDirectiveEven(DirectiveID.getLoc());
11095  else if (IDVal == ".personalityindex")
11096    parseDirectivePersonalityIndex(DirectiveID.getLoc());
11097  else if (IDVal == ".unwind_raw")
11098    parseDirectiveUnwindRaw(DirectiveID.getLoc());
11099  else if (IDVal == ".movsp")
11100    parseDirectiveMovSP(DirectiveID.getLoc());
11101  else if (IDVal == ".arch_extension")
11102    parseDirectiveArchExtension(DirectiveID.getLoc());
11103  else if (IDVal == ".align")
11104    return parseDirectiveAlign(DirectiveID.getLoc()); // Use Generic on failure.
11105  else if (IDVal == ".thumb_set")
11106    parseDirectiveThumbSet(DirectiveID.getLoc());
11107  else if (IDVal == ".inst")
11108    parseDirectiveInst(DirectiveID.getLoc());
11109  else if (IDVal == ".inst.n")
11110    parseDirectiveInst(DirectiveID.getLoc(), 'n');
11111  else if (IDVal == ".inst.w")
11112    parseDirectiveInst(DirectiveID.getLoc(), 'w');
11113  else if (!IsMachO && !IsCOFF) {
11114    if (IDVal == ".arch")
11115      parseDirectiveArch(DirectiveID.getLoc());
11116    else if (IDVal == ".cpu")
11117      parseDirectiveCPU(DirectiveID.getLoc());
11118    else if (IDVal == ".eabi_attribute")
11119      parseDirectiveEabiAttr(DirectiveID.getLoc());
11120    else if (IDVal == ".fpu")
11121      parseDirectiveFPU(DirectiveID.getLoc());
11122    else if (IDVal == ".fnstart")
11123      parseDirectiveFnStart(DirectiveID.getLoc());
11124    else if (IDVal == ".object_arch")
11125      parseDirectiveObjectArch(DirectiveID.getLoc());
11126    else if (IDVal == ".tlsdescseq")
11127      parseDirectiveTLSDescSeq(DirectiveID.getLoc());
11128    else
11129      return true;
11130  } else if (IsCOFF) {
11131    if (IDVal == ".seh_stackalloc")
11132      parseDirectiveSEHAllocStack(DirectiveID.getLoc(), /*Wide=*/false);
11133    else if (IDVal == ".seh_stackalloc_w")
11134      parseDirectiveSEHAllocStack(DirectiveID.getLoc(), /*Wide=*/true);
11135    else if (IDVal == ".seh_save_regs")
11136      parseDirectiveSEHSaveRegs(DirectiveID.getLoc(), /*Wide=*/false);
11137    else if (IDVal == ".seh_save_regs_w")
11138      parseDirectiveSEHSaveRegs(DirectiveID.getLoc(), /*Wide=*/true);
11139    else if (IDVal == ".seh_save_sp")
11140      parseDirectiveSEHSaveSP(DirectiveID.getLoc());
11141    else if (IDVal == ".seh_save_fregs")
11142      parseDirectiveSEHSaveFRegs(DirectiveID.getLoc());
11143    else if (IDVal == ".seh_save_lr")
11144      parseDirectiveSEHSaveLR(DirectiveID.getLoc());
11145    else if (IDVal == ".seh_endprologue")
11146      parseDirectiveSEHPrologEnd(DirectiveID.getLoc(), /*Fragment=*/false);
11147    else if (IDVal == ".seh_endprologue_fragment")
11148      parseDirectiveSEHPrologEnd(DirectiveID.getLoc(), /*Fragment=*/true);
11149    else if (IDVal == ".seh_nop")
11150      parseDirectiveSEHNop(DirectiveID.getLoc(), /*Wide=*/false);
11151    else if (IDVal == ".seh_nop_w")
11152      parseDirectiveSEHNop(DirectiveID.getLoc(), /*Wide=*/true);
11153    else if (IDVal == ".seh_startepilogue")
11154      parseDirectiveSEHEpilogStart(DirectiveID.getLoc(), /*Condition=*/false);
11155    else if (IDVal == ".seh_startepilogue_cond")
11156      parseDirectiveSEHEpilogStart(DirectiveID.getLoc(), /*Condition=*/true);
11157    else if (IDVal == ".seh_endepilogue")
11158      parseDirectiveSEHEpilogEnd(DirectiveID.getLoc());
11159    else if (IDVal == ".seh_custom")
11160      parseDirectiveSEHCustom(DirectiveID.getLoc());
11161    else
11162      return true;
11163  } else
11164    return true;
11165  return false;
11166}
11167
11168/// parseLiteralValues
11169///  ::= .hword expression [, expression]*
11170///  ::= .short expression [, expression]*
11171///  ::= .word expression [, expression]*
11172bool ARMAsmParser::parseLiteralValues(unsigned Size, SMLoc L) {
11173  auto parseOne = [&]() -> bool {
11174    const MCExpr *Value;
11175    if (getParser().parseExpression(Value))
11176      return true;
11177    getParser().getStreamer().emitValue(Value, Size, L);
11178    return false;
11179  };
11180  return (parseMany(parseOne));
11181}
11182
11183/// parseDirectiveThumb
11184///  ::= .thumb
11185bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
11186  if (parseEOL() || check(!hasThumb(), L, "target does not support Thumb mode"))
11187    return true;
11188
11189  if (!isThumb())
11190    SwitchMode();
11191
11192  getParser().getStreamer().emitAssemblerFlag(MCAF_Code16);
11193  return false;
11194}
11195
11196/// parseDirectiveARM
11197///  ::= .arm
11198bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
11199  if (parseEOL() || check(!hasARM(), L, "target does not support ARM mode"))
11200    return true;
11201
11202  if (isThumb())
11203    SwitchMode();
11204  getParser().getStreamer().emitAssemblerFlag(MCAF_Code32);
11205  return false;
11206}
11207
11208void ARMAsmParser::doBeforeLabelEmit(MCSymbol *Symbol, SMLoc IDLoc) {
11209  // We need to flush the current implicit IT block on a label, because it is
11210  // not legal to branch into an IT block.
11211  flushPendingInstructions(getStreamer());
11212}
11213
11214void ARMAsmParser::onLabelParsed(MCSymbol *Symbol) {
11215  if (NextSymbolIsThumb) {
11216    getParser().getStreamer().emitThumbFunc(Symbol);
11217    NextSymbolIsThumb = false;
11218  }
11219}
11220
11221/// parseDirectiveThumbFunc
11222///  ::= .thumbfunc symbol_name
11223bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
11224  MCAsmParser &Parser = getParser();
11225  const auto Format = getContext().getObjectFileType();
11226  bool IsMachO = Format == MCContext::IsMachO;
11227
11228  // Darwin asm has (optionally) function name after .thumb_func direction
11229  // ELF doesn't
11230
11231  if (IsMachO) {
11232    if (Parser.getTok().is(AsmToken::Identifier) ||
11233        Parser.getTok().is(AsmToken::String)) {
11234      MCSymbol *Func = getParser().getContext().getOrCreateSymbol(
11235          Parser.getTok().getIdentifier());
11236      getParser().getStreamer().emitThumbFunc(Func);
11237      Parser.Lex();
11238      if (parseEOL())
11239        return true;
11240      return false;
11241    }
11242  }
11243
11244  if (parseEOL())
11245    return true;
11246
11247  // .thumb_func implies .thumb
11248  if (!isThumb())
11249    SwitchMode();
11250
11251  getParser().getStreamer().emitAssemblerFlag(MCAF_Code16);
11252
11253  NextSymbolIsThumb = true;
11254  return false;
11255}
11256
11257/// parseDirectiveSyntax
11258///  ::= .syntax unified | divided
11259bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
11260  MCAsmParser &Parser = getParser();
11261  const AsmToken &Tok = Parser.getTok();
11262  if (Tok.isNot(AsmToken::Identifier)) {
11263    Error(L, "unexpected token in .syntax directive");
11264    return false;
11265  }
11266
11267  StringRef Mode = Tok.getString();
11268  Parser.Lex();
11269  if (check(Mode == "divided" || Mode == "DIVIDED", L,
11270            "'.syntax divided' arm assembly not supported") ||
11271      check(Mode != "unified" && Mode != "UNIFIED", L,
11272            "unrecognized syntax mode in .syntax directive") ||
11273      parseEOL())
11274    return true;
11275
11276  // TODO tell the MC streamer the mode
11277  // getParser().getStreamer().Emit???();
11278  return false;
11279}
11280
11281/// parseDirectiveCode
11282///  ::= .code 16 | 32
11283bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
11284  MCAsmParser &Parser = getParser();
11285  const AsmToken &Tok = Parser.getTok();
11286  if (Tok.isNot(AsmToken::Integer))
11287    return Error(L, "unexpected token in .code directive");
11288  int64_t Val = Parser.getTok().getIntVal();
11289  if (Val != 16 && Val != 32) {
11290    Error(L, "invalid operand to .code directive");
11291    return false;
11292  }
11293  Parser.Lex();
11294
11295  if (parseEOL())
11296    return true;
11297
11298  if (Val == 16) {
11299    if (!hasThumb())
11300      return Error(L, "target does not support Thumb mode");
11301
11302    if (!isThumb())
11303      SwitchMode();
11304    getParser().getStreamer().emitAssemblerFlag(MCAF_Code16);
11305  } else {
11306    if (!hasARM())
11307      return Error(L, "target does not support ARM mode");
11308
11309    if (isThumb())
11310      SwitchMode();
11311    getParser().getStreamer().emitAssemblerFlag(MCAF_Code32);
11312  }
11313
11314  return false;
11315}
11316
11317/// parseDirectiveReq
11318///  ::= name .req registername
11319bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
11320  MCAsmParser &Parser = getParser();
11321  Parser.Lex(); // Eat the '.req' token.
11322  MCRegister Reg;
11323  SMLoc SRegLoc, ERegLoc;
11324  if (check(parseRegister(Reg, SRegLoc, ERegLoc), SRegLoc,
11325            "register name expected") ||
11326      parseEOL())
11327    return true;
11328
11329  if (RegisterReqs.insert(std::make_pair(Name, Reg)).first->second != Reg)
11330    return Error(SRegLoc,
11331                 "redefinition of '" + Name + "' does not match original.");
11332
11333  return false;
11334}
11335
11336/// parseDirectiveUneq
11337///  ::= .unreq registername
11338bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) {
11339  MCAsmParser &Parser = getParser();
11340  if (Parser.getTok().isNot(AsmToken::Identifier))
11341    return Error(L, "unexpected input in .unreq directive.");
11342  RegisterReqs.erase(Parser.getTok().getIdentifier().lower());
11343  Parser.Lex(); // Eat the identifier.
11344  return parseEOL();
11345}
11346
11347// After changing arch/CPU, try to put the ARM/Thumb mode back to what it was
11348// before, if supported by the new target, or emit mapping symbols for the mode
11349// switch.
11350void ARMAsmParser::FixModeAfterArchChange(bool WasThumb, SMLoc Loc) {
11351  if (WasThumb != isThumb()) {
11352    if (WasThumb && hasThumb()) {
11353      // Stay in Thumb mode
11354      SwitchMode();
11355    } else if (!WasThumb && hasARM()) {
11356      // Stay in ARM mode
11357      SwitchMode();
11358    } else {
11359      // Mode switch forced, because the new arch doesn't support the old mode.
11360      getParser().getStreamer().emitAssemblerFlag(isThumb() ? MCAF_Code16
11361                                                            : MCAF_Code32);
11362      // Warn about the implcit mode switch. GAS does not switch modes here,
11363      // but instead stays in the old mode, reporting an error on any following
11364      // instructions as the mode does not exist on the target.
11365      Warning(Loc, Twine("new target does not support ") +
11366                       (WasThumb ? "thumb" : "arm") + " mode, switching to " +
11367                       (!WasThumb ? "thumb" : "arm") + " mode");
11368    }
11369  }
11370}
11371
11372/// parseDirectiveArch
11373///  ::= .arch token
11374bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
11375  StringRef Arch = getParser().parseStringToEndOfStatement().trim();
11376  ARM::ArchKind ID = ARM::parseArch(Arch);
11377
11378  if (ID == ARM::ArchKind::INVALID)
11379    return Error(L, "Unknown arch name");
11380
11381  bool WasThumb = isThumb();
11382  Triple T;
11383  MCSubtargetInfo &STI = copySTI();
11384  STI.setDefaultFeatures("", /*TuneCPU*/ "",
11385                         ("+" + ARM::getArchName(ID)).str());
11386  setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
11387  FixModeAfterArchChange(WasThumb, L);
11388
11389  getTargetStreamer().emitArch(ID);
11390  return false;
11391}
11392
11393/// parseDirectiveEabiAttr
11394///  ::= .eabi_attribute int, int [, "str"]
11395///  ::= .eabi_attribute Tag_name, int [, "str"]
11396bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) {
11397  MCAsmParser &Parser = getParser();
11398  int64_t Tag;
11399  SMLoc TagLoc;
11400  TagLoc = Parser.getTok().getLoc();
11401  if (Parser.getTok().is(AsmToken::Identifier)) {
11402    StringRef Name = Parser.getTok().getIdentifier();
11403    std::optional<unsigned> Ret = ELFAttrs::attrTypeFromString(
11404        Name, ARMBuildAttrs::getARMAttributeTags());
11405    if (!Ret) {
11406      Error(TagLoc, "attribute name not recognised: " + Name);
11407      return false;
11408    }
11409    Tag = *Ret;
11410    Parser.Lex();
11411  } else {
11412    const MCExpr *AttrExpr;
11413
11414    TagLoc = Parser.getTok().getLoc();
11415    if (Parser.parseExpression(AttrExpr))
11416      return true;
11417
11418    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(AttrExpr);
11419    if (check(!CE, TagLoc, "expected numeric constant"))
11420      return true;
11421
11422    Tag = CE->getValue();
11423  }
11424
11425  if (Parser.parseToken(AsmToken::Comma, "comma expected"))
11426    return true;
11427
11428  StringRef StringValue = "";
11429  bool IsStringValue = false;
11430
11431  int64_t IntegerValue = 0;
11432  bool IsIntegerValue = false;
11433
11434  if (Tag == ARMBuildAttrs::CPU_raw_name || Tag == ARMBuildAttrs::CPU_name)
11435    IsStringValue = true;
11436  else if (Tag == ARMBuildAttrs::compatibility) {
11437    IsStringValue = true;
11438    IsIntegerValue = true;
11439  } else if (Tag < 32 || Tag % 2 == 0)
11440    IsIntegerValue = true;
11441  else if (Tag % 2 == 1)
11442    IsStringValue = true;
11443  else
11444    llvm_unreachable("invalid tag type");
11445
11446  if (IsIntegerValue) {
11447    const MCExpr *ValueExpr;
11448    SMLoc ValueExprLoc = Parser.getTok().getLoc();
11449    if (Parser.parseExpression(ValueExpr))
11450      return true;
11451
11452    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ValueExpr);
11453    if (!CE)
11454      return Error(ValueExprLoc, "expected numeric constant");
11455    IntegerValue = CE->getValue();
11456  }
11457
11458  if (Tag == ARMBuildAttrs::compatibility) {
11459    if (Parser.parseToken(AsmToken::Comma, "comma expected"))
11460      return true;
11461  }
11462
11463  std::string EscapedValue;
11464  if (IsStringValue) {
11465    if (Parser.getTok().isNot(AsmToken::String))
11466      return Error(Parser.getTok().getLoc(), "bad string constant");
11467
11468    if (Tag == ARMBuildAttrs::also_compatible_with) {
11469      if (Parser.parseEscapedString(EscapedValue))
11470        return Error(Parser.getTok().getLoc(), "bad escaped string constant");
11471
11472      StringValue = EscapedValue;
11473    } else {
11474      StringValue = Parser.getTok().getStringContents();
11475      Parser.Lex();
11476    }
11477  }
11478
11479  if (Parser.parseEOL())
11480    return true;
11481
11482  if (IsIntegerValue && IsStringValue) {
11483    assert(Tag == ARMBuildAttrs::compatibility);
11484    getTargetStreamer().emitIntTextAttribute(Tag, IntegerValue, StringValue);
11485  } else if (IsIntegerValue)
11486    getTargetStreamer().emitAttribute(Tag, IntegerValue);
11487  else if (IsStringValue)
11488    getTargetStreamer().emitTextAttribute(Tag, StringValue);
11489  return false;
11490}
11491
11492/// parseDirectiveCPU
11493///  ::= .cpu str
11494bool ARMAsmParser::parseDirectiveCPU(SMLoc L) {
11495  StringRef CPU = getParser().parseStringToEndOfStatement().trim();
11496  getTargetStreamer().emitTextAttribute(ARMBuildAttrs::CPU_name, CPU);
11497
11498  // FIXME: This is using table-gen data, but should be moved to
11499  // ARMTargetParser once that is table-gen'd.
11500  if (!getSTI().isCPUStringValid(CPU))
11501    return Error(L, "Unknown CPU name");
11502
11503  bool WasThumb = isThumb();
11504  MCSubtargetInfo &STI = copySTI();
11505  STI.setDefaultFeatures(CPU, /*TuneCPU*/ CPU, "");
11506  setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
11507  FixModeAfterArchChange(WasThumb, L);
11508
11509  return false;
11510}
11511
11512/// parseDirectiveFPU
11513///  ::= .fpu str
11514bool ARMAsmParser::parseDirectiveFPU(SMLoc L) {
11515  SMLoc FPUNameLoc = getTok().getLoc();
11516  StringRef FPU = getParser().parseStringToEndOfStatement().trim();
11517
11518  unsigned ID = ARM::parseFPU(FPU);
11519  std::vector<StringRef> Features;
11520  if (!ARM::getFPUFeatures(ID, Features))
11521    return Error(FPUNameLoc, "Unknown FPU name");
11522
11523  MCSubtargetInfo &STI = copySTI();
11524  for (auto Feature : Features)
11525    STI.ApplyFeatureFlag(Feature);
11526  setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
11527
11528  getTargetStreamer().emitFPU(ID);
11529  return false;
11530}
11531
11532/// parseDirectiveFnStart
11533///  ::= .fnstart
11534bool ARMAsmParser::parseDirectiveFnStart(SMLoc L) {
11535  if (parseEOL())
11536    return true;
11537
11538  if (UC.hasFnStart()) {
11539    Error(L, ".fnstart starts before the end of previous one");
11540    UC.emitFnStartLocNotes();
11541    return true;
11542  }
11543
11544  // Reset the unwind directives parser state
11545  UC.reset();
11546
11547  getTargetStreamer().emitFnStart();
11548
11549  UC.recordFnStart(L);
11550  return false;
11551}
11552
11553/// parseDirectiveFnEnd
11554///  ::= .fnend
11555bool ARMAsmParser::parseDirectiveFnEnd(SMLoc L) {
11556  if (parseEOL())
11557    return true;
11558  // Check the ordering of unwind directives
11559  if (!UC.hasFnStart())
11560    return Error(L, ".fnstart must precede .fnend directive");
11561
11562  // Reset the unwind directives parser state
11563  getTargetStreamer().emitFnEnd();
11564
11565  UC.reset();
11566  return false;
11567}
11568
11569/// parseDirectiveCantUnwind
11570///  ::= .cantunwind
11571bool ARMAsmParser::parseDirectiveCantUnwind(SMLoc L) {
11572  if (parseEOL())
11573    return true;
11574
11575  UC.recordCantUnwind(L);
11576  // Check the ordering of unwind directives
11577  if (check(!UC.hasFnStart(), L, ".fnstart must precede .cantunwind directive"))
11578    return true;
11579
11580  if (UC.hasHandlerData()) {
11581    Error(L, ".cantunwind can't be used with .handlerdata directive");
11582    UC.emitHandlerDataLocNotes();
11583    return true;
11584  }
11585  if (UC.hasPersonality()) {
11586    Error(L, ".cantunwind can't be used with .personality directive");
11587    UC.emitPersonalityLocNotes();
11588    return true;
11589  }
11590
11591  getTargetStreamer().emitCantUnwind();
11592  return false;
11593}
11594
11595/// parseDirectivePersonality
11596///  ::= .personality name
11597bool ARMAsmParser::parseDirectivePersonality(SMLoc L) {
11598  MCAsmParser &Parser = getParser();
11599  bool HasExistingPersonality = UC.hasPersonality();
11600
11601  // Parse the name of the personality routine
11602  if (Parser.getTok().isNot(AsmToken::Identifier))
11603    return Error(L, "unexpected input in .personality directive.");
11604  StringRef Name(Parser.getTok().getIdentifier());
11605  Parser.Lex();
11606
11607  if (parseEOL())
11608    return true;
11609
11610  UC.recordPersonality(L);
11611
11612  // Check the ordering of unwind directives
11613  if (!UC.hasFnStart())
11614    return Error(L, ".fnstart must precede .personality directive");
11615  if (UC.cantUnwind()) {
11616    Error(L, ".personality can't be used with .cantunwind directive");
11617    UC.emitCantUnwindLocNotes();
11618    return true;
11619  }
11620  if (UC.hasHandlerData()) {
11621    Error(L, ".personality must precede .handlerdata directive");
11622    UC.emitHandlerDataLocNotes();
11623    return true;
11624  }
11625  if (HasExistingPersonality) {
11626    Error(L, "multiple personality directives");
11627    UC.emitPersonalityLocNotes();
11628    return true;
11629  }
11630
11631  MCSymbol *PR = getParser().getContext().getOrCreateSymbol(Name);
11632  getTargetStreamer().emitPersonality(PR);
11633  return false;
11634}
11635
11636/// parseDirectiveHandlerData
11637///  ::= .handlerdata
11638bool ARMAsmParser::parseDirectiveHandlerData(SMLoc L) {
11639  if (parseEOL())
11640    return true;
11641
11642  UC.recordHandlerData(L);
11643  // Check the ordering of unwind directives
11644  if (!UC.hasFnStart())
11645    return Error(L, ".fnstart must precede .personality directive");
11646  if (UC.cantUnwind()) {
11647    Error(L, ".handlerdata can't be used with .cantunwind directive");
11648    UC.emitCantUnwindLocNotes();
11649    return true;
11650  }
11651
11652  getTargetStreamer().emitHandlerData();
11653  return false;
11654}
11655
11656/// parseDirectiveSetFP
11657///  ::= .setfp fpreg, spreg [, offset]
11658bool ARMAsmParser::parseDirectiveSetFP(SMLoc L) {
11659  MCAsmParser &Parser = getParser();
11660  // Check the ordering of unwind directives
11661  if (check(!UC.hasFnStart(), L, ".fnstart must precede .setfp directive") ||
11662      check(UC.hasHandlerData(), L,
11663            ".setfp must precede .handlerdata directive"))
11664    return true;
11665
11666  // Parse fpreg
11667  SMLoc FPRegLoc = Parser.getTok().getLoc();
11668  int FPReg = tryParseRegister();
11669
11670  if (check(FPReg == -1, FPRegLoc, "frame pointer register expected") ||
11671      Parser.parseToken(AsmToken::Comma, "comma expected"))
11672    return true;
11673
11674  // Parse spreg
11675  SMLoc SPRegLoc = Parser.getTok().getLoc();
11676  int SPReg = tryParseRegister();
11677  if (check(SPReg == -1, SPRegLoc, "stack pointer register expected") ||
11678      check(SPReg != ARM::SP && SPReg != UC.getFPReg(), SPRegLoc,
11679            "register should be either $sp or the latest fp register"))
11680    return true;
11681
11682  // Update the frame pointer register
11683  UC.saveFPReg(FPReg);
11684
11685  // Parse offset
11686  int64_t Offset = 0;
11687  if (Parser.parseOptionalToken(AsmToken::Comma)) {
11688    if (Parser.getTok().isNot(AsmToken::Hash) &&
11689        Parser.getTok().isNot(AsmToken::Dollar))
11690      return Error(Parser.getTok().getLoc(), "'#' expected");
11691    Parser.Lex(); // skip hash token.
11692
11693    const MCExpr *OffsetExpr;
11694    SMLoc ExLoc = Parser.getTok().getLoc();
11695    SMLoc EndLoc;
11696    if (getParser().parseExpression(OffsetExpr, EndLoc))
11697      return Error(ExLoc, "malformed setfp offset");
11698    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
11699    if (check(!CE, ExLoc, "setfp offset must be an immediate"))
11700      return true;
11701    Offset = CE->getValue();
11702  }
11703
11704  if (Parser.parseToken(AsmToken::EndOfStatement))
11705    return true;
11706
11707  getTargetStreamer().emitSetFP(static_cast<unsigned>(FPReg),
11708                                static_cast<unsigned>(SPReg), Offset);
11709  return false;
11710}
11711
11712/// parseDirective
11713///  ::= .pad offset
11714bool ARMAsmParser::parseDirectivePad(SMLoc L) {
11715  MCAsmParser &Parser = getParser();
11716  // Check the ordering of unwind directives
11717  if (!UC.hasFnStart())
11718    return Error(L, ".fnstart must precede .pad directive");
11719  if (UC.hasHandlerData())
11720    return Error(L, ".pad must precede .handlerdata directive");
11721
11722  // Parse the offset
11723  if (Parser.getTok().isNot(AsmToken::Hash) &&
11724      Parser.getTok().isNot(AsmToken::Dollar))
11725    return Error(Parser.getTok().getLoc(), "'#' expected");
11726  Parser.Lex(); // skip hash token.
11727
11728  const MCExpr *OffsetExpr;
11729  SMLoc ExLoc = Parser.getTok().getLoc();
11730  SMLoc EndLoc;
11731  if (getParser().parseExpression(OffsetExpr, EndLoc))
11732    return Error(ExLoc, "malformed pad offset");
11733  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
11734  if (!CE)
11735    return Error(ExLoc, "pad offset must be an immediate");
11736
11737  if (parseEOL())
11738    return true;
11739
11740  getTargetStreamer().emitPad(CE->getValue());
11741  return false;
11742}
11743
11744/// parseDirectiveRegSave
11745///  ::= .save  { registers }
11746///  ::= .vsave { registers }
11747bool ARMAsmParser::parseDirectiveRegSave(SMLoc L, bool IsVector) {
11748  // Check the ordering of unwind directives
11749  if (!UC.hasFnStart())
11750    return Error(L, ".fnstart must precede .save or .vsave directives");
11751  if (UC.hasHandlerData())
11752    return Error(L, ".save or .vsave must precede .handlerdata directive");
11753
11754  // RAII object to make sure parsed operands are deleted.
11755  SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Operands;
11756
11757  // Parse the register list
11758  if (parseRegisterList(Operands, true, true) || parseEOL())
11759    return true;
11760  ARMOperand &Op = (ARMOperand &)*Operands[0];
11761  if (!IsVector && !Op.isRegList())
11762    return Error(L, ".save expects GPR registers");
11763  if (IsVector && !Op.isDPRRegList())
11764    return Error(L, ".vsave expects DPR registers");
11765
11766  getTargetStreamer().emitRegSave(Op.getRegList(), IsVector);
11767  return false;
11768}
11769
11770/// parseDirectiveInst
11771///  ::= .inst opcode [, ...]
11772///  ::= .inst.n opcode [, ...]
11773///  ::= .inst.w opcode [, ...]
11774bool ARMAsmParser::parseDirectiveInst(SMLoc Loc, char Suffix) {
11775  int Width = 4;
11776
11777  if (isThumb()) {
11778    switch (Suffix) {
11779    case 'n':
11780      Width = 2;
11781      break;
11782    case 'w':
11783      break;
11784    default:
11785      Width = 0;
11786      break;
11787    }
11788  } else {
11789    if (Suffix)
11790      return Error(Loc, "width suffixes are invalid in ARM mode");
11791  }
11792
11793  auto parseOne = [&]() -> bool {
11794    const MCExpr *Expr;
11795    if (getParser().parseExpression(Expr))
11796      return true;
11797    const MCConstantExpr *Value = dyn_cast_or_null<MCConstantExpr>(Expr);
11798    if (!Value) {
11799      return Error(Loc, "expected constant expression");
11800    }
11801
11802    char CurSuffix = Suffix;
11803    switch (Width) {
11804    case 2:
11805      if (Value->getValue() > 0xffff)
11806        return Error(Loc, "inst.n operand is too big, use inst.w instead");
11807      break;
11808    case 4:
11809      if (Value->getValue() > 0xffffffff)
11810        return Error(Loc, StringRef(Suffix ? "inst.w" : "inst") +
11811                              " operand is too big");
11812      break;
11813    case 0:
11814      // Thumb mode, no width indicated. Guess from the opcode, if possible.
11815      if (Value->getValue() < 0xe800)
11816        CurSuffix = 'n';
11817      else if (Value->getValue() >= 0xe8000000)
11818        CurSuffix = 'w';
11819      else
11820        return Error(Loc, "cannot determine Thumb instruction size, "
11821                          "use inst.n/inst.w instead");
11822      break;
11823    default:
11824      llvm_unreachable("only supported widths are 2 and 4");
11825    }
11826
11827    getTargetStreamer().emitInst(Value->getValue(), CurSuffix);
11828    return false;
11829  };
11830
11831  if (parseOptionalToken(AsmToken::EndOfStatement))
11832    return Error(Loc, "expected expression following directive");
11833  if (parseMany(parseOne))
11834    return true;
11835  return false;
11836}
11837
11838/// parseDirectiveLtorg
11839///  ::= .ltorg | .pool
11840bool ARMAsmParser::parseDirectiveLtorg(SMLoc L) {
11841  if (parseEOL())
11842    return true;
11843  getTargetStreamer().emitCurrentConstantPool();
11844  return false;
11845}
11846
11847bool ARMAsmParser::parseDirectiveEven(SMLoc L) {
11848  const MCSection *Section = getStreamer().getCurrentSectionOnly();
11849
11850  if (parseEOL())
11851    return true;
11852
11853  if (!Section) {
11854    getStreamer().initSections(false, getSTI());
11855    Section = getStreamer().getCurrentSectionOnly();
11856  }
11857
11858  assert(Section && "must have section to emit alignment");
11859  if (Section->useCodeAlign())
11860    getStreamer().emitCodeAlignment(Align(2), &getSTI());
11861  else
11862    getStreamer().emitValueToAlignment(Align(2));
11863
11864  return false;
11865}
11866
11867/// parseDirectivePersonalityIndex
11868///   ::= .personalityindex index
11869bool ARMAsmParser::parseDirectivePersonalityIndex(SMLoc L) {
11870  MCAsmParser &Parser = getParser();
11871  bool HasExistingPersonality = UC.hasPersonality();
11872
11873  const MCExpr *IndexExpression;
11874  SMLoc IndexLoc = Parser.getTok().getLoc();
11875  if (Parser.parseExpression(IndexExpression) || parseEOL()) {
11876    return true;
11877  }
11878
11879  UC.recordPersonalityIndex(L);
11880
11881  if (!UC.hasFnStart()) {
11882    return Error(L, ".fnstart must precede .personalityindex directive");
11883  }
11884  if (UC.cantUnwind()) {
11885    Error(L, ".personalityindex cannot be used with .cantunwind");
11886    UC.emitCantUnwindLocNotes();
11887    return true;
11888  }
11889  if (UC.hasHandlerData()) {
11890    Error(L, ".personalityindex must precede .handlerdata directive");
11891    UC.emitHandlerDataLocNotes();
11892    return true;
11893  }
11894  if (HasExistingPersonality) {
11895    Error(L, "multiple personality directives");
11896    UC.emitPersonalityLocNotes();
11897    return true;
11898  }
11899
11900  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(IndexExpression);
11901  if (!CE)
11902    return Error(IndexLoc, "index must be a constant number");
11903  if (CE->getValue() < 0 || CE->getValue() >= ARM::EHABI::NUM_PERSONALITY_INDEX)
11904    return Error(IndexLoc,
11905                 "personality routine index should be in range [0-3]");
11906
11907  getTargetStreamer().emitPersonalityIndex(CE->getValue());
11908  return false;
11909}
11910
11911/// parseDirectiveUnwindRaw
11912///   ::= .unwind_raw offset, opcode [, opcode...]
11913bool ARMAsmParser::parseDirectiveUnwindRaw(SMLoc L) {
11914  MCAsmParser &Parser = getParser();
11915  int64_t StackOffset;
11916  const MCExpr *OffsetExpr;
11917  SMLoc OffsetLoc = getLexer().getLoc();
11918
11919  if (!UC.hasFnStart())
11920    return Error(L, ".fnstart must precede .unwind_raw directives");
11921  if (getParser().parseExpression(OffsetExpr))
11922    return Error(OffsetLoc, "expected expression");
11923
11924  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
11925  if (!CE)
11926    return Error(OffsetLoc, "offset must be a constant");
11927
11928  StackOffset = CE->getValue();
11929
11930  if (Parser.parseToken(AsmToken::Comma, "expected comma"))
11931    return true;
11932
11933  SmallVector<uint8_t, 16> Opcodes;
11934
11935  auto parseOne = [&]() -> bool {
11936    const MCExpr *OE = nullptr;
11937    SMLoc OpcodeLoc = getLexer().getLoc();
11938    if (check(getLexer().is(AsmToken::EndOfStatement) ||
11939                  Parser.parseExpression(OE),
11940              OpcodeLoc, "expected opcode expression"))
11941      return true;
11942    const MCConstantExpr *OC = dyn_cast<MCConstantExpr>(OE);
11943    if (!OC)
11944      return Error(OpcodeLoc, "opcode value must be a constant");
11945    const int64_t Opcode = OC->getValue();
11946    if (Opcode & ~0xff)
11947      return Error(OpcodeLoc, "invalid opcode");
11948    Opcodes.push_back(uint8_t(Opcode));
11949    return false;
11950  };
11951
11952  // Must have at least 1 element
11953  SMLoc OpcodeLoc = getLexer().getLoc();
11954  if (parseOptionalToken(AsmToken::EndOfStatement))
11955    return Error(OpcodeLoc, "expected opcode expression");
11956  if (parseMany(parseOne))
11957    return true;
11958
11959  getTargetStreamer().emitUnwindRaw(StackOffset, Opcodes);
11960  return false;
11961}
11962
11963/// parseDirectiveTLSDescSeq
11964///   ::= .tlsdescseq tls-variable
11965bool ARMAsmParser::parseDirectiveTLSDescSeq(SMLoc L) {
11966  MCAsmParser &Parser = getParser();
11967
11968  if (getLexer().isNot(AsmToken::Identifier))
11969    return TokError("expected variable after '.tlsdescseq' directive");
11970
11971  const MCSymbolRefExpr *SRE =
11972    MCSymbolRefExpr::create(Parser.getTok().getIdentifier(),
11973                            MCSymbolRefExpr::VK_ARM_TLSDESCSEQ, getContext());
11974  Lex();
11975
11976  if (parseEOL())
11977    return true;
11978
11979  getTargetStreamer().annotateTLSDescriptorSequence(SRE);
11980  return false;
11981}
11982
11983/// parseDirectiveMovSP
11984///  ::= .movsp reg [, #offset]
11985bool ARMAsmParser::parseDirectiveMovSP(SMLoc L) {
11986  MCAsmParser &Parser = getParser();
11987  if (!UC.hasFnStart())
11988    return Error(L, ".fnstart must precede .movsp directives");
11989  if (UC.getFPReg() != ARM::SP)
11990    return Error(L, "unexpected .movsp directive");
11991
11992  SMLoc SPRegLoc = Parser.getTok().getLoc();
11993  int SPReg = tryParseRegister();
11994  if (SPReg == -1)
11995    return Error(SPRegLoc, "register expected");
11996  if (SPReg == ARM::SP || SPReg == ARM::PC)
11997    return Error(SPRegLoc, "sp and pc are not permitted in .movsp directive");
11998
11999  int64_t Offset = 0;
12000  if (Parser.parseOptionalToken(AsmToken::Comma)) {
12001    if (Parser.parseToken(AsmToken::Hash, "expected #constant"))
12002      return true;
12003
12004    const MCExpr *OffsetExpr;
12005    SMLoc OffsetLoc = Parser.getTok().getLoc();
12006
12007    if (Parser.parseExpression(OffsetExpr))
12008      return Error(OffsetLoc, "malformed offset expression");
12009
12010    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
12011    if (!CE)
12012      return Error(OffsetLoc, "offset must be an immediate constant");
12013
12014    Offset = CE->getValue();
12015  }
12016
12017  if (parseEOL())
12018    return true;
12019
12020  getTargetStreamer().emitMovSP(SPReg, Offset);
12021  UC.saveFPReg(SPReg);
12022
12023  return false;
12024}
12025
12026/// parseDirectiveObjectArch
12027///   ::= .object_arch name
12028bool ARMAsmParser::parseDirectiveObjectArch(SMLoc L) {
12029  MCAsmParser &Parser = getParser();
12030  if (getLexer().isNot(AsmToken::Identifier))
12031    return Error(getLexer().getLoc(), "unexpected token");
12032
12033  StringRef Arch = Parser.getTok().getString();
12034  SMLoc ArchLoc = Parser.getTok().getLoc();
12035  Lex();
12036
12037  ARM::ArchKind ID = ARM::parseArch(Arch);
12038
12039  if (ID == ARM::ArchKind::INVALID)
12040    return Error(ArchLoc, "unknown architecture '" + Arch + "'");
12041  if (parseToken(AsmToken::EndOfStatement))
12042    return true;
12043
12044  getTargetStreamer().emitObjectArch(ID);
12045  return false;
12046}
12047
12048/// parseDirectiveAlign
12049///   ::= .align
12050bool ARMAsmParser::parseDirectiveAlign(SMLoc L) {
12051  // NOTE: if this is not the end of the statement, fall back to the target
12052  // agnostic handling for this directive which will correctly handle this.
12053  if (parseOptionalToken(AsmToken::EndOfStatement)) {
12054    // '.align' is target specifically handled to mean 2**2 byte alignment.
12055    const MCSection *Section = getStreamer().getCurrentSectionOnly();
12056    assert(Section && "must have section to emit alignment");
12057    if (Section->useCodeAlign())
12058      getStreamer().emitCodeAlignment(Align(4), &getSTI(), 0);
12059    else
12060      getStreamer().emitValueToAlignment(Align(4), 0, 1, 0);
12061    return false;
12062  }
12063  return true;
12064}
12065
12066/// parseDirectiveThumbSet
12067///  ::= .thumb_set name, value
12068bool ARMAsmParser::parseDirectiveThumbSet(SMLoc L) {
12069  MCAsmParser &Parser = getParser();
12070
12071  StringRef Name;
12072  if (check(Parser.parseIdentifier(Name),
12073            "expected identifier after '.thumb_set'") ||
12074      parseToken(AsmToken::Comma, "expected comma after name '" + Name + "'"))
12075    return true;
12076
12077  MCSymbol *Sym;
12078  const MCExpr *Value;
12079  if (MCParserUtils::parseAssignmentExpression(Name, /* allow_redef */ true,
12080                                               Parser, Sym, Value))
12081    return true;
12082
12083  getTargetStreamer().emitThumbSet(Sym, Value);
12084  return false;
12085}
12086
12087/// parseDirectiveSEHAllocStack
12088/// ::= .seh_stackalloc
12089/// ::= .seh_stackalloc_w
12090bool ARMAsmParser::parseDirectiveSEHAllocStack(SMLoc L, bool Wide) {
12091  int64_t Size;
12092  if (parseImmExpr(Size))
12093    return true;
12094  getTargetStreamer().emitARMWinCFIAllocStack(Size, Wide);
12095  return false;
12096}
12097
12098/// parseDirectiveSEHSaveRegs
12099/// ::= .seh_save_regs
12100/// ::= .seh_save_regs_w
12101bool ARMAsmParser::parseDirectiveSEHSaveRegs(SMLoc L, bool Wide) {
12102  SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Operands;
12103
12104  if (parseRegisterList(Operands) || parseEOL())
12105    return true;
12106  ARMOperand &Op = (ARMOperand &)*Operands[0];
12107  if (!Op.isRegList())
12108    return Error(L, ".seh_save_regs{_w} expects GPR registers");
12109  const SmallVectorImpl<unsigned> &RegList = Op.getRegList();
12110  uint32_t Mask = 0;
12111  for (size_t i = 0; i < RegList.size(); ++i) {
12112    unsigned Reg = MRI->getEncodingValue(RegList[i]);
12113    if (Reg == 15) // pc -> lr
12114      Reg = 14;
12115    if (Reg == 13)
12116      return Error(L, ".seh_save_regs{_w} can't include SP");
12117    assert(Reg < 16U && "Register out of range");
12118    unsigned Bit = (1u << Reg);
12119    Mask |= Bit;
12120  }
12121  if (!Wide && (Mask & 0x1f00) != 0)
12122    return Error(L,
12123                 ".seh_save_regs cannot save R8-R12, needs .seh_save_regs_w");
12124  getTargetStreamer().emitARMWinCFISaveRegMask(Mask, Wide);
12125  return false;
12126}
12127
12128/// parseDirectiveSEHSaveSP
12129/// ::= .seh_save_sp
12130bool ARMAsmParser::parseDirectiveSEHSaveSP(SMLoc L) {
12131  int Reg = tryParseRegister();
12132  if (Reg == -1 || !MRI->getRegClass(ARM::GPRRegClassID).contains(Reg))
12133    return Error(L, "expected GPR");
12134  unsigned Index = MRI->getEncodingValue(Reg);
12135  if (Index > 14 || Index == 13)
12136    return Error(L, "invalid register for .seh_save_sp");
12137  getTargetStreamer().emitARMWinCFISaveSP(Index);
12138  return false;
12139}
12140
12141/// parseDirectiveSEHSaveFRegs
12142/// ::= .seh_save_fregs
12143bool ARMAsmParser::parseDirectiveSEHSaveFRegs(SMLoc L) {
12144  SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Operands;
12145
12146  if (parseRegisterList(Operands) || parseEOL())
12147    return true;
12148  ARMOperand &Op = (ARMOperand &)*Operands[0];
12149  if (!Op.isDPRRegList())
12150    return Error(L, ".seh_save_fregs expects DPR registers");
12151  const SmallVectorImpl<unsigned> &RegList = Op.getRegList();
12152  uint32_t Mask = 0;
12153  for (size_t i = 0; i < RegList.size(); ++i) {
12154    unsigned Reg = MRI->getEncodingValue(RegList[i]);
12155    assert(Reg < 32U && "Register out of range");
12156    unsigned Bit = (1u << Reg);
12157    Mask |= Bit;
12158  }
12159
12160  if (Mask == 0)
12161    return Error(L, ".seh_save_fregs missing registers");
12162
12163  unsigned First = 0;
12164  while ((Mask & 1) == 0) {
12165    First++;
12166    Mask >>= 1;
12167  }
12168  if (((Mask + 1) & Mask) != 0)
12169    return Error(L,
12170                 ".seh_save_fregs must take a contiguous range of registers");
12171  unsigned Last = First;
12172  while ((Mask & 2) != 0) {
12173    Last++;
12174    Mask >>= 1;
12175  }
12176  if (First < 16 && Last >= 16)
12177    return Error(L, ".seh_save_fregs must be all d0-d15 or d16-d31");
12178  getTargetStreamer().emitARMWinCFISaveFRegs(First, Last);
12179  return false;
12180}
12181
12182/// parseDirectiveSEHSaveLR
12183/// ::= .seh_save_lr
12184bool ARMAsmParser::parseDirectiveSEHSaveLR(SMLoc L) {
12185  int64_t Offset;
12186  if (parseImmExpr(Offset))
12187    return true;
12188  getTargetStreamer().emitARMWinCFISaveLR(Offset);
12189  return false;
12190}
12191
12192/// parseDirectiveSEHPrologEnd
12193/// ::= .seh_endprologue
12194/// ::= .seh_endprologue_fragment
12195bool ARMAsmParser::parseDirectiveSEHPrologEnd(SMLoc L, bool Fragment) {
12196  getTargetStreamer().emitARMWinCFIPrologEnd(Fragment);
12197  return false;
12198}
12199
12200/// parseDirectiveSEHNop
12201/// ::= .seh_nop
12202/// ::= .seh_nop_w
12203bool ARMAsmParser::parseDirectiveSEHNop(SMLoc L, bool Wide) {
12204  getTargetStreamer().emitARMWinCFINop(Wide);
12205  return false;
12206}
12207
12208/// parseDirectiveSEHEpilogStart
12209/// ::= .seh_startepilogue
12210/// ::= .seh_startepilogue_cond
12211bool ARMAsmParser::parseDirectiveSEHEpilogStart(SMLoc L, bool Condition) {
12212  unsigned CC = ARMCC::AL;
12213  if (Condition) {
12214    MCAsmParser &Parser = getParser();
12215    SMLoc S = Parser.getTok().getLoc();
12216    const AsmToken &Tok = Parser.getTok();
12217    if (!Tok.is(AsmToken::Identifier))
12218      return Error(S, ".seh_startepilogue_cond missing condition");
12219    CC = ARMCondCodeFromString(Tok.getString());
12220    if (CC == ~0U)
12221      return Error(S, "invalid condition");
12222    Parser.Lex(); // Eat the token.
12223  }
12224
12225  getTargetStreamer().emitARMWinCFIEpilogStart(CC);
12226  return false;
12227}
12228
12229/// parseDirectiveSEHEpilogEnd
12230/// ::= .seh_endepilogue
12231bool ARMAsmParser::parseDirectiveSEHEpilogEnd(SMLoc L) {
12232  getTargetStreamer().emitARMWinCFIEpilogEnd();
12233  return false;
12234}
12235
12236/// parseDirectiveSEHCustom
12237/// ::= .seh_custom
12238bool ARMAsmParser::parseDirectiveSEHCustom(SMLoc L) {
12239  unsigned Opcode = 0;
12240  do {
12241    int64_t Byte;
12242    if (parseImmExpr(Byte))
12243      return true;
12244    if (Byte > 0xff || Byte < 0)
12245      return Error(L, "Invalid byte value in .seh_custom");
12246    if (Opcode > 0x00ffffff)
12247      return Error(L, "Too many bytes in .seh_custom");
12248    // Store the bytes as one big endian number in Opcode. In a multi byte
12249    // opcode sequence, the first byte can't be zero.
12250    Opcode = (Opcode << 8) | Byte;
12251  } while (parseOptionalToken(AsmToken::Comma));
12252  getTargetStreamer().emitARMWinCFICustom(Opcode);
12253  return false;
12254}
12255
12256/// Force static initialization.
12257extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMAsmParser() {
12258  RegisterMCAsmParser<ARMAsmParser> X(getTheARMLETarget());
12259  RegisterMCAsmParser<ARMAsmParser> Y(getTheARMBETarget());
12260  RegisterMCAsmParser<ARMAsmParser> A(getTheThumbLETarget());
12261  RegisterMCAsmParser<ARMAsmParser> B(getTheThumbBETarget());
12262}
12263
12264#define GET_REGISTER_MATCHER
12265#define GET_SUBTARGET_FEATURE_NAME
12266#define GET_MATCHER_IMPLEMENTATION
12267#define GET_MNEMONIC_SPELL_CHECKER
12268#include "ARMGenAsmMatcher.inc"
12269
12270// Some diagnostics need to vary with subtarget features, so they are handled
12271// here. For example, the DPR class has either 16 or 32 registers, depending
12272// on the FPU available.
12273const char *
12274ARMAsmParser::getCustomOperandDiag(ARMMatchResultTy MatchError) {
12275  switch (MatchError) {
12276  // rGPR contains sp starting with ARMv8.
12277  case Match_rGPR:
12278    return hasV8Ops() ? "operand must be a register in range [r0, r14]"
12279                      : "operand must be a register in range [r0, r12] or r14";
12280  // DPR contains 16 registers for some FPUs, and 32 for others.
12281  case Match_DPR:
12282    return hasD32() ? "operand must be a register in range [d0, d31]"
12283                    : "operand must be a register in range [d0, d15]";
12284  case Match_DPR_RegList:
12285    return hasD32() ? "operand must be a list of registers in range [d0, d31]"
12286                    : "operand must be a list of registers in range [d0, d15]";
12287
12288  // For all other diags, use the static string from tablegen.
12289  default:
12290    return getMatchKindDiag(MatchError);
12291  }
12292}
12293
12294// Process the list of near-misses, throwing away ones we don't want to report
12295// to the user, and converting the rest to a source location and string that
12296// should be reported.
12297void
12298ARMAsmParser::FilterNearMisses(SmallVectorImpl<NearMissInfo> &NearMissesIn,
12299                               SmallVectorImpl<NearMissMessage> &NearMissesOut,
12300                               SMLoc IDLoc, OperandVector &Operands) {
12301  // TODO: If operand didn't match, sub in a dummy one and run target
12302  // predicate, so that we can avoid reporting near-misses that are invalid?
12303  // TODO: Many operand types dont have SuperClasses set, so we report
12304  // redundant ones.
12305  // TODO: Some operands are superclasses of registers (e.g.
12306  // MCK_RegShiftedImm), we don't have any way to represent that currently.
12307  // TODO: This is not all ARM-specific, can some of it be factored out?
12308
12309  // Record some information about near-misses that we have already seen, so
12310  // that we can avoid reporting redundant ones. For example, if there are
12311  // variants of an instruction that take 8- and 16-bit immediates, we want
12312  // to only report the widest one.
12313  std::multimap<unsigned, unsigned> OperandMissesSeen;
12314  SmallSet<FeatureBitset, 4> FeatureMissesSeen;
12315  bool ReportedTooFewOperands = false;
12316
12317  // Process the near-misses in reverse order, so that we see more general ones
12318  // first, and so can avoid emitting more specific ones.
12319  for (NearMissInfo &I : reverse(NearMissesIn)) {
12320    switch (I.getKind()) {
12321    case NearMissInfo::NearMissOperand: {
12322      SMLoc OperandLoc =
12323          ((ARMOperand &)*Operands[I.getOperandIndex()]).getStartLoc();
12324      const char *OperandDiag =
12325          getCustomOperandDiag((ARMMatchResultTy)I.getOperandError());
12326
12327      // If we have already emitted a message for a superclass, don't also report
12328      // the sub-class. We consider all operand classes that we don't have a
12329      // specialised diagnostic for to be equal for the propose of this check,
12330      // so that we don't report the generic error multiple times on the same
12331      // operand.
12332      unsigned DupCheckMatchClass = OperandDiag ? I.getOperandClass() : ~0U;
12333      auto PrevReports = OperandMissesSeen.equal_range(I.getOperandIndex());
12334      if (std::any_of(PrevReports.first, PrevReports.second,
12335                      [DupCheckMatchClass](
12336                          const std::pair<unsigned, unsigned> Pair) {
12337            if (DupCheckMatchClass == ~0U || Pair.second == ~0U)
12338              return Pair.second == DupCheckMatchClass;
12339            else
12340              return isSubclass((MatchClassKind)DupCheckMatchClass,
12341                                (MatchClassKind)Pair.second);
12342          }))
12343        break;
12344      OperandMissesSeen.insert(
12345          std::make_pair(I.getOperandIndex(), DupCheckMatchClass));
12346
12347      NearMissMessage Message;
12348      Message.Loc = OperandLoc;
12349      if (OperandDiag) {
12350        Message.Message = OperandDiag;
12351      } else if (I.getOperandClass() == InvalidMatchClass) {
12352        Message.Message = "too many operands for instruction";
12353      } else {
12354        Message.Message = "invalid operand for instruction";
12355        LLVM_DEBUG(
12356            dbgs() << "Missing diagnostic string for operand class "
12357                   << getMatchClassName((MatchClassKind)I.getOperandClass())
12358                   << I.getOperandClass() << ", error " << I.getOperandError()
12359                   << ", opcode " << MII.getName(I.getOpcode()) << "\n");
12360      }
12361      NearMissesOut.emplace_back(Message);
12362      break;
12363    }
12364    case NearMissInfo::NearMissFeature: {
12365      const FeatureBitset &MissingFeatures = I.getFeatures();
12366      // Don't report the same set of features twice.
12367      if (FeatureMissesSeen.count(MissingFeatures))
12368        break;
12369      FeatureMissesSeen.insert(MissingFeatures);
12370
12371      // Special case: don't report a feature set which includes arm-mode for
12372      // targets that don't have ARM mode.
12373      if (MissingFeatures.test(Feature_IsARMBit) && !hasARM())
12374        break;
12375      // Don't report any near-misses that both require switching instruction
12376      // set, and adding other subtarget features.
12377      if (isThumb() && MissingFeatures.test(Feature_IsARMBit) &&
12378          MissingFeatures.count() > 1)
12379        break;
12380      if (!isThumb() && MissingFeatures.test(Feature_IsThumbBit) &&
12381          MissingFeatures.count() > 1)
12382        break;
12383      if (!isThumb() && MissingFeatures.test(Feature_IsThumb2Bit) &&
12384          (MissingFeatures & ~FeatureBitset({Feature_IsThumb2Bit,
12385                                             Feature_IsThumbBit})).any())
12386        break;
12387      if (isMClass() && MissingFeatures.test(Feature_HasNEONBit))
12388        break;
12389
12390      NearMissMessage Message;
12391      Message.Loc = IDLoc;
12392      raw_svector_ostream OS(Message.Message);
12393
12394      OS << "instruction requires:";
12395      for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
12396        if (MissingFeatures.test(i))
12397          OS << ' ' << getSubtargetFeatureName(i);
12398
12399      NearMissesOut.emplace_back(Message);
12400
12401      break;
12402    }
12403    case NearMissInfo::NearMissPredicate: {
12404      NearMissMessage Message;
12405      Message.Loc = IDLoc;
12406      switch (I.getPredicateError()) {
12407      case Match_RequiresNotITBlock:
12408        Message.Message = "flag setting instruction only valid outside IT block";
12409        break;
12410      case Match_RequiresITBlock:
12411        Message.Message = "instruction only valid inside IT block";
12412        break;
12413      case Match_RequiresV6:
12414        Message.Message = "instruction variant requires ARMv6 or later";
12415        break;
12416      case Match_RequiresThumb2:
12417        Message.Message = "instruction variant requires Thumb2";
12418        break;
12419      case Match_RequiresV8:
12420        Message.Message = "instruction variant requires ARMv8 or later";
12421        break;
12422      case Match_RequiresFlagSetting:
12423        Message.Message = "no flag-preserving variant of this instruction available";
12424        break;
12425      case Match_InvalidOperand:
12426        Message.Message = "invalid operand for instruction";
12427        break;
12428      default:
12429        llvm_unreachable("Unhandled target predicate error");
12430        break;
12431      }
12432      NearMissesOut.emplace_back(Message);
12433      break;
12434    }
12435    case NearMissInfo::NearMissTooFewOperands: {
12436      if (!ReportedTooFewOperands) {
12437        SMLoc EndLoc = ((ARMOperand &)*Operands.back()).getEndLoc();
12438        NearMissesOut.emplace_back(NearMissMessage{
12439            EndLoc, StringRef("too few operands for instruction")});
12440        ReportedTooFewOperands = true;
12441      }
12442      break;
12443    }
12444    case NearMissInfo::NoNearMiss:
12445      // This should never leave the matcher.
12446      llvm_unreachable("not a near-miss");
12447      break;
12448    }
12449  }
12450}
12451
12452void ARMAsmParser::ReportNearMisses(SmallVectorImpl<NearMissInfo> &NearMisses,
12453                                    SMLoc IDLoc, OperandVector &Operands) {
12454  SmallVector<NearMissMessage, 4> Messages;
12455  FilterNearMisses(NearMisses, Messages, IDLoc, Operands);
12456
12457  if (Messages.size() == 0) {
12458    // No near-misses were found, so the best we can do is "invalid
12459    // instruction".
12460    Error(IDLoc, "invalid instruction");
12461  } else if (Messages.size() == 1) {
12462    // One near miss was found, report it as the sole error.
12463    Error(Messages[0].Loc, Messages[0].Message);
12464  } else {
12465    // More than one near miss, so report a generic "invalid instruction"
12466    // error, followed by notes for each of the near-misses.
12467    Error(IDLoc, "invalid instruction, any one of the following would fix this:");
12468    for (auto &M : Messages) {
12469      Note(M.Loc, M.Message);
12470    }
12471  }
12472}
12473
12474bool ARMAsmParser::enableArchExtFeature(StringRef Name, SMLoc &ExtLoc) {
12475  // FIXME: This structure should be moved inside ARMTargetParser
12476  // when we start to table-generate them, and we can use the ARM
12477  // flags below, that were generated by table-gen.
12478  static const struct {
12479    const uint64_t Kind;
12480    const FeatureBitset ArchCheck;
12481    const FeatureBitset Features;
12482  } Extensions[] = {
12483      {ARM::AEK_CRC, {Feature_HasV8Bit}, {ARM::FeatureCRC}},
12484      {ARM::AEK_AES,
12485       {Feature_HasV8Bit},
12486       {ARM::FeatureAES, ARM::FeatureNEON, ARM::FeatureFPARMv8}},
12487      {ARM::AEK_SHA2,
12488       {Feature_HasV8Bit},
12489       {ARM::FeatureSHA2, ARM::FeatureNEON, ARM::FeatureFPARMv8}},
12490      {ARM::AEK_CRYPTO,
12491       {Feature_HasV8Bit},
12492       {ARM::FeatureCrypto, ARM::FeatureNEON, ARM::FeatureFPARMv8}},
12493      {ARM::AEK_FP,
12494       {Feature_HasV8Bit},
12495       {ARM::FeatureVFP2_SP, ARM::FeatureFPARMv8}},
12496      {(ARM::AEK_HWDIVTHUMB | ARM::AEK_HWDIVARM),
12497       {Feature_HasV7Bit, Feature_IsNotMClassBit},
12498       {ARM::FeatureHWDivThumb, ARM::FeatureHWDivARM}},
12499      {ARM::AEK_MP,
12500       {Feature_HasV7Bit, Feature_IsNotMClassBit},
12501       {ARM::FeatureMP}},
12502      {ARM::AEK_SIMD,
12503       {Feature_HasV8Bit},
12504       {ARM::FeatureNEON, ARM::FeatureVFP2_SP, ARM::FeatureFPARMv8}},
12505      {ARM::AEK_SEC, {Feature_HasV6KBit}, {ARM::FeatureTrustZone}},
12506      // FIXME: Only available in A-class, isel not predicated
12507      {ARM::AEK_VIRT, {Feature_HasV7Bit}, {ARM::FeatureVirtualization}},
12508      {ARM::AEK_FP16,
12509       {Feature_HasV8_2aBit},
12510       {ARM::FeatureFPARMv8, ARM::FeatureFullFP16}},
12511      {ARM::AEK_RAS, {Feature_HasV8Bit}, {ARM::FeatureRAS}},
12512      {ARM::AEK_LOB, {Feature_HasV8_1MMainlineBit}, {ARM::FeatureLOB}},
12513      {ARM::AEK_PACBTI, {Feature_HasV8_1MMainlineBit}, {ARM::FeaturePACBTI}},
12514      // FIXME: Unsupported extensions.
12515      {ARM::AEK_OS, {}, {}},
12516      {ARM::AEK_IWMMXT, {}, {}},
12517      {ARM::AEK_IWMMXT2, {}, {}},
12518      {ARM::AEK_MAVERICK, {}, {}},
12519      {ARM::AEK_XSCALE, {}, {}},
12520  };
12521  bool EnableFeature = true;
12522  if (Name.startswith_insensitive("no")) {
12523    EnableFeature = false;
12524    Name = Name.substr(2);
12525  }
12526  uint64_t FeatureKind = ARM::parseArchExt(Name);
12527  if (FeatureKind == ARM::AEK_INVALID)
12528    return Error(ExtLoc, "unknown architectural extension: " + Name);
12529
12530  for (const auto &Extension : Extensions) {
12531    if (Extension.Kind != FeatureKind)
12532      continue;
12533
12534    if (Extension.Features.none())
12535      return Error(ExtLoc, "unsupported architectural extension: " + Name);
12536
12537    if ((getAvailableFeatures() & Extension.ArchCheck) != Extension.ArchCheck)
12538      return Error(ExtLoc, "architectural extension '" + Name +
12539                               "' is not "
12540                               "allowed for the current base architecture");
12541
12542    MCSubtargetInfo &STI = copySTI();
12543    if (EnableFeature) {
12544      STI.SetFeatureBitsTransitively(Extension.Features);
12545    } else {
12546      STI.ClearFeatureBitsTransitively(Extension.Features);
12547    }
12548    FeatureBitset Features = ComputeAvailableFeatures(STI.getFeatureBits());
12549    setAvailableFeatures(Features);
12550    return true;
12551  }
12552  return false;
12553}
12554
12555/// parseDirectiveArchExtension
12556///   ::= .arch_extension [no]feature
12557bool ARMAsmParser::parseDirectiveArchExtension(SMLoc L) {
12558
12559  MCAsmParser &Parser = getParser();
12560
12561  if (getLexer().isNot(AsmToken::Identifier))
12562    return Error(getLexer().getLoc(), "expected architecture extension name");
12563
12564  StringRef Name = Parser.getTok().getString();
12565  SMLoc ExtLoc = Parser.getTok().getLoc();
12566  Lex();
12567
12568  if (parseEOL())
12569    return true;
12570
12571  if (Name == "nocrypto") {
12572    enableArchExtFeature("nosha2", ExtLoc);
12573    enableArchExtFeature("noaes", ExtLoc);
12574  }
12575
12576  if (enableArchExtFeature(Name, ExtLoc))
12577    return false;
12578
12579  return Error(ExtLoc, "unknown architectural extension: " + Name);
12580}
12581
12582// Define this matcher function after the auto-generated include so we
12583// have the match class enum definitions.
12584unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
12585                                                  unsigned Kind) {
12586  ARMOperand &Op = static_cast<ARMOperand &>(AsmOp);
12587  // If the kind is a token for a literal immediate, check if our asm
12588  // operand matches. This is for InstAliases which have a fixed-value
12589  // immediate in the syntax.
12590  switch (Kind) {
12591  default: break;
12592  case MCK__HASH_0:
12593    if (Op.isImm())
12594      if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm()))
12595        if (CE->getValue() == 0)
12596          return Match_Success;
12597    break;
12598  case MCK__HASH_8:
12599    if (Op.isImm())
12600      if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm()))
12601        if (CE->getValue() == 8)
12602          return Match_Success;
12603    break;
12604  case MCK__HASH_16:
12605    if (Op.isImm())
12606      if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm()))
12607        if (CE->getValue() == 16)
12608          return Match_Success;
12609    break;
12610  case MCK_ModImm:
12611    if (Op.isImm()) {
12612      const MCExpr *SOExpr = Op.getImm();
12613      int64_t Value;
12614      if (!SOExpr->evaluateAsAbsolute(Value))
12615        return Match_Success;
12616      assert((Value >= std::numeric_limits<int32_t>::min() &&
12617              Value <= std::numeric_limits<uint32_t>::max()) &&
12618             "expression value must be representable in 32 bits");
12619    }
12620    break;
12621  case MCK_rGPR:
12622    if (hasV8Ops() && Op.isReg() && Op.getReg() == ARM::SP)
12623      return Match_Success;
12624    return Match_rGPR;
12625  case MCK_GPRPair:
12626    if (Op.isReg() &&
12627        MRI->getRegClass(ARM::GPRRegClassID).contains(Op.getReg()))
12628      return Match_Success;
12629    break;
12630  }
12631  return Match_InvalidOperand;
12632}
12633
12634bool ARMAsmParser::isMnemonicVPTPredicable(StringRef Mnemonic,
12635                                           StringRef ExtraToken) {
12636  if (!hasMVE())
12637    return false;
12638
12639  return Mnemonic.startswith("vabav") || Mnemonic.startswith("vaddv") ||
12640         Mnemonic.startswith("vaddlv") || Mnemonic.startswith("vminnmv") ||
12641         Mnemonic.startswith("vminnmav") || Mnemonic.startswith("vminv") ||
12642         Mnemonic.startswith("vminav") || Mnemonic.startswith("vmaxnmv") ||
12643         Mnemonic.startswith("vmaxnmav") || Mnemonic.startswith("vmaxv") ||
12644         Mnemonic.startswith("vmaxav") || Mnemonic.startswith("vmladav") ||
12645         Mnemonic.startswith("vrmlaldavh") || Mnemonic.startswith("vrmlalvh") ||
12646         Mnemonic.startswith("vmlsdav") || Mnemonic.startswith("vmlav") ||
12647         Mnemonic.startswith("vmlaldav") || Mnemonic.startswith("vmlalv") ||
12648         Mnemonic.startswith("vmaxnm") || Mnemonic.startswith("vminnm") ||
12649         Mnemonic.startswith("vmax") || Mnemonic.startswith("vmin") ||
12650         Mnemonic.startswith("vshlc") || Mnemonic.startswith("vmovlt") ||
12651         Mnemonic.startswith("vmovlb") || Mnemonic.startswith("vshll") ||
12652         Mnemonic.startswith("vrshrn") || Mnemonic.startswith("vshrn") ||
12653         Mnemonic.startswith("vqrshrun") || Mnemonic.startswith("vqshrun") ||
12654         Mnemonic.startswith("vqrshrn") || Mnemonic.startswith("vqshrn") ||
12655         Mnemonic.startswith("vbic") || Mnemonic.startswith("vrev64") ||
12656         Mnemonic.startswith("vrev32") || Mnemonic.startswith("vrev16") ||
12657         Mnemonic.startswith("vmvn") || Mnemonic.startswith("veor") ||
12658         Mnemonic.startswith("vorn") || Mnemonic.startswith("vorr") ||
12659         Mnemonic.startswith("vand") || Mnemonic.startswith("vmul") ||
12660         Mnemonic.startswith("vqrdmulh") || Mnemonic.startswith("vqdmulh") ||
12661         Mnemonic.startswith("vsub") || Mnemonic.startswith("vadd") ||
12662         Mnemonic.startswith("vqsub") || Mnemonic.startswith("vqadd") ||
12663         Mnemonic.startswith("vabd") || Mnemonic.startswith("vrhadd") ||
12664         Mnemonic.startswith("vhsub") || Mnemonic.startswith("vhadd") ||
12665         Mnemonic.startswith("vdup") || Mnemonic.startswith("vcls") ||
12666         Mnemonic.startswith("vclz") || Mnemonic.startswith("vneg") ||
12667         Mnemonic.startswith("vabs") || Mnemonic.startswith("vqneg") ||
12668         Mnemonic.startswith("vqabs") ||
12669         (Mnemonic.startswith("vrint") && Mnemonic != "vrintr") ||
12670         Mnemonic.startswith("vcmla") || Mnemonic.startswith("vfma") ||
12671         Mnemonic.startswith("vfms") || Mnemonic.startswith("vcadd") ||
12672         Mnemonic.startswith("vadd") || Mnemonic.startswith("vsub") ||
12673         Mnemonic.startswith("vshl") || Mnemonic.startswith("vqshl") ||
12674         Mnemonic.startswith("vqrshl") || Mnemonic.startswith("vrshl") ||
12675         Mnemonic.startswith("vsri") || Mnemonic.startswith("vsli") ||
12676         Mnemonic.startswith("vrshr") || Mnemonic.startswith("vshr") ||
12677         Mnemonic.startswith("vpsel") || Mnemonic.startswith("vcmp") ||
12678         Mnemonic.startswith("vqdmladh") || Mnemonic.startswith("vqrdmladh") ||
12679         Mnemonic.startswith("vqdmlsdh") || Mnemonic.startswith("vqrdmlsdh") ||
12680         Mnemonic.startswith("vcmul") || Mnemonic.startswith("vrmulh") ||
12681         Mnemonic.startswith("vqmovn") || Mnemonic.startswith("vqmovun") ||
12682         Mnemonic.startswith("vmovnt") || Mnemonic.startswith("vmovnb") ||
12683         Mnemonic.startswith("vmaxa") || Mnemonic.startswith("vmaxnma") ||
12684         Mnemonic.startswith("vhcadd") || Mnemonic.startswith("vadc") ||
12685         Mnemonic.startswith("vsbc") || Mnemonic.startswith("vrshr") ||
12686         Mnemonic.startswith("vshr") || Mnemonic.startswith("vstrb") ||
12687         Mnemonic.startswith("vldrb") ||
12688         (Mnemonic.startswith("vstrh") && Mnemonic != "vstrhi") ||
12689         (Mnemonic.startswith("vldrh") && Mnemonic != "vldrhi") ||
12690         Mnemonic.startswith("vstrw") || Mnemonic.startswith("vldrw") ||
12691         Mnemonic.startswith("vldrd") || Mnemonic.startswith("vstrd") ||
12692         Mnemonic.startswith("vqdmull") || Mnemonic.startswith("vbrsr") ||
12693         Mnemonic.startswith("vfmas") || Mnemonic.startswith("vmlas") ||
12694         Mnemonic.startswith("vmla") || Mnemonic.startswith("vqdmlash") ||
12695         Mnemonic.startswith("vqdmlah") || Mnemonic.startswith("vqrdmlash") ||
12696         Mnemonic.startswith("vqrdmlah") || Mnemonic.startswith("viwdup") ||
12697         Mnemonic.startswith("vdwdup") || Mnemonic.startswith("vidup") ||
12698         Mnemonic.startswith("vddup") || Mnemonic.startswith("vctp") ||
12699         Mnemonic.startswith("vpnot") || Mnemonic.startswith("vbic") ||
12700         Mnemonic.startswith("vrmlsldavh") || Mnemonic.startswith("vmlsldav") ||
12701         Mnemonic.startswith("vcvt") ||
12702         MS.isVPTPredicableCDEInstr(Mnemonic) ||
12703         (Mnemonic.startswith("vmov") &&
12704          !(ExtraToken == ".f16" || ExtraToken == ".32" ||
12705            ExtraToken == ".16" || ExtraToken == ".8"));
12706}
12707